Semiconductor process monitoring method

Abstract

The invention provides a semiconductor process monitoring method, which comprises the following steps of: sputtering metal on the surface of a semiconductor sample to form a thin film, and depositing a marking material in a target area to form a marking layer to cover an action space of a target process. The method comprises the following steps of: firstly, carrying out glue sealing treatment, removing the mark layer to expose a target surface containing a target process effect, and finally, scanning by utilizing a scanning electron microscope to obtain an image capable of being used for evaluating the target process effect. According to the method, through the arrangement of the marking layer, the uniformity of the target area in removal processing is ensured, and edge damage is avoided; and the mark layer defines the removal end point position, so that the section of the reaction target process effect can be accurately exposed, and a reliable basis is provided for process optimization. Compared with a traditional scanning electron microscope section observation technology, the method can obtain key information more quickly and accurately, and is beneficial to improving the yield and the performance stability of semiconductor products.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor process monitoring method. Background Art

[0002] In the semiconductor manufacturing industry, the ion implantation process is one of the core processes that determine the performance and quality of semiconductor devices. In this process, specific ions are accelerated and implanted into semiconductor materials to change their electrical properties to meet the design requirements of different devices. Even minor deviations in parameters such as the dose, depth, and uniformity of ion implantation can lead to a decline in device performance or even failure. Therefore, precise monitoring of the ion implantation process is crucial to effectively ensure the yield and performance stability of semiconductor products.

[0003] Currently, the scanning electron microscope cross-section observation monitoring technology is one of the commonly used means for monitoring the semiconductor ion implantation process. Its principle is to use a focused electron beam to scan the surface of the sample, and by detecting signals such as secondary electrons, obtain a microscopic morphology image of the sample cross-section to assist in judging the ion implantation situation. However, this technology has obvious limitations. Existing scanning electron microscope cross-section observations are difficult to accurately locate the ion implantation area for targeted monitoring. The internal structure of semiconductor materials is complex, and the differences in microscopic morphology between the ion implantation area and other areas are not prominent, making it difficult to accurately distinguish by conventional scanning electron microscope observations. This makes it difficult to quickly and accurately obtain key information in the ion implantation process, affecting the optimization of the process and the improvement of product quality. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor process monitoring method that can improve the above problems.

[0005] The embodiments of this application are implemented as follows: This application provides a semiconductor process monitoring method, which includes: Providing a semiconductor sample after being processed by a target process; Sputtering a metal material on the surface of the semiconductor sample to form a metal thin film; Depositing a marking material on the target area on the surface of the semiconductor sample with the metal thin film formed to form a marking layer, where the target area at least partially covers the action space of the target process; Performing a sealing treatment on the semiconductor sample to form a sealed composite; Performing a removal treatment on the sealed composite along a direction parallel to the surface to the marking layer, so that the sealed composite exposes a target surface including at least part of the action space; Scanning the target surface with a scanning electron microscope to obtain a scanning electron microscope image.

[0006] It can be understood that the present application provides a semiconductor process monitoring method. By sputtering a metal on the surface of a semiconductor sample to form a thin film, and depositing a marking material in a target area to form a marking layer, the action space of the target process is covered. Subsequently, a glue sealing treatment is performed, and through a removal process to the marking layer, a target surface containing the target process effect is exposed. Finally, a scanning electron microscope is used for scanning to obtain an image that can be used to evaluate the target process effect. Through the setting of the marking layer, the unity of the target area during the removal process is ensured, and edge damage is avoided; the marking layer clarifies the removal end position, enabling the accurate exposure of the cross-section reflecting the target process effect, providing a reliable basis for process optimization. Compared with the traditional scanning electron microscope cross-section observation technology, this method can obtain key information more quickly and accurately, which helps to improve the yield and performance stability of semiconductor products.

[0007] In an alternative embodiment of the present application, depositing a marking material in a target area on the surface of the semiconductor sample to form a marking layer includes: using a focused ion beam technology to deposit a marking material in a target area on the surface of the semiconductor sample to form a marking layer. The focused ion beam technology is a high-precision micro-nano processing technology that uses a focused ion beam to perform precise deposition, etching, or modification on the material surface. In the present application, this technology is used to deposit a marking material in the target area of the semiconductor sample to form a marking layer. The advantage is that the focused ion beam technology can achieve extremely high processing precision, ensure that the marking layer precisely covers the target area, improve the accuracy and consistency of the subsequent removal process, thereby more effectively exposing the cross-section reflecting the target process effect, and enhancing the precision of process monitoring.

[0008] In an alternative embodiment of the present application, the marking material includes at least one of the following: platinum (Pt), carbon (C), tungsten (W), silicon dioxide (SiO2), silicon nitride (Si3N4). The selection criteria for the marking material are mainly based on its stability, conductivity, chemical inertness, and compatibility with the semiconductor sample in the semiconductor process.

[0009] In an alternative embodiment of the present application, the metal material includes at least one of the following: gold (Au), platinum (Pt), copper (Cu), aluminum (Al). It can be understood that gold, platinum, copper, aluminum, etc. all have good ductility, which means they can be easily processed into thin films and uniformly cover the surface of the semiconductor sample.

[0010] In an alternative embodiment of the present application, the removal process includes: grinding and polishing the encapsulated composite using a metallographic grinder. It can be understood that compared with the traditional crystal cracking method, the removal process of grinding and polishing the encapsulated composite using a metallographic grinder in the present application has significant advantages. The traditional crystal cracking method is prone to causing significant mechanical damage to the sample during operation, resulting in cracking at the edge of the sample or damage to the internal structure. This not only increases the loss of the sample but also may affect the accuracy of subsequent process monitoring. The grinding and polishing method is more gentle. By precisely controlling the grinding force and polishing parameters, it can gradually remove the encapsulated composite to the marking layer, expose the target surface, and cause less damage to the sample.

[0011] In an alternative embodiment of the present application, the removal process may also include: soaking and corroding the encapsulated composite with the corrosion solution. The corrosion depth can be estimated based on the position of the marking layer, and then the material ratio and soaking duration of the corrosion solution can be determined according to the corrosion depth. It can be understood that for a target process such as ion implantation, the ion implantation material often reacts more strongly with a specific corrosion solution. Solution corrosion can utilize this characteristic to perform targeted corrosion on the ion implantation area, precisely expose the target surface, and meet the requirements of process monitoring for observing specific areas.

[0012] In an alternative embodiment of the present application, the removal process may also include: using a combined method of grinding and polishing and solution corrosion for treatment, which will not be elaborated here.

[0013] In an alternative embodiment of the present application, the encapsulation process includes: placing the semiconductor sample into a mold and encapsulating the mold with an encapsulating adhesive, and obtaining an encapsulated composite after curing at room temperature. It can be understood that the preparation of the encapsulated composite provides physical support for the semiconductor sample on the one hand, preventing the sample from shifting or deforming during removal processes such as grinding and corrosion, and ensuring the processing accuracy. On the other hand, the encapsulated composite can isolate the sample from the external environment, reduce the contamination of the sample by impurities such as dust and moisture, maintain the initial state of the sample, provide clear and accurate sample surface information for subsequent process monitoring links such as electron microscope observation, and ensure the reliability of the process monitoring results.

[0014] In an alternative embodiment of the present application, the marking layer covers the orthographic projection area of the action space on the surface of the semiconductor sample. It can be understood that this embodiment is suitable for situations where the action space of the target process is small. Covering the orthographic projection area of the action space on the surface of the semiconductor sample with the marking layer can accurately identify the action position of the target process.

[0015] In an alternative embodiment of the present application, the orthographic projection area of a single said action space on the surface of the semiconductor sample includes at least two strip-shaped marking layers, and the extending directions of the at least two strip-shaped marking layers in a single said semiconductor sample are parallel to each other. It can be understood that this embodiment is suitable for the case where the target process action space is relatively large. By providing at least two strip-shaped marking layers with parallel extending directions in the orthographic projection area of a single action space, it brings a lot of convenience to subsequent process monitoring.

[0016] In an alternative embodiment of the present application, the providing of the semiconductor sample after being subjected to the target process includes: providing at least two semiconductor samples after being subjected to the same batch of target processes. In addition, the above method further includes: when depositing and forming the strip-shaped marking layer, the extending directions of the strip-shaped marking layers in each said semiconductor sample are different. It can be understood that by providing at least two semiconductor samples of the same batch and depositing and forming strip-shaped marking layers with different extending directions in each sample, the sample after being subjected to the target process can be removed from different directions, thereby exposing the target surface at different angles. The strip-shaped marking layers with different extending directions guide the removal process to proceed along a specific path, enabling the internal structure of the sample to be presented from different perspectives.

[0017] In an alternative embodiment of the present application, the scanning of the target surface by using a scanning electron microscope includes: using a scanning electron microscope to scan the area to be observed covered by the marking layer in the target surface. It can be understood that using a scanning electron microscope to only scan the area to be observed covered by the marking layer in the target surface avoids unnecessary full scanning. The marking layer accurately defines the key observation range, and the area to be observed is often the core part where the target process acts or the part prone to problems. By concentrating on scanning these areas, key information can be quickly obtained, reducing the scanning time and data volume.

[0018] In an alternative embodiment of the present application, the semiconductor sample includes at least one of the following: a dummy wafer for target process, a test wafer, a product wafer, a bare die, and a packaged module.

[0019] It can be understood that in the step of removing part of the sample to expose the target surface of the sample, different from the traditional method of cleaving the crystal which is likely to cause greater mechanical damage to the sample, the removal treatment methods such as grinding and polishing or solution corrosion used in the present application are more gentle. They can gradually remove the encapsulation composite to the marking layer to expose the target surface, with less loss to the sample. Therefore, the method provided by the present application has a wider application range. It can not only perform target process monitoring on the dummy wafer for target process, test wafer, product wafer, and packaged module, but also perform target process monitoring on the smaller bare die, thereby reducing the damage range to semiconductor products.

[0020] To make the above objects, features, and advantages of the present application more apparent and understandable, the following provides alternative embodiments in conjunction with the accompanying drawings and detailed descriptions are as follows. Description of the Drawings

[0021] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of sputtering a metal thin film and depositing a marking layer on a vertical cavity surface emitting laser die provided by the present application; Figure 2 It is a schematic diagram of the orthographic projection area of the marking layer covering the action space on the surface of the semiconductor sample provided by the present application; Figure 3 It is a schematic diagram of a single action space including three strip marking layers in the orthographic projection area on the surface of the semiconductor sample provided by the present application; Figure 4 It is according to Figure 3 A schematic diagram of the target surface after the removal process of the three strip marking layers shown; Figure 5 It is a schematic diagram of the strip marking layer of another semiconductor sample provided by the present application. Detailed Embodiments

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0024] The present application provides a semiconductor process monitoring method, which includes the following steps: Provide a semiconductor sample after being processed by a target process; Sputter a metal material on the surface of the semiconductor sample to form a metal thin film; Deposit a marking material on the target area on the surface of the semiconductor sample with the metal thin film formed to form a marking layer, and the target area at least partially covers the action space of the target process; Perform a potting process on the semiconductor sample to form a potted composite; Perform a removal process on the potted composite along a direction parallel to the surface to the marking layer, so that the potted composite exposes a target surface including at least a part of the action space; The target surface is scanned using a scanning electron microscope to obtain a scanning electron microscope image.

[0025] Regarding the step of "providing a semiconductor sample after being processed by a target process".

[0026] The above-mentioned target process may include semiconductor processing processes such as a lithography process, an etching process, a thin film deposition process, etc. In an alternative embodiment of the present application, the semiconductor sample includes at least one of the following: a dummy wafer processed by the target process, a test wafer, a product wafer, a bare die, and a packaged module.

[0027] Regarding the step of "sputtering a metal material on the surface of the semiconductor sample to form a metal thin film".

[0028] This operation plays an important role in semiconductor process monitoring. First of all, sputtering the metal thin film can ensure the consistency of the surface material of the sample. Since the surface of the semiconductor sample may contain preparation areas of various different materials, these areas may have inconsistent removal degrees due to material differences during subsequent removal processes such as grinding or solution etching, thereby damaging the integrity of the sample edge. The sputtering of the metal thin film can cover these areas of different materials to form a uniform and continuous thin film, thus ensuring the consistency of the sample surface during the removal process and avoiding edge damage. Secondly, the introduction of the metal thin film significantly improves the conductivity of the sample. During scanning electron microscope observation, the electron beam needs to penetrate the sample to obtain internal information. However, semiconductor materials themselves have poor conductivity, and the electron beam is prone to energy loss and scattering due to resistance during the penetration process, affecting the image quality. The sputtering of the metal thin film provides a thin film with good conductivity on the surface of the sample, which helps the electron beam penetrate the sample more efficiently, reducing energy loss and scattering, and thus obtaining a clearer and more accurate image. Moreover, the metal thin film can also effectively reduce the accumulation of charges on the surface of the sample. During the scanning electron microscope observation process, the interaction between the electron beam and the sample surface will generate charge accumulation. If the charge accumulation is excessive, it will cause image distortion and resolution reduction. The metal thin film has good conductivity and can quickly conduct the accumulated charges, preventing excessive charges from interfering with the observation results, thereby ensuring the stability and reliability of the electron microscope observation. In summary, the operation of sputtering a metal thin film on the surface of the semiconductor sample not only ensures the consistency of the surface material of the sample, but also improves the conductivity of the sample, reduces charge accumulation, provides strong support for scanning electron microscope observation, and also lays a solid foundation for the accuracy of semiconductor process monitoring.

[0029] In an alternative embodiment of the present application, the metal material includes at least one of the following: gold (Au), platinum (Pt), copper (Cu), and aluminum (Al).

[0030] It is understandable that gold, platinum, copper, aluminum, etc. all have good ductility, which means they can be easily processed into thin films and evenly cover the surface of semiconductor samples. This property is crucial for ensuring the integrity and consistency of metal thin films, helping to reduce errors caused by film rupture or non-uniformity during subsequent processing. In addition to ductility, these metal materials also have good electrical conductivity, which can significantly improve the electrical conductivity of semiconductor samples, thereby optimizing the observation effect of the scanning electron microscope. Moreover, these metals exhibit high chemical stability in the semiconductor manufacturing environment, are not easily reactive with semiconductor samples, and ensure the stability and reliability of metal thin films during sputtering and subsequent processing. Gold, platinum, copper, and aluminum have good compatibility with semiconductor samples, can form a good bond with the sample surface during sputtering, and will not damage the sample, meeting the precise requirements of semiconductor process monitoring.

[0031] For example, Figure 1 The figure shows a schematic diagram of sputtering a metal thin film and depositing a marking layer on a vertical cavity surface emitting laser (VCSEL) die. The VCSEL die includes a substrate layer 11, a bottom mirror structure 12 (such as an N-type doped semiconductor layer), an active layer 13, and a top mirror structure 14 (such as a P-type doped semiconductor layer) stacked in sequence. A bottom metal 15 is provided on the surface of the substrate layer 11 facing away from the bottom mirror structure 12. When carriers in the P region and N region are injected into the active layer 13 under the action of an external circuit, electrons and holes recombine in the active layer 13, releasing energy and generating photons. Since the cavity of the VCSEL is vertical, the photons are reflected multiple times between the mirrors composed of two doped semiconductor layers and are stimulated to amplify, forming coherent light. Finally, these photons vertically emit from the top of the chip, forming a laser beam. The metal thin film is sputtered on the surface of the VCSEL die sample. It can be seen that there are different materials on the upper surface of the chip cross-section, and the upper surface of the chip cracks during side grinding. Essentially, it is the failure of brittle materials under mechanical stress and thermal stress. The main functions of sputtering the metal thin film are as follows: Utilize the ultra-high ductility of the metal thin film to form a plastic buffer layer, absorb and disperse grinding stress, and prevent crack initiation and propagation. Utilize the excellent thermal conductivity of the metal thin film to quickly dissipate frictional heat and reduce thermal stress.

[0032] Regarding the step of "depositing a marking material on the target area on the surface of the semiconductor sample with the metal thin film formed, and the target area at least partially covers the action space of the target process".

[0033] It can be understood that during the semiconductor manufacturing process, when target processes such as ion implantation act on the sample surface, preparation regions containing different materials are often formed. Due to the differences in material properties of these regions, during subsequent removal processes such as grinding or solution etching, the degree of removal may be inconsistent, thereby damaging the integrity of the sample edge and affecting the accuracy of the process and the quality of the product. This solution cleverly solves this problem by depositing a marking material in the target region covering the space where the target process acts to form a marking layer. The presence of the marking layer ensures the consistency of the surface materials in the target region, enabling effective protection of the target region edge during grinding or solution etching, preventing it from being overly removed or damaged, and thus ensuring the uniformity of the removal process. In addition, the marking layer also serves as a clear indication of the removal end point, facilitating accurate judgment of the removal degree, and precisely exposing the cross-section reflecting the target process effect through subsequent processing, providing a strong guarantee for process optimization and product quality control.

[0034] In an alternative embodiment of the present application, depositing a marking material on the target region on the surface of a semiconductor sample to form a marking layer includes: using a focused ion beam technique to deposit a marking material on the target region on the surface of the semiconductor sample to form a marking layer. The focused ion beam technique is a high-precision micro-nano processing technique that uses a focused ion beam to perform precise deposition, etching, or modification on the material surface. In the present application, this technique is used to deposit a marking material in the target region of the semiconductor sample to form a marking layer. The advantage is that the focused ion beam technique can achieve extremely high processing precision, ensuring that the marking layer precisely covers the target region, improving the accuracy and consistency of subsequent removal processes, and thus more effectively exposing the cross-section reflecting the target process effect and enhancing the precision of process monitoring.

[0035] In an alternative embodiment of the present application, the marking material includes at least one of the following: platinum (Pt), carbon (C), tungsten (W), silicon dioxide (SiO2), and silicon nitride (Si3N4). The selection criteria for the marking material are mainly based on its stability, conductivity, chemical inertness, and compatibility with the semiconductor sample in the semiconductor process. The selection of platinum, carbon, tungsten, silicon dioxide, and silicon nitride is because they have high chemical stability and thermal stability in the semiconductor manufacturing environment, are not easily reactive with the semiconductor sample; at the same time, they have good conductivity or insulation, which can meet different process requirements; in addition, these materials have good compatibility with the semiconductor sample, ensuring that they will not damage the sample during deposition and subsequent processing, thus guaranteeing the quality of the marking layer and the smooth progress of subsequent processes.

[0036] For example, continue to refer to Figure 1, there is a working space for the target process shown by the red frame in the vertical-cavity surface-emitting laser die, that is, the target ion implantation region, and the marking layer is deposited and covered on the target ion implantation region. On the one hand, it can protect the upper surface of the chip cross-section and prevent cracking; on the other hand, it serves as a mark to accurately locate the area to be observed. The deposition method of the marking layer can be completed by the focused ion beam technology, with high precision, and can be adjusted simultaneously in terms of direction / size.

[0037] Regarding the step of "encapsulating the semiconductor sample to form an encapsulated composite".

[0038] In an alternative embodiment of the present application, the encapsulation process includes: placing the semiconductor sample in a mold and encapsulating the mold with an encapsulating adhesive, and obtaining the encapsulated composite after curing at room temperature. It can be understood that the preparation of the encapsulated composite provides physical support for the semiconductor sample on the one hand, preventing the sample from shifting or deforming during the removal processes such as grinding and etching, and ensuring the processing accuracy. On the other hand, the encapsulated composite can isolate the sample from the external environment, reduce the contamination of the sample by impurities such as dust and moisture, maintain the initial state of the sample, provide clear and accurate sample surface information for subsequent process monitoring links such as electron microscopy observation, and ensure the reliability of the process monitoring results.

[0039] Optionally, the encapsulating adhesive can be an AB glue composed of materials such as epoxy resin, acrylate, and polyurethane. When in use, the two components A and B need to be mixed evenly in a certain proportion and then cured. This glue has excellent bonding properties, chemical resistance, and high strength.

[0040] Regarding the step of "performing a removal process on the encapsulated composite along a direction parallel to the surface to the marking layer, so that the encapsulated composite exposes a target surface including at least part of the working space".

[0041] In an alternative embodiment of the present application, the removal process includes: grinding and polishing the encapsulant composite using a metallographic grinder. It can be understood that compared with the traditional crystal cleavage method, the removal process of grinding and polishing the encapsulant composite in the present application has significant advantages. The traditional crystal cleavage method is prone to causing significant mechanical damage to the sample during operation, resulting in cracks at the edges of the sample or damage to the internal structure. This not only increases the loss of the sample but also may affect the accuracy of subsequent process monitoring. The grinding and polishing method is more gentle. By precisely controlling the grinding force and polishing parameters, it can gradually remove the encapsulant composite to the marking layer, expose the target surface, and cause less damage to the sample. This processing method ensures the flatness and integrity of the sample surface, provides a more reliable sample basis for subsequent scanning electron microscope observation, and thus improves the accuracy and efficiency of process monitoring. Taking the ion implantation process as an example, in the subsequent scanning electron microscope, the non-implanted area and the implanted area will show a difference in brightness. The implanted area appears as a dark area under the scanning electron microscope parameters of 1kv 0.17nA secondary electron mode. In addition, of course, the color is also related to the material, and different materials have different shades of color. The target surface processed by the grinding method can show a difference in brightness in the subsequent scanning electron microscope image.

[0042] In an alternative embodiment of the present application, the removal process may also include: immersing and corroding the encapsulant composite with a corrosion solution. The corrosion depth can be estimated based on the position of the marking layer, and then the material ratio and immersion duration of the corrosion solution can be determined according to the corrosion depth. For example, the corrosion solution generally uses a solution with a ratio of ammonia water, hydrogen peroxide, and water of 1:1:10 and is immersed for about 10 - 30S. It can be understood that for the target process of ion implantation, the ion implantation area often accelerates the oxidation reaction due to the defects in the implanted area. Ammonia water preferentially etches the damaged area and will present a rougher morphology in the subsequent scanning electron microscope image. The implanted and non-implanted areas can also be distinguished by the surface roughness.

[0043] At the same time, the corrosion depth is estimated based on the position of the marking layer, and the immersion duration is determined accordingly, which can precisely control the degree of corrosion and avoid over-corrosion or under-corrosion. This precise control not only improves the accuracy of the removal process but also reduces the impact on non-target areas, ensures the integrity of other parts of the sample, and provides a reliable guarantee for subsequent process analysis and quality inspection.

[0044] In an alternative embodiment of the present application, the removal process may also include: using a combined method of grinding and polishing and solution corrosion for treatment, which will not be elaborated here.

[0045] In an alternative embodiment of the present application, the marked layer covers the orthographic projection area of the action space on the surface of the semiconductor sample. As Figure 1As shown, on the first semiconductor sample 100, region 101 is the orthographic projection region of the ion implantation process on the sample surface, and the first marking layer 102 is deposited and covered on this region 101.

[0046] It can be understood that this embodiment is suitable for the situation where the action space of the target process is small. Covering the orthographic projection region of the action space on the semiconductor sample surface with the marking layer can accurately identify the action position of the target process. The marking layer is like a "positioning label", providing a clear guide for subsequent scanning electron microscope operations. The scanning electron microscope can quickly and accurately locate the target surface based on the marking layer, avoiding blind scanning and saving operation time. At the same time, accurate positioning can reduce the image error caused by the deviation of the scanning range, ensure that the information of the target surface obtained is accurate and reliable, provide strong support for accurately evaluating the effect of the target process, and improve the efficiency and quality of process monitoring.

[0047] In an alternative embodiment of the present application, at least two strip-shaped marking layers are included in the orthographic projection region of a single action space on the semiconductor sample surface, and the extension directions of at least two strip-shaped marking layers in a single semiconductor sample are parallel to each other. As Figure 3 shown, on the second semiconductor sample 200, region 201 is the orthographic projection region of the ion implantation process on the sample surface. Since the area of region 201 is large, three strip-shaped marking layers, namely the first marking layer 202, the second marking layer 203, and the third marking layer 204, are deposited on region 201. As Figure 4 shown are schematic diagrams of the sample target surfaces corresponding to the three strip-shaped marking layers respectively.

[0048] It can be understood that this embodiment is suitable for the situation where the action space of the target process is large. Setting at least two strip-shaped marking layers with parallel extension directions in the orthographic projection region of a single action space brings many conveniences to subsequent process monitoring. The multiple strip-shaped marking layers are like "multiple guiding lines", and subsequent removal processes such as grinding or solution etching can be carried out along each marking layer, so as to expose the sample target surfaces at different positions. After the scanning electron microscope images these target surfaces, more abundant information can be obtained. Different target surfaces may show different effects of the target process due to position differences, such as the uniformity of the process, edge effects, etc. By comprehensively analyzing these images, the performance of the target process in the entire action space can be comprehensively understood, and problems that are difficult to detect by observing a single target surface can be found, such as local process defects, parameter fluctuations, etc. This provides a more accurate direction for process optimization, helps improve the quality and performance of semiconductor products, and enhances the controllability and stability of the production process.

[0049] In an alternative embodiment of the present application, semiconductor samples processed by the target process are provided, including: providing at least two semiconductor samples processed by the same batch of target processes. In addition, the above method further includes: when depositing and forming the strip-shaped marking layer, the extension directions of the strip-shaped marking layers in each semiconductor sample are different. AsFigure 5 The third semiconductor sample 300 processed by the target process in the same batch as the second semiconductor sample 200 is provided. On the third semiconductor sample 300, the region 301 is the orthographic projection region of the ion implantation process on the sample surface. Three strip marking layers, namely the fourth marking layer 302, the fifth marking layer 303, and the sixth marking layer 304, are deposited on the region 301. It can be seen that the extension direction of the strip marking layer on the third semiconductor sample 300 is different from that of the strip marking layer on the second semiconductor sample 200.

[0050] It can be understood that providing at least two semiconductor samples in the same batch and depositing strip marking layers with different extension directions in each sample can perform removal processing on the samples processed by the target process from different directions, thereby exposing the target surface at different angles. The strip marking layers with different extension directions guide the removal processing along specific paths, presenting the internal structure of the sample from different perspectives. When observing with a scanning electron microscope, the target surface at different angles can provide richer information. For example, the differences in the effects of the target process in different directions can be observed, and defects or abnormalities that are difficult to detect by traditional single-direction observation can be found. This helps to comprehensively evaluate the uniformity, consistency, and potential problems that may exist in the target process, providing a more accurate basis for process optimization. By comprehensively analyzing the scanning electron microscope images at different angles, it is more conducive to a deeper understanding of the essence of the target process, improving the process quality control level, and ensuring the performance and reliability of semiconductor products.

[0051] Regarding the step of "scanning the target surface with a scanning electron microscope to obtain a scanning electron microscope image".

[0052] It can be understood that in semiconductor manufacturing, target processes such as the implantation process will have subtle and crucial effects on the surface and internal structure of the sample, which are difficult to detect by the naked eye and other ordinary detection means. The scanning electron microscope has high resolution and can clearly present the microscopic structure of the sample. Obtaining its image can directly observe the details after the process treatment, providing a direct basis for evaluating the process effect. Taking the implantation process as an example, first observe the interface between the implanted region and the non-implanted region. A clear interface indicates good control of the implantation depth; if the interface is blurred, there may be over-implantation or under-implantation. Secondly, check the crystal structure of the implanted region. If defects such as lattice distortion and dislocation appear, it indicates that the implantation process has damaged the crystal structure. In addition, analyze the impurity distribution. Determine whether the impurities are evenly diffused by the element distribution characteristics in the image. If there is impurity agglomeration or uneven distribution, it will affect the device performance. By synthesizing these image information, the effects of target processes such as the implantation process can be comprehensively and accurately evaluated.

[0053] In an alternative embodiment of the present application, scanning the target surface using a scanning electron microscope includes: scanning the area to be observed covered by the marking layer in the target surface with the scanning electron microscope. It can be understood that only the area to be observed covered by the marking layer in the target surface is scanned using the scanning electron microscope, avoiding unnecessary full scanning. The marking layer accurately defines the key observation range, and the area to be observed is often the core of the target process or the part prone to problems. By focusing on scanning these areas, key information can be quickly obtained, reducing the scanning time and data volume. At the same time, there is no need to process a large amount of irrelevant data during subsequent analysis, and it is possible to focus more on the images of the key areas, quickly locate process features or defects, greatly shorten the analysis cycle, improve the overall process monitoring efficiency, and facilitate the efficient progress of semiconductor production.

[0054] In an alternative embodiment of the present application, the semiconductor sample includes at least one of the following: a dummy wafer processed by the target process, a test wafer, a product wafer, a bare die, and a packaged module.

[0055] It can be understood that in the step of removing part of the sample to expose the target surface of the sample, different from the traditional die splitting method that is likely to cause greater mechanical damage to the sample, the removal treatment methods such as grinding and polishing or solution etching used in the present application are more gentle, capable of gradually removing the encapsulation composite to the marking layer to expose the target surface, and causing less damage to the sample. Therefore, the method provided by the present application has a wider application range and can not only perform target process monitoring on the dummy wafers, test wafers, product wafers, and packaged modules processed by the target process, but also perform target process monitoring on the smaller bare dies, thereby reducing the damage range to semiconductor products.

[0056] In the various embodiments of the present disclosure, the expressions "first", "second", "the first", or "the second" used may modify various components regardless of order and / or importance, but these expressions do not limit the corresponding components. The above expressions are only configured for the purpose of distinguishing an element from other elements. For example, the first user device and the second user device represent different user devices, although both are user devices. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0057] When an element (e.g., a first element) is referred to as being “(operatively or communicatively) coupled” or “(operatively or communicatively) coupled to” or “connected to” another element (e.g., a second element), it should be understood that the one element is directly connected to the other element or the one element is indirectly connected to the other element via yet another element (e.g., a third element). Conversely, it is understood that when an element (e.g., a first element) is referred to as being “directly connected” or “directly coupled” to another element (a second element), no element (e.g., a third element) is inserted therebetween.

[0058] It should be noted that, in this document, the terms “comprising,” “including,” or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a series of elements includes not only those elements but also other elements not expressly listed, or elements that are inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the statement “comprising a...” does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or may have different meanings, and their specific meanings need to be determined based on their interpretations in the specific embodiments or further in combination with the context in the specific embodiments.

[0059] The above description is only an alternative embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

[0060] Depending on the context, the words “if,” “when” as used herein can be interpreted as “when” or “while” or “in response to determining” or “in response to detecting.” Similarly, depending on the context, the phrase “if determined” or “if detected (stated condition or event)” can be interpreted as “when determined” or “in response to determining” or “when detected (stated condition or event)” or “in response to detecting (stated condition or event).”

[0061] The above description is only an optional embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present application.

[0062] The above is only an optional embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor process monitoring method, characterized in that, Including: Providing a semiconductor sample after being processed by a target process; Sputtering a metal material on the surface of the semiconductor sample to form a metal thin film; Depositing a marking material on a target area on the surface of the semiconductor sample with the metal thin film formed thereon to form a marking layer, where the target area at least partially covers the action space of the target process; Performing a potting process on the semiconductor sample to form a potted composite; Performing a removal process on the potted composite along a direction parallel to the surface until the marking layer is reached, so that the potted composite exposes a target surface including at least a part of the action space; Scanning the target surface with a scanning electron microscope to obtain a scanning electron microscope image.

2. The semiconductor process monitoring method according to claim 1, wherein: The metal material includes at least one of the following: gold (Au), platinum (Pt), copper (Cu), aluminum (Al).

3. The semiconductor process monitoring method according to claim 1, wherein: The depositing a marking material on a target area on the surface of the semiconductor sample to form a marking layer includes: using a focused ion beam technique to deposit a marking material on a target area on the surface of the semiconductor sample to form a marking layer.

4. The semiconductor process monitoring method according to claim 2, wherein: The marking material includes at least one of the following: platinum (Pt), carbon (C), tungsten (W), silicon dioxide (SiO2), silicon nitride (Si3N4).

5. The semiconductor process monitoring method according to claim 1, wherein: The removal process includes at least one of the following: Polishing the potted composite with a metallographic grinder; Soaking and corroding the potted composite with the corrosion solution.

6. The semiconductor process monitoring method according to claim 5, wherein: The potting process includes: placing the semiconductor sample in a mold and encapsulating the mold with an encapsulating adhesive, and obtaining a potted composite after curing at room temperature.

7. The semiconductor process monitoring method according to any one of claims 1 to 6, wherein: The marking layer includes at least one of the following: The marking layer covers the orthographic projection area of the action space on the surface of the semiconductor sample; Within the orthographic projection area of a single action space on the surface of the semiconductor sample, there are at least two strip-shaped marking layers, and the extending directions of the at least two strip-shaped marking layers in a single semiconductor sample are parallel to each other.

8. The semiconductor process monitoring method according to claim 7, wherein: The providing a semiconductor sample after being processed by a target process includes: providing at least two semiconductor samples after being processed by the same batch of target processes; The method further includes: when depositing and forming the strip-shaped marking layer, the extending directions of the strip-shaped marking layers in each semiconductor sample are different.

9. The semiconductor process monitoring method according to any one of claims 1 to 6, wherein: The scanning the target surface with a scanning electron microscope includes: scanning a to-be-observed area covered by the marking layer on the target surface with a scanning electron microscope.

10. The semiconductor process monitoring method according to any one of claims 1 to 6, characterized in that the semiconductor sample includes at least one of the following: a dummy wafer processed by the target process, a test wafer, a product wafer, a bare die, and a packaged module.

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