Phase shift detection circuit, clock phase shift circuit, chip and electronic equipment

Abstract

The invention provides a phase shift detection circuit, a clock phase shift circuit, a chip and electronic equipment. The phase shift detection circuit comprises an energy storage circuit and a comparison circuit; when the adjusting period starts, the voltage of the first input end and the voltage of the second input end of the comparison circuit are the same, and the energy storage circuit controls the voltage of the first input end of the comparison circuit to rise or fall based on different logic states of the first control signal. Wherein the voltage increase rate and the voltage decrease rate of the first input end of the comparison circuit are the same, and the duration of the first control signal in the first logic state indicates the phase difference of the two clock signals; when the adjusting period is finished, the voltage of the first input end of the comparison circuit is compared with the voltage of the second input end of the comparison circuit, that is, the voltage of the first input end of the comparison circuit at the beginning of the adjusting period and the voltage of the first input end at the end of the adjusting period are compared, and the phase difference of the two clock signals is adjusted based on the two voltages. The phase difference of the two clock signals can be finally kept around 180 degrees.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and in particular, to a phase shift detection circuit, a clock phase shift circuit, a chip, and an electronic device. Background Art

[0002] In a multi-phase direct current-direct current (DC-DC) converter, when the phase difference between the output voltages of each DC-DC conversion circuit is 180°, the ripple of the output voltage of each DC-DC conversion circuit is the smallest and the anti-interference ability is the strongest.

[0003] The DC-DC conversion circuit adjusts the on-off time of its internal switch based on the received clock signal, thereby adjusting the output voltage. In a multi-phase DC-DC converter, the phase difference between the output voltages of multiple DC-DC conversion circuits is related to the phase difference between the clock signals of the multiple DC-DC conversion circuits. If the phase difference between the output voltages of multiple DC-DC conversion circuits is to be 180°, the phase difference that the clock signals of each DC-DC conversion circuit need to satisfy is 180°.

[0004] In the related art, the clock signal of one DC-DC conversion circuit can be used to generate the clock signal of another DC-DC conversion circuit; however, the phase difference between the two is not necessarily exactly 180°; if the phase difference between the clock signals input to each DC-DC conversion circuit in a multi-phase DC-DC converter does not satisfy 180°, the ripple of the output voltage of the DC-DC conversion circuit is relatively high, which is not conducive to use. Summary of the Invention

[0005] The present application provides a phase shift detection circuit, a clock phase shift circuit, a chip, and an electronic device. The energy storage circuit of the phase shift detection circuit controls the voltage at the first input end of the comparison circuit to increase or decrease based on the first control signal; at the end of the adjustment period, the voltage at the first input end of the comparison circuit of the phase shift detection circuit is compared with the voltage at the second input end, and the phase difference between the two clock signals is increased or decreased based on their magnitudes, so that the phase difference between the two clock signals can finally be maintained near 180°, thereby making the ripple of the output voltage of the voltage converter smaller.

[0006] In a first aspect, the present application provides a phase shift detection circuit, including an energy storage circuit and a comparison circuit; wherein, a first end of the energy storage circuit is configured to receive a first control signal, a second end of the energy storage circuit is electrically connected to a first input end of the comparison circuit, and a voltage of a second input end of the comparison circuit is configured to be the same as a voltage of the first input end of the comparison circuit at the beginning of each adjustment period; an output end of the comparison circuit is electrically connected to a phase shift oscillation circuit; the phase shift oscillation circuit is configured to output a first clock signal; the energy storage circuit is configured to control the voltage of the first input end of the comparison circuit to increase or decrease based on the first control signal within a first adjustment period; wherein, when the first control signal is in a first logic state, the voltage of the first input end of the comparison circuit increases; when the first control signal is in a second logic state, the voltage of the first input end of the comparison circuit decreases; a rate at which the voltage of the first input end of the comparison circuit increases is the same as a rate at which the voltage of the first input end of the comparison circuit decreases; a first phase difference of the first clock signal within the first adjustment period is determined based on a duration during which the first control signal is in the first logic state within the first adjustment period; the comparison circuit is configured to, at the end of the first adjustment period, adjust a duration during which the first clock signal of the phase shift oscillation circuit is in the first logic state within a second adjustment period based on a comparison result between the voltage of the first input end of the comparison circuit and the voltage of the second input end of the comparison circuit, so as to adjust a second phase difference between the second clock signal and the first clock signal within the second adjustment period; wherein, the second adjustment period is a next adjustment period of the first adjustment period; when the comparison result indicates that the voltage of the first input end of the comparison circuit is less than the voltage of the second input end of the comparison circuit, the duration during which the first clock signal is in the first logic state within the second adjustment period increases, such that the second phase difference is greater than the first phase difference; when the comparison result indicates that the voltage of the first input end of the comparison circuit is greater than or equal to the voltage of the second input end of the comparison circuit, the duration during which the first clock signal is in the first logic state within the second adjustment period decreases, such that the second phase difference is less than the first phase difference.

[0007] In some embodiments, the energy storage circuit includes a first transistor, a second transistor, and a first capacitor; wherein, the control terminals of the first transistor and the second transistor are both configured to receive a first control signal; a first terminal of the first transistor is electrically connected to a power supply, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and a first terminal of the second transistor is grounded; a first terminal of the first capacitor is electrically connected to the second terminal of the second transistor, and a second terminal of the first capacitor is electrically connected to the first terminal of the second transistor; when the first control signal is in a first logic state, the first transistor is in an on state, the second transistor is in an off state, and the power supply charges the first capacitor, so that the voltage at the first input terminal of the comparison circuit increases; when the first control signal is in a second logic state, the first transistor is in an off state, the second transistor is in an on state, and the first capacitor is in a discharging state, so that the voltage at the first input terminal of the comparison circuit decreases; wherein, the charging current and the discharging current of the first capacitor have the same current value.

[0008] In some embodiments, the energy storage circuit further includes a first current source and a second current source; wherein, a first terminal of the first transistor is electrically connected to a negative electrode of the first current source, and a positive electrode of the first current source is electrically connected to the power supply; a first terminal of the second transistor is connected to a positive electrode of the second current source, and a negative electrode of the second current source is grounded; the first current source is configured to control the charging current of the first capacitor; the second current source is configured to control the discharging current of the first capacitor.

[0009] In some embodiments, the comparison circuit includes a comparator and a first control sub-circuit; wherein, the inverting input terminal of the comparator is electrically connected to the first end of the first capacitor, and the non-inverting input terminal of the comparator is configured to have the same voltage as the voltage at the inverting input terminal of the comparator at the start of each adjustment period; the output terminal of the comparator is electrically connected to the first input terminal of the first control sub-circuit, and the output terminal of the first control sub-circuit is electrically connected to the phase shift oscillation circuit; wherein, the comparator is configured to generate a comparison signal based on the voltage at the first end of the first capacitor and the voltage at the non-inverting input terminal of the comparator, and send the comparison signal to the first control sub-circuit; the first control sub-circuit is configured to generate a second control signal based on the comparison signal at the end of the first adjustment period, and send the second control signal to the phase shift oscillation circuit; wherein, the second control signal is used to control the duration of the first clock signal of the phase shift oscillation circuit in the first logic state during the second adjustment period; wherein, when the comparison signal is in the second logic state, the second control signal is used to increase the duration of the first clock signal in the first logic state during the second adjustment period; when the comparison signal is in the first logic state, the second control signal is used to decrease the duration of the first clock signal in the first logic state during the second adjustment period.

[0010] In some embodiments, the comparison circuit further includes a first switch; wherein, the inverting input terminal of the comparator is electrically connected to the non-inverting input terminal of the comparator through the first switch; the first switch is configured to conduct at the start of each adjustment period, so that the voltage at the non-inverting input terminal of the comparator is the same as the voltage at the inverting input terminal of the comparator at the start of each adjustment period.

[0011] In some embodiments, the phase shift detection circuit further includes a first latch circuit; the first input terminal of the first latch circuit is configured to receive the second clock signal, the second input terminal of the first latch circuit is configured to receive the first clock signal, and the output terminal of the first latch circuit is electrically connected to the control terminals of the first transistor and the second transistor respectively; the first latch circuit is configured to generate the first control signal based on the first clock signal and the second clock signal, and input the first control signal to the control terminals of the first transistor and the second transistor; when the second clock signal changes from the first logic state to the second logic state, the first control signal changes from the second logic state to the first logic state; when the first clock signal changes from the first logic state to the second logic state, the first control signal changes from the first logic state to the second logic state.

[0012] In a second aspect, the present application provides a clock phase shift circuit, including the phase shift detection circuit and the phase shift oscillation circuit described in the first aspect; wherein, a first end of the energy storage circuit of the phase shift detection circuit is used to receive a first control signal, and a second end of the energy storage circuit is electrically connected to a first input end of the comparison circuit of the phase shift detection circuit; the voltage at a second input end of the comparison circuit is configured to be the same as the voltage at the first input end of the comparison circuit at the beginning of each adjustment period; an output end of the comparison circuit is electrically connected to a first input end of the phase shift oscillation circuit; the phase shift oscillation circuit is used to output a first clock signal; the energy storage circuit is used to control the voltage at the first input end of the comparison circuit to increase or decrease based on the first control signal within a first adjustment period; wherein, when the first control signal is in a first logic state, the voltage at the first input end of the comparison circuit increases; when the first control signal is in a second logic state, the voltage at the first input end of the comparison circuit decreases; the rate of increase of the voltage at the first input end of the comparison circuit is the same as the rate of decrease; the first phase difference of the first clock signal within the first adjustment period is determined based on the duration during which the first control signal is in the first logic state within the first adjustment period; the comparison circuit is used to, at the end of the first adjustment period, adjust the duration during which the first clock signal of the phase shift oscillation circuit is in the first logic state within a second adjustment period based on the comparison result between the voltage at the first input end of the comparison circuit and the voltage at the second input end of the comparison circuit, so as to adjust the second phase difference between the second clock signal and the first clock signal within the second adjustment period; wherein, the second adjustment period is the next adjustment period of the first adjustment period; when the comparison result indicates that the voltage at the first input end of the comparison circuit is less than the voltage at the second input end of the comparison circuit, the comparison circuit controls the phase shift oscillation circuit to increase the duration during which the first clock signal is in the first logic state within the second adjustment period, so that the second phase difference is greater than the first phase difference; when the comparison result indicates that the voltage at the first input end of the comparison circuit is greater than or equal to the voltage at the second input end of the comparison circuit, the comparison circuit controls the phase shift oscillation circuit to decrease the duration during which the first clock signal is in the second logic state within the second adjustment period, so that the second phase difference is less than the first phase difference.

[0013] In some embodiments, the phase shift oscillation circuit includes a third transistor, a fourth transistor, a fifth transistor, an adjustable resistance circuit, a second capacitor, and a second control sub-circuit; wherein, the second end of the third transistor is electrically connected to the power supply and the control end of the third transistor respectively; the first end of the third transistor is electrically connected to the first end of the adjustable resistance circuit, the second end of the adjustable circuit is grounded, and the control end of the adjustable resistance circuit is electrically connected to the output end of the comparison circuit; the control end of the fourth transistor is electrically connected to the control end of the third transistor, the second end of the fourth transistor is electrically connected to the power supply, the first end of the fourth transistor is electrically connected to the first end of the second capacitor, and the second end of the second capacitor is grounded; the second end of the fifth transistor is electrically connected to the first end of the first capacitor, and the first end of the fifth transistor is grounded; the first input end of the second control sub-circuit is electrically connected to the second end of the fourth transistor, and the second input end of the second control sub-circuit is used to receive the second clock signal; the first output end of the second control sub-circuit is electrically connected to the second input end of the first latch circuit of the phase shift detection circuit; the second output end of the second control sub-circuit is electrically connected to the control end of the fifth transistor; the second control sub-circuit is configured to generate the first clock signal and the third control signal based on the second clock signal and the voltage signal at the second end of the fourth transistor during the first adjustment period, input the first clock signal to the second input end of the first latch circuit, so that the first latch circuit generates the first control signal based on the first clock signal and the second clock signal; input the third control signal to the control end of the fifth transistor, and control the duration of the first clock signal in the first logic state based on the third control signal; wherein, when the second clock signal changes from the first logic state to the second logic state, the third control signal changes from the second logic state to the first logic state, the fifth transistor is in the off state, the power supply charges the second capacitor, and when the voltage at the first end of the second capacitor is greater than the voltage at the first end of the adjustable resistance circuit, the first clock signal changes from the first logic state to the second logic state; the comparison circuit is configured to adjust the resistance value of the adjustable resistance circuit based on the comparison result of the voltage at the first input end and the voltage at the second input end of the comparison circuit at the end of the first adjustment period, so as to adjust the duration of the first clock signal in the second adjustment period in the first logic state; wherein, the resistance value of the adjustable resistance circuit is positively correlated with the duration of the first clock signal in the second adjustment period in the first logic state.

[0014] In some embodiments, in each adjustment period, the adjustment step of the resistance value of the adjustable resistance circuit is the same.

[0015] In some embodiments, the phase shift oscillation circuit further includes a third current source and a fourth current source; wherein, the positive electrode of the third current source is electrically connected to the power supply, and the negative electrode of the third current source is electrically connected to the second end of the third transistor; the positive electrode of the fourth current source is electrically connected to the power supply, and the negative electrode of the fourth current source is electrically connected to the second end of the fourth transistor; the third current source is configured to control the current flowing through the adjustable resistor circuit; the fourth current source is configured to control the charging current of the second capacitor; wherein, the current flowing through the adjustable resistor circuit is the same as the charging current of the second capacitor.

[0016] In some embodiments, the second control sub-circuit includes a fifth current source, a sixth transistor, a second inverter, a second latch circuit, and a third inverter; wherein, the positive electrode of the fifth current source is electrically connected to the power supply, the negative electrode of the fifth current source is electrically connected to the second end of the sixth transistor, the second end of the sixth transistor is connected to the input end of the second inverter, the first end of the sixth transistor is grounded, and the control end of the sixth transistor is electrically connected to the second end of the fourth transistor; the output end of the second inverter is electrically connected to the second input end of the second latch circuit and the second input end of the first latch circuit respectively, and the first input end of the second latch circuit is configured to receive the second clock signal; the output end of the second latch circuit is electrically connected to the input end of the third inverter, and the output end of the third inverter is electrically connected to the control end of the fifth transistor; the second inverter is configured to input the first clock signal to the second input end of the second latch circuit based on the voltage signal at the second end of the fourth transistor; the second latch circuit and the third inverter are configured to generate the third control signal based on the second clock signal and the first clock signal; when the third control signal is in the first logic state and the voltage at the first end of the first capacitor is greater than the voltage at the first end of the adjustable resistor circuit, the sixth transistor is in the conducting state, the voltage signal at the second end of the sixth transistor is in the first logic state, and the first clock signal output by the second inverter changes from the first logic state to the second logic state.

[0017] In some embodiments, the second control sub-circuit further includes a seventh transistor; wherein, the first end of the seventh transistor is electrically connected to the positive electrode of the fifth current source, and the second end of the seventh transistor is electrically connected to the second end of the sixth transistor; when the first clock signal changes from the first logic state to the second logic state, the voltage signal at the output end of the second latch circuit changes from the second logic state to the first logic state, such that the voltage signal at the second end of the seventh transistor changes from the first logic state to the second logic state, and the first clock signal output by the second inverter changes from the second logic state to the first logic state.

[0018] In a third aspect, the present application provides a voltage converter, including a first DC-DC conversion circuit, a second DC-DC conversion circuit, and the clock phase shift circuit described in the second aspect; wherein, the phase shift detection circuit of the clock phase shift circuit is configured to adjust a first clock signal output by the phase shift oscillation circuit of the clock phase shift circuit, so that the phase difference between the first clock signal and the second clock signal satisfies 180°, and input the first clock signal into the first DC-DC conversion circuit; the first DC-DC conversion circuit is configured to perform voltage conversion on the input voltage of the first DC-DC conversion circuit based on the first clock signal; the second DC-DC conversion circuit is configured to perform voltage conversion on the input voltage of the second DC-DC conversion circuit based on the second clock signal.

[0019] In a fourth aspect, the present application provides a chip, including the phase shift detection circuit described in the first aspect and any embodiment of the first aspect, or, the clock phase shift circuit described in the second aspect and any embodiment of the second aspect, or, the voltage converter described in the third aspect.

[0020] In a fifth aspect, the present application provides an electronic device, including the chip described in the fourth aspect.

[0021] The present application provides a phase shift detection circuit, a clock phase shift circuit, a chip, and an electronic device; wherein, the phase shift detection circuit includes an energy storage circuit and a comparison circuit; at the start of a first adjustment period, the voltages at the first input terminal and the second input terminal of the comparison circuit are the same, and within the first adjustment period, the energy storage circuit controls the voltage at the first input terminal of the comparison circuit to increase or decrease based on different logic states of a first control signal; wherein, the duration of the first control signal in the first logic state indicates the phase difference between the second clock signal and the first clock signal; the rates of increase and decrease of the voltage at the first input terminal of the comparison circuit are the same; the comparison circuit increases or decreases the phase difference between two clock signals in a second adjustment period based on the magnitude of the voltage at the first input terminal and the voltage at the second input terminal at the end of the first adjustment period, so that the phase difference between the second clock signal and the first clock signal finally remains near 180°, thereby making the output voltage ripple of the voltage converter smaller. Description of the Drawings

[0022] Figure 1 It is a schematic structural diagram of the phase shift detection circuit provided by an embodiment of the present application;

[0023] Figure 2 It is a working timing diagram of the phase shift detection circuit provided by an embodiment of the present application;

[0024] Figure 3 It is a schematic structural diagram of the phase shift detection circuit provided by an embodiment of the present application;

[0025] Figure 4 This is a schematic structural diagram of the phase shift detection circuit provided by the embodiment of the present application;

[0026] Figure 5 This is a schematic structural diagram of the phase shift detection circuit provided by the embodiment of the present application;

[0027] Figure 6 This is a schematic structural diagram of the clock phase shift circuit provided by the embodiment of the present application;

[0028] Figure 7 This is a schematic structural diagram of the clock phase shift circuit provided by the embodiment of the present application;

[0029] Figure 8 This is a schematic structural diagram of the voltage converter provided by the embodiment of the present application. Detailed implementation manners

[0030] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a alone, b alone, or c alone can represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0031] The orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0032] The terms "connected" and "coupled" should be understood in a broad sense. For example, the "connection" or "coupling" of a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or it can be indirectly connected through at least one intermediate component, as long as the circuit is electrically connected. It can also be the internal connection of two components; the signal connection can be through a circuit for signal connection, or it can also refer to signal connection through a media medium, such as radio waves. For those of ordinary skill in the art, the specific meaning of the above terms in this application can be understood according to the specific situation. The DC-DC conversion circuit is a circuit that converts the voltage of a certain DC power supply into different voltage values. There is a phase difference between the input voltage and the output voltage of the DC-DC conversion circuit. Multiple DC-DC conversion circuits with different phase differences are connected in parallel to form a multi-phase DC-DC converter. In a multi-phase DC-DC converter, when the phase difference between the output voltages of each DC-DC conversion circuit is 180°, the ripple of the output voltage of each DC-DC conversion circuit is the smallest and the anti-interference ability is the strongest.

[0033] The DC-DC conversion circuit adjusts the on and off time of its internal switch based on the received clock signal, thereby adjusting the output voltage. In a multi-phase DC-DC converter, the phase difference between the output voltages of multiple DC-DC conversion circuits is related to the phase difference of the clock signals of multiple DC-DC conversion circuits. If the phase difference between the output voltages of multiple DC-DC conversion circuits is to be 180°, the phase difference that the clock signals of each DC-DC conversion circuit need to satisfy is 180°.

[0034] In the prior art, the clock signal of another DC-DC conversion circuit can be generated based on the clock signal of one DC-DC conversion circuit; however, the phase difference between the two is not necessarily exactly 180°; if the phase difference between the clock signals of each DC-DC conversion circuit in a multi-phase DC-DC converter is significantly different from 180°, its output ripple is relatively high, which is not conducive to use.

[0035] Based on this, the present application provides a phase shift detection circuit, including an energy storage circuit and a comparison circuit; the energy storage circuit controls the voltage at the first input end of the comparison circuit to increase or decrease based on a first control signal; at the end of the adjustment period, the voltage at the first input end of the comparison circuit is compared with the voltage at the second input end, and based on the magnitude relationship between the two, the phase difference between the two clock signals is increased or decreased, so that the phase difference between the two clock signals can finally be maintained near 180°.

[0036] Next, through Figure 1 exemplarily illustrate the structure of the phase shift detection circuit.

[0037] Figure 1 is a schematic structural diagram of the phase shift detection circuit 10 provided by an embodiment of the present application; asFigure 1 As shown, the phase shift detection circuit 10 includes an energy storage circuit 11 and a comparison circuit 12; wherein, the first end of the energy storage circuit 11 is used to receive a first control signal, and the second end of the energy storage circuit 11 is electrically connected to the first input end of the comparison circuit 12. The voltage at the second input end of the comparison circuit 12 is configured to be the same as the voltage at the first input end of the comparison circuit 12 at the beginning of each adjustment period; the output end of the comparison circuit 12 is electrically connected to the phase shift oscillation circuit 20, and the phase shift oscillation circuit 20 is used to output a first clock signal. Specifically, the phase shift oscillation circuit 20 generates the first clock signal based on a second clock signal.

[0038] The phase shift detection circuit 10 and the phase shift oscillation circuit 20 constitute a clock phase shift circuit 30.

[0039] In this application, the adjustment period can be the same as the signal period of the first control signal, or the same as the signal period of the second clock signal.

[0040] In Figure 1 it, the first control signal is represented by V_CTRL.

[0041] The energy storage circuit 11 is used to control the voltage at the first input end of the comparison circuit 12 to rise or fall based on the first control signal within the first adjustment period.

[0042] Wherein, the first adjustment period can be any signal period of the first control signal, or any signal period of the second clock signal. Exemplarily, the first adjustment period is the current adjustment period.

[0043] Wherein, at the beginning of an adjustment period, the first control signal changes from a second logic state to a first logic state, and after remaining in the first logic state for a period of time, it changes back to the second logic state; when the next adjustment period arrives, the first control signal changes from the second logic state to the first logic state again. Wherein, the duration that the first control signal remains in the first logic state indicates the phase difference between the second clock signal and the first clock signal in this adjustment period.

[0044] If within an adjustment period, the first control signal is in the first logic state and there is no second logic state, then the phase difference between the second clock signal and the first clock signal is the largest, which is 2π, corresponding to 360°. If the first control signal is in the second logic state and there is no first logic state, then the phase difference between the second clock signal and the first clock signal is the smallest, which is 0. If the duration that the first control signal is in the first logic state is the same as the duration that the first control signal is in the second logic state, then the phase difference between the second clock signal and the first clock signal is the center of [0, 2π], and the phase difference is π, corresponding to 180°.

[0045] At the start of an adjustment period, the second clock signal changes from a first logic state to a second logic state, remains in the second logic state for a short time, and then changes back to the first logic state; when the next adjustment period arrives, the second clock signal changes from the first logic state to the second logic state again.

[0046] In some embodiments, the first logic state and the second logic state are not limited. The first logic state can be a low level or a high level, and the second logic state can be a high level and a low level; the first logic state is different from the second logic state.

[0047] If the first logic state is a low level, then the second logic state is a high level; or, if the first logic state is a high level, then the second logic state is a low level.

[0048] In this application, an example is given with the first logic state being a low level state and the second logic state being a high level state.

[0049] During the first adjustment period, when the first control signal is in the first logic state, the voltage at the first input terminal of the comparison circuit 12 increases; when the first control signal is in the second logic state, the voltage at the first input terminal of the comparison circuit 12 decreases.

[0050] Specifically, when the first control signal is in the first logic state, the energy storage circuit 11 is in a charging state, and the voltage at the second terminal of the energy storage circuit 11 increases, causing the voltage at the first input terminal of the comparison circuit 12 to increase.

[0051] When the first control signal is in the second logic state, the energy storage circuit 11 is in a discharging state, and the voltage at the second terminal of the energy storage circuit 11 increases, causing the voltage at the first input terminal of the comparison circuit 12 to increase.

[0052] Among them, during the duration of the first logic state, the voltage at the first input terminal of the comparison circuit 12 continuously rises until the first control signal changes from the first logic state to the second logic state. The first phase difference of the first clock signal in the first adjustment period is determined based on the duration of the first control signal being in the first logic state within the first adjustment period.

[0053] Specifically, the first phase difference = 2π * (the duration of the first control signal being in the first logic state within the first adjustment period) / (the duration of the first adjustment period).

[0054] During the duration of the second logic state, the voltage at the first input terminal of the comparison circuit 12 continuously decreases until the first control signal changes from the second logic state back to the first logic state again.

[0055] Among them, the rate of increase of the voltage at the first input terminal of the comparison circuit 12 is the same as the rate of decrease of the voltage at the first input terminal of the comparison circuit 12.

[0056] A comparison circuit 12, configured to, at the end of a first adjustment period, adjust the duration of the first clock signal of the phase-shift oscillation circuit 20 in a first logic state during a second adjustment period based on the comparison result of the voltage at the first input terminal of the comparison circuit 12 and the voltage at the second input terminal of the comparison circuit 12, thereby adjusting the second phase difference between the second clock signal and the first clock signal during the second adjustment period;

[0057] Wherein, the second adjustment period is the next adjustment period after the first adjustment period.

[0058] When the duration of the first clock signal in the first logic state during the second adjustment period increases, so that the second phase difference is greater than the first phase difference; when the comparison result indicates that the voltage at the first input terminal of the comparison circuit 12 is greater than the voltage at the second input terminal of the comparison circuit 12, the duration of the first clock signal in the first logic state during the second adjustment period decreases, so that the second phase difference is less than the first phase difference.

[0059] It can be understood that the phase difference between the second clock signal and the first clock signal can be used to represent the duration between the moment when the second clock signal changes from the first logic state to the second logic state and the moment when the first clock signal changes from the first logic state to the second logic state within an adjustment period. Therefore, when the second clock signal remains unchanged, by increasing or decreasing the duration of the first clock signal in the first logic state, the moment when the first clock signal changes from the first logic state to the second logic state can be postponed or advanced, thereby increasing or decreasing the phase difference between the two.

[0060] The increase or decrease in the duration of the first clock signal in the first logic state during the second adjustment period means that the duration of the first clock signal in the first logic state during the second adjustment period increases or decreases based on the duration of the first clock signal in the first logic state during the first adjustment period.

[0061] In this application, after the phase difference between the first control signal and the second control signal changes, the duration of the first control signal in the first logic state is also updated as the phase difference changes.

[0062] In this application, the first adjustment period can be the current adjustment period. When the next adjustment period arrives, the next adjustment period is updated as the first adjustment period, and the comparison circuit 12 and the energy storage circuit 11 continue to adjust the phase difference of the second clock signal during the first adjustment period.

[0063] Next, through Figure 2 Examples are used to illustrate the adjustment process of the phase difference.

[0064] Figure 2 This is the working timing diagram of the phase-shift detection circuit 10 provided by the embodiment of the present application.

[0065] As Figure 2 shown, the second clock signal is CLK_A, which remains unchanged in each adjustment period. The first clock signal corresponding to the i-th adjustment period is CLK_B[i], and the first control signal corresponding to the i-th adjustment period is V_CTRL[i], where i is greater than or equal to 0 and less than n; n is the maximum number of times required to first adjust the first clock signal to a 180° phase difference from the second clock signal.

[0066] VREF is the voltage signal at the second input terminal of the comparison circuit 12. V_SAW is the voltage signal at the first terminal of the comparison circuit 12. COM_OUT[i] is the comparison signal between the first input terminal and the second input terminal of the comparison circuit 12 in the i-th adjustment period; when this comparison signal is at a high level, the voltage at the first input terminal of the comparison circuit 12 is less than the voltage at the second input terminal of the comparison circuit 12, indicating that the phase difference needs to be increased in the next adjustment period. When this comparison signal is at a low level, the voltage at the first input terminal of the comparison circuit 12 is greater than or equal to the voltage at the second input terminal of the comparison circuit 12, indicating that the phase difference needs to be decreased in the next adjustment period.

[0067] Among them, the horizontal direction represents time, and the numerical direction corresponds to the intensity of each signal.

[0068] Among them, t0 is the start time of each adjustment period, and t4 is the end time of each adjustment period. The length of the adjustment period is TA.

[0069] For the 0-th adjustment period, t1 is the time when CLK_B[0] changes from a low level to a high level, and t4 is the time when CLK_A changes from a high level to a low level, that is, the end time of the 0-th adjustment period and the start time of the 1-st adjustment period. Between t0 and t1, V_CTRL[0] is at a low level, and V_SAW[0] gradually increases; after t1, it gradually decreases until it is less than VREF at t2. After t2, the voltage at the first input terminal of the comparison circuit 12 continues to decrease until it reaches a low level state.

[0070] Then, during the period from t0 to t2, the comparison signal COM_OUT[0] outputs a low level. At t4, the end time of the 0-th adjustment period, the comparison signal COM_OUT[0] outputs a high level, indicating that the duration of the first control signal being at a low level needs to be increased in the 1-st adjustment period, that is, the phase difference of the 1-st adjustment period needs to be increased.

[0071] Among them, the duration T1[0] between t0 and t1 corresponds to the phase difference between CLK_B[0] and CLK_A; from Figure 2It can be seen that the time duration T2[0] between t1 and t4 is greater than T1[0], that is, T1[0] is less than 0.5TA, and the phase difference between CLK_B[0] and CLK_A is less than 180°.

[0072] If the phase difference is still less than 180° after increasing the phase difference in the first adjustment period, then continue to increase the phase difference in the second adjustment period until the phase difference between the (n - k)-th clock cycle CLK_B[n - k] and CLK_A is equal to 180°.

[0073] As Figure 2 shown, the first clock signal CLK_B[n - k] in the (n - k)-th adjustment period is marked on the basis of CLK_B[0], where the differences between CLK_B[n - k] and CLK_B[0] are marked with dotted lines.

[0074] The first control signal V_CTRL[n - k] in the (n - k)-th adjustment period is marked on the basis of V_CTRL[0], where the differences between V_CTRL[n - k] and V_CTRL[0] are marked with dotted lines.

[0075] The comparison signal V_SAW[n - k] in the (n - k)-th adjustment period is marked on the basis of V_SAW[0], where the differences between V_SAW[n - k] and V_SAW[0] are marked with dotted lines.

[0076] Among them, t3 is the moment when CLK_B[n - k] changes from low level to high level, and t4 is the end moment of the third adjustment period; in the time period from t0 to t3, V_CTRL[n - k] is at low level and V_SAW[n - k] gradually increases; after the moment t3, it gradually decreases until it is equal to VREF at the moment t4.

[0077] Then before the moment t4, the comparison signal COM_OUT[0] outputs a low level; at the moment t4, since V_SAW[n - k] is equal to VREF, the comparison signal outputs a high level at the moment t4. Then it indicates that the phase difference needs to be continued to be increased in the (n - k + 1)-th adjustment period.

[0078] Among them, the time duration T1[n - k] between t0 and t3 corresponds to the phase difference between CLK_B[n - k] and CLK_A; the time duration T2[n - k] between t3 and t4 is less than T1[n - k], that is, T1[n - k] is less than 0.5TA, and the phase difference between CLK_B[n - k] and CLK_A is equal to 180°.

[0079] After increasing the phase difference in the (n - k + 1)-th adjustment period, if the phase difference between CLK_B[n - k + 1] and CLK_A is greater than 180°, the comparison signal outputs a low level at time t4, indicating to decrease the phase difference in the (n - k + 2)-th adjustment period.

[0080] After decreasing the phase difference in the (n - k + 2)-th adjustment period, if the phase difference between CLK_B[n - k + 2] and CLK_A is equal to 180°, the comparison signal outputs a high level at time t4, indicating to increase the phase difference in the next adjustment period.

[0081] It can be seen that in each adjustment period, based on the comparison result of the first input end and the second input end, the phase difference between the second clock signal and the first clock signal is adjusted. After multiple adjustment periods, finally, the phase difference between the two will oscillate back and forth around 180°.

[0082] The present application provides a phase shift detection circuit 10, including an energy storage circuit 11 and a comparison circuit 12; at the beginning of the first adjustment period, the voltages at the first input end and the second input end of the comparison circuit 12 are the same. During the first adjustment period, the energy storage circuit 11 controls the voltage at the first input end of the comparison circuit 12 to rise or fall based on different logic states of the first control signal; wherein, the duration of the first control signal in the first logic state indicates the phase difference between the second clock signal and the first clock signal; the rising and falling rates of the voltage at the first input end of the comparison circuit 12 are the same; the comparison circuit 12 increases or decreases the phase difference between the two clock signals in the second adjustment period based on the magnitude of the voltage at the first input end and the voltage at the second input end at the end of the first adjustment period, so that the phase difference between the first clock signal and the second clock signal finally remains near 180°.

[0083] Next, through Figure 3 Examples are used to illustrate the structure of the energy storage circuit 11 and how the energy storage circuit 11 controls the voltage at the first input end of the comparison circuit 12.

[0084] Figure 3 FIG. is a schematic structural diagram of the phase shift detection circuit 10 provided by the embodiment of the present application. As Figure 3 shown, the energy storage circuit 11 includes a first transistor SP1, a second transistor SN2, and a first capacitor C1.

[0085] The control ends of the first transistor SP1 and the second transistor SN2 are both used to receive the first control signal; the first end of the first transistor SP1 is electrically connected to the power supply, the second end of the first transistor SP1 is electrically connected to the second end of the second transistor SN2, the first end of the second transistor SN2 is grounded, the first end of the first capacitor C1 is electrically connected to the second end of the first transistor SP1, and the second end of the first capacitor C1 is electrically connected to the first end of the second transistor SN2.

[0086] In this application, the first transistor SP1 is a P-type Metal-Oxide-Semiconductor (PMOS) transistor. The first end of the first transistor SP1 is the source s of the first transistor SP1, and the second end of the first transistor SP1 is the drain d of the first transistor SP1. The control end of the first transistor SP1 is the gate of the first transistor SP1.

[0087] The second transistor SN2 is an N-type Metal-Oxide-Semiconductor (NMOS) transistor. The first end of the second transistor SN2 is the source s of the second transistor SN2, and the second end of the second transistor SN2 is the drain d of the second transistor SN2. The control end of the second transistor SN2 is the gate of the second transistor SN2.

[0088] When the first control signal is in the first logic state, the first transistor SP1 is in the on state and the second transistor SN2 is in the off state. The power supply charges the first capacitor C1, and the voltage at the first end of the first capacitor C1 increases, thereby increasing the voltage at the first input terminal of the comparison circuit 12.

[0089] When the first control signal is in the second logic state, the first transistor SP1 is in the off state and the second transistor SN2 is in the on state, causing the first capacitor C1 to discharge and the voltage at the first end of the first capacitor C1 to decrease, thereby decreasing the voltage at the first input terminal of the comparison circuit 12.

[0090] Among them, the charging current and the discharging current of the first capacitor C1 have the same current value.

[0091] In this application, the first control signal controls the charging and discharging states of the first capacitor C1 by controlling the on-off states of the first transistor SP1 and the second transistor SN2, thereby increasing or decreasing the voltage at the first end of the first capacitor C1 to achieve an increase or decrease in the voltage at the first input terminal of the comparison circuit 12. And the charging current of the first capacitor C1 is the same as the discharging current of the first capacitor C1. In this way, the rate of increase or decrease in the voltage at the first input terminal of the first comparison circuit 12 is the same.

[0092] In this application, the charging current and the discharging current of the first capacitor C1 can be controlled by a current source.

[0093] As Figure 3 shown, the energy storage circuit 11 further includes a first current source Ia and a second current source Ib; among them, the first end of the first transistor is electrically connected to the negative electrode of the first current source Ia, and the positive electrode of the first current source Ia is electrically connected to the power supply.

[0094] The positive electrode of the second current source Ib is electrically connected to the first end of the second transistor SN2, and the negative electrode of the second current source Ib is grounded;

[0095] When the first control signal is in the first logic state, the power supply charges the first capacitor C1 through the first current source Ia, and the first current source Ia is used to control the charging current of the first capacitor C1.

[0096] When the first control signal is in the second logic state, the first capacitor C1 discharges through the second current source Ib, and the second current source Ib is used to control the discharging current of the first capacitor C1.

[0097] In this application, by designing the specific parameters of the first current source Ia and the second current source Ib, the current value of the charging current provided by the first current mirror can be made the same as the current value of the discharging current provided by the second current mirror.

[0098] The comparison circuit 12 of this application can be composed of a comparator COMP and a control sub-circuit. Next, Figure 4 The specific structure of the comparison circuit 12 is further described through embodiments.

[0099] Figure 4 FIG. is a schematic structural diagram of the phase shift detection circuit 10 provided by the embodiment of this application.

[0100] As Figure 4 shown, the comparison circuit 12 includes a comparator COMP and a first control sub-circuit 121; wherein, the first input terminal of the comparator COMP is electrically connected to the first end of the first capacitor C1, the second input terminal of the comparator COMP is configured to have the same voltage as the voltage of the first input terminal of the comparator COMP at the beginning of each adjustment period, the output terminal of the comparator COMP is electrically connected to the first input terminal of the first control sub-circuit 121, and the output terminal of the first control sub-circuit 121 is electrically connected to the phase shift oscillation circuit 20;

[0101] Wherein, the comparator COMP is used to generate a comparison signal based on the voltage at the first end of the first capacitor C1 (i.e., the voltage at the first input terminal of the comparator COMP) and the voltage at the second input terminal of the comparator COMP, and send the comparison signal to the first input terminal of the first control sub-circuit 121.

[0102] Wherein, the first input terminal of the comparator COMP is the inverting input terminal of the comparator COMP, and the second input terminal of the comparator COMP is the non-inverting input terminal of the comparator COMP.

[0103] When the voltage at the first input terminal of the comparator COMP is less than the voltage at the second input terminal of the comparator COMP, the comparison signal is in the second logic state.

[0104] When the voltage at the first input terminal of the comparator COMP is greater than or equal to the voltage at the second input terminal of the comparator COMP, the comparison signal is in the first logic state.

[0105] The first control sub-circuit 121 generates a second control signal based on the comparison signal at the end of the first adjustment period and sends the second control signal to the phase shift oscillation circuit 20; wherein, the second control signal is used to instruct the phase shift oscillation circuit 20 to adjust the duration of the second clock signal in the second logic state during the second adjustment period.

[0106] Specifically, the first control sub-circuit 121 further includes a second input terminal. The second input terminal of the first control sub-circuit 121 is used to receive the second clock signal. When the second clock signal changes from the first logic state to the second logic state, the first control sub-circuit 121 determines the end of the first adjustment period and generates a second control signal based on the comparison signal.

[0107] Figure 4 In this case, the comparison signal is represented by CMP_OUT, and the second clock signal is represented by CLK_A.

[0108] Wherein, when the comparison signal is in the second logic state at the end of the first adjustment period, the second control signal is used to control the phase shift oscillation circuit 20 to increase the duration of the first clock signal in the first logic state during the second adjustment period; when the comparison signal is in the first logic state, the second control signal is used to control the phase shift oscillation circuit 20 to decrease the duration of the first clock signal in the first logic state during the second adjustment period.

[0109] In some embodiments, as Figure 4 shown, the comparison circuit 12 further includes a first switch S1; wherein, the second input terminal of the comparator COMP is electrically connected to the first input terminal of the comparator COMP through the first switch S1.

[0110] The first switch S1 is used to make the voltage at the first input terminal of the comparator COMP the same as the voltage at the second input terminal of the comparator COMP at the start of the first adjustment period.

[0111] Specifically, the first switch S1 is configured to conduct at the start of the first adjustment period, so that the voltage at the first input terminal of the comparator COMP is the same as the voltage at the second input terminal of the comparator COMP at the start of the first adjustment period.

[0112] In some embodiments, after the first switch S1 conducts at the start of the first adjustment period, it disconnects, so that the voltage at the second input terminal of the comparator COMP remains unchanged during the first adjustment period.

[0113] Wherein, at the start of the first adjustment period, the duration between the conduction and disconnection of the first switch S1 is short and can be ignored.

[0114] In this embodiment, the comparison circuit 12 includes a comparator COMP and a first control sub-circuit 121. The comparator COMP is configured to compare the voltage at the first end of the first capacitor C1 of the comparator COMP with the voltage at the second input terminal of the comparator COMP. The first control sub-circuit 121 is configured to, at the end of the first adjustment period, adjust the duration of the second clock period of the phase shift oscillation circuit 20 in the first logic state during the second adjustment period based on the comparison signal, so as to adjust the phase difference between the second clock signal and the first clock signal.

[0115] In some embodiments, the phase shift detection circuit 10 further includes a first latch circuit 13, and the first latch circuit 13 is configured to generate a first control signal based on the first clock signal and the second clock signal.

[0116] Wherein, the first input terminal of the first latch circuit 13 is configured to receive the second clock signal, the second input terminal of the first latch circuit 13 is configured to receive the first clock signal, and the output terminal of the first latch circuit 13 is electrically connected to the control terminals of the first transistor SP1 and the second transistor SN2 respectively.

[0117] The first latch circuit 13 is configured to generate a first control signal based on the first clock signal and the second clock signal, and input the first control signal to the control terminals of the first transistor SP1 and the second transistor SN2.

[0118] When the second clock signal changes from the first logic state to the second logic state, the first control signal output by the first latch circuit 13 changes from the second logic state to the first logic state;

[0119] When the first clock signal changes from the first logic state to the second logic state, the first control signal output by the first latch circuit 13 changes from the first logic state to the second logic state.

[0120] In some embodiments, the first latch circuit 13 may be composed of two NOR gates and an inverter; next, Figure 5 the structure of the first latch circuit 13 is described.

[0121] Figure 5 FIG. is a schematic structural diagram of the phase shift detection circuit 10 provided by the embodiment of the present application; wherein, the first latch circuit 13 includes a first NOR gate NR1, a second NOR gate NR2, and a first inverter INV1.

[0122] Wherein, the first input terminal of the first NOR gate NR1 is used to receive a second clock signal, the second input terminal of the first NOR gate NR1 is electrically connected to the output terminal of the second NOR gate NR2, the output terminal of the first NOR gate NR1 is electrically connected to the first input terminal of the second NOR gate NR2, and the second input terminal of the second NOR gate NR2 is used to receive a first clock signal; the output terminal of the second NOR gate NR2 is electrically connected to the input terminal of the first inverter INV1, and the output terminal of the first inverter INV1 is electrically connected to the control terminals of the first transistor SP1 and the second transistor SN2 respectively.

[0123] Wherein, the second clock signal is CLK_A and the first clock signal is CLK_B.

[0124] Next, taking the first logic state as the low level and the second logic state as the high level as an example, the working principle of the first latch circuit 13 will be described.

[0125] When the first clock signal changes from the low level to the high level, the first NOR gate NR1 outputs a low-level signal. Since the second clock signal has not changed to the high level yet, both input terminals of the second NOR gate NR2 are at the low level, the second NOR gate NR2 outputs a high-level signal, and the first inverter INV1 outputs a low-level signal; since the second NOR gate NR2 outputs a high-level signal to the second input terminal of the first NOR gate NR1, even if the high-level duration of the first clock signal is very short, before the second clock signal changes to the high level, the first NOR gate NR1 can continuously output a low-level signal. The second NOR gate NR2 can continuously output a high-level signal, and the first inverter INV1 can continuously output a low-level signal.

[0126] When the second clock signal changes from the low level to the high level, the second NOR gate NR2 outputs a low-level signal, and the first inverter INV1 outputs a high-level signal; at this time, the output of the first NOR gate NR1 inputs a high-level signal to the first input terminal of the second NOR gate NR2; then even if the high-level duration of the second clock signal is very short, before the first clock signal changes to the high level, the second NOR gate NR2 can continuously output a low-level signal, and the first inverter INV1 can continuously output a high-level signal.

[0127] In this way, when the first clock signal changes from the first logic state to the second logic state, the first control signal can change from the second logic state to the first logic state through the first latch circuit 13; when the second clock signal changes from the first logic state to the first logic state, the first control signal changes from the first logic state to the second logic state.

[0128] As Figure 1 shown, the phase shift detection circuit 10 and the phase shift oscillation circuit 20 constitute a clock phase shift circuit 30; next, through Figure 6The structure of the phase shift oscillation circuit 20 will be described with reference to the embodiments.

[0129] Figure 6 FIG. is a schematic structural diagram of the phase shift detection circuit 10 provided by the embodiment of the present application; as Figure 6 shown, the phase shift oscillation circuit 20 includes a third transistor MN3, a fourth transistor MN4, a fifth transistor MN5, a second capacitor C2, and a second control sub-circuit 21.

[0130] Among them, the second end of the third transistor MN3 is electrically connected to the power supply and the control end of the third transistor MN3, the second end of the third transistor MN3 is electrically connected to the first end of the adjustable resistor circuit R1, the second end of the adjustable resistor circuit R1 is grounded, and the control end of the adjustable resistor circuit R1 is electrically connected to the output end of the comparison circuit 12.

[0131] Among them, the third transistor MN3 is an NMOS, the second end of the third transistor MN3 is the drain d of the third transistor MN3, the first end of the third transistor MN3 is the source s of the third transistor MN3, and the control end of the third transistor MN3 is the gate of the third transistor MN3.

[0132] The control end of the fourth transistor MN4 is electrically connected to the control end of the third transistor MN3, the second end of the fourth transistor MN4 is electrically connected to the power supply, the first end of the fourth transistor MN4 is electrically connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is grounded.

[0133] Among them, the fourth transistor MN4 is an NMOS, the second end of the fourth transistor MN4 is the drain d of the fourth transistor MN4, the first end of the fourth transistor MN4 is the source s of the fourth transistor MN4, and the control end of the fourth transistor MN4 is the gate of the fourth transistor MN4.

[0134] The second end of the fifth transistor MN5 is electrically connected to the first end of the first capacitor C1, the first end of the fifth transistor MN5 is grounded, and the control end of the fifth transistor MN5 is electrically connected to the second output end of the second control sub-circuit 21.

[0135] Among them, the fifth transistor MN5 is an NMOS, the second end of the fifth transistor MN5 is the drain of the fifth transistor MN5, the first end of the fifth transistor MN5 is the source of the fifth transistor MN5, and the control end of the fifth transistor MN5 is the gate of the fifth transistor MN5.

[0136] The first input end of the second control sub-circuit 21 is electrically connected to the second end of the fourth transistor MN4, the second input end of the second control sub-circuit 21 is used to receive the second clock signal; the first output end of the second control sub-circuit 21 is electrically connected to the second input end of the first latch circuit 13 of the phase shift detection circuit 10.

[0137] Among them, the second control sub-circuit 21 is configured to generate a first clock signal and a third control signal based on the received second clock signal and the voltage signal at the second end of the fourth transistor MN4 within the first adjustment period. Among them, at the beginning of the first adjustment period, the first clock signal is in the first logic state.

[0138] The second control sub-circuit 21 inputs the output first clock signal to the second input terminal of the first latch circuit 13, so that the first latch circuit 13 generates a first control signal based on the first clock signal and the second clock signal.

[0139] The second control sub-circuit 21 inputs the third control signal to the control terminal of the fifth transistor MN5, and controls the duration of the first clock signal in the first logic state based on the third control signal.

[0140] Among them, when the second clock signal changes from the first logic state to the second logic state, the third control signal changes from the second logic state to the first logic state, the fifth transistor MN5 is in the off state, and the power supply charges the second capacitor C2, so that the voltage at the first end of the second capacitor C2 increases.

[0141] When the voltage at the first end of the second capacitor C2 is greater than the voltage at the first end of the adjustable resistor circuit R1, the voltage difference Vg-Vs between the gate and source of the fourth transistor MN4 is less than the conduction threshold, the fourth transistor MN4 is turned off, and the voltage signal at the second end of the fourth transistor MN4 changes from the first logic state to the second logic state, so that the first clock signal output by the second control sub-circuit 21 changes from the first logic state to the second logic state, corresponding to the second control sub-circuit 21 outputting a pulse signal.

[0142] The comparison circuit 12 adjusts the resistance value of the adjustable resistor circuit R1 within the second adjustment period based on the comparison result of the voltage at the first input terminal and the voltage at the second input terminal of the comparison circuit 12 at the end of the first adjustment period, so as to adjust the duration of the first clock signal in the first logic state within the second adjustment period.

[0143] Among them, the resistance value of the adjustable resistor circuit R1 is positively correlated with the duration of the first clock signal in the first logic state within the second adjustment period.

[0144] It can be understood that the larger the resistance value of the adjustable resistor circuit R1, the longer the duration required for the second capacitor C2 to be charged until the voltage at the first end is greater than or equal to the voltage at the first end of the adjustable resistor circuit R1, the later the voltage signal at the second end of the fourth transistor MN4 changes from the first logic state to the second logic state, the later the first clock signal changes from the first logic state to the second logic state, the longer the duration of the first logic state of the first clock signal, and the greater the phase difference between the second clock signal and the first clock signal.

[0145] The smaller the resistance value of the adjustable resistor circuit R1, the shorter the time required for the second capacitor C2 to charge until the voltage at the first end is greater than or equal to the voltage at the first end of the adjustable resistor, the earlier the voltage signal at the second end of the fourth transistor MN4 changes from the first logic state to the second logic state, the earlier the first clock signal changes from the first logic state to the second logic state, the shorter the duration of the first logic state of the first clock signal, and the smaller the phase difference between the first clock signal and the second clock signal.

[0146] Specifically, the output terminal of the first control sub-circuit 121 of the comparison circuit 12 is electrically connected to the control terminal of the adjustable resistor circuit R1, and the first control sub-circuit 121 sends a second control signal to the control terminal of the adjustable resistor circuit R1 to control the resistance value of the adjustable resistor circuit R1.

[0147] At the end of the first adjustment period, if the comparison result indicates that the voltage at the first input terminal of the comparison circuit 12 is less than the voltage at the second input terminal, the second control signal is used to increase the resistance value of the adjustable resistor circuit R1 to increase the second phase difference between the second clock signal and the first clock signal in the second adjustment period.

[0148] If at the end of the first adjustment period, the comparison result indicates that the voltage at the first input terminal of the comparison circuit 12 is greater than or equal to the voltage at the second input terminal, the second control signal is used to decrease the resistance value of the adjustable resistor circuit R1 to decrease the phase difference between the second clock signal and the first clock signal in the second adjustment period.

[0149] In this application, an adjustable resistor circuit R1 with an adjustable resistance value is provided in the phase shift oscillator circuit 20. In this way, the comparison circuit 12 can increase or decrease the resistance value of the adjustable resistor circuit R1 based on the comparison result, thereby increasing or decreasing the phase difference between the second clock signal and the first clock signal, and finally stabilizing the phase difference between the first clock signal and the second clock signal at around 180°.

[0150] In this application, the adjustment step size for adjusting the resistance value of the adjustable resistor circuit R1 is the same each time. Among them, the first control sub-circuit 121 can be implemented by a decoder circuit. The decoder circuit has N outputs for outputting a second control signal to control the resistance value of the adjustable resistor circuit R1.

[0151] The N outputs of the decoder circuit correspond one-to-one with N-bit binary. In the 0th adjustment period, the code value of the N-bit binary is 0, then all N outputs are at a low level; correspondingly, the resistance value of the adjustable resistor circuit R1 is a specific value, and the phase difference between the second clock signal and the first clock signal output by the phase shift oscillator circuit 20 is 30°.

[0152] In the next adjustment cycle, if it is necessary to increase the adjustable resistor circuit R1, the N-bit binary code value is incremented by 1, and the signals output by the N channels of the decoder circuit are adjusted based on the updated binary code value, so as to adjust the resistance value of the adjustable resistor, and further adjust the phase difference between the second clock circuit and the phase shift oscillation circuit 20.

[0153] Wherein, N is the same as the maximum value of the binary code value and the maximum number of times n required to first adjust the first clock signal to a phase difference of 180° from the second clock signal.

[0154] In this application, the phase difference between the second clock signal and the first clock signal can be calculated by the current flowing through the adjustable circuit resistor circuit and the charging current of the second capacitor C2.

[0155] In any adjustment cycle, the calculation formula for the phase difference between the second clock signal and the first clock signal is as shown in Formula 1:

[0156]

[0157] Wherein, Tph is the phase difference between the second clock signal and the first clock signal, C2 is the capacitance value of the second capacitor C2, I1 is the current flowing through the adjustable resistor circuit R1, I2 is the charging current of the second capacitor C2, that is, the current flowing through the second capacitor C2; V R is the voltage at the first end of the adjustable resistor circuit R1.

[0158] In some embodiments, as Figure 6 shown, the phase shift oscillation circuit 20 further includes two current sources, namely a third current source Ic and a fourth current source Id, which are respectively used to control the currents flowing through the adjustable resistor circuit R1 and the second capacitor C2 to keep the currents of the two stable.

[0159] Wherein, the positive electrode of the third current source Ic is electrically connected to the power supply, and the negative electrode of the third current source Ic is electrically connected to the second end of the third transistor MN3; the positive electrode of the fourth current source Id is electrically connected to the power supply, and the negative electrode of the fourth current source Id is electrically connected to the second end of the fourth transistor MN4.

[0160] The third current source Ic is used to control the current flowing through the adjustable resistor circuit R1.

[0161] The fourth current source Id is used to control the charging current of the second capacitor C2.

[0162] In the embodiments of this application, by setting the specific parameters of the third current source Ic and the fourth current source Id, the current flowing through the adjustable resistor circuit R1 can be made the same as the charging current of the second capacitor C2.

[0163] In this way, the phase difference between the second clock signal and the first clock signal can be expressed by Formula 2:

[0164] Tph = C2 * V R Formula 2;

[0165] It can be seen that by adjusting the resistance value of the adjustable resistor circuit R1, the phase difference between the second clock signal and the first clock signal can be adjusted.

[0166] Next, Figure 7 An embodiment is used to illustrate the structure and working principle of the second control sub - circuit 21.

[0167] Figure 7 FIG. is a schematic structural diagram of the clock phase - shift circuit 30 provided by the embodiment of the present application.

[0168] As Figure 7 shown, the second control sub - circuit 21 includes a fifth current source Ie, a sixth transistor MN6, a seventh transistor MP7, a second inverter INV2, a second latch circuit 212, and a third inverter INV3;

[0169] Among them, the positive pole of the fifth current source Ie is electrically connected to the power supply, the negative pole of the fifth current source Ie is electrically connected to the second end of the sixth transistor MN6, the first end of the sixth transistor MN6 is grounded, and the control end of the sixth transistor MN6 is electrically connected to the second end of the fourth transistor MN4.

[0170] Among them, the sixth transistor MN6 is an NMOS, the second end of the sixth transistor MN6 is the drain d of the sixth transistor MN6, the first end of the sixth transistor MN6 is the source s of the sixth transistor MN6, and the control end of the sixth transistor MN6 is the gate of the sixth transistor MN6.

[0171] The first end of the seventh transistor MP7 is electrically connected to the positive pole of the fifth current source, the second end of the seventh transistor MP7 is electrically connected to the second end of the sixth transistor MN6, the second end of the seventh transistor MP7 is also electrically connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is used as the first output end of the second control sub - circuit 21 and is electrically connected to the second input end of the second latch circuit 212 and the second input end of the first latch circuit 13 respectively, and the first input end of the second latch circuit 212 is used as the second input end of the second control sub - circuit 21 to receive the second clock signal.

[0172] Among them, the seventh transistor MP7 is a PMOS, the second end of the seventh transistor MP7 is the drain d of the seventh transistor MP7, the first end of the seventh transistor MP7 is the source s of the seventh transistor MP7, and the control end of the seventh transistor MP7 is the gate of the seventh transistor MP7.

[0173] The output terminal of the second latch circuit 212 is electrically connected to the control terminal of the seventh transistor MP7. The output terminal of the second latch circuit 212 is also electrically connected to the input terminal of the third inverter INV3. The output terminal of the third inverter INV3 serves as the second output terminal of the second control sub-circuit 21 and is electrically connected to the control terminal of the fifth transistor MN5.

[0174] The second inverter INV2 inputs the first clock signal to the second input terminal of the second latch circuit 212 based on the voltage signal at the second terminal of the fourth transistor MN4. The second latch circuit 212 and the third inverter INV3 generate a third control signal based on the second clock signal and the first clock signal.

[0175] The second latch circuit 212 has one more third inverter INV3 compared to the first latch circuit 13. Among them, the second latch circuit 212 includes a third NOR gate NR3 and a fourth NOR gate NR4.

[0176] As Figure 7 shown, the first input terminal of the third NOR gate NR3 is used to receive the first clock signal. The second input terminal of the third NOR gate NR3 is electrically connected to the first input terminal of the fourth NOR gate NR4. The output terminal of the third NOR gate NR3 is electrically connected to the first input terminal of the fourth NOR gate NR4. The output terminal of the third NOR gate NR3 is also electrically connected to the input terminal of the third inverter INV3. The second input terminal of the fourth NOR gate NR4 is used to receive the second clock signal.

[0177] Among them, the working principle of the second latch circuit 212 is similar to that of the first latch circuit 13 and will not be elaborated here.

[0178] Next, in combination with Figure 7 , the principle of the phase shift oscillator circuit 20 generating the first clock signal based on the second clock signal will be exemplarily described.

[0179] As Figure 7 shown, the third control signal is denoted as RSTN, and the signal at the output terminal of the second latch circuit 212 is denoted as RSTP.

[0180] Specifically, in one adjustment period, when the second clock signal changes from the first logic state to the second logic state, the third control signal changes from the second logic state to the first logic state, the fifth transistor MN5 is in the off state, and the second capacitor C2 starts to charge; the voltage at the second terminal of the fourth transistor MN4 gradually increases. When the voltage at the first terminal of the second capacitor C2 is greater than the voltage at the first terminal of the adjustable resistor circuit R1, the fourth transistor MN4 turns off, and the voltage signal at the second terminal of the fourth transistor MN4 is pulled high by the power supply, causing the voltage signal at the second terminal of the fourth transistor MN4 to change from the first logic state to the second logic state and causing the sixth transistor MN6 to conduct.

[0181] After the sixth transistor MN6 is turned on, the voltage at the second terminal of the sixth transistor MN6 is pulled down, and the voltage signal at the second terminal of the sixth transistor MN6 is at the first logic state. Therefore, the first clock signal output by the second inverter INV2 changes from the first logic state to the second logic state.

[0182] Since the duration of the second clock signal in the second logic state is very short, when the first clock signal changes from the first logic state to the second logic state, the second clock signal has already changed from the second logic state to the first logic state. Then, the output terminal of the second latch circuit 212 is at the first logic state, the third control signal is at the second logic state, the fifth transistor MN5 is turned on, and the second capacitor C2 starts to discharge, causing the fourth transistor MN4 to turn on. The voltage signal at the second terminal of the fourth transistor MN4 is reset from the second logic state to the first logic state.

[0183] In this application, the logic states of the third control signal and the first control signal are the same.

[0184] The duration of the first clock signal in the second logic state is also very short. Specifically, when the output terminal of the second latch circuit 212 is at the first logic state, the seventh transistor MP7 is in the on state, and the voltage at the second terminal of the seventh transistor MP7, which is also the voltage at the second terminal of the sixth transistor MN6, is pulled up. The voltage signal at the second terminal of the sixth transistor MN6 is reset to the second logic state, and the first clock signal output by the second inverter INV2 changes from the second logic state to the first logic state again.

[0185] Based on the above embodiments, this application provides a voltage converter. Figure 8 It is a schematic structural diagram of the voltage converter provided by this application, as Figure 8 shown. The voltage converter 80 includes a first DC-DC conversion circuit 81, a second DC-DC conversion circuit 82, and a clock phase shift circuit 30.

[0186] Among them, the phase shift detection circuit 10 of the clock phase shift circuit 30 is used to adjust the first clock signal output by the phase shift oscillation circuit 20 of the clock phase shift circuit 30 so that the phase difference between the first clock signal and the second clock signal satisfies 180°, and input the first clock signal to the first DC-DC conversion circuit.

[0187] The first DC-DC conversion circuit 81 is used to perform voltage conversion on the input voltage of the first DC-DC conversion circuit 81 based on the first clock signal.

[0188] The second DC-DC conversion circuit 82 is used to receive the second clock signal and perform voltage conversion on the input voltage of the second DC-DC conversion circuit 82 based on the second clock signal.

[0189] Finally, it should be noted that the above embodiments are only specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A phase shift detection circuit, characterized in that, Comprising: An energy storage circuit and a comparison circuit; wherein, a first end of the energy storage circuit is configured to receive a first control signal, a second end of the energy storage circuit is electrically connected to a first input end of the comparison circuit, and a voltage of a second input end of the comparison circuit is configured to be the same as a voltage of the first input end of the comparison circuit at the start of each adjustment period; an output end of the comparison circuit is electrically connected to a phase shift oscillation circuit; the phase shift oscillation circuit is configured to output a first clock signal; The energy storage circuit is configured to control the voltage of the first input end of the comparison circuit to increase or decrease based on the first control signal within a first adjustment period; Wherein, when the first control signal is in a first logic state, the voltage of the first input end of the comparison circuit increases; when the first control signal is in a second logic state, the voltage of the first input end of the comparison circuit decreases; a rate at which the voltage of the first input end of the comparison circuit increases is the same as a rate at which the voltage of the first input end of the comparison circuit decreases; a first phase difference of the first clock signal within the first adjustment period is determined based on a duration during which the first control signal is in the first logic state within the first adjustment period; The comparison circuit is configured to, at the end of the first adjustment period, adjust a duration during which the first clock signal of the phase shift oscillation circuit is in the first logic state within a second adjustment period based on a comparison result between the voltage of the first input end of the comparison circuit and the voltage of the second input end of the comparison circuit, thereby adjusting a second phase difference between the second clock signal and the first clock signal within the second adjustment period; Wherein, the second adjustment period is a next adjustment period of the first adjustment period; when the comparison result indicates that the voltage of the first input end of the comparison circuit is less than the voltage of the second input end of the comparison circuit, the duration during which the first clock signal is in the first logic state within the second adjustment period increases, such that the second phase difference is greater than the first phase difference; when the comparison result indicates that the voltage of the first input end of the comparison circuit is greater than or equal to the voltage of the second input end of the comparison circuit, the duration during which the first clock signal is in the first logic state within the second adjustment period decreases, such that the second phase difference is less than the first phase difference.

2. The circuit according to claim 1, wherein The energy storage circuit includes a first transistor, a second transistor, and a first capacitor; Wherein, control ends of the first transistor and the second transistor are both configured to receive the first control signal; a first end of the first transistor is electrically connected to a power supply, a second end of the first transistor is electrically connected to a second end of the second transistor, and a first end of the second transistor is grounded; a first end of the first capacitor is electrically connected to the second end of the second transistor, and a second end of the first capacitor is electrically connected to the first end of the second transistor; When the first control signal is in the first logic state, the first transistor is in an on state, the second transistor is in an off state, and the power supply charges the first capacitor, thereby increasing the voltage of the first input end of the comparison circuit; When the first control signal is in the second logic state, the first transistor is in the off state, the second transistor is in the on state, and the first capacitor is in the discharge state, so that the voltage at the first input terminal of the comparison circuit decreases; wherein, the charging current and the discharging current of the first capacitor have the same current value.

3. The circuit according to claim 2, wherein The energy storage circuit further includes a first current source and a second current source; Wherein, the first end of the first transistor is electrically connected to the negative electrode of the first current source, and the positive electrode of the first current source is electrically connected to the power supply; the first end of the second transistor is connected to the positive electrode of the second current source, and the negative electrode of the second current source is grounded; the first current source is used to control the charging current of the first capacitor; the second current source is used to control the discharging current of the first capacitor.

4. The circuit according to claim 2, wherein The comparison circuit includes a comparator and a first control sub-circuit; wherein, the inverting input terminal of the comparator is electrically connected to the first end of the first capacitor, and the non-inverting input terminal of the comparator is configured to have the same voltage as the voltage at the inverting input terminal of the comparator at the beginning of each adjustment period; the output terminal of the comparator is electrically connected to the first input terminal of the first control sub-circuit, and the output terminal of the first control sub-circuit is electrically connected to the phase shift oscillation circuit; Wherein, the comparator is configured to generate a comparison signal based on the voltage at the first end of the first capacitor and the voltage at the non-inverting input terminal of the comparator, and send the comparison signal to the first control sub-circuit; The first control sub-circuit is configured to generate a second control signal based on the comparison signal at the end of the first adjustment period, and send the second control signal to the phase shift oscillation circuit; wherein, the second control signal is used to control the duration of the first clock signal of the phase shift oscillation circuit in the first logic state during the second adjustment period; Wherein, when the comparison signal is in the second logic state, the second control signal is used to increase the duration of the first clock signal in the first logic state during the second adjustment period; when the comparison signal is in the first logic state, the second control signal is used to decrease the duration of the first clock signal in the first logic state during the second adjustment period.

5. The circuit according to claim 4, characterized in that, The comparison circuit further includes a first switch; wherein, the inverting input terminal of the comparator is electrically connected to the non-inverting input terminal of the comparator through the first switch; The first switch is configured to conduct at the beginning of each adjustment period, so that the voltage at the non-inverting input terminal of the comparator is the same as the voltage at the inverting input terminal of the comparator at the beginning of each adjustment period.

6. The circuit according to claim 1, characterized in that, It further includes a first latch circuit; the first input terminal of the first latch circuit is used to receive the second clock signal, the second input terminal of the first latch circuit is used to receive the first clock signal, and the output terminal of the first latch circuit is electrically connected to the control terminals of the first transistor and the second transistor respectively; The first latch circuit is configured to generate the first control signal based on the first clock signal and the second clock signal, and input the first control signal to the control terminal of the first transistor and the control terminal of the second transistor; When the second clock signal changes from the first logic state to the second logic state, the first control signal changes from the second logic state to the first logic state; When the first clock signal changes from the first logic state to the second logic state, the first control signal changes from the first logic state to the second logic state.

7. A clock phase shift circuit, characterized in that, It includes a phase shift oscillation circuit and the phase shift detection circuit according to any one of claims 1 to 6; wherein, the first end of the energy storage circuit of the phase shift detection circuit is configured to receive the first control signal, and the second end of the energy storage circuit is electrically connected to the first input terminal of the comparison circuit of the phase shift detection circuit; the voltage of the second input terminal of the comparison circuit is configured to be the same as the voltage of the first input terminal of the comparison circuit at the beginning of each adjustment period; the output terminal of the comparison circuit is electrically connected to the first input terminal of the phase shift oscillation circuit; the phase shift oscillation circuit is configured to output the first clock signal; The energy storage circuit is configured to control the voltage of the first input terminal of the comparison circuit to increase or decrease based on the first control signal during the first adjustment period; Wherein, when the first control signal is in the first logic state, the voltage of the first input terminal of the comparison circuit increases; when the first control signal is in the second logic state, the voltage of the first input terminal of the comparison circuit decreases; the rate of increase of the voltage of the first input terminal of the comparison circuit is the same as the rate of decrease; the first phase difference of the first clock signal in the first adjustment period is determined based on the duration of the first control signal in the first logic state during the first adjustment period; The comparison circuit is configured to, at the end of the first adjustment period, adjust the duration of the first clock signal of the phase shift oscillation circuit in the second logic state in the second adjustment period based on the comparison result between the voltage of the first input terminal of the comparison circuit and the voltage of the second input terminal of the comparison circuit, so as to adjust the second phase difference between the second clock signal and the first clock signal in the second adjustment period; Wherein, the second adjustment period is the next adjustment period of the first adjustment period; when the comparison result indicates that the voltage of the first input terminal of the comparison circuit is less than the voltage of the second input terminal of the comparison circuit, the comparison circuit controls the phase shift oscillation circuit to increase the duration of the first clock signal in the second logic state in the second adjustment period, so that the second phase difference is greater than the first phase difference; when the comparison result indicates that the voltage of the first input terminal of the comparison circuit is greater than or equal to the voltage of the second input terminal of the comparison circuit, the comparison circuit controls the phase shift oscillation circuit to decrease the duration of the first clock signal in the second logic state in the second adjustment period, so that the second phase difference is less than the first phase difference.

8. The circuit according to claim 7, wherein, The phase shift oscillation circuit includes a third transistor, a fourth transistor, a fifth transistor, an adjustable resistance circuit, a second capacitor, and a second control sub - circuit; Wherein, the second end of the third transistor is electrically connected to the power supply and the control end of the third transistor respectively; the first end of the third transistor is electrically connected to the first end of the adjustable resistance circuit, the second end of the adjustable circuit is grounded, and the control end of the adjustable resistance circuit is electrically connected to the output end of the comparison circuit; The control end of the fourth transistor is electrically connected to the control end of the third transistor, the second end of the fourth transistor is electrically connected to the power supply, the first end of the fourth transistor is electrically connected to the first end of the second capacitor, and the second end of the second capacitor is grounded; the second end of the fifth transistor is electrically connected to the first end of the first capacitor, and the first end of the fifth transistor is grounded; The first input end of the second control sub - circuit is electrically connected to the second end of the fourth transistor, and the second input end of the second control sub - circuit is used to receive the second clock signal; the first output end of the second control sub - circuit is electrically connected to the second input end of the first latch circuit of the phase shift detection circuit; the second output end of the second control sub - circuit is electrically connected to the control end of the fifth transistor; The second control sub - circuit is configured to generate the first clock signal and the third control signal based on the second clock signal and the voltage signal at the second end of the fourth transistor during the first adjustment period, input the first clock signal to the second input end of the first latch circuit, so that the first latch circuit generates the first control signal based on the first clock signal and the second clock signal; input the third control signal to the control end of the fifth transistor, and control the duration of the first clock signal in the first logic state based on the third control signal; Wherein, when the second clock signal changes from the first logic state to the second logic state, the third control signal changes from the second logic state to the first logic state, the fifth transistor is in the off state, the power supply charges the second capacitor, and when the voltage at the first end of the second capacitor is greater than the voltage at the first end of the adjustable resistance circuit, the first clock signal changes from the first logic state to the second logic state; The comparison circuit is configured to adjust the resistance value of the adjustable resistance circuit based on the comparison result of the voltage at the first input end and the voltage at the second input end of the comparison circuit at the end of the first adjustment period, so as to adjust the duration of the first clock signal in the first logic state during the second adjustment period; wherein, the resistance value of the adjustable resistance circuit is positively correlated with the duration of the first clock signal in the first logic state during the second adjustment period.

9. The circuit according to claim 8, wherein, In each adjustment period, the adjustment step of the resistance value of the adjustable resistance circuit is the same.

10. The circuit according to claim 8, wherein The phase shift oscillation circuit further includes a third current source and a fourth current source; wherein, the positive electrode of the third current source is electrically connected to the power supply, and the negative electrode of the third current source is electrically connected to the second end of the third transistor; the positive electrode of the fourth current source is electrically connected to the power supply, and the negative electrode of the fourth current source is electrically connected to the second end of the fourth transistor; The third current source is used to control the current flowing through the adjustable resistance circuit; The fourth current source is used to control the charging current of the second capacitor; wherein, the current flowing through the adjustable resistance circuit is the same as the charging current of the second capacitor.

11. The circuit according to claim 8, wherein, The second control sub-circuit includes a fifth current source, a sixth transistor, a second inverter, a second latch circuit, and a third inverter; Wherein, the positive electrode of the fifth current source is electrically connected to the power supply, the negative electrode of the fifth current source is electrically connected to the second end of the sixth transistor, the second end of the sixth transistor is connected to the input end of the second inverter, the first end of the sixth transistor is grounded, and the control end of the sixth transistor is electrically connected to the second end of the fourth transistor; the output end of the second inverter is electrically connected to the second input end of the second latch circuit and the second input end of the first latch circuit respectively, and the first input end of the second latch circuit is used to receive the second clock signal; the output end of the second latch circuit is electrically connected to the input end of the third inverter, and the output end of the third inverter is electrically connected to the control end of the fifth transistor; The second inverter is used to input the first clock signal to the second input end of the second latch circuit based on the voltage signal at the second end of the fourth transistor; the second latch circuit and the third inverter are used to generate the third control signal based on the second clock signal and the first clock signal; When the third control signal is in the first logic state and the voltage at the first end of the first capacitor is greater than the voltage at the first end of the adjustable resistance circuit, the sixth transistor is in the conducting state, the voltage signal at the second end of the sixth transistor is in the first logic state, and the first clock signal output by the second inverter changes from the first logic state to the second logic state.

12. The circuit according to claim 11, wherein The second control sub-circuit further includes a seventh transistor; Wherein, the first end of the seventh transistor is electrically connected to the positive electrode of the fifth current source, and the second end of the seventh transistor is electrically connected to the second end of the sixth transistor; When the first clock signal changes from the first logic state to the second logic state, the voltage signal at the output end of the second latch circuit changes from the second logic state to the first logic state, so that the voltage signal at the second end of the seventh transistor changes from the first logic state to the second logic state, and the first clock signal output by the second inverter changes from the second logic state to the first logic state.

13. A voltage converter, characterized in that, Comprising a first DC-DC conversion circuit, a second DC-DC conversion circuit, and the clock phase shift circuit according to any one of claims 7 to 12; Among them, the phase shift detection circuit of the clock phase shift circuit is used to adjust the first clock signal output by the phase shift oscillation circuit of the clock phase shift circuit, so that the phase difference between the first clock signal and the second clock signal meets 180°, and input the first clock signal into the first DC-DC conversion circuit; The first DC-DC conversion circuit is used to perform voltage conversion on the input voltage of the first DC-DC conversion circuit based on the first clock signal; The second DC-DC conversion circuit is used to perform voltage conversion on the input voltage of the second DC-DC conversion circuit based on the second clock signal.

14. A chip, characterized in that, It includes the phase shift detection circuit according to any one of claims 1 to 6, or the clock phase shift circuit according to any one of claims 7 to 12, or the voltage converter according to claim 13.

15. An electronic device, characterized in that, It includes the chip according to claim 14.

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