Balancing system for regulating flying capacitor voltage in three-level step-down acting on ramp waves

Abstract

The invention relates to a balancing system for regulating flying capacitor voltage in a three-level step-down transformer acting on ramp waves. A three-level DC-DC converter includes a power stage having high-side and low-side transistors, a flying capacitor, and an inductor coupled between an output tap of the power stage and an output node of the converter. A feedback voltage divider is coupled in parallel with an output capacitor between the output node and ground and generates a feedback voltage. The ramp generator generates a first ramp signal based on a constant reference voltage and a second ramp signal based on a difference between a voltage across the flying capacitor and half of the input voltage. The control circuitry generates an error signal based on a comparison between the feedback voltage and a reference voltage, generates a first high-side control signal and a first low-side control signal for the power stage based on a comparison between the first ramp signal and the error signal, and generate a second high-side control signal and a second low-side control signal for the power stage based on a comparison between the second ramp signal and the error signal.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics, and particularly to a control system for a three-level buck converter. Background Art

[0002] DC-DC converters are often used in modern electronic devices to provide the necessary voltage conversion for various applications. Buck converters are particularly utilized for their efficiency in stepping down voltages.

[0003] Two-level buck converters are widely used in low to medium power applications. However, as power demands increase, issues such as electromagnetic interference, switching losses, and the need for larger inductors and capacitors become more prominent. To address these concerns, three-level buck converters have been developed, which utilize additional switches and capacitors to generate an intermediate voltage level. This design reduces the voltage stress on each switch, thereby allowing the use of lower-rated and more efficient components.

[0004] Now refer to Figure 1 a known three-level buck converter 10. The three-level buck converter 10 includes: a first n-channel transistor MN1, whose drain is connected to the input voltage , and whose source is connected to a first tap TAP1; a second n-channel transistor MN2, whose drain is connected to the first tap TAP1, and whose source is connected to a second tap TAP2; a third n-channel transistor MN3, whose drain is connected to the second tap TAP2, and whose source is connected to a third tap TAP3; and a fourth n-channel transistor MN4, whose drain is connected to the third tap TAP3, and whose source is coupled to ground. The gates of the n-channel transistors MN1, MN2, MN3, MN4 are driven by respective control voltages HS1, HS2, LS2, LS1 generated by a logic / driver circuit 15 - the assertion of the control voltage HS1 turns on the transistor MN1, while the deassertion of the control voltage HS1 turns off the transistor MN1, the assertion of the control voltage HS2 turns on the transistor MN2, while the deassertion of the control voltage HS2 turns off the transistor MN2, the assertion of the control voltage LS2 turns on the transistor MN3, while the deassertion of the control voltage LS2 turns off the transistor MN3, and the assertion of the control voltage LS1 turns on the transistor MN4, while the deassertion of the control voltage LS1 turns off the transistor MN4.

[0005] Flying capacitor is connected between the first tap TAP1 and the third tap TAP3. An inductor L is connected between the second tap TAP2 and the output capacitor , and the output voltage is across the output capacitor is generated. The feedback voltage divider is formed by feedback resistors , which are connected in series between the output capacitor and ground, and a feedback voltage , is formed at the tap between the resistors .

[0006] The proportional integral derivative (PID) controller 14 receives the feedback voltage and a reference voltage as inputs, and generates an error voltage based on the difference between the feedback voltage and the reference voltage . The first comparator 11 receives the error voltage at its non-inverting input terminal, compares the error voltage with a first ramp signal RAMP1 from the ramp generator 13 received at its inverting input terminal, and provides an output OUT1 to the logic / driver circuit 15. The second comparator 12 receives the error voltage at its non-inverting input terminal, compares the error voltage with a second ramp signal RAMP2 from the ramp generator 13 received at its inverting input terminal, and provides an output OUT2 to the logic / driver circuit 15. The ramp signals RAMP1 and RAMP2 are 180º out of phase.

[0007] The operation with a duty cycle less than 50% (where ) includes three phases. In the first phase, the control voltages HS1 and LS2 are asserted, causing current to flow from through the transistor MN1, through the capacitor , and out through the transistor MN3 to the inductor L. As shown in the graph of Figures 2A - 2B , during this first phase, assuming , the voltage VLX formed at the second tap TAP2 is equal to half of the input voltage, i.e., , and the inductor current increases at a rate of . In the second phase, the control voltages LS1 and LS2 are asserted to turn on the transistors MN3 and MN4, causing the inductor L to discharge. As shown in the graph of Figures 2A - 2B , during this second phase, the voltage VLX is equal to 0 and the inductor current decreases at a rate of . In the third phase, the control voltages HS2 and LS1 are asserted to turn on the transistors MN2 and MN4, causing the flying capacitor to discharge to the inductor L. As shown in Figures 2A - 2BAs shown in the curve graph of , and the inductor current increases at a rate of .

[0008] As Figure 2C shown, the order of phase execution is Phase 1, Phase 2, Phase 3, Phase 2, Phase 1, Phase 2, Phase 3, Phase 2, and so on.

[0009] The operations with a duty cycle greater than 50% (where ) include the above-mentioned first and third phases, as well as the fourth phase. In the fourth phase, the control voltages HS1 and HS2 are asserted, resulting in current flowing from the input voltage through the transistor MN1, through the transistor MN2 to the inductor L.

[0010] As Figures 3A - 3B shown in the curve graph of , during this fourth phase, the voltage VLX formed at the second tap TAP2 is equal to the input voltage, that is, , and the inductor current increases at a rate of . During the first phase, the voltage VLX formed at the second tap TAP2 is , and the inductor current decreases at a rate of . During the third phase, the voltage VLX formed at the second tap TAP2 is , and the inductor current decreases at a rate of

[0011] As Figure 3C shown, the order of phase execution is Phase 4, Phase 1, Phase 4, Phase 3, Phase 4, Phase 1, Phase 4, Phase 3, and so on.

[0012] The advantages of a three-level buck converter (such as the three-level buck converter of Figure 1 ) are that, assuming the flying capacitor is maintained at a constant voltage of , then they can employ power MOSFETs MN1, MN2, MN3, MN4 with an absolute maximum rating (AMR) equivalent to . This not only improves the efficiency of the three-level converter but also allows the use of low-rated and thus potentially more economical power MOSFETs. The actual implementation incorporates safety margins to account for dynamic variations and provides the reliability of the three-level buck converter under fluctuating operating conditions. The deviation from the ideal conditions (where the voltage across the flying capacitor is not equal to the voltage across It may generate a suboptimal current waveform flowing through the inductor L, which may degrade the performance of the three-level buck converter.

[0013] Therefore, it is necessary to develop a technique for maintaining the voltage across the flying capacitor at Summary of the Invention

[0014] Disclosed herein is a DC-DC converter including a power stage that includes: a first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap; a flying capacitor coupled between the high-side tap and the low-side tap; an inductor coupled between the output tap and an output node; an output capacitor coupled between the output node and ground; and a feedback voltage divider coupled in parallel with the output capacitor, wherein a feedback voltage is formed at a tap of the feedback voltage divider. The DC-DC converter further includes a ramp generator configured to generate a first ramp signal and a second ramp signal, wherein the ramp generator generates the first ramp signal based on a constant reference voltage and generates the second ramp signal based on a difference between the voltage across the flying capacitor and half of the input voltage.

[0015] The control circuitry in the DC-DC converter is configured to: generate an error signal based on a comparison between the feedback voltage and a reference voltage; generate a first high-side control signal for the first high-side transistor and a first low-side control signal for the first low-side transistor based on a comparison between the first ramp signal and the error signal; and generate a second high-side control signal for the second high-side transistor and a second low-side control signal for the second low-side transistor based on a comparison between the second ramp signal and the error signal.

[0016] The ramp generator may be formed by a first ramp generation circuitry that includes: a first voltage-to-current converter configured to generate a first charging current based on a constant reference voltage; a first timing capacitor configured to receive the first charging current; and a first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated based on the charging and discharging of the first timing capacitor.

[0017] The first voltage-to-current converter may include: a first amplifier having a non-inverting input terminal receiving a constant reference voltage, an inverting input terminal coupled to ground through a first sense resistor, and an output terminal; a first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output terminal of the first amplifier, and a drain; a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor; a second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and a second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, the assertion of the first reset signal corresponding to a first edge of the clock signal.

[0018] The ramp generator may also have a second ramp generation circuitry that includes: a second voltage-to-current converter configured to generate a second charging current based on a difference between a voltage across a flying capacitor and half of an input voltage; a second timing capacitor configured to receive the second charging current; and a second reset transistor configured to discharge the second timing capacitor at a second edge of the clock signal; wherein a second ramp signal is generated in accordance with charging and discharging of the second timing capacitor.

[0019] The second voltage-to-current converter may include: a second amplifier having a non-inverting input terminal receiving a differential voltage, an inverting input terminal coupled to ground through a second sense resistor, and an output terminal, the slope of the differential voltage being proportional to a difference between half of the input voltage and the voltage across the flying capacitor; a third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output terminal of the second amplifier, and a drain; a third p-channel transistor having a source coupled to the supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor; a fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and a fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, the assertion of the second reset signal corresponding to a second edge of the clock signal.

[0020] A DC-DC converter may include a balancing circuit system having an amplifier with a first input terminal coupled to receive half of an input voltage, a second input terminal coupled through a balancing resistor to a voltage across a flying capacitor, and an output terminal coupled through a balancing capacitor to the second input terminal, wherein a differential voltage is generated at the output terminal of the amplifier, the differential voltage having a slope proportional to a difference between half of the input voltage and the voltage across the flying capacitor. A second voltage-to-current converter generates a second charging current based on the differential voltage.

[0021] A DC-DC converter may include a balancing circuit system having an amplifier with a non-inverting input terminal coupled to receive half of an input voltage, an inverting input terminal coupled through a balancing resistor to a voltage across a flying capacitor, and an output terminal coupled through a balancing capacitor to the inverting input terminal, wherein a differential voltage is generated at the output terminal of the amplifier, the differential voltage having a slope proportional to a difference between half of the input voltage and the voltage across the flying capacitor. A second voltage-to-current converter generates a second charging current based on the differential voltage.

[0022] Method aspects are disclosed. For example, a method of operating a DC-DC converter is disclosed herein, including: converting an input voltage to an output voltage using a power stage; generating a first ramp signal based on a constant reference voltage; generating a second ramp signal based on a difference between half of the input voltage and a voltage across a flying capacitor of the power stage; generating an error signal based on a comparison between the reference voltage and a feedback voltage representative of the output voltage; generating a first high-side control signal for a first high-side transistor of the power stage and a first low-side control signal for a first low-side transistor of the power stage based on a comparison between the first ramp signal and the error signal; and generating a second high-side control signal for a second high-side transistor of the power stage and a second low-side control signal for a second low-side transistor of the power stage based on a comparison between the second ramp signal and the error signal.

[0023] Generating the first ramp signal may include: generating a first charging current based on the constant reference voltage; receiving the first charging current at a first timing capacitor; and discharging the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated based on charging and discharging of the first timing capacitor.

[0024] Generating the second ramp signal may include: generating a second charging current based on the differential voltage, the slope of the differential voltage being proportional to a difference between half of the input voltage and the voltage across the flying capacitor; receiving the second charging current at a second timing capacitor; and discharging the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated based on charging and discharging of the second timing capacitor.

[0025] The present disclosure also discloses a DC-DC converter, including: a power stage configured to convert an input voltage into an output voltage using the power stage; and a ramp generator. The ramp generator is configured to: generate a first ramp signal based on a constant reference voltage; and generate a second ramp signal based on a difference between half of the input voltage and a voltage across a flying capacitor of the power stage. An error amplifier is configured to generate an error signal based on a comparison between a reference voltage and a feedback voltage representative of the output voltage. A control circuitry is configured to: generate a first high-side control signal for a first high-side transistor of the power stage and a first low-side control signal for a first low-side transistor of the power stage based on a comparison between the first ramp signal and the error signal; and generate a second high-side control signal for a second high-side transistor of the power stage and a second low-side control signal for a second low-side transistor of the power stage based on a comparison between the second ramp signal and the error signal.

[0026] The ramp generator can generate the first ramp signal by: generating a first charging current based on the constant reference voltage; receiving the first charging current at a first timing capacitor; and discharging the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated according to charging and discharging of the first timing capacitor.

[0027] The ramp generator can generate the second ramp signal by: generating a second charging current based on a differential voltage, the slope of which is proportional to a difference between half of the input voltage and a voltage across the flying capacitor; receiving the second charging current at a second timing capacitor; and discharging the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated according to charging and discharging of the second timing capacitor. Description of the Drawings

[0028] Figure 1 is a schematic block diagram of a known three-level buck converter.

[0029] Figure 2A is Figure 1 the inductor current curve of the three-level buck converter when operating with a duty cycle less than 50%.

[0030] Figure 2B is Figure 1 the voltage curve at a second tap node of the three-level buck converter when operating with a duty cycle less than 50%.

[0031] Figure 2C is a graph showing Figure 1 the ramp voltage, error signal, and gate control voltage of the three-level buck converter when operating with a duty cycle less than 50%.

[0032] Figure 3A Is Figure 1 A graph of the inductor current during operation of a three-level buck converter when the duty cycle is greater than 50%.

[0033] Figure 3B Is Figure 1 A graph of the voltage at the second tap node during operation of a three-level buck converter when the duty cycle is greater than 50%.

[0034] Figure 3C Shows Figure 1 A graph of the ramp voltage, error signal, and gate control voltage during operation of a three-level buck converter when the duty cycle is greater than 50%.

[0035] Figure 4 Can be used with Figure 1 A three-level buck converter to operate the three-level buck converter so that the voltage across the flying capacitor Is maintained at A schematic block diagram of a ramp generator.

[0036] Figure 5A Is at the flying capacitor Voltage across Lower than In the case of using Figure 4 The ramp generator of Figure 1 A graph of the ramp voltage and control signal of a three-level buck converter.

[0037] Figure 5B Is at the flying capacitor Voltage across Higher than In the case of using Figure 4 The ramp generator of Figure 1 A graph of the ramp voltage and control signal of a three-level buck converter. Detailed Description

[0038] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those described above without departing from the spirit and scope of this disclosure. It is not intended to limit this disclosure to the embodiments shown, but rather to give it the broadest scope consistent with the principles and features disclosed or suggested herein.

[0039] Note that in the descriptions given above or below, unless otherwise specified, any resistor or resistance mentioned is a discrete device, rather than just an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between these two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, any capacitor or capacitance mentioned is a discrete device, unless otherwise specified, and is not a parasitic element, unless otherwise specified. In addition, any inductor or inductance mentioned is a discrete device, unless otherwise specified, and is not a parasitic element, unless otherwise specified.

[0040] This text first refers to Figure 4 the ramp generator 13', which can be used with the three-level buck converter 10'. This ramp generator enables the three-level buck converter or any suitable three-level buck converter to maintain the voltage across the flying capacitor at an expected value. . Figure 4 The difference between the three-level buck converter 10' and Figure 1 the three-level buck converter 10 is that Figure 4 the three-level buck converter 10' includes the ramp generator 13' instead of the ramp generator 13.

[0041] The ramp generator 13' includes a first ramp generator circuit 16 for generating a first ramp signal RAMP1 and a second ramp generator circuit 17 for generating a second ramp signal RAMP2.

[0042] The first ramp generator circuit 16 includes an amplifier 21. The non-inverting input terminal of this amplifier is coupled to receive a fixed ramp reference voltage , its inverting input terminal is coupled to ground through a sense resistor , and its output terminal is connected to the gate of the n-channel transistor MN5. The source of the n-channel transistor MN5 is connected to the inverting input terminal of the amplifier 21, and its drain is connected to the drain and gate of the p-channel transistor MP1. The source of the p-channel transistor MP1 is coupled to the power supply voltage VCC, and its drain is connected to its gate and the drain of the n-channel transistor MN5. The source of the p-channel transistor MP2 is coupled to the power supply voltage VCC, its drain is coupled to ground through a timing capacitor , and its gate is connected to the gate of the p-channel transistor MP1. The drain of the n-channel transistor MN6 is connected to the drain of the p-channel transistor MP2, its source is coupled to ground, and its gate is coupled to the first reset signal RESET1.

[0043] The second ramp generator circuit 17 includes an amplifier 22 having a non-inverting input coupled to receive a voltage DELTA (difference) having a slope similar to the desired voltage and flying capacitors The voltage across The inverting input of amplifier 22 is connected via a sensing resistor The output terminal of the n-channel transistor MN7 is coupled to ground. The source of the n-channel transistor MN7 is connected to the inverting input terminal of the amplifier 22, and the drain thereof is connected to the drain and gate of the p-channel transistor MP3. The source of the p-channel transistor MP3 is coupled to the power supply voltage VCC, and the drain thereof is connected to its gate and the drain of the n-channel transistor MN7. The source of the p-channel transistor MP4 is coupled to the power supply voltage VCC, and the drain thereof is connected to the gate of the n-channel transistor MN7 through the timing capacitor. The drain of the N-channel transistor MN8 is connected to the drain of the p-channel transistor MP4, the source of the N-channel transistor MN8 is coupled to the ground, and the gate of the N-channel transistor MN8 is coupled to the gate of the p-channel transistor MP3.

[0044] The voltage DELTA is generated by a balancing circuit 25. The balancing circuit 25 comprises an amplifier 23, whose inverting input terminal is coupled to a resistor Receiving voltage , whose non-inverting input is coupled to receive the desired voltage , and its output is connected to the inverting input of amplifier 22 to provide DELTA thereto. Feedback capacitor Connected between the inverting input terminal and the output terminal of the amplifier 23.

[0045] Now describe Figure 4 The logic / driver circuit system 15 generates the control voltages HS1, HS2, LS1, LS2. The comparator 11 receives the error voltage at its non-inverting input terminal. , receiving the first ramp signal RAMP1 at its inverting input terminal, and providing an output to the logic / driver circuit system 15, which is based on The comparison between and RAMP1 generates a control voltage HS1, and generates a control voltage LS1 which is the inverse of the control voltage HS1. The comparator 12 receives the error voltage at its non-inverting input terminal. , receiving the second ramp signal RAMP2 at its inverting input terminal, and providing an output to the logic / driver circuit system 15, which is based on Comparison between RAMP2 and control voltage HS2 is performed to generate control voltage LS2, which is the inverse of control voltage HS2.

[0046] In operation, the arrangement of the amplifier 21 and the n-channel transistor MN5 acts as a voltage-to-current converter, where the n-channel transistor MN5 sinks a current equal to . The current sunk by the n-channel transistor MN5 is mirrored by the current mirror arrangement of the p-channel transistors MP1 and MP2 to generate a charging current . Beginning with the de-assertion of the reset signal RESET1 (which may occur on the rising or falling edge of the clock signal), the charging current charges the timing capacitor . Due to the above voltage-to-current converter arrangement, the charging current is equal to , and charges the timing capacitor until the reset signal RESET is asserted at the next edge of the clock signal.

[0047] The peak voltage of the first ramp signal RAMP1 reached during the cycle can be calculated as , where is the switching period of the clock signal (and thus the reset signal RESET1).

[0048] The arrangement of the amplifier 22 and the n-channel transistor MN7 acts as a voltage-to-current converter, where the n-channel transistor MN7 sinks a current equal to . The current sunk by the n-channel transistor MN7 is mirrored by the current mirror arrangement of the p-channel transistors MP3 and MP4 to generate a charging current . Beginning with the de-assertion of the reset signal RESET2 (which may occur on the falling or rising edge of the clock signal, where RESET2 is opposite to RESET1), the charging current charges the timing capacitor . The charging current is equal to , and charges the timing capacitor until the reset signal RESET2 is asserted at the next edge of the clock signal.

[0049] The peak voltage of the second ramp signal RAMP2 reached during the cycle can be calculated as , where is the switching period of the clock signal (and thus the reset signal RESET2).

[0050] As can be seen from the above, the first ramp signal RAMP1 has a fixed amplitude because it is based on the ramp reference voltage which is a fixed signal generated, while the second ramp signal RAMP2 has a variable amplitude proportional to DELTA. This generation of the second ramp signal RAMP2 proportional to DELTA (where DELTA itself has a slope proportional to the difference between the desired voltage and the flying capacitor voltage across the ends provides correction for the mismatch between the first ramp signal RAMP1 and the second ramp signal RAMP2 due to process, device variations, etc.

[0051] For example, if the voltage across the flying capacitor ends is lower than , then DELTA will increase, and as a result, the amplitude of the ramp signal RAMP2 will be higher than the amplitude of RAMP1, thus having the effect that the pulse widths of the control voltages HS1, LS1 are wider than the pulse widths of the control voltages HS2, LS2. Therefore, the charging phase of the first ramp generator circuit 16 will be longer than the discharging phase of the second ramp generator circuit 17, resulting in an increase in the voltage across the flying capacitor ends until this voltage is equal to .

[0052] This condition (where the voltage across the flying capacitor ends is lower than ) operation is shown in the graph of Figure 5A , where the above effects on the control voltages HS2, LS2 and the ramp signal RAMP2 can be observed.

[0053] Conversely, if the voltage across the flying capacitor ends is higher than , then DELTA will decrease, and as a result, the amplitude of the ramp signal RAMP2 will be lower than the amplitude of the ramp signal RAMP1, thus having the effect that the pulse widths of the control voltages HS2, LS2 are wider than the pulse widths of the control voltages HS1, LS1. Therefore, the discharging phase of the second ramp generator circuit 17 will be longer than the charging phase of the first ramp generator circuit 16, resulting in a decrease in the voltage across the flying capacitor ends until this voltage is equal to .

[0054] This condition (where the voltage across the flying capacitor ends is higher than ) operation is shown in Figure 5Bis shown in the graph, where the above-mentioned effects on the control voltages HS2, LS2 and the ramp signal RAMP2 can be observed.

[0055] When a steady state is achieved, the voltage DELTA will be substantially equal to the ramp reference voltage, except for the mismatch between the two ramp generators 16 and 17. .

[0056] Using the ramp generator 13' provides for maintaining the voltage across the flying capacitor at , which is desirable, as explained above, for efficiency reasons and for the normal performance of the three-level buck converter.

[0057] Obviously, modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the disclosure. For example, the ramp generator 13' described herein can be used with other types of three-level DC-DC converters, such as a three-level boost converter.

[0058] Although the disclosure has been described by way of a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, can envision other embodiments that do not deviate from the disclosed scope. In addition, those skilled in the art can envision embodiments representing various combinations of the disclosed embodiments herein.

Claims

1. A DC-DC converter, comprising: A power stage, comprising: A first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap; A flying capacitor coupled between the high-side tap and the low-side tap; An inductor coupled between the output tap and an output node; An output capacitor coupled between the output node and ground; and A feedback voltage divider coupled in parallel with the output capacitor, wherein a feedback voltage is formed at a tap of the feedback voltage divider; A ramp generator configured to generate a first ramp signal and a second ramp signal, wherein the ramp generator generates the first ramp signal based on a constant reference voltage, and generates the second ramp signal based on a difference between a voltage across the flying capacitor and half of the input voltage; A control circuitry configured to: Generate an error signal based on a comparison between the feedback voltage and a reference voltage; Generate a first high-side control signal for the first high-side transistor and a first low-side control signal for the first low-side transistor based on a comparison between the first ramp signal and the error signal; and Generate a second high-side control signal for the second high-side transistor and a second low-side control signal for the second low-side transistor based on a comparison between the second ramp signal and the error signal.

2. The DC-DC converter according to claim 1, wherein the ramp generator comprises: A first ramp generation circuitry, comprising: A first voltage-to-current converter configured to generate a first charging current based on a constant reference voltage; A first timing capacitor configured to receive the first charging current; and A first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal; Wherein the first ramp signal is generated based on charging and discharging of the first timing capacitor.

3. The DC-DC converter according to claim 2, wherein the first voltage-to-current converter comprises: A first amplifier having a non-inverting input terminal receiving the constant reference voltage, an inverting input terminal coupled to ground through a first sense resistor, and an output terminal; A first n-channel transistor having a source terminal coupled to ground through the first sense resistor, a gate terminal coupled to the output terminal of the first amplifier, and a drain terminal; A first p-channel transistor having a source terminal coupled to a supply voltage, a drain terminal coupled to the drain terminal of the first n-channel transistor, and a gate terminal coupled to the drain terminal of the first p-channel transistor; A second p-channel transistor having a source terminal coupled to the supply voltage, a drain terminal coupled to the first timing capacitor, and a gate terminal coupled to the gate terminal of the first p-channel transistor; And A second n-channel transistor having a drain terminal coupled to the first timing capacitor, a source terminal coupled to ground, and a gate terminal coupled to a first reset signal, an assertion of the first reset signal corresponding to the first edge of the clock signal.

4. The DC-DC converter according to claim 2, wherein the ramp generator further comprises: A second ramp generation circuitry, comprising: A second voltage-to-current converter configured to generate a second charging current based on a difference between a voltage across a flying capacitor and half of an input voltage; A second timing capacitor configured to receive the second charging current; and A second reset transistor configured to discharge the second timing capacitor at a second edge of a clock signal; wherein a second ramp signal is generated in accordance with charging and discharging of the second timing capacitor.

5. The DC-DC converter of claim 4, wherein the second voltage-to-current converter comprises: A second amplifier having a non-inverting input terminal receiving a differential voltage, an inverting input terminal coupled to ground through a second sense resistor, and an output terminal, the slope of the differential voltage being proportional to a difference between half of the input voltage and the voltage across the flying capacitor; A third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output terminal of the second amplifier, and a drain; A third p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor; A fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and A fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, an assertion of the second reset signal corresponding to the second edge of the clock signal.

6. The DC-DC converter of claim 4, further comprising a balance circuitry including an amplifier having a first input terminal coupled to receive half of the input voltage, a second input terminal coupled to the voltage across the flying capacitor through a balance resistor, and an output terminal coupled to the second input terminal through a balance capacitor, wherein a differential voltage is generated at the output terminal of the amplifier, the differential voltage having a slope proportional to a difference between half of the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based on the differential voltage.

7. The DC-DC converter of claim 4, further comprising a balance circuitry including an amplifier having a non-inverting input terminal coupled to receive half of the input voltage, an inverting input terminal coupled to the voltage across the flying capacitor through a balance resistor, and an output terminal coupled to the inverting input terminal through a balance capacitor, wherein a differential voltage is generated at the output terminal of the amplifier, the differential voltage having a slope proportional to a difference between half of the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based on the differential voltage.

8. A method of operating a DC-DC converter, the method comprising: Converting an input voltage to an output voltage using a power stage; Generating a first ramp signal based on a constant reference voltage; Generating a second ramp signal based on a difference between half of the input voltage and the voltage across a flying capacitor of the power stage; An error signal is generated based on a comparison between a reference voltage and a feedback voltage representative of an output voltage; Based on a comparison between a first ramp signal and the error signal, a first high-side control signal is generated for a first high-side transistor of a power stage, and a first low-side control signal is generated for a first low-side transistor of the power stage; and Based on a comparison between a second ramp signal and the error signal, a second high-side control signal is generated for a second high-side transistor of the power stage, and a second low-side control signal is generated for a second low-side transistor of the power stage.

9. The method according to claim 8, wherein generating the first ramp signal includes: Generating a first charging current based on a constant reference voltage; Receiving the first charging current at a first timing capacitor; and Discharging the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated based on the charging and discharging of the first timing capacitor.

10. The method according to claim 9, wherein generating the second ramp signal includes: Generating a second charging current based on a differential voltage, the slope of which is proportional to the difference between half of the input voltage and the voltage across a flying capacitor; Receiving the second charging current at a second timing capacitor; Discharging the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated based on the charging and discharging of the second timing capacitor.

11. A DC-DC converter, comprising: A power stage configured to convert an input voltage to an output voltage using the power stage; A ramp generator configured to: Generate a first ramp signal according to a constant reference voltage; and Generate a second ramp signal according to the difference between half of the input voltage and the voltage across a flying capacitor of the power stage; An error amplifier configured to generate an error signal based on a comparison between a reference voltage and a feedback voltage representative of an output voltage; and A control circuitry configured to: Based on a comparison between the first ramp signal and the error signal, generate a first high-side control signal for a first high-side transistor of the power stage, and generate a first low-side control signal for a first low-side transistor of the power stage; and Based on a comparison between the second ramp signal and the error signal, generate a second high-side control signal for a second high-side transistor of the power stage, and generate a second low-side control signal for a second low-side transistor of the power stage.

12. The DC-DC converter according to claim 11, wherein the ramp generator generates the first ramp signal by: Generating a first charging current based on a constant reference voltage; Receiving a first charging current at a first timing capacitor; and Discharging a first timing capacitor at a first edge of a clock signal; and wherein the first ramp signal is generated based on the charging and discharging of the first timing capacitor.

13. The DC-DC converter according to claim 12, wherein the ramp generator generates the second ramp signal by: Generating a second charging current based on a differential voltage, the slope of which is proportional to the difference between half of the input voltage and the voltage across a flying capacitor; Receive a second charging current at a second timing capacitor; and Discharging a second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated based on the charging and discharging of the second timing capacitor.

14. A DC-DC converter, comprising: A power stage, comprising: A first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap; A flying capacitor coupled between the high-side tap and the low-side tap; An inductor coupled between the output tap and an output node; An output capacitor coupled between the output node and ground; and A feedback voltage divider coupled in parallel with the output capacitor, wherein a feedback voltage is formed at a tap of the feedback voltage divider; A ramp generator, comprising: A first ramp generation circuitry, comprising: A first voltage-to-current converter configured to generate a first charging current based on a constant reference voltage; A first timing capacitor configured to receive the first charging current; and A first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal; Wherein a first ramp signal is generated according to charging and discharging of the first timing capacitor; and Wherein the first voltage-to-current converter comprises: A first amplifier having a non-inverting input terminal receiving the constant reference voltage, an inverting input terminal coupled to ground through a first sense resistor, and an output terminal; A first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output terminal of the first amplifier, and a drain; A first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor; A second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and A second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, an assertion of the first reset signal corresponding to the first edge of the clock signal; A second ramp generation circuitry, comprising: A second voltage-to-current converter configured to generate a second charging current based on a difference between a voltage across the flying capacitor and half of the input voltage; A second timing capacitor configured to receive the second charging current; and A second reset transistor configured to discharge the second timing capacitor at a second edge of the clock signal; Wherein a second ramp signal is generated according to charging and discharging of the second timing capacitor; Wherein the second voltage-to-current converter comprises: A second amplifier having a non-inverting input terminal receiving a differential voltage, an inverting input terminal coupled to ground through a second sense resistor, and an output terminal, the differential voltage slope being proportional to a difference between half of the input voltage and the voltage across the flying capacitor; A third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output terminal of the second amplifier, and a drain; A third p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor; A fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and A fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, the assertion of the second reset signal corresponding to a second edge of the clock signal; A control circuitry configured to: Generate an error signal based on a feedback voltage and a reference voltage; Generate a first high-side control signal for a first high-side transistor and a first low-side control signal for a first low-side transistor based on a first ramp signal and the error signal; and Generate a second high-side control signal for a second high-side transistor and a second low-side control signal for a second low-side transistor based on a second ramp signal and the error signal.

15. The DC-DC converter of claim 14, further comprising a balancing circuitry including an amplifier having a first input terminal coupled to receive half of an input voltage, a second input terminal coupled to a voltage across a flying capacitor through a balancing resistor, and an output terminal coupled to the second input terminal through a balancing capacitor, wherein a differential voltage is generated at the output terminal of the amplifier, the differential voltage having a slope proportional to a difference between half of the input voltage and the voltage across the flying capacitor; and wherein a second voltage-to-current converter generates a second charging current based on the differential voltage.

16. The DC-DC converter of claim 14, further comprising a balancing circuitry including an amplifier having a non-inverting input terminal coupled to receive half of an input voltage, an inverting input terminal coupled to a voltage across a flying capacitor through a balancing resistor, and an output terminal coupled to the inverting input terminal through a balancing capacitor, wherein a differential voltage is generated at the output terminal of the amplifier, the differential voltage having a slope proportional to a difference between half of the input voltage and the voltage across the flying capacitor; and wherein a second voltage-to-current converter generates a second charging current based on the differential voltage.

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