Single-pole double-throw switch with high power processing capability

Abstract

The embodiment of the invention provides a single-pole double-throw switch with high power processing capability, which belongs to the technical field of radio frequency chip power amplifiers and comprises a first coupling line, a second coupling line, an antenna end, a receiving end, a transmitting end, a first switch transistor and a second switch transistor, wherein the first end of the first coupling line is electrically connected with the first switch transistor, the second end of the first coupling line is electrically connected with the antenna end, the third end of the first coupling line is grounded, the fourth end of the first coupling line is electrically connected with the receiving end, and the first end of the second coupling line is electrically connected with the second switch transistor; the second end of the second coupling line is electrically connected with the antenna end, the third end of the second coupling line is grounded, the fourth end of the second coupling line is electrically connected with the transmitting end, and when the first switching transistor is in a conducting state, the first coupling line and the first switching transistor form a band-pass filtering network structure, so that signals are transmitted between the antenna end and the receiving end. According to the invention, the power processing capability of the single-pole double-throw switch can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency chip power amplifiers, and more particularly to a single-pole double-throw switch with high power handling capability. Background Art

[0002] With the rapid development of mobile communication technology, the number of wireless communication channels is increasing continuously, the radio frequency signal path becomes more complex, and at the same time, the power and frequency of radio frequency signals are also gradually increasing. As a key component of the radio frequency front-end, the single-pole double-throw switch used in the radio frequency field needs to have characteristics such as low insertion loss, high isolation, and high power handling capability.

[0003] In the related art, with the continuous progress and maturity of complementary metal oxide semiconductor technology, the application of CMOS technology in the field of radio frequency switches has gradually attracted attention. However, the single-pole double-throw switch based on CMOS technology has significant deficiencies in power handling capability, especially when the operating frequency reaches the E-band or W-band, this problem is more prominent. The power handling capability of the radio frequency switch has a great impact on the performance of the receiver. Therefore, there is an urgent need for a single-pole double-throw switch with strong power handling capability. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to propose a single-pole double-throw switch with high power handling capability, aiming to improve the power handling capability of the single-pole double-throw switch.

[0005] To achieve the above object, the first aspect of the embodiments of the present application proposes a single-pole double-throw switch with high power handling capability, including: a first coupled line, a second coupled line, an antenna terminal, a receiving terminal, a transmitting terminal, a first switching transistor, and a second switching transistor;

[0006] Wherein, the first end of the first coupled line is electrically connected to the first switching transistor, the second end of the first coupled line is electrically connected to the antenna terminal, the third end of the first coupled line is grounded, the fourth end of the first coupled line is electrically connected to the receiving terminal, the first end of the second coupled line is electrically connected to the second switching transistor, the second end of the second coupled line is electrically connected to the antenna terminal, the third end of the second coupled line is grounded, the fourth end of the second coupled line is electrically connected to the transmitting terminal. When the first switching transistor is in the conducting state, the first coupled line and the first switching transistor form a band-pass filter network structure to enable signals to be transmitted between the antenna terminal and the receiving terminal. When the second switching transistor is in the conducting state, the second coupled line and the second switching transistor form a band-pass filter network structure to enable signals to be transmitted between the antenna terminal and the transmitting terminal.

[0007] In some embodiments, it further includes a first control voltage terminal. The first switching transistor includes a source, a drain, and a gate. Wherein, the source of the first switching transistor is grounded, the drain of the first switching transistor is electrically connected to the first end of the first coupling line, and the gate of the first switching transistor is electrically connected to the first control voltage terminal.

[0008] In some embodiments, it further includes a second control voltage terminal. The second switching transistor includes a source, a drain, and a gate. Wherein, the source of the second switching transistor is grounded, the drain of the second switching transistor is electrically connected to the first end of the second coupling line, and the gate of the second switching transistor is electrically connected to the second control voltage terminal.

[0009] In some embodiments, when the first switching transistor is in the cut-off state, the first coupling line and the first switching transistor form a band-stop filter network structure, so that the signal transmission between the antenna terminal and the receiving terminal is blocked.

[0010] In some embodiments, when the second switching transistor is in the on state, the second coupling line and the second switching transistor form a band-stop filter network structure, so that the signal transmission between the antenna terminal and the transmitting terminal is blocked.

[0011] In some embodiments, the single-pole double-throw switch is implemented using complementary metal-oxide-semiconductor technology and includes an eight-layer metal structure, which are, in sequence, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a local interconnect layer, a capping layer, a capping antireflection layer, and a bottom antireflection layer;

[0012] Wherein, the first coupling line and the second coupling line are constructed using the local interconnect layer, and metal walls are constructed around the first coupling line and the second coupling line by stacking metal layers.

[0013] In some embodiments, the first coupling line and the first switching transistor are symmetric with respect to the second coupling line and the second switching transistor about the antenna terminal.

[0014] In some embodiments, the voltage at the first ends of the first coupling line and the second coupling line is less than the voltage at the second ends.

[0015] In some embodiments, the operating frequency range of the single-pole double-throw switch is from 70 GHz to 110 GHz, the insertion loss is less than 2.5 dB, and the isolation is greater than 30 dB.

[0016] In some embodiments, the 1 dB gain compression point of the single-pole double-throw switch reaches or exceeds 17 dBm.

[0017] The single-pole double-throw switch with high power handling capacity proposed in this application includes a first coupled line, a second coupled line, an antenna terminal, a receiving terminal, a transmitting terminal, a first switching transistor, and a second switching transistor. When the first switching transistor is in the on state, the first coupled line and the first switching transistor form a band-pass filter network structure to enable signal transmission between the antenna terminal and the receiving terminal. When the second switching transistor is in the on state, the second coupled line and the second switching transistor form a band-pass filter network structure to enable signal transmission between the antenna terminal and the transmitting terminal. The combination of the coupled line and the switching transistor realizes the band-pass filtering function in different states, ensuring efficient signal transmission between the antenna terminal and the receiving terminal or the transmitting terminal. The switching transistor conducts signal transmission in the on state, avoiding the power limitation problem caused by the open state in the traditional design and reducing signal leakage caused by parasitic effects, thereby greatly improving the power handling capacity of the single-pole double-throw switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. is a schematic diagram of the single-pole double-throw switch with high power handling capacity provided by an embodiment of the present application;

[0019] Figure 2 FIG. is another schematic diagram of the single-pole double-throw switch with high power handling capacity provided by an embodiment of the present application;

[0020] Figure 3 FIG. is another schematic diagram of the single-pole double-throw switch with high power handling capacity provided by an embodiment of the present application;

[0021] Figure 4 FIG. is a schematic diagram of the relationship between transmission impedance and electrical length provided by an embodiment of the present application;

[0022] Figure 5 FIG. is a schematic diagram of the insertion loss of the single-pole double-throw switch with high power handling capacity provided by an embodiment of the present application;

[0023] Figure 6 FIG. is a schematic diagram of the isolation of the single-pole double-throw switch with high power handling capacity provided by an embodiment of the present application;

[0024] Figure 7 FIG. is a schematic diagram of the power handling capacity of the single-pole double-throw switch with high power handling capacity provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] It should be noted that although the functional modules are divided in the device schematic diagram and the logical sequence is shown in the flowchart, in some cases, the steps shown or described can be executed in a different module division in the device or a different order in the flowchart. Terms such as "first" and "second" in the specification, claims and the above-mentioned drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0028] With the development of mobile communication technology, the number of wireless communication channels is increasing continuously, the radio frequency (RF) signal path is more complex, and the power and frequency of RF signals are also increasing continuously. As a key component of the RF front-end, the RF switch is required to have low insertion loss, high isolation, and high power handling ability, etc., and usually the performance of the switch needs to be balanced during design.

[0029] Currently, most high-frequency and high-performance RF integrated circuits adopt technologies such as GaAs and SiGe to implement. However, with the continuous progress and maturity of the CMOS process, the design of a single-pole double-throw (SPDT) switch using the CMOS process has been achieved. The emergence of CMOS on insulator (CMOS SOI) has solved the loss problem and latch-up effect caused by the substrate parasitic effect that cannot be solved by the traditional CMOS process, and its integration density is much higher than that of the GaAs and SiGe processes. However, the power handling ability of the existing SPDT switch based on the CMOS process is very limited, especially when the operating frequency reaches the E or W band. The power handling ability of the RF switch has a great impact on the performance of the receiver. The intermodulation generated by the received signal of the switch and the external strong interference signal is likely to cause interference and even block the receiving channel, directly affecting the linearity of the RF receiver.

[0030] For the E band and above, one of the main influencing factors of the power handling ability of the CMOS SPDT switch is caused by the low threshold voltage of the scaled CMOS device. In addition, the architecture of parallel transistors and quarter-wavelength lines has been widely used in the design of SPDT switches for the E band and above. The main limitation of this method for power handling ability is due to the capacitive voltage division at the gate by the voltage at the TX port through the parasitic capacitance. When the voltage at the gate of the switch transistor becomes large enough, the parasitic diode associated with the transistor starts to conduct, and provides a serious leakage path for the signal. Therefore, this method inevitably results in poor power handling ability. Therefore, the design of a high-power handling ability switch based on the CMOS process for the E band and above faces great challenges.

[0031] Based on this, the embodiments of the present application provide a single-pole double-throw switch with high power handling capability, aiming to improve the power handling capability of the single-pole double-throw switch.

[0032] The single-pole double-throw switch with high power handling capability provided by the embodiments of the present application will be specifically described through the following embodiments.

[0033] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the single-pole double-throw switch with high power handling capability provided by the embodiments of the present application, including: a first coupling line 101, a second coupling line 102, an antenna terminal 103, a receiving terminal 104, a transmitting terminal 105, a first switching transistor 106, and a second switching transistor 107.

[0034] Among them, the first end of the first coupling line 101 is electrically connected to the first switching transistor 106, the second end of the first coupling line 101 is electrically connected to the antenna terminal 103, the third end of the first coupling line 101 is grounded, the fourth end of the first coupling line 101 is electrically connected to the receiving terminal 104, the first end of the second coupling line 102 is electrically connected to the second switching transistor 107, the second end of the second coupling line 102 is electrically connected to the antenna terminal 103, the third end of the second coupling line 102 is grounded, the fourth end of the second coupling line 102 is electrically connected to the transmitting terminal 105. When the first switching transistor 106 is in the conducting state, the first coupling line 101 and the first switching transistor 106 form a band-pass filter network structure to enable signals to be transmitted between the antenna terminal 103 and the receiving terminal 104. When the second switching transistor 107 is in the conducting state, the second coupling line 102 and the second switching transistor 107 form a band-pass filter network structure to enable signals to be transmitted between the antenna terminal 103 and the transmitting terminal 105.

[0035] It can be understood that the first coupling line 101, as a part of the signal transmission path, its first end is electrically connected to the first switching transistor 106 to control the conduction and cut-off of the signal; the second end is connected to the antenna terminal 103 to achieve signal interaction with the antenna; the third end is grounded to provide a stable reference potential; the fourth end is connected to the receiving terminal 104 to transmit the signal to the receiving terminal. The second coupling line 102 is similar in function to the first coupling line 101. Its first end is electrically connected to the second switching transistor 107, the second end is also connected to the antenna terminal 103, the third end is grounded, and the fourth end is connected to the transmitting terminal 105 to transmit the signal to the transmitting terminal.

[0036] Exemplarily, the antenna terminal 103 serves as the input / output port of the signal and is connected to the second ends of the first coupling line 101 and the second coupling line 102, responsible for receiving or transmitting radio frequency signals. The first switching transistor 106 controls the signal transmission of the first coupling line 101 through its on and off states. When the first switching transistor 106 is turned on, the first coupling line 101 forms a band-pass filter network structure with it, enabling the signal to be efficiently transmitted between the antenna terminal 103 and the receiving terminal 104.

[0037] Exemplarily, the second switching transistor 107 is similar to the first switching transistor 106. When it is turned on, the second coupling line 102 forms a band-pass filter network structure with it, enabling the signal to be efficiently transmitted between the antenna terminal 103 and the transmitting terminal 105.

[0038] The single-pole double-throw switch with high power handling capacity proposed in this application includes a first coupling line, a second coupling line, an antenna terminal, a receiving terminal, a transmitting terminal, a first switching transistor, and a second switching transistor. When the first switching transistor is in the on state, the first coupling line and the first switching transistor form a band-pass filter network structure to enable signal transmission between the antenna terminal and the receiving terminal. When the second switching transistor is in the on state, the second coupling line and the second switching transistor form a band-pass filter network structure to enable signal transmission between the antenna terminal and the transmitting terminal. The combination of the coupling line and the switching transistor realizes the band-pass filtering function in different states, ensuring efficient signal transmission between the antenna terminal and the receiving terminal or the transmitting terminal. The switching transistor conducts signal transmission in the on state, avoiding the power limitation problem caused by the open state in the traditional design and reducing signal leakage caused by parasitic effects, thereby greatly improving the power handling capacity of the single-pole double-throw switch.

[0039] Please refer to Figure 2 , in some embodiments, the single-pole double-throw switch with high power handling capacity proposed in this embodiment further includes a first control voltage terminal 201. The first switching transistor 106 includes a source, a drain, and a gate. Among them, the source of the first switching transistor 106 is grounded, the drain of the first switching transistor 106 is electrically connected to the first end of the first coupling line 101, and the gate of the first switching transistor 106 is electrically connected to the first control voltage terminal 201.

[0040] It can be understood that the first control voltage terminal 201 serves as the input terminal of the external control signal, used to adjust the on and off states of the first switching transistor 106. By applying different control voltages, the switching behavior of the first switching transistor 106 can be precisely controlled, thereby realizing the dynamic switching of the signal path. The design of this control voltage terminal enables the single-pole double-throw switch to be flexibly adjusted according to different application scenarios and working modes, further optimizing the performance of the switch.

[0041] Exemplarily, the first switching transistor 106, as the core component of the switch, has a structure including a source electrode, a drain electrode, and a gate electrode. The source electrode is grounded to provide a stable reference potential for the switching transistor, ensuring the stability and reliability of signal transmission. The grounded source electrode can also effectively reduce the influence of parasitic effects and reduce losses and interference during signal transmission. The drain electrode is electrically connected to the first end of the first coupling line 101. The drain electrode serves as the outlet for signal transmission. Through the connection with the first coupling line 101, efficient transmission of the signal from the switching transistor to the coupling line is achieved. This connection method ensures that the signal can smoothly enter the coupling line when the switch is turned on and is transmitted through the coupling line to the antenna terminal 103 or the receiving terminal 104. The gate electrode is electrically connected to the first control voltage terminal 201. The gate electrode is the key part for controlling the conduction and cutoff of the switching transistor. By applying a control voltage through the first control voltage terminal 201, the potential of the gate electrode can be adjusted, thereby controlling the switching state of the first switching transistor 106. When an appropriate voltage is applied to the gate electrode, the first switching transistor 106 conducts, and the signal can be transmitted between the antenna terminal 103 and the receiving terminal 104; when the gate voltage changes, the first switching transistor 106 cuts off, and the signal transmission path is cut off, thus realizing flexible switching of the signal path.

[0042] Please refer to Figure 2 , in some embodiments, the single-pole double-throw switch with high power handling capability proposed in this embodiment further includes a second control voltage terminal 202. The second switching transistor 107 includes a source electrode, a drain electrode, and a gate electrode. Among them, the source electrode of the second switching transistor 107 is grounded, the drain electrode of the second switching transistor 107 is electrically connected to the first end of the second coupling line 102, and the gate electrode of the second switching transistor 107 is electrically connected to the second control voltage terminal 202.

[0043] It can be understood that the single-pole double-throw switch with high power handling capability proposed in this embodiment has a structure that is symmetric about the antenna port. Therefore, similar to the first control voltage terminal 201, the second control voltage terminal 202 controls the conduction and cutoff states of the second switching transistor 107 by applying different voltage signals. When the second switching transistor 107 conducts, the second coupling line 102 forms a band-pass filter network structure with it, and the signal can be efficiently transmitted between the antenna terminal 103 and the transmitting terminal 105. At this time, the characteristic impedance of the second coupling line 102 matches the signal frequency, ensuring low loss and high efficiency of signal transmission. When the second switching transistor 107 cuts off, the signal transmission path is cut off, and high isolation is achieved between the antenna terminal 103 and the transmitting terminal 105, avoiding signal leakage and interference.

[0044] It can be understood that since the single-pole double-throw switch with high power handling capability proposed in this embodiment has a structure that is symmetric about the antenna port, for the sake of simplicity in analysis, half of the structure is extracted for theoretical analysis. Please refer to Figure 3, the coupled line has four ports. Port 1 (301) is the first end of the first coupled line or the second coupled line, port 2 (302) is the antenna port, port 3 (303) is the third end of the first coupled line or the second coupled line, port 4 (304) is the transmitting or receiving port, and 305 is the first control voltage port or the second control voltage port.

[0045] Exemplarily, the voltages and currents at the first end of the first coupled line or the second coupled line to the transmitting or receiving port can be written as V1 to V4 and I1 to I1 respectively. The admittance matrix of the coupled line structure with all ports open can be expressed as:

[0046]

[0047] Wherein,

[0048] Y 11 = Y 22 = Y 33 = Y 44 = -j / 2(Y oo + Y oe )cotθ

[0049] Y 12 = Y 21 = Y 34 = Y 43 = -j / 2(Y oo - Y oe )cotθ

[0050] Y 13 = Y 31 = Y 24 = Y 42 = -j / 2(Y oo - Y oe )cscθ

[0051] Y 14 = Y 41 = Y 23 = Y 32 = -j / 2(Y oo + Y oe )cscθ

[0052] Wherein, Y cl represents the admittance matrix, Y ii represents the self-admittance of port i. When other ports except port i are short-circuited, it is the ratio of current to voltage; Y ij represents the mutual admittance between port i and port j. When other ports except port j are short-circuited, it is the ratio of the current at port i to the voltage at port j; Yoo is the odd-mode admittance; Yoe is the even-mode admittance; θ is the electrical length.

[0053] When the switching transistor is in the closed state, port 1 can be regarded as short-circuited, so there is V1 = V3 = 0. The four-port admittance matrix equation will be simplified to:

[0054] I2 = Y 22 V2 + Y 24 V4

[0055] I4 = Y 24 V2 + Y 44 V4

[0056] Therefore, the impedances at port 2 and port 4 can be expressed as:

[0057]

[0058] where Zoo is the odd-mode impedance; Zoe is the even-mode impedance; Zoe and Zoo are selected as 100 Ω and 50 Ω.

[0059] Please refer to Figure 4 , it can be understood that when θ1 < θ < θ2, the value of Z iT is greater than 0, and the lowest point value appears at the center frequency point of θ = 90°. Obviously, when the electrical length of the coupled line is selected as a quarter wavelength and the input impedance is matched, this structure can be used as a band-pass filter network, so in this case the signal will be completely transmitted.

[0060] In some embodiments, when the first switching transistor 106 is in the cut-off state, the first coupled line 101 and the first switching transistor 106 form a band-stop filter network structure, so that the signal transmission between the antenna terminal 103 and the receiving terminal 104 is blocked.

[0061] In some embodiments, when the second switching transistor 107 is in the conducting state, the second coupled line 102 and the second switching transistor 107 form a band-stop filter network structure, so that the signal transmission between the antenna terminal 103 and the transmitting terminal 105 is blocked.

[0062] It can be understood that when the first switching transistor 106 or the second switching transistor 107 is in the open state, Figure 3 port 1 in

[0063]

[0064] can be regarded as open-circuited. In this case, I1 = 0, V3 = 0. Therefore, the impedances at port 2 and port 4 can be expressed as: i2 and Z i4is a pure imaginary number. Therefore, at any θ, the impedances at Port 2 and Port 4 are equal to 0. Thus, when the switching transistor is in the "on" state, the single-pole double-throw switch with high power handling capability proposed in this embodiment can operate as a band-stop filter network. Therefore, in this case, no signal passes from the receive / transmit port to the antenna port, which provides the required ISO for the switch.

[0065] In some embodiments, the single-pole double-throw switch with high power handling capability proposed in this embodiment is implemented using a complementary metal-oxide-semiconductor process and includes an eight-layer metal structure, which are, in sequence, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a local interconnect layer, a capping layer, a capping anti-reflection layer, and a bottom anti-reflection layer;

[0066] Among them, the first coupling line and the second coupling line are constructed using the local interconnect layer, and a metal wall is constructed around the first coupling line and the second coupling line by stacking metal layers.

[0067] It can be understood that the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer (M1 to M4 metal layers) are used to implement the conventional wiring and connection functions of the circuit, including power lines, ground lines, and signal connections between transistors. Around the first coupling line and the second coupling line, a metal wall structure is constructed by stacking metal layers. The metal wall can effectively shield the parasitic capacitance and parasitic inductance around the coupling lines, reduce interference and loss during signal transmission, improve the electromagnetic characteristics of the coupling lines, and enable them to exhibit better transmission performance in the high-frequency band. The local interconnect layer (LD layer) constructs local interconnections; the capping layer (OB layer) prevents interference from upper-layer metals to lower-layer circuits; the capping anti-reflection layer (OA layer) reduces reflection during the lithography process and improves lithography accuracy; the bottom anti-reflection layer (UA layer) further reduces reflection during the lithography process.

[0068] In some embodiments, the first coupling line and the first switching transistor are symmetric with respect to the second coupling line and the second switching transistor about the antenna terminal.

[0069] It can be understood that they are symmetrically arranged on both sides of the antenna terminal 103 and have the same electrical characteristics and physical structure. This symmetry ensures that the characteristics of the signal during transmission between the antenna terminal 103 and the receive terminal 104 are the same as those during transmission between the antenna terminal 103 and the transmit terminal 105, thereby reducing signal distortion and transmission loss caused by structural asymmetry.

[0070] In some embodiments, the voltage at the first ends of the first coupling line and the second coupling line is less than the voltage at the second ends.

[0071] The limited power handling ability is also one of the most urgent problems to be improved in the performance of E-band CMOS single-pole double-throw switches. The main limitation is caused by the low threshold voltage of CMOS devices. Since the voltage at the TX port is capacitively divided at the gate through parasitic capacitance. When the voltage at the gate of the switching transistor becomes large enough, the parasitic diode associated with the transistor starts to conduct, resulting in serious signal leakage and deterioration of P1 dB. Therefore, P1 dB is limited when the voltage at the port connecting the switching transistor is large.

[0072] For the single-pole double-throw switch with high power handling ability proposed in this embodiment, when the switching transistor is in the "off" state, the following relationships can be established:

[0073] I1 = V3 = 0

[0074] V2 = jI4Z0

[0075] V4 = jI2Z0

[0076] It can be found that

[0077] V2·I2 = V4·I4.

[0078] It can be understood that when the first switching transistor or the second switching transistor is turned on, energy can be transmitted from the antenna port to the receiving end and the transmitting end. This result is useful for switches with enhanced P1 dB because its working principle is different from the quarter-wavelength method based on line conversion. In traditional designs, the switching transistor must remain "on" to support the transmission mode between the receiving port and the antenna port. Therefore, it has an inherent problem related to low P1 dB. Since the switch described in the present invention conducts signals when the switching transistor is in the "off" state, this problem is tacitly solved without affecting other performances. Therefore, the P1 dB of the designed switch may be improved.

[0079] I1 = V3 = 0

[0080]

[0081] At this time, the voltage at port 1 is less than the voltage at port 2, indicating that higher power handling ability can be obtained.

[0082] In some embodiments, the operating frequency range of the single-pole double-throw switch with high power handling ability proposed in this embodiment is from 70 GHz to 110 GHz, the insertion loss is less than 2.5 dB, and the isolation is greater than 30 dB.

[0083] Please refer to Figure 5 and Figure 6 , Figure 5 and Figure 6They are the insertion loss and isolation of the single-pole double-throw switch after chip testing, respectively. The operating frequency range of the single-pole double-throw switch of the present invention is 70 - 110 GHz, the insertion loss is 2.2 dB, and the isolation is 33 dBm. Figure 5 It shows the insertion loss and port matching performance of the single-pole double-throw switch at different frequencies. The abscissa in the figure represents the frequency in GHz, and the ordinate represents the insertion loss and reflection coefficient in dB. There are multiple curves in the figure, and each curve represents the simulation (Sim) or measurement (Meas) results under different test conditions; the line with the circle pointing to the left represents the insertion loss, which describes the power loss when the signal passes through the single-pole double-throw switch. The lower the insertion loss, the smaller the attenuation of the switch to the signal, and the better the performance. It can be seen from the figure that the variation of the insertion loss curve at different frequencies reflects the transmission efficiency of the switch in a wide frequency band; the line with the circle pointing to the right represents the port match, which is measured by the reflection coefficient. The closer the matching curve shown in the figure is to 0 dB, the better the matching performance and the lower the reflection loss.

[0084] Figure 6 It shows the isolation and port matching performance of the single-pole double-throw switch with high power handling ability proposed in this embodiment at different frequencies. The abscissa represents the frequency in GHz, and the ordinate represents the isolation and reflection coefficient, measured in dB. The line with the circle pointing to the left represents the isolation, which describes the ability of the single-pole double-throw switch to block signal transmission between different ports. High isolation means that when a signal passes through one port, very little or no signal will leak to other ports, which is crucial for preventing signal interference and ensuring communication quality. The line with the circle pointing to the right represents the port match, which reflects the reflection loss when the port inputs or outputs a signal.

[0085] In some embodiments, the 1 dB gain compression point of the single-pole double-throw switch with high power handling ability proposed in this embodiment reaches or exceeds 17 dBm.

[0086] Please refer to Figure 7 , Figure 7Schematic diagram of the power handling capacity of the single-pole double-throw switch with high power handling capacity provided by the embodiments of the present application. The abscissa represents the input power in dBm, which reflects the operating conditions of the single-pole double-throw switch at different input power levels. The left side of the ordinate represents the gain in dB, used to measure the signal amplification ability of the switch at different input powers; the right side represents the output power, also in dBm, showing the strength of the switch output signal. The curves in the figure depict the relationship between the gain and output power of the single-pole double-throw switch as the input power changes. As the input power increases, the gain curve (the circle arrow points to the left) remains relatively stable at first, indicating that the switch can maintain a constant gain level in the low input power range. However, when the input power continues to increase and exceeds a certain threshold, the gain begins to decline, indicating that the switch has entered the saturation region and gain compression begins to occur. The input power at this time is the 1 dB gain compression point (P1dB point). As shown in the figure, P1dB reaches 17 dBm, which is a key indicator for measuring the power handling capacity, indicating that when the single-pole double-throw switch reaches an input power of 17 dBm, the gain drops by 1 dB. The circle arrow pointing to the right curve represents the output power, which increases with the increase of the input power until it reaches a maximum value and then saturates due to the power limitation of the switch. Figure 7 Clearly demonstrates the performance of the single-pole double-throw switch with high power handling capacity proposed by the present invention at different input power levels, proving its excellent power handling capacity.

[0087] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation to the technical solutions provided by the embodiments of the present application. Those skilled in the art know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0088] Those skilled in the art can understand that the technical solutions shown in the figure do not constitute a limitation to the embodiments of the present application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0089] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware and their appropriate combinations.

[0091] In the description of the present application and the above-mentioned accompanying drawings, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0092] It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expression means any combination of these items, including any combination of single item (one) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0093] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above-mentioned division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0094] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0096] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application. The foregoing storage medium includes: various media that can store programs such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0097] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, and thus do not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. A single-pole double-throw switch with high power handling capacity, characterized in that, Comprising: A first coupling line, a second coupling line, an antenna terminal, a receiving terminal, a transmitting terminal, a first switching transistor, and a second switching transistor; Wherein, the first end of the first coupling line is electrically connected to the first switching transistor, the second end of the first coupling line is electrically connected to the antenna terminal, the third end of the first coupling line is grounded, the fourth end of the first coupling line is electrically connected to the receiving terminal, the first end of the second coupling line is electrically connected to the second switching transistor, the second end of the second coupling line is electrically connected to the antenna terminal, the third end of the second coupling line is grounded, the fourth end of the second coupling line is electrically connected to the transmitting terminal. When the first switching transistor is in the on state, the first coupling line and the first switching transistor form a band-pass filter network structure to enable signal transmission between the antenna terminal and the receiving terminal. When the second switching transistor is in the on state, the second coupling line and the second switching transistor form a band-pass filter network structure to enable signal transmission between the antenna terminal and the transmitting terminal.

2. The single-pole double-throw switch with high power handling capacity according to claim 1, wherein It further includes a first control voltage terminal. The first switching transistor includes a source, a drain, and a gate. Wherein, the source of the first switching transistor is grounded, the drain of the first switching transistor is electrically connected to the first end of the first coupling line, and the gate of the first switching transistor is electrically connected to the first control voltage terminal.

3. The single-pole double-throw switch with high power handling capacity according to claim 1, wherein It further includes a second control voltage terminal. The second switching transistor includes a source, a drain, and a gate. Wherein, the source of the second switching transistor is grounded, the drain of the second switching transistor is electrically connected to the first end of the second coupling line, and the gate of the second switching transistor is electrically connected to the second control voltage terminal.

4. The single-pole double-throw switch with high power handling capability according to claim 2, wherein When the first switching transistor is in the off state, the first coupling line and the first switching transistor form a band-stop filter network structure to block signal transmission between the antenna terminal and the receiving terminal.

5. The single-pole double-throw switch with high power handling capability according to claim 3, characterized in that When the second switching transistor is in the on state, the second coupling line and the second switching transistor form a band-stop filter network structure to block signal transmission between the antenna terminal and the transmitting terminal.

6. The single-pole double-throw switch with high power handling capacity according to claim 1, wherein The single-pole double-throw switch is implemented using complementary metal-oxide-semiconductor technology and includes an eight-layer metal structure, which are, in sequence, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a local interconnect layer, a capping layer, a capping antireflection layer, and a bottom antireflection layer; Wherein, the first coupling line and the second coupling line are constructed using the local interconnect layer, and metal walls are constructed around the first coupling line and the second coupling line by stacking metal layers.

7. The single-pole double-throw switch with high power handling capacity according to claim 1, characterized in that, The first coupling line and the first switching transistor are symmetric with the second coupling line and the second switching transistor with respect to the antenna terminal.

8. The single-pole double-throw switch with high power handling capability according to claim 1, characterized in that, The voltage at the first ends of the first coupling line and the second coupling line is less than the voltage at the second ends.

9. The single-pole double-throw switch with high power handling ability according to claim 1, characterized in that The operating frequency range of the single-pole double-throw switch is from 70 GHz to 110 GHz, the insertion loss is less than 2.5 dB, and the isolation is greater than 30 dB.

10. The single-pole double-throw switch with high power handling capacity according to claim 1, characterized in that, The 1 dB gain compression point of the single-pole double-throw switch reaches or exceeds 17 dBm.

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