Asynchronous ADC pseudo-synchronous sampling method based on DFT sampling point offset

Abstract

The invention provides an asynchronous ADC (Analog to Digital Converter) pseudo-synchronous sampling method based on DFT (Discrete Fourier Transform) sampling point offset, which is realized based on a discrete Fourier algorithm and comprises the following steps: step (1), DFT sampling point offset of phase difference is caused based on channel switching and conversion time delay of an asynchronous ADC; obtaining a DFT coefficient of any channel in the same ADC after DFT sampling point offset; step (2), DFT sampling point offset based on a phase difference caused by asynchronous sampling between different ADC chips; sampling point offsets caused by phase differences between AD channels and between different ADCs are superposed, a DFT coefficient of any AD channel of the relay protection device after DFT sampling point offsets is obtained, sampling point offset compensation is carried out on asynchronous sampling signals by utilizing the spectral characteristics of DFT, pseudo-synchronous sampling is achieved, and the sampling point offset compensation accuracy is improved. And the signal reconstruction precision and the spectrum analysis accuracy are improved.

Description

Technical Field

[0001] The present invention belongs to the field of power protection and control, and relates to a pseudo-synchronous sampling method for an asynchronous analog-to-digital converter (ADC) based on the sampling point offset of the discrete Fourier transform (DFT), which is applicable to signal reconstruction and spectrum analysis in an asynchronous sampling system. Background Art

[0002] In power system relay protection devices, voltage and current phasors are important variables for describing the operating state of the system, and the phase relationship between the voltage and current in each node is an important basis for stable discrimination and analysis. Phasor measurement includes the measurement of frequency, phase angle, and amplitude, mainly focusing on phase angle measurement and frequency measurement, among which measuring the phase difference between different signals is crucial for ensuring the safety of the power grid. A synchronous sampling and independent multi-channel input analog-to-digital converter (ADC) is an ideal choice for such applications. However, in practical engineering applications, to reduce the number of channels and control costs, asynchronous sampling and multi-channel input ADCs with internal multiplexers are mostly used, such as AD7616, ADS8686S, BL1088, etc.

[0003] When a multiplexed input asynchronous sampling ADC cyclically selects and sequentially converts its input channels, a conversion time delay is introduced between the channels. The delay time depends on the channel switching and sampling rate of the ADC. From a system perspective, this time delay will generate a system-level phase error between each analog channel. Suppose the same 50Hz sine wave signal is applied to the input of an 8-channel multiplexed ADC (all channels share the same input source), and the ADC polls and samples each channel at a rate of 1MSPS. When the final conversion result of the ADC is read, the discrete Fourier transform (DFT) algorithm is used to calculate the phase angle between the channels. Theoretically, the phase angle difference between the first channel and the second channel is: .

[0004] In response to the above problems, the reference designs in the patents CN102946251 "A Method for Implementing Multi-Channel Synchronous Sampling with a Multi-Channel Asynchronous Sampling ADC" and CN101764614 "V-Shaped Sampling Method for an AD Converter Based on FPGA" introduce a method to compensate for the additional phase delay caused by channel switching on the multiplexer. This method samples twice on both sides of the reference sampling time point, and then averages the two sampling values of the same channel as the data of the quasi-synchronous sampling point. To ensure that the time differences between the two sampling points and the reference sampling time point are as identical as possible, a V-shaped sampling method is proposed, that is, sequential sampling and reverse sampling are alternated. This brings additional operations for channel switching, and the time differences between each channel are different, which also have different effects on the quasi-synchronous sampling values (averages) of each channel, and may introduce new errors. Summary of the Invention

[0005] Aiming at the deficiencies of existing methods, the present invention proposes a pseudo-synchronous sampling method based on the offset of DFT sampling points, which can compensate for the phase angle difference between asynchronous sampling ADC channels without changing the sampling order and the amount of sampled data, achieving the calculation effect of synchronous sampling. Based on this method, it can also be used to solve the problem of asynchronous sampling between different ADCs, further expanding the number of AC input channels of the device.

[0006] To compensate for the phase angle difference between asynchronous sampling ADC channels, the present invention introduces a sampling point offset method on the basis of the conventional discrete Fourier algorithm, performs DFT operations on the data of each sampling channel, and then realizes the phase difference compensation of each channel, achieving pseudo-synchronous sampling of asynchronous sampling ADCs.

[0007] This technical solution is implemented based on the discrete Fourier algorithm and includes the following steps: Step (1): Based on the DFT sampling point offset caused by the channel switching and conversion time delay of the asynchronous ADC, obtaining the DFT coefficients after DFT sampling point offset of any channel within the same ADC, and realizing the pseudo-synchronous conversion of the sampled data of the asynchronous ADC; Step (2): Based on the DFT sampling point offset caused by the phase difference due to asynchronous sampling between different ADC chips, superimposing the sampling point offsets caused by the phase differences between AD channels and between different ADCs, obtaining the DFT coefficients after DFT sampling point offset of any AD channel of the relay protection device, and then realizing the pseudo-synchronous conversion of the sampled data of the asynchronous ADCs of the entire device.

[0008] As a preferred embodiment of the present invention, between different channels within the same ADC, through the sampling sequence and burst mode settings, after receiving a conversion start signal, all channel switching and data conversion are autonomously completed in sequence.

[0009] As a preferred embodiment of the present invention, the control signals for triggering conversion between different ADCs are from one signal source, and the start conversion times between different ADCs are asynchronous.

[0010] Step (1-1): Connect the standard sine signal to all input channels of the ADC. Assuming there are 8 channels, the input signal is:

[0011] where: X: input signal, A: signal amplitude, f: signal frequency, t: time.

[0012] Step (1-2): Design the sampling frequency fs. The number of sampling points within one cycle at the time interval of Ts is N, forming an N-point sequence. After each sampling starts, 8 or 16 channels of the asynchronous ADC perform channel switching and data conversion on the ADC channels in sequence in burst mode. The time delay between each channel is relatively determined, such as . The phase difference caused by the time delay between each channel is ψ.

[0013] Step (1-3): The CPU or FPGA reads the conversion data of the ADC through the data bus, reading the data of all channels of this ADC at one time. After N times of conversion and reading, each channel can form a set of N discrete data .

[0014]

[0015] i: The i-th point sampling; c: The c-th channel of the same ADC, usually with a maximum value of 8 or 16; X c (i): The i-th sampling value of the c-th channel; T s : Sampling time interval; ψ: Sampling phase difference between adjacent channels within the same ADC; Step (1-4): Based on the conversion data of each channel ADC collected, using the data of the first channel as a reference. First, perform a conventional DFT operation on the first channel to obtain the real and imaginary parts of each harmonic, and then calculate the phase angle of this channel. In order to reduce the frequency leakage in the discrete Fourier operation, a window function processing method is adopted here to optimize the calculation.

[0016]

[0017] X1[k]: The k-th harmonic of the first channel, N: Total N-point sampling; X1(i): The i-th sampling value of the first channel; ψ k : The phase angle of the k-th harmonic; Equation 3-1 is the complex plane representation of the DFT; Equation 3-2 is the polar coordinate representation of the DFT; Equation 3-3 is the real part calculated according to 3-1; Equation 3-4 is the imaginary part calculated according to 3-1; Equation 3-5 is the phase angle calculated according to 3-3 and 3-4.

[0018] The DFT coefficients at this time are obtained based on the coefficients when Z0 = 1 in the Z-transform. That is, the starting point Z0 is on the positive semi-axis of the real axis in the complex plane.

[0019] Steps (1 - 5): Recalculate the DFT coefficients of other channels based on the phase difference ψ caused by the time delay between channels, and perform DFT operations on the sampled data based on the DFT coefficients of this channel to calculate the AC characteristic quantities. To reduce the computational load, the DFT coefficients of each channel are calculated and stored in memory, and the stored DFT coefficients are directly called during the DFT calculation. Each channel corresponds to a set of DFT coefficients.

[0020]

[0021] Where: X c [k]: The kth harmonic of the cth channel; N: A total of N sampled points; X c (i): The ith sampled value of the cth channel; ψ: The sampling phase difference between adjacent channels within the same ADC; Equation 4 - 1 is the complex plane representation of DFT, and Equation 4 - 2 is the polar coordinate representation of DFT.

[0022] The DFT coefficients at this time are the coefficients after rotating and offsetting Z0 by an angle of (c - 1)ψ in the complex plane according to the angle of sampling lag of each channel.

[0023] Step (2): Although the same start signal is used to trigger the ADC conversion between different ADCs, due to factors such as the delay of hardware signals and the differences of individual ADCs, there will still be a certain phase difference between different ADCs, and this phase difference is not fixed. At this time, when performing channel calibration, taking the first channel of the first ADC as the reference, calculate the phase of the first channel of each ADC and compare it with the phase value of the reference channel to obtain the phase difference ψ A of each ADC. Add the phase difference values of each ADC to the phase offset between different channels of the corresponding ADC to form the DFT coefficients of each channel. Taking an 8 - channel ADC as an example:

[0024] Where: : The kth harmonic of the cth channel of the Ath ADC; ψ: The sampling phase difference between adjacent channels within the same ADC; ψ A : The sampling phase difference between the first channel of the Ath ADC and the first channel of the 1st ADC; Equation 5 - 1 is the complex plane representation of DFT; Equation 5 - 2 is the polar coordinate representation of DFT.

[0025] Through the calculation of the AC characteristic quantities after the offset of the DFT coefficients, the influence of the phase difference caused by the channel conversion delay of asynchronous ADCs can be well compensated. It can be seen from the exponential form of the DFT coefficients that the offset of the DFT sampling points is equivalent to performing a phase shift operation on the sampled data in advance. By performing a phase shift operation on the non - synchronous sampled data, the phase synchronization is achieved, and then the DFT operation is performed synchronously.

[0026] Compared with the prior art, the present invention can effectively reduce the spectral leakage caused by asynchronous sampling and improve the signal reconstruction accuracy through DFT spectrum analysis and sampling point offset compensation. The present invention is completely based on digital signal processing technology, without the need for an additional hardware clock synchronization circuit, reducing the system cost and complexity, and can be widely applied to various asynchronous sampling systems, such as power system harmonic analysis, communication signal processing, vibration signal measurement and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the AC sampling hardware in this embodiment.

[0028] Figure 2 It is a schematic diagram of the asynchronous ADC burst mode sampling in this embodiment.

[0029] Figure 3 It is a schematic diagram of the conventional DFT coefficient calculation in this embodiment.

[0030] Figure 4 It is a schematic diagram of the DFT coefficient calculation after the DFT sampling point offset in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0032] In Figure 1 , the connection between the CPU or FPGA and the ADC includes a data bus and a control signal. Under the control of the control signal, different ADCs trigger the ADC conversion simultaneously. Inside the ADC, through the sampling sequence and burst mode setting, all channel switching and data conversion are completed in sequence. The CPU or FPGA reads the conversion result data of all channels from the ADC through the data bus to complete one data sampling. Then, when the next sampling time arrives, the ADC conversion is triggered again, and the cycle continues.

[0033] Inside a single ADC, when the ADC receives the trigger signal to start the conversion, it starts this conversion. At this time, the ADC will complete all channel switching and conversion at the fastest speed, as Figure 2 shown. The time delay between each channel is relatively determined, such as Δt = 1us. The phase difference caused by the time delay between each channel is ψ.

[0034] After reading the conversion results of each ADC, to compensate for the impact of the phase difference caused by the channel conversion delay of the asynchronous ADC. Starting from the exponential formula of the DFT coefficients, for the offset of the DFT sampling points, that is, first perform a phase shift operation on the sampled data. Through the phase shift operation on the asynchronous sampled data, achieve pseudo-synchronization in terms of phase, and then perform the DFT operation synchronously. The specific steps include: (1) Due to the channel switching and conversion time delay of the asynchronous ADC resulting in a phase difference, there is an offset of the DFT sampling points. Obtain the DFT coefficients after the DFT sampling point offset for any channel within the same ADC, and achieve the pseudo-synchronous conversion of the sampled data of the asynchronous ADC.

[0035] (2) Due to the phase difference caused by asynchronous sampling between different ADC chips, there is an offset of the DFT sampling points. Superimpose the sampling point offsets caused by the phase differences between AD channels and between different ADCs to obtain the DFT coefficients after the DFT sampling point offset for any AD channel of the relay protection device, and further achieve the pseudo-synchronous conversion of the sampled data of the asynchronous ADCs of the entire device.

[0036] Step (1-1): Connect the standard sine signal to all input channels of the ADC. Assume there are 8 channels, and the input signal is:

[0037] Where: X: input signal, A: signal amplitude, f: signal frequency, t: time.

[0038] Step (1-2): Design the sampling frequency fs. The number of sampling points within one cycle at a time interval of Ts is N, forming an N-point sequence. After each sampling starts, 8 or 16 channels of the asynchronous ADC switch channels and convert data for the ADC channels in sequence in burst mode. The time delay between each channel is relatively determined, such as Δt = 1us. The phase difference caused by the time delay between each channel is ψ, as Figure 2 shown.

[0039] Step (1-3): The CPU or FPGA reads the conversion data of the ADC through the data bus, reads the data of all channels of this ADC at one time. After N times of conversion and reading, each channel can form a set of N discrete data .

[0040]

[0041] i: the i-th sampling; c: the c-th channel of the same ADC, usually the maximum value is 8 or 16; X c (i): the i-th sampling value of the c-th channel; Ts: sampling time interval; ψ: sampling phase difference between adjacent channels within the same ADC; Steps (1-4): Based on the conversion data of each channel's ADC, using the data of the first channel as a reference. First, perform a conventional DFT operation on the first channel to obtain the real and imaginary parts of each harmonic, and then calculate the phase angle of this channel. To reduce frequency leakage in the discrete Fourier operation, a window function processing method is adopted here to optimize the calculation.

[0042]

[0043] X1[k]: The k-th harmonic of the first channel, N: Total N-point sampling; X1(i): The i-th sampling value of the first channel; ψ k : The phase angle of the k-th harmonic; Equation 3-1 is the complex plane representation of the DFT; Equation 3-2 is the polar coordinate representation of the DFT; Equation 3-3 is the real part calculated according to 3-1; Equation 3-4 is the imaginary part calculated according to 3-1; Equation 3-5 is the phase angle calculated according to 3-3 and 3-4.

[0044] The DFT coefficients at this time are the coefficients obtained when Z0 = 1 in the Z-transform. That is, the starting point Z0 is on the positive semi-axis of the real axis in the complex plane, as Figure 3 .

[0045] Steps (1-5): Based on the phase difference ψ caused by the time delay between channels, recalculate the DFT coefficients of other channels, and perform a DFT operation on the sampling data according to the DFT coefficients of this channel to calculate the AC characteristic quantities. To reduce the calculation amount, the DFT coefficients of each channel are calculated and stored in memory, and the stored DFT coefficients are directly called during the DFT calculation process. Each channel corresponds to a set of DFT coefficients.

[0046]

[0047] Where: X c [k]: The K-th harmonic of the c-th channel; N: Total N-point sampling; X c (i): The i-th sampling value of the c-th channel; ψ: The sampling phase difference between adjacent channels within the same ADC; Equation 4-1 is the complex plane representation of the DFT, and Equation 4-2 is the polar coordinate representation of the DFT.

[0048] The DFT coefficients at this time are the coefficients after rotating and offsetting the angle of Z0 by (c-1)ψ in the complex plane according to the sampling lag angle of each channel, as Figure 4 .

[0049] Step (2): Although the same start signal is used to trigger the ADC conversion among different ADCs, due to factors such as the delay of hardware signals and the differences among individual ADCs, there will still be a certain phase difference among different ADCs, and this phase difference is not fixed. At this time, when performing channel calibration, taking the first channel of the first ADC as the reference, calculate the phase of the first channel of each ADC and compare it with the phase value of the reference channel to obtain the phase difference ψ of each ADC. A . Add the phase difference values of each ADC to the phase offset between different channels of the corresponding ADC to form the DFT coefficients of their respective channels. Taking an 8-channel ADC as an example:

[0050] Where: : The Kth harmonic of the cth channel of the Ath ADC; ψ: The sampling phase difference between adjacent channels within the same ADC; ψ A : The sampling phase difference between the first channel of the Ath ADC and the first channel of the 1st ADC; Equation 5-1 is the complex plane representation of the DFT; Equation 5-2 is the polar coordinate representation of the DFT.

[0051] Through the calculation of the AC characteristic quantity after the offset of the DFT coefficient, the influence of the phase difference caused by the channel conversion delay of the asynchronous ADC can be well compensated. It can be seen from the exponential form of the DFT coefficient that the offset of the DFT sampling point is equivalent to performing a phase shift operation on the sampling data in advance, performing a phase shift operation on the non-synchronous sampling data to achieve phase synchronization, and then performing the DFT operation synchronously.

[0052] The above is only a preferred embodiment of the present invention and is not used to limit the protection scope of the present invention. Any equivalent structural changes made by using the description and drawings of the present invention should be included in the patent protection scope of the invention.

Claims

1. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset, characterized in that, Including: Step (1): Based on the phase difference caused by the time delay of channel switching and conversion of the asynchronous ADC, resulting in the offset of DFT sampling points, obtain the DFT coefficients after DFT sampling point offset for any channel within the same ADC, and realize the pseudo-synchronous conversion of the sampling data of the asynchronous ADC; Step (2): Based on the DFT sampling point offset caused by the phase difference due to asynchronous sampling between different ADC chips, superimpose the sampling point offsets caused by the phase differences between AD channels and between different ADCs, obtain the DFT coefficients after DFT sampling point offset for any AD channel of the relay protection device, and further realize the pseudo-synchronous conversion of the sampling data of the asynchronous ADCs of the entire device.

2. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to claim 1, characterized in that: Between different channels within the same ADC, through the sampling sequence and burst mode setting, after receiving a conversion start signal once, all channel switching and data conversion are autonomously completed in sequence.

3. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to claim 1, characterized in that: The control signals for triggering conversion between different ADCs are from a single signal source, and the start conversion times between different ADCs are asynchronous.

4. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to any one of claims 1-3, characterized in that The specific steps of step (1) include: Step (1-1): Connect a standard sine signal to all input channels of the ADC. Assume there are 8 channels, and the input signal X is: ， Where: A: signal amplitude, f: signal frequency, t: time; Step (1-2): Design the sampling frequency fs, with the number of sampling points within one cycle at a time interval of Ts being N, forming an N-point sequence; Steps (1-3): The CPU or FPGA reads the conversion data of the ADC through the data bus, reading the data of all channels of this ADC at one time. After N conversions and readings, a set of N discrete data can be formed for each channel. ; where i is the i-th point sampling; c is the c-th channel of the same ADC, with a maximum value of 8 or 16; is the i-th sampling value of the c-th channel; is the sampling time interval; Step (1-4): According to the conversion data collected from each channel ADC, using the data of the first channel as a reference; Step (1-5): Based on the phase difference ψ caused by the time delay between channels, recalculate the DFT coefficients of other channels, and based on the DFT coefficients of this channel, perform DFT operations on the sampling data to calculate the AC characteristic quantities.

5. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to claim 4, characterized in that In step (1-2): After each sampling starts, 8 or 16 channels of the asynchronous ADC perform channel switching and data conversion on the ADC channels in sequence in burst mode; the time delay between each channel is relatively determined, and the phase difference caused by the time delay between each channel is ψ.

6. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to claim 4, characterized in that, In step (1-3): ， Where ψ is the sampling phase difference between adjacent channels within the same ADC.

7. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to claim 4, characterized in that The specific steps of step (1-4) are: First, perform a conventional DFT operation on the first channel to obtain the real and imaginary parts of each harmonic, and then calculate the phase angle of this channel; in order to reduce frequency leakage in the discrete Fourier operation, a window function processing method is adopted to optimize the calculation. Specifically: The complex plane representation of DFT is: ， The polar coordinate representation of DFT is: ， The real part calculated according to equation (3-1) is: ， The imaginary part calculated according to equation (3-1) is: ， The phase angle calculated according to equations (3-3) and (3-4) is: ， Among them, is the k-th harmonic of the first channel; N is the total of N-point sampling; is the i-th sampling value of the first channel; is the phase angle of the k-th harmonic; in Equation (3-5) ; The DFT coefficients at this time are the coefficients obtained when Z0 = 1 in the Z-transform, that is, the starting point Z0 is on the positive semi-axis of the real axis in the complex plane.

8. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to claim 4, characterized in that The specific steps of step (1-5) are: To reduce the computational load, the DFT coefficients of each channel are calculated and stored in memory, and the stored DFT coefficients are directly called during the DFT calculation. Each channel corresponds to a set of DFT coefficients, and the complex plane representation of the DFT is as follows: ， The polar coordinate representation of the DFT is as follows: ， Wherein: is the Kth harmonic of the c-th channel; N is the total of N-point sampling; is the i-th sampling value of the c-th channel; ψ is the sampling phase difference between adjacent channels within the same ADC; The DFT coefficients at this time are the coefficients after angular rotation and offset of Z0 in the complex plane according to the angles of sampling lags of each channel. ​ 9. A pseudo-synchronous sampling method for an asynchronous ADC based on DFT sampling point offset according to claim 4, characterized in that The specific content of step (2) is as follows: When channel calibration is required, taking the first channel of the first ADC as the reference, calculate the phase of the first channel of each ADC and compare it with the phase value of the reference channel to obtain the phase difference ψA of each ADC; And add the phase difference values of each ADC to the phase offset between different channels of the corresponding ADC to form the DFT coefficients of their respective channels. Taking an 8-channel ADC as an example, the complex plane representation of the DFT is as follows: ， The polar coordinate representation of the DFT is as follows: ， Wherein: is the K-th harmonic of the c-th channel of the A-th ADC; ψ is the sampling phase difference between adjacent channels within the same ADC; is the sampling phase difference between the first channel of the A-th ADC and the first channel of the first ADC; Through the calculation of the AC characteristic quantity after the DFT coefficient offset, the influence of the phase difference caused by the channel conversion delay of the asynchronous ADC is compensated for.

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