A PVT-stable successive approximation analog-to-digital converter

Abstract

The present invention discloses a PVT-stable successive approximation analog-to-digital converter, which belongs to the field of analog-to-digital converter design technology. The analog-to-digital converter is composed of a switched capacitor DAC module, a comparator, a successive approximation logic circuit, and a delay adjustment circuit. The switched capacitor DAC module IDAC receives differential input signals Vip, Vin and reference levels Vrefp, Vrefn. The capacitor top plate output voltages Vcp and Vcn of the switched capacitor DAC module are respectively connected to the positive and negative input terminals of the comparator ICMP. The present invention is compatible with the fastest and slowest PVT (process angle, power supply voltage, temperature) conditions by automatically detecting the remaining conversion time and adjusting the delay. This solves the problem that in traditional designs, in order to be compatible with the fastest and slowest conditions, the slowest condition will just use up the entire conversion time. The overall switching capacitor DAC drive and reference level generation circuit are added with additional power consumption and decoupling to compensate for the switching capacitor DAC settling time problem in the fastest condition.

Description

Technical Field

[0001] The invention belongs to the technical field of analog-to-digital converter design, and in particular relates to a PVT-stable successive approximation analog-to-digital converter. Background Art

[0002] With the advancement of process technology, successive approximation analog-to-digital converters (ADCs) are becoming increasingly important in high-speed applications. Their successive approximation timing uses asynchronous logic timing to increase conversion speed and avoid high-speed clocks. However, because asynchronous timing implements delays through logic circuits, timing can vary significantly across PVT (process angle, power supply voltage, and temperature). The difference in conversion time between the slowest and fastest cases can be as much as 100%. This can easily lead to insufficient total conversion time in the slowest case and excessive logic delay in the fastest case, resulting in insufficient settling time for the switched capacitor DAC (digital-to-analog converter) in the ADC. Summary of the Invention

[0003] The present invention aims to provide a PVT-stable successive approximation analog-to-digital converter that automatically detects the remaining conversion time and adjusts the delay to achieve compatibility with both the fastest and slowest cases. This solves the problem in which, in traditional designs, in order to accommodate both the fastest and slowest cases, the slowest case will just use up the entire conversion time, adding additional power consumption and decoupling capacitors to the switch capacitor DAC drive and reference level generation circuits to compensate for the switch capacitor DAC settling time in the fastest case, and resulting in a significant increase in the area and power consumption of the entire analog-to-digital converter.

[0004] To achieve the above object, the present invention provides the following technical solutions: a PVT-stable successive approximation analog-to-digital converter, the analog-to-digital converter comprising a switched capacitor DAC module, a comparator, a successive approximation logic circuit, and a delay adjustment circuit;

[0005] Among them, the switched capacitor DAC module IDAC receives the differential input signal Vip, Vin and the reference level Vrefp, Vrefn; the capacitor top plate output voltage Vcp, Vcn of the switched capacitor DAC module is connected to the positive and negative input terminals of the comparator ICMP respectively; the positive and negative output signals of the comparator are Q, QB as input signals connected to the successive approximation logic circuit; the delay circuit module of the successive approximation logic circuit generates the comparator input clock CMP_CK and inputs it to the input terminal of the comparator. The successive approximation logic circuit gradually outputs the control signal Dac_ctl of the switched capacitor array according to the result of the comparator. <n-1:0>At the same time, the successive approximation logic circuit outputs the reset signal rst_syn and the delayed conversion completion signal finish_dly to the delay adjustment circuit; the delay adjustment circuit outputs the adjusted comparator clock delay control signal dly_out<2:0> to the delay circuit of the successive approximation logic circuit to control the delay gear of the comparison clock; the successive approximation logic circuit outputs the final analog-to-digital conversion digital signal Dout <n-1:0>.

[0006] Preferably, the delay adjustment circuit compares the delayed conversion completion signal finish_dly output by the successive approximation logic circuit with the input clock ckdff;

[0007] The input clock ckdff has the same frequency and phase as the sampling clock of the entire analog-to-digital converter. The input clock ckdff is high in the sampling phase and low in the conversion phase.

[0008] When there is sufficient redundancy after the successive approximation conversion is completed, the delay adjustment circuit will increase the gear of the input delay control signal dly_out<2:0>, utilizing this redundancy to alleviate the settling pressure of the switched capacitor DAC under fast PVT conditions, thereby reducing the driving pressure of the switched capacitor DAC and the power consumption of the reference level generation circuit.

[0009] Preferably, the successive approximation logic circuit includes a delay circuit IDLY, a NAND gate I1, successive approximation units I5, I6, I7 and I8, a delay unit I9, an AND gate I10, a D flip-flop I3 and an inverter I4;

[0010] Among them, the positive and negative output signals of the comparator are Q and QB, which are connected as input signals to the two input terminals of the NAND gate I1 in the successive approximation logic circuit; the output signal of the NAND gate I1 is a valid signal, and the output terminal of the NAND gate I1 is respectively connected to the input terminal cki of the delay circuit IDLY and the CK terminal of the successive approximation units I5, I6, I7 and I8; the positive and negative output signals Q and QB of the comparator are also simultaneously connected to the positive data input D terminal and the negative data input DB terminal of the successive approximation units I5, I6, I7 and I8; the enable input terminal EN of the successive approximation unit I5 is connected to the input clock ckdff through the inverter I2; the next-level enable output terminal EN_N of the successive approximation unit I5 is connected to the EN terminal of the successive approximation unit I6; the output terminal EN_N of the successive approximation unit I6 is connected to the EN terminal of the successive approximation unit I7; the output terminal EN_N of the successive approximation unit I7 is connected to the line EN <3> Connect to the next successive approximation unit; the EN terminal of the nth successive approximation unit I8 is connected to the EN_N terminal of the n-1th successive logic unit; the output terminal EN_N of the successive approximation unit I8 is connected to the input terminal A of the delay unit I9, and after being delayed by the delay unit I9, it is input to one input terminal of the AND gate I10 through its O terminal. The output terminal EN_N of the successive approximation unit I8 is directly connected to the other input terminal of the AND gate I10; the output terminal line of the AND gate I10 is named finish_dly; the data input terminal Q of the D flip-flop I3 is connected to a logic high level "1", the CK terminal is connected to the input clock ckdff, the reset input terminal R is connected to the input reset signal sar_rst, and the output terminal D is passed through the inverter I4 to obtain the synchronous reset signal rst_syn;

[0011] The RST terminals of the successive approximation units I5, I6, I7 and I8 are all connected to rst_syn; the output CTL terminals of the successive approximation units I5, I6, I7 and I8 respectively output n-bit control signals Dac_ctl <n-1>to Dac_ctl <0> To the IDAC, it is used to control the switch of the capacitor bottom plate of the switched capacitor DAC; the output Q end of the successive approximation unit I5, I6, I7 and I8 is the data output end, which outputs the output data D of n respectively. out <n-1:0>As the output data of the entire analog-to-digital converter; the input terminal dly of the delay circuit IDLY is connected to the delay control signal dly_out<2:0>; the output terminal cko of the delay circuit IDLY is connected to the comparator enable clock line CMP_CK and connected to the ck terminal of the comparator ICMP.

[0012] Preferably, the delay adjustment circuit includes D flip-flops I11, I13, I15, I17, I20, I21, I25, I27, I29, I31 and I33, inverters I12, I14, I16, I18, I26, I28, I30, I32 and I34, NOR gates I19, I39, NAND gates I37, I38, AND gates I40, OR gates I36, I41, I42, I43, adders I22, I23, I24 and a delay unit I35;

[0013] Among them, the finish_dly line is connected to the CK terminal of the D flip-flop I11, and the output D terminal of the D flip-flop I11 is connected to the input Q terminal of I11 and the CK terminal of the D flip-flop I13 through the inverter I12; the output D terminal of the D flip-flop I13 is connected to the input Q terminal of I13 and the CK terminal of the D flip-flop I15 through the inverter I14; the output D terminal of the D flip-flop I15 is connected to the input Q terminal of the D flip-flop I15, the CK terminal of the D flip-flop I17 and one of the input terminals of the NOR gate I19 through the inverter I16; the output D terminal of the D flip-flop I17 is connected to the input Q terminal of the D flip-flop I17 and the other input terminal of the NOR gate I19 through the inverter I18.

[0014] Preferably, the reset terminals R of the D flip-flops I11, I13, I15 and I17 are all connected to cnt_rst; the input clock ckdff line is connected to the CK terminal of the D flip-flop I25, and the D terminal connection signal ckcnt0 of the D flip-flop I25 is connected to the Q terminal of the D flip-flop I25 and the CK terminal of the D flip-flop I27 through the inverter I26; the output D terminal connection signal ckcnt1 of the D flip-flop I27 is connected to the Q terminal of the D flip-flop I27 and the CK terminal of the D flip-flop I29 through the inverter I28; the output D terminal connection signal ckcnt2 of the D flip-flop I29 is connected to the Q terminal of the D flip-flop I29 and the CK terminal of the D flip-flop I31 through the inverter I30; the output D terminal connection signal ckcnt3 of the D flip-flop I31 is connected to the Q terminal of the D flip-flop I31 and the CK terminal of the D flip-flop I33 through the inverter I32; the output D terminal of the D flip-flop I33 is connected to the signal ckcnt4 is connected to the Q terminal of the D flip-flop I33 through the inverter I34; the signals ckcnt0 and ckcnt1 are respectively connected to the two input terminals of the NAND gate I37; the signals ckcnt2 and ckcnt3 are respectively connected to the two input terminals of the NAND gate I38; the output terminals of the NAND gates I37 and I38 are respectively connected to the two input terminals of the NOR gate I39; the output terminal of the NOR gate I39 and the input clock ckdff are respectively connected to the two input terminals of the AND gate I40; the reset terminals of the D flip-flops I25, I27, I29, I31 and I33 are all connected to the cnt_rst signal; the signal ckcnt4 is connected to the input terminal A of the delay unit I35, and is connected to one of the input terminals of the OR gate I36 through the output terminal O of the logic unit I35. The other input terminal of the OR gate I36 is connected to rst_syn, and the output terminal of the OR gate I36 is connected to the signal cnt_rst.

[0015] Preferably, the output of the NOR gate I19 is connected to the Q terminal of the D flip-flop I20; the output terminal of the AND gate I40 is connected to the CK terminal of the D flip-flop I20; the output terminal D of the D flip-flop I20 is connected to the Q terminal of the D flip-flop I21; the D terminal of the D flip-flop I21 is connected to the A terminal of the adder I22, and the CK terminal of the D flip-flop I21 is connected to the input signal ck terminal; the reset terminals R of the D flip-flops I20 and I21 are both connected to rst_syn; the B terminals of the adders I22, I23 and I24 are respectively input with the original Delay control signal dly_in<2:0>; the CO terminal of adder I22 is connected to the A terminal of adder I23, and the CO terminal of adder I23 is connected to the CO terminal of adder I24; the S terminals of adders I22, I23 and I24 are respectively connected to the input terminals of OR gates I41, I42 and I43; the CO terminal of adder I24 is connected to the other input terminals of OR gates I41, I42 and I43; the output terminals of OR gates I41, I42 and I43 respectively output delay control signals dly_out<2:0>.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention automatically detects the redundant time after each successive approximation conversion is completed through a delay adjustment circuit working in the background. When the redundant time is large enough, it will be counted in the delay adjustment circuit. When the redundant time for most conversions is sufficient, the delay adjustment circuit will increase the gear of the delay control signal, so that the redundant time after the conversion is completed is reduced. This method can alleviate the settling pressure of the switched capacitor DAC under fast PVT conditions, thereby reducing the driving pressure of the switched capacitor DAC and the power consumption of the reference level generation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a block diagram of a traditional comparator amplifier.

[0019] Figure 2 This is a circuit block diagram of a PVT-stabilized successive approximation analog-to-digital converter according to the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0021] In traditional designs, to accommodate both the fastest and slowest cases, the slowest case is used to the fullest conversion time. This adds extra power and decoupling capacitors to the switch-capacitor DAC driver and reference level generation circuits to compensate for the settling time in the fastest case. This significantly increases the area and power consumption of the entire ADC. This invention proposes a PVT-stable successive approximation ADC that accommodates both the fastest and slowest cases by automatically detecting the remaining conversion time and adjusting the delay.

[0022] Figure 1 This is the block diagram of a traditional successive approximation analog-to-digital converter, which mainly consists of a switched capacitor DAC (Digital to Analog Converter) array, a comparator, and a successive approximation logic circuit.

[0023] like Figure 2 As shown, the analog-to-digital converter of the present invention comprises a switched capacitor DAC, a comparator, a successive approximation logic circuit, and a delay adjustment circuit. Differential input signals Vip and Vin, as well as reference voltages Vrefp and Vrefn, are input to the switched capacitor DAC module IDAC. The top plate output voltages of the switched capacitor DAC, Vcp and Vcn, are connected to the positive and negative input terminals of the comparator ICMP, respectively. The comparator's positive and negative output signals are Q and QB. The switched capacitor DAC and comparator are conventional structures.

[0024] The positive and negative output signals of the comparator are Q and QB, which are connected as input signals to the two input terminals of the NAND gate I1 in the successive approximation logic circuit. The output signal of I1 is a valid signal, and the output terminal of the NAND gate I1 is connected to the input terminal cki of the delay circuit IDLY and the CK terminal of the successive approximation units I5-I8 respectively. The positive and negative output signals of the comparison are Q and QB, which are simultaneously connected to the positive data input D terminal and the negative data input DB terminal of the successive approximation units I5-I8. The input clock ckdff passes through the inverter I2 and is connected to the enable input EN terminal of I5; the next stage enable output EN_N of I5 is connected to the EN terminal of I6; the output terminal EN_N of I6 is connected to the EN terminal of I7; the output terminal EN_N of I7 is connected to the line EN <3> Connect to the next successive approximation unit; the EN terminal of the nth successive approximation unit I8 is connected to the EN_N terminal of the n-1th logic unit; the output terminal EN_N of I8 is connected to the input terminal A of the delay unit I9, and after the delay of the delay unit, it is input to one of the input terminals of the AND gate I10 through the O terminal of I9. The output terminal EN_N of I8 is directly connected to the other input terminal of the AND gate I10. The output terminal line of I10 is named finish_dly. The data input Q terminal of the D flip-flop I3 is connected to the logic high level "1", the CK terminal is connected to the input clock ckdff, the reset input R terminal is connected to the input reset signal sar_rst, and the output D terminal passes through the inverter I4 to obtain the synchronous reset signal rst_syn. The RST terminals of I5-I8 are all connected to rst_syn. The output CTL terminals of I5-I8 respectively output the n-bit control signal Dac_ctl <n-1>to Dac_ctl <0> To the IDAC, it is used to control the switch of the capacitor bottom plate of the switched capacitor DAC. The output Q end of I5-I8 is the data output end, which outputs the output data D of n respectively. out <n-1:0>The input terminal dly of the delay circuit IDLY is connected to the delay control signal dly_out<2:0>; the output terminal cko of the delay circuit IDLY is connected to the comparator enable clock line CMP_CK and to the ck terminal of the comparator ICMP.

[0025] The delay adjustment circuit is connected as follows: the finish_dly line is connected to the CK terminal of D flip-flop I11. The D output of I11 is connected to the Q input of I11 and the CK terminal of D flip-flop I13 via inverter I12. The D output of I13 is connected to the Q input of I13 and the CK terminal of D flip-flop I15 via inverter I14. The D output of I15 is connected to the Q input of I15, the CK terminal of D flip-flop I17, and one input of NOR gate I19 via inverter I16. The D output of I17 is connected to the Q input of I17 and the other input of NOR gate I19 via inverter I18. The reset terminals (R) of I11, I13, I15, and I17 are all connected to cnt_rst. The input clock line (ckdff) is connected to the CK terminal of D flip-flop I25. The D terminal of I25 is connected to the signal ckcnt0, which is connected to the Q terminal of I25 and the CK terminal of D flip-flop I27 via inverter I26. The D-terminal output of I27 is connected to signal ckcnt1, which is then connected to the Q-terminal of I27 and the CK-terminal of D-type flip-flop I29 via inverter I28. The D-terminal output of I29 is connected to signal ckcnt2, which is then connected to the Q-terminal of I29 and the CK-terminal of D-type flip-flop I31 via inverter I30. The D-terminal output of I31 is connected to signal ckcnt3, which is then connected to the Q-terminal of I31 and the CK-terminal of D-type flip-flop I33 via inverter I32. The D-terminal output of I33 is connected to signal ckcnt4, which is then connected to the Q-terminal of I33 via inverter I34. Signals ckcnt0 and ckcnt1 are connected to the two inputs of NAND gate I37, respectively. Signals ckcnt2 and ckcnt3 are connected to the two inputs of NAND gate I38, respectively. The outputs of I37 and I38 are connected to the two inputs of NOR gate I39, respectively. The output of I39 and the input clock ckdff are connected to the two inputs of AND gate I40, respectively. The reset terminals of I25, I27, I29, I31, and I33 are all connected to the cnt_rst signal. ckcnt4 is connected to the input A of delay unit I35, and then to one of the inputs of OR gate I36 via its output O. The other input of I36 is connected to rst_syn, and the output of I36 is connected to the cnt_rst signal. The output of I19 is connected to the Q terminal of D-type flip-flop I20. The output of I40 is connected to the CK terminal of I20. The output D of I20 is connected to the Q terminal of D-type flip-flop I21. The D terminal of I21 is connected to the A terminal of adder I22, and the CK terminal of I21 is connected to the input signal ck. The reset terminals R of I20 and I21 are both connected to rst_syn. The original delay control signal dly_in<2:0> is input to the B terminals of adders I24, I23, and I22, respectively. The CO terminal of I22 is connected to the A terminal of I23, and the CO terminal of I23 is connected to the CO terminal of I24.The S terminals of I22, I23, and I24 are connected to the input terminals of OR gates I41, I42, and I43, respectively. The CO terminal of I24 is connected to the other input terminals of I41, I42, and I43. The output terminals of I43, I42, and I41 respectively output the delay control signal dly_out<2:0>.

[0026] The timing is as follows: the input clock ckdff has the same frequency and phase as the analog-to-digital converter sampling clock. The input clock ckdff is high during the sampling phase and low during the conversion phase. The entire successive approximation conversion process is the same as the traditional structure, obtaining n results of successive comparisons from I5 to I8. The output signal EN of EN_N of the last successive approximation unit I8 is <n>The change from 0 to 1 marks the end of the successive approximation conversion. <n>The time from the high level to the next sampling is different. In most PVT cases, EN <n>There is still a certain amount of redundancy until the next sampling clock high level. When there is still time from the rising edge of finish_dly to the next sampling high level, it means that the redundancy time is still sufficient under this PVT situation. The original input delay control signal dly_in<2:0> is increased through the delay adjustment circuit. In the present invention, 1 gear is added, and 2 gears or more can also be added. Similarly, the input delay control signal dly_in<2:0> can also be increased to more than 3 bits or reduced to 2 bits or even 1 bit. The delay control signal dly_out<2:0> after the gear is increased is input into the delay circuit IDLY to increase the time of each conversion. It is ensured that the added delay time of n times is less than the delay of I9. At the same time, the delay adjustment circuit is adjusted based on the sampling result of the analog-to-digital converter, so it can work in the background of the analog-to-digital converter without affecting the normal operation of the analog-to-digital converter.

[0027] The present invention automatically detects the redundant time after each successive approximation conversion is completed through a delay adjustment circuit working in the background. When the redundant time is large enough, it will be counted in the delay adjustment circuit. When the redundant time for most conversions is sufficient, the delay adjustment circuit will increase the gear of the delay control signal, so that the redundant time after the conversion is completed is reduced. This method can alleviate the settling pressure of the switched capacitor DAC under fast PVT conditions, thereby reducing the driving pressure of the switched capacitor DAC and the power consumption of the reference level generation circuit.

[0028] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0029] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.< / n> < / n> < / n>

Claims

1. A PVT-stable successive approximation analog-to-digital converter, characterized in that: The analog-to-digital converter is composed of a switched capacitor DAC module, a comparator, a successive approximation logic circuit and a delay adjustment circuit; Among them, the switched capacitor DAC module IDAC receives the differential input signals Vip, Vin and the reference levels Vrefp, Vrefn; the capacitor top plate output voltages Vcp and Vcn of the switched capacitor DAC module are respectively connected to the positive and negative input terminals of the comparator ICMP; the positive and negative output signals of the comparator are Q and QB, which are connected to the successive approximation logic circuit as input signals; the delay circuit of the successive approximation logic circuit generates the comparator input clock CMP_CK and inputs it to the input terminal of the comparator. The successive approximation logic circuit gradually outputs the control signal Dac_ctl of the switched capacitor array according to the result of the comparator. <n-1:0>At the same time, the successive approximation logic circuit outputs the reset signal rst_syn and the delayed conversion completion signal finish_dly to the delay adjustment circuit; the delay adjustment circuit outputs the adjusted comparator clock delay control signal dly_out<2:0> to the delay circuit of the successive approximation logic circuit to control the delay gear of the comparison clock; the successive approximation logic circuit outputs the final analog-to-digital conversion digital signal Dout <n-1:0> ；< / n-1:0> The delay adjustment circuit compares the delayed conversion completion signal finish_dly output by the successive approximation logic circuit with the input clock ckdff; The input clock ckdff has the same frequency and phase as the sampling clock of the entire analog-to-digital converter. The input clock ckdff is high in the sampling phase and low in the conversion phase. When there is still redundant time after the successive approximation conversion is completed, the delay adjustment circuit will increase the gear of the input delay control signal dly_out<2:0>, utilizing the aforementioned redundant time to alleviate the settling pressure of the switched capacitor DAC under fast PVT conditions, thereby reducing the driving pressure of the switched capacitor DAC and the power consumption of the reference level generation circuit; The delay adjustment circuit includes D flip-flops I11, I13, I15, I17, I20, I21, I25, I27, I29, I31 and I33, inverters I12, I14, I16, I18, I26, I28, I30, I32 and I34, NOR gates I19, I39, NAND gates I37, I38, AND gates I40, OR gates I36, I41, I42, I43, adders I22, I23, I24 and a delay unit I35; Among them, the finish_dly line is connected to the CK terminal of the D flip-flop I11, and the output D terminal of the D flip-flop I11 is connected to the input Q terminal of I11 and the CK terminal of the D flip-flop I13 through the inverter I12; the output D terminal of the D flip-flop I13 is connected to the input Q terminal of I13 and the CK terminal of the D flip-flop I15 through the inverter I14; the output D terminal of the D flip-flop I15 is connected to the input Q terminal of the D flip-flop I15, the CK terminal of the D flip-flop I17 and one input terminal of the NOR gate I19 through the inverter I16; the output D terminal of the D flip-flop I17 is connected to the input Q terminal of the D flip-flop I17 and the other input terminal of the NOR gate I19 through the inverter I18; The reset terminals R of the D flip-flops I11, I13, I15 and I17 are all connected to cnt_rst; the input clock ckdff line is connected to the CK terminal of the D flip-flop I25, and the D terminal of the D flip-flop I25 is connected to the Q terminal of the D flip-flop I25 and the CK terminal of the D flip-flop I27 through the inverter I26; the output D terminal of the D flip-flop I27 is connected to the Q terminal of the D flip-flop I27 and the CK terminal of the D flip-flop I29 through the inverter I28; the output D terminal of the D flip-flop I29 is connected to the Q terminal of the D flip-flop I29 and the CK terminal of the D flip-flop I31 through the inverter I30; the output D terminal of the D flip-flop I31 is connected to the signal ckcnt3 through the inverter I32 to the Q terminal of the D flip-flop I31 and the CK terminal of the D flip-flop I33; the output D terminal of the D flip-flop I33 is connected to the signal ckcnt cnt4 is connected to the Q terminal of the D flip-flop I33 through the inverter I34; the signals ckcnt0 and ckcnt1 are respectively connected to the two input terminals of the NAND gate I37; the signals ckcnt2 and ckcnt3 are respectively connected to the two input terminals of the NAND gate I38; the output terminals of the NAND gates I37 and I38 are respectively connected to the two input terminals of the NOR gate I39; the output terminal of the NOR gate I39 and the input clock ckdff are respectively connected to the two input terminals of the AND gate I40; the reset terminals of the D flip-flops I25, I27, I29, I31 and I33 are all connected to the cnt_rst signal; the signal ckcnt4 is connected to the input terminal A of the delay unit I35, and is connected to one of the input terminals of the OR gate I36 through the output terminal O of the logic unit I35. The other input terminal of the OR gate I36 is connected to rst_syn, and the output terminal of the OR gate I36 is connected to the signal cnt_rst; The output of the NOR gate I19 is connected to the Q terminal of the D flip-flop I20; the output terminal of the AND gate I40 is connected to the CK terminal of the D flip-flop I20; the output terminal D of the D flip-flop I20 is connected to the Q terminal of the D flip-flop I21; the D terminal of the D flip-flop I21 is connected to the A terminal of the adder I22, and the CK terminal of the D flip-flop I21 is connected to the input signal ck terminal; the reset terminals R of the D flip-flops I20 and I21 are both connected to rst_syn; the B terminals of the adders I22, I23 and I24 are respectively input with the original delay control signal dly_in<2:0>; the CO terminal of adder I22 is connected to the A terminal of adder I23, and the CO terminal of adder I23 is connected to the CO terminal of adder I24; the S terminals of adders I22, I23 and I24 are respectively connected to the input terminals of OR gates I41, I42 and I43; the CO terminal of adder I24 is connected to the other input terminals of OR gates I41, I42 and I43; the output terminals of OR gates I41, I42 and I43 respectively output delay control signals dly_out<2:0>.

2. The PVT-stabilized successive approximation analog-to-digital converter according to claim 1, wherein: The successive approximation logic circuit includes a delay circuit IDLY, a NAND gate I1, successive approximation units I5, I6, I7 and I8, a delay unit I9, an AND gate I10, a D flip-flop I3 and an inverter I4; Among them, the positive and negative output signals of the comparator are Q and QB, which are connected as input signals to the two input terminals of the NAND gate I1 in the successive approximation logic circuit; the output signal of the NAND gate I1 is valid, which is respectively connected to the input terminal cki of the delay circuit IDLY and the CK terminal of the successive approximation units I5, I6, I7 and I8; the positive and negative output signals Q and QB of the comparator are also simultaneously connected to the positive data input D terminal and the negative data input DB terminal of the successive approximation units I5, I6, I7 and I8; the enable input terminal EN of the successive approximation unit I5 is connected to the input clock ckdff through the inverter I2; the next-level enable output terminal EN_N of the successive approximation unit I5 is connected to the EN terminal of the successive approximation unit I6; the output terminal EN_N of the successive approximation unit I6 is connected to the EN terminal of the successive approximation unit I7; the output terminal EN_N of the successive approximation unit I7 is connected to the line EN <3> Connect to the next successive approximation unit; the EN terminal of the nth successive approximation unit I8 is connected to the EN_N terminal of the n-1th successive logic unit; the output terminal EN_N of the successive approximation unit I8 is connected to the input terminal A of the delay unit I9, and after being delayed by the delay unit I9, it is input to one input terminal of the AND gate I10 through its O terminal. The output terminal EN_N of the successive approximation unit I8 is directly connected to the other input terminal of the AND gate I10; the output terminal line of the AND gate I10 is named finish_dly; the data input terminal Q of the D flip-flop I3 is connected to a logic high level "1", the clock input terminal CK is connected to the input clock ckdff, the reset input terminal R is connected to the input reset signal sar_rst, and the output terminal D is passed through the inverter I4 to obtain the synchronous reset signal rst_syn; The RST terminals of the successive approximation units I5, I6, I7 and I8 are all connected to rst_syn; the output CTL terminals of the successive approximation units I5, I6, I7 and I8 respectively output n-bit control signals Dac_ctl <n-1>to Dac_ctl <0> To the IDAC, it is used to control the lower plate switch of the capacitor of the switched capacitor DAC; the output Q end of the successive approximation unit I5, I6, I7 and I8 is the data output end, which outputs the output data Dout of n respectively. <n-1:0> As the output data of the entire analog-to-digital converter; the input terminal dly of the delay circuit IDLY is connected to the delay control signal dly_out<2:0>; the output terminal cko of the delay circuit IDLY is connected to the comparator enable clock line CMP_CK and connected to the ck terminal of the comparator ICMP.< / n-1:0>

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