Multiplexed signal parallel demultiplexing method based on FPGA and demultiplexing equalizer

Abstract

The invention provides a multiplexed signal parallel demultiplexing method based on an FPGA and a demultiplexing equalizer. The method comprises the following steps: receiving multiple paths of serial multiplexed signals from a high-speed link, performing oversampling processing on the received multiple paths of serial multiplexed signals, and performing parallelization processing on each path of serial multiplexed signals subjected to oversampling processing; inputting each path of parallelized signal into a butterfly equalization demultiplexing module, performing equalization processing on the input by using a periodically updated tap coefficient of the butterfly equalization demultiplexing module, and performing demultiplexing processing by using a CMA algorithm to obtain a received output signal for demultiplexing a multiplexing signal; sequentially selecting output signals of the butterfly equalization demultiplexing module at intervals according to a preset proportion, and calculating a tap coefficient accumulative error vector by combining the selected output signals and the corresponding input signals; and according to the iteration step length of the CMA algorithm, the tap coefficient of the butterfly equalization demultiplexing module is updated based on the tap coefficient accumulative error vector.

Description

Technical Field

[0001] The present invention relates to the field of digital communication technologies, and in particular, to a method for parallel demultiplexing of multiplexed signals based on FPGA and a demultiplexing equalizer. Background Art

[0002] In the context of the surging global data traffic, the capacity of single-mode fiber optic communication systems is gradually approaching the bottleneck of the non-linear Shannon limit. To break through this limitation, Polarization Division Multiplexing (PDM) technology enables dual-channel parallel transmission by utilizing the orthogonal polarization states of optical signals, directly doubling the transmission capacity of single-mode fibers. However, the random polarization coupling effect caused by Polarization Mode Dispersion (PMD) in the fiber will cause aliasing of the two polarization signals at the receiving end, severely restricting the system performance.

[0003] In this context, the Constant Modulus Blind Equalization Algorithm (MIMO-CMA) based on the Multiple Input Multiple Output (MIMO) architecture has shown significant advantages. This algorithm uses a 2×2 MIMO equalizer to track the dynamically changing polarization coupling state in real time, and can complete channel blind estimation and demultiplexing only by using the constant modulus characteristic of the signal itself. Compared with the traditional training sequence method, MIMO-CMA can achieve polarization decoupling without prior channel information, and is particularly suitable for fast polarization perturbation scenarios caused by factors such as temperature changes and mechanical stress in high-speed fiber optic systems. Experiments show that the separation error rate of this algorithm for polarization multiplexed signals can be reduced to 10 -4 order of magnitude, and at the same time has a dynamic response speed of sub-microsecond level, providing key support for single-mode fibers to achieve higher-order modulation formats and super-Nyquist rate transmission. Through the collaborative optimization of the polarization dimension and advanced equalization algorithms, single-mode fiber optic systems can continuously improve the spectral efficiency while maintaining the existing infrastructure, effectively delaying the urgency of upgrading to multi-mode fibers.

[0004] As a popular technology for high-speed signal transmission in the next-generation data center, PAM4 (4 Pulse Amplitude Modulation) signals have been widely used in the electrical and optical signal transmissions of 200G / 400G interfaces. With the continuous growth of social data demand, not only the data volume increases, but also the data transmission speed accelerates, making the traditional modulation scheme based on NRZ coding gradually insufficient. It is necessary to achieve data acquisition from point A to point B as efficiently as possible, whether it is the application of chips on PC boards or long-distance transmission at both ends of optical fibers. Among many modulation schemes, PAM4 is favored due to its advantages in multiple aspects.

[0005] In the prior art, the blind equalization of the Constant Modulus Algorithm (CMA) requires no other prior knowledge and has the advantages of low computational complexity, insensitivity to phase information, and easy implementation. As a channel adaptive equalization algorithm, it has good application potential and prospects in the fields of communication and signal processing. Therefore, it is often used as the target for hardware implementation of the demultiplexing algorithm in MDM systems.

[0006] However, common CMA algorithms are all serially implemented, which are not only inefficient but also have redundant implementation, and are not suitable for being arranged on an FPGA for Digital Signal Processing (DSP) at the receiving end of high-speed optical communication. In addition, problems such as inter-symbol interference and mode crosstalk exist in high-speed few-mode multiplexing demodulation systems.

[0007] Therefore, how to improve the CMA algorithm through parallelization and low-complexity processing to arrange it on an FPGA for efficient digital signal processing at the receiving end in high-speed optical communication scenarios is a technical problem to be solved urgently. Summary of the Invention

[0008] In view of this, embodiments of the present invention provide a method and a demultiplexing equalizer for parallel demultiplexing of multiplexed signals based on an FPGA to eliminate or improve one or more defects existing in the prior art.

[0009] One aspect of the present invention provides a method for parallel demultiplexing of multiplexed signals based on an FPGA, the method including the following steps: receiving multiple serial multiplexed signals from a high-speed link, performing oversampling processing on the received multiple serial multiplexed signals, and performing parallelization processing on each serial multiplexed signal that has completed oversampling processing; inputting each signal that has completed parallelization processing into a butterfly equalization demultiplexing module, performing equalization processing on the input using the tap coefficients periodically updated by the butterfly equalization demultiplexing module, and performing demultiplexing processing on the signal after equalization processing based on the CMA algorithm to obtain an output signal for demultiplexing the received multiplexed signal; sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, and calculating a tap coefficient cumulative error vector by combining the selected output signals and corresponding input signals; wherein, the preset ratio is the reciprocal of the oversampling processing multiple; and updating the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient cumulative error vector according to the iteration step of the CMA algorithm.

[0010] In some embodiments of the present invention, the modes of the multiplexed signals in multiple serial paths include a first mode and a second mode; the butterfly equalization demultiplexing module includes four sub-filters, wherein the first sub-filter and the second sub-filter are used to independently process the multiplexed signals in the first mode and the second mode respectively, and the third sub-filter and the fourth sub-filter are orthogonal to the first sub-filter and the second sub-filter.

[0011] In some embodiments of the present invention, the step of sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, and calculating the tap coefficient cumulative error vector by combining the selected output signals and the corresponding input signals includes: sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, calculating the error signal based on the selected output signals, and calculating the tap coefficient cumulative error vector by combining the calculated error signal and the corresponding input signals.

[0012] In some embodiments of the present invention, the step of updating the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient cumulative error vector according to the iteration step of the CMA algorithm includes: performing a multiplication operation on the iteration step of the CMA algorithm and the tap coefficient cumulative error vector, and the result of the multiplication operation is used to iteratively calculate and update the tap coefficients of the butterfly equalization demultiplexing module based on the momentum gradient algorithm; wherein, the range of the momentum factor of the momentum gradient algorithm is (0, 1).

[0013] In some embodiments of the present invention, the method further includes: delaying the update of the tap coefficients of the butterfly equalization demultiplexing module.

[0014] In some embodiments of the present invention, the method further includes: controlling the iteration step of the CMA algorithm through an error function; wherein, in the step control algorithm, the Taylor expansion is used to convert the exponential operation into addition, multiplication or division operations, and the divisor in the division operation is converted into the corresponding power of 2 it is close to.

[0015] In some embodiments of the present invention, the relationship of the fixed-point setting of the step control algorithm on the FPGA development board is set to 0.

[0016] Correspondingly to the above method, the present invention further provides a parallel demultiplexing equalizer for multiplexed signals based on FPGA, including: an input data module, configured to receive multiplexed serial signals from a high-speed link, perform oversampling processing on the received multiplexed serial signals, parallelize each oversampled multiplexed serial signal, and input each parallelized signal into a butterfly equalization demultiplexing module; a butterfly equalization demultiplexing module, configured to perform equalization processing on the input with periodically updated tap coefficients, and perform demultiplexing processing on the equalized signal based on the CMA algorithm to obtain an output signal for demultiplexing the received multiplexed signal; a Q proportion error accumulation module, configured to sequentially select the output signals of the butterfly equalization demultiplexing module at preset intervals, and calculate a tap coefficient accumulation error vector by combining the selected output signals and corresponding input signals; wherein the preset proportion is the reciprocal of the oversampling multiple; a tap coefficient update module, configured to update the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient accumulation error vector according to the iteration step of the CMA algorithm.

[0017] In some embodiments of the present invention, it further includes: a step size update module, configured to control the iteration step of the CMA algorithm through an error function; wherein, in the control step size algorithm, the exponential operation is converted into addition, multiplication or division operations by using the Taylor expansion formula, and the divisor in the division operation is converted into the corresponding power of 2 it is close to.

[0018] In some embodiments of the present invention, the butterfly equalization demultiplexing module includes four sub-filters, wherein the first sub-filter and the second sub-filter are used to independently process the multiplexed signals of the first mode and the second mode respectively, and the third sub-filter and the fourth sub-filter are orthogonal to the first sub-filter and the second sub-filter.

[0019] The parallel demultiplexing method and demultiplexing equalizer for multiplexed signals based on FPGA proposed by the present invention propose a new tap coefficient update method. Without changing the relatively low clock frequency of the FPGA, by setting different filters to be orthogonal to each other, the update of the tap coefficients of several of the demultiplexing channels is avoided.

[0020] The additional advantages, objects, and features of the present invention will be partially described below, and will become partially apparent to those of ordinary skill in the art after studying the following text, or can be learned from the practice of the present invention. The objects and other advantages of the present invention can be realized and obtained by the structures specifically pointed out in the specification and the drawings.

[0021] Those skilled in the art will understand that the purposes and advantages achievable with the present invention are not limited to those specifically described above, and the above and other purposes achievable with the present invention will be more clearly understood from the following detailed description. Description of the Drawings

[0022] The drawings described herein are used to provide a further understanding of the present invention, form a part of this application, and do not limit the present invention. The components in the drawings are not drawn to scale, but are only for showing the principles of the present invention. For the convenience of showing and describing some parts of the present invention, the corresponding parts in the drawings may be enlarged, that is, may become larger relative to other components in the exemplary device actually manufactured according to the present invention. In the drawings:

[0023] Figure 1 It is a flowchart of a method for parallel demultiplexing of multiplexed signals based on FPGA in an embodiment of the present invention.

[0024] Figure 2 It is a modeling of a parallel low-complexity MIMO demultiplexing algorithm based on FPGA in an embodiment of the present invention.

[0025] Figure 3 It is a modeling of a butterfly equalization demultiplexing module in an embodiment of the present invention.

[0026] Figure 4 It is a schematic diagram of tap coefficient update in an embodiment of the present invention.

[0027] Figure 5 It is a comparison diagram of algorithm performance in an embodiment of the present invention. Detailed Embodiments

[0028] To make the purposes, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the embodiments and the drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but do not limit the present invention.

[0029] Here, it should also be noted that in order to avoid obscuring the present invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the present invention are shown in the drawings, and other details less related to the present invention are omitted.

[0030] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, elements, steps, or components, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0031] Here, it should also be noted that if not specifically stated, the term "connection" in this article can not only refer to a direct connection, but also represent an indirect connection with an intermediate.

[0032] In the following, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0033] In the prior art, common CMA algorithms are all serially implemented, which are not only inefficient but also have redundant implementation, and are not suitable for being arranged on an FPGA for digital signal processing (DSP) at the receiving end of high-speed optical communication. In addition, problems such as inter-symbol interference and mode crosstalk exist in high-speed few-mode multiplexing demodulation systems.

[0034] To solve the problems existing in the prior art, the present invention proposes a parallel demultiplexing method for multiplexed signals based on an FPGA. In order to improve the parallelization and low-complexity processing of the constant modulus algorithm, it is arranged on the FPGA for multi-input multi-output (MIMO) demultiplexing at the receiving end in high-speed optical communication scenarios.

[0035] For the equalizer of few-mode multiplexing PAM4 signals in the present invention, on the basis of the original parallel implementation of the CMA algorithm, the improvements include: (1) A new tap coefficient update method is proposed. Without changing the relatively low clock frequency of the FPGA, by setting the filters of different paths to an orthogonal relationship, the update of the tap coefficients of several paths during demultiplexing is avoided; (2) An adaptive control step size method is introduced to improve the global convergence ability and maintain the stability of the algorithm without affecting the hardware implementation due to the increased complexity; (3) The method of delaying the update of weights is adopted, so that the CMA algorithm can be pipelined, reducing the timing pressure inside the FPGA and increasing the calculation speed, thereby meeting the requirement of maximizing the data throughput of blind equalization.

[0036] Figure 1 The flowchart of the parallel demultiplexing method for multiplexed signals based on an FPGA in an embodiment of the present invention is as follows. The steps include:

[0037] Step S110: Receive multiple serial multiplexed signals from a high-speed link, perform oversampling processing on the received multiple serial multiplexed signals, and parallelize each serial multiplexed signal that has completed oversampling processing.

[0038] In the specific implementation process, each serial multiplexed signal contains multiple multiplexed signals, and the multiple signals can be adjusted to be parallel. Each parallel multiplexed signal corresponds to an output, each output corresponds to an error signal, and each error signal corresponds to a tap coefficient cumulative error vector.

[0039] Step S120: Input the signals that have completed parallel processing for each path into the butterfly equalization demultiplexing module, perform equalization processing on the input using the tap coefficients periodically updated by the butterfly equalization demultiplexing module, and perform demultiplexing processing on the equalized signals based on the CMA algorithm to obtain the output signals for demultiplexing the received multiplexed signals.

[0040] Step S130: Sequentially select the output signals of the butterfly equalization demultiplexing module at preset intervals according to a preset ratio, and calculate the tap coefficient cumulative error vector by combining the selected output signals and the corresponding input signals; wherein, the preset ratio is the reciprocal of the oversampling processing multiple.

[0041] In the specific implementation process, the butterfly equalization demultiplexing module includes a butterfly equalizer for implementing equalization processing, and the update of the tap coefficients is the update of the tap coefficients in the butterfly equalizer.

[0042] Step S140: Update the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient cumulative error vector according to the iteration step size of the CMA algorithm.

[0043] By adopting the proposed parallel demultiplexing method for multiplexed signals based on FPGA, a new method for updating tap coefficients is proposed. Without changing the relatively low clock frequency of the FPGA, by setting different paths of filters to an orthogonal relationship, the update of the tap coefficients of several paths during demultiplexing is avoided.

[0044] In some embodiments of the present invention, the modes of the multiplexed signals in multiple paths in series include a first mode and a second mode.

[0045] Correspondingly, the butterfly equalization demultiplexing module includes four sub-filters, wherein the first sub-filter and the second sub-filter are used to independently process the multiplexed signals in the first mode and the second mode respectively, and the third sub-filter and the fourth sub-filter are in an orthogonal relationship with the first sub-filter and the second sub-filter.

[0046] In the specific implementation process, the optical fiber for transmitting the multiplexed signals in multiple paths in series is a few-mode optical fiber, and the multiplexing of PAM4 signals is realized in a mode division multiplexing system based on the few-mode optical fiber.

[0047] In another specific implementation process, the first mode is the LP01 mode, the second mode is the LP11a mode, and the signal type of the multiplexed signals in multiple paths in series includes PAM4 signals.

[0048] Adopting the embodiment of the present invention is beneficial to applying the parallel demultiplexing method of the multiplexed signal proposed by the present invention to multiplexed signals of various modes, and is beneficial to solving the interaction between non-degenerate mode coupling and differential mode group delay in the butterfly equalization demultiplexing module, so as to ensure the demultiplexing quality of the processed PAM4 signal. The structural design of this filter can not only initially prevent the appearance of singularities in terms of structure, but also eliminate the process of updating the tap coefficients of two of the paths, reducing the complexity of the algorithm.

[0049] In some embodiments of the present invention, the step of sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, and calculating the tap coefficient cumulative error vector by combining the selected output signals and the corresponding input signals includes: sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, calculating the error signal based on the selected output signals, and calculating the tap coefficient cumulative error vector by combining the calculated error signal and the corresponding input signals.

[0050] Adopting the embodiment of the present invention can reduce the calculation complexity compared with the prior art that needs to calculate each parallel error signal, and only needs to calculate the number of error signals of the preset ratio or quantity selected according to the Q ratio in each parallel path number.

[0051] In some embodiments of the present invention, the step of updating the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient cumulative error vector according to the iteration step of the CMA algorithm includes: performing a multiplication operation on the iteration step of the CMA algorithm and the tap coefficient cumulative error vector, and the result of the multiplication operation is iteratively calculated based on the momentum gradient algorithm to update the tap coefficients of the butterfly equalization demultiplexing module; wherein, the range of the momentum factor of the momentum gradient algorithm is (0, 1).

[0052] In the specific implementation process, the momentum gradient calculation is based on the current tap coefficients for momentum gradient calculation, and the result of the momentum gradient calculation is added to the result of the multiplication operation to obtain the updated tap coefficients. In the MIMO demultiplexing scenario applied by the present invention, the tap coefficients are not just a simple scalar, but a finite impulse response filter, where the length of the filter is determined by the total inter-mode parameter differential mode group delay of the system, and the strength of mode coupling determines the magnitude of each tap coefficient of the filter.

[0053] Adopting the embodiment of the present invention is beneficial to obtaining a better equalization effect by increasing a small amount of calculation, and the momentum term has no impact on the accelerated convergence of the algorithm.

[0054] In some embodiments of the present invention, the method further includes: delaying the update of the tap coefficients of the butterfly equalization demultiplexing module.

[0055] By adopting the embodiment of the present invention and delaying the update of weights, the CMA algorithm can be pipelined, reducing the timing pressure inside the FPGA and improving the calculation speed, thereby meeting the requirement of maximizing data throughput in blind equalization.

[0056] In some embodiments of the present invention, the method further includes: controlling the iteration step size of the CMA algorithm through an error function; wherein, in the step size control algorithm, the Taylor expansion is used to convert the exponential operation into addition, multiplication or division operations, and the divisor in the division operation is converted into the corresponding power of 2 it is close to.

[0057] By adopting the embodiment of the present invention, the calculation complexity of the step size factor can be simplified.

[0058] In some embodiments of the present invention, the fixed-point relationship setting of the step size control algorithm on the FPGA development board is 0.

[0059] By adopting the embodiment of the present invention, it can be avoided that the step size factor becomes too small in the later stage due to the step size control algorithm.

[0060] Figure 2 Modeling of a parallel low-complexity MIMO demultiplexing algorithm based on FPGA in an embodiment of the present invention. In this embodiment, the input signals are respectively from two PAM4 signals of the x polarization mode and the y polarization mode of single-mode fiber passing through 10 km. In this mode-division multiplexing (MDM) system based on few-mode fiber (FMF), the main impacts on the signals are the interaction between non-degenerate mode coupling and differential mode group delay (DMGD). The input-output relationship of the mode-division multiplexing system is expressed by the formula:

[0061]

[0062] In the formula, h 12 represents the channel impulse response between the first input mode and the second output mode. In the formula, x(t)=[x1(t), x2(t)] T represents the electrical signal sent to the MIMO equalizer after sampling and dispersion compensation. t represents the discrete time index, * represents convolution, and y(t)=[y1(t), y2(t)] T is the output signal of the equalizer. When each mode signal propagates independently in each section, a certain length of propagation delay will be accumulated. Therefore, at this time, h ijIt is no longer a simple scalar but a finite impulse response filter. The length of this filter is determined by the total inter-modal parameter differential mode group delay (DMGD) of the system, while the strength of mode coupling determines the magnitude of each tap coefficient of the filter.

[0063] Here, is the tap coefficient, which is the h mentioned later. xx This also indicates the mutual independence and orthogonality relationship among the four sub-filters.

[0064] The input data module receives a certain number of PAM4 signals from the high-speed link after a certain time and parallelizes them into a group of signals to be transmitted to the FPGA for processing, thus completing the cross-clock domain processing. The two signals after parallelization processing are sent to the butterfly equalizer for demultiplexing processing. Here, the two signals after parallelization processing are the signals after parallelizing the serial signals affected by the channel transmission matrix. As Figure 2 shown, X PB refers to when the serial LP01 mode PAM4 signal is parallelized, there are a total of X1, X2,..., X PB a total of PB signals are parallelized. The serial signal X1 is processed into the parallelized signal Input(X1), and the serial signal X PB is processed into the parallelized signal Input(XPB). output(X1) is the output signal after passing through the butterfly equalizer demultiplexing module. The same applies to the PAM4 signal of the LP11a mode.

[0065] It can be seen from the above description of the MDM system transmission model that the combined action of mode coupling and DMGD seriously affects the transmission performance of the MDM system. To recover the source signal, it is necessary to obtain the inverse of the channel transmission matrix at the receiving end through MIMO digital signal processing methods to achieve demultiplexing of the received signal. The channel transmission matrix here describes the influence on the two serial signals. Figure 2 The butterfly equalizer demultiplexing module in

[0066] Figure 3 models the butterfly equalizer demultiplexing module in an embodiment of the present invention, where a2, a3, a0 are the vector representations of I AA . Figure 3 The PB serial signals in AA are parallelized. k refers to the k-th parallelization, and Kpb refers to the index of the serial signal during the k-th parallelization. In the mathematical formula for calculating C Figure 3 , (i - 1)*PB is used to represent

[0067] For the two signals output by the butterfly demultiplexing module, according to the requirements of the traditional PCMA (Pulse Code Modulation with Adaptive Delta Modulation) algorithm, each parallel error signal ε AA (n) needs to be calculated and directly added, and finally multiplied by the input vector Xin(n) * to obtain the tap coefficient cumulative error vector C AA (i) during the i-th parallel processing, where the mathematical expression of C AA (i) is:

[0068]

[0069] Among them, n refers to the index of the signal participating in the calculation, and the formula expression of the error signal ε AA (i) is:

[0070] ε AA (n) = (R 2 -|x out (n)| 2 )*x out (n);

[0071] Among them, i can be understood as the parallel data input for the i-th time or the i-th parallelization, and based on this, the index of the signal that needs to participate in the calculation is calculated. C AA (i) refers to the tap coefficient cumulative error vector calculated by the i-th parallelization, which is used to calculate the tap coefficient h xx required for the next equalization.

[0072] It can be seen from the above expressions that the traditional PCMA algorithm needs to calculate each parallel error signal ε AA (i), which will lead to an increase in the complexity of the algorithm.

[0073] However, the method proposed in the present invention determines the Q ratio through the multiple of the previous oversampling process. This Q ratio is the reciprocal of the multiple of the oversampling process. According to this ratio, several error signals in parallel are sequentially selected at intervals to calculate C AA (i). Based on this, the complexity of the algorithm can be reduced. Finally, the mathematical expression of C AA (i) is updated to:

[0074]

[0075] Among them, Q represents the number of error signals selected in each parallel path, and R 2It represents a preset target value, which is used to define the squared amplitude that the signal should reach in an ideal situation. The selection of this value is based on the specific requirements of the system and the characteristics of the input signal. And due to the loss of some information of the error signal, the final converged missteady-state error will increase. At this time, it is necessary to make improvements in the tap coefficient update to reduce the steady-state error in exchange for a relatively low complexity. The function implemented by the Q proportional error accumulation module is This formula calculates the tap coefficient cumulative error vector C of the LP01 mode from the extracted error signal ε AA (n). Similarly, the tap coefficient cumulative error vector C of the LP11a mode can be calculated based on this AA . BA .

[0076] Figure 4 This is a schematic diagram of tap coefficient update in an embodiment of the present invention. In the figure, the momentum gradient algorithm is to calculate the momentum term α m [h(k - 1) - h(k - 2)], where α m is the momentum factor. The value of the momentum term has a great influence on the performance of the algorithm, which is controlled by the momentum factor α m . To ensure the robustness of the algorithm, it is required that the momentum factor |α| < 1. If α < 0, the momentum term has no effect on the accelerated convergence of the algorithm. Therefore, the value range of the momentum factor is 0 < α < 1. When the ideal equilibrium condition is reached, at this time h(k - 1) - h(k - 2) = 0. Compared with the CMA algorithm, the computational complexity increases slightly, but the increased complexity does not affect its hardware implementation.

[0077] Furthermore, in some embodiments of the present invention, a method for delaying the update of the tap coefficients of the filter is proposed, aiming to make the CMA algorithm pipelined and relieve the timing pressure brought by the algorithm on the FPGA board. In the specific implementation process, m is used to represent the number of cycles after the data input and the update of its corresponding filter coefficients are completed. That is to say, in the i-th cycle, the filter coefficient will be updated to the error value in the (i - m)-th cycle, rather than the error value in the (i - 1)-th cycle. In the first m cycles, all filter coefficients have the same value h(1), and they are updated in the (m - 1)-th cycle. The expression for the delayed update of the tap coefficients is:

[0078]

[0079] Among them, μ is the iteration step size of the algorithm. However, when using the CMA algorithm for demultiplexing, the convergence speed of CMA is relatively slow, the convergence accuracy is not good enough, and it is very easy to fall into singularity during convergence. Singularity means that during the demultiplexing process, the two output signals will converge to the same input signal with a certain probability. Only when two sub-filters are independent of each other, and the other two sub-filters are orthogonal to them. Then not only can the appearance of singularity be initially prevented in terms of structure, but also the process of updating the tap coefficients of two of them can be omitted, reducing the complexity of the algorithm. To sum up, the new expression for updating the tap coefficients is as follows:

[0080] h xx (i) = h xx (i - 1) + μC xx (i - m) + σ m [h xx (i - 1) - h xx (i - 2)];

[0081] h xy (i) = -h yx (i) * ;

[0082] h yx (i) = h yx (i - 1) + μC yx (i - m) + σ m [h yx (i - 1) - h yx (i - 2)];

[0083] h yy (i) = h xx (i) * ;

[0084] Furthermore, in order to improve the global convergence ability and stability of the algorithm, the step size factor can also be controlled by the error function e(n) to dynamically track signal changes. The traditional expression for variable step size is:

[0085] μ(n) = α(1 - exp(-e 2 (n)));

[0086] In the formula, α is the step size control parameter, usually between 10 -2 -10 -1 and, and the greater α is, the more significant the control effect of e(n) on the step size factor. The traditional expression for variable step size involves exponential operations and is not suitable for FPGA implementation. The exponential operation can be transformed into addition, multiplication, and division by using the Taylor expansion. And in order to further avoid division operations, each divisor is transformed into the corresponding power of 2 it is close to, so that the division operation can be transformed into a shift operation. Finally, ex It can be approximately obtained by the following expression:

[0087]

[0088] where x is the independent variable value of the function of e x By calculating the sum of the polynomials on the right side of the following formula, the corresponding value of e is approximately fitted. x Thus, when calculating μ(n) = α(1 - exp(-e 2 (n))), there is no need to calculate e x .

[0089] The algorithm runs on an FPGA development board. Generally, all data needs to be represented in fixed-point form. During actual operation, each data has a fixed bit width set in advance, so that the values that the data can represent are within a certain range. To avoid the situation where the step factor of the control step algorithm becomes too small in the later stage and is set to 0 due to the fixed-point relationship, resulting in non-convergence of the algorithm in the later stage, the new variable step-size expression is:

[0090]

[0091] Finally, the improved parallel CMA algorithm is compared with the traditional PCMA algorithm. The improved CMA algorithm abandons the practice of fully accumulating the error function in the traditional PCMA, and avoids the calculation of two of them by constructing the relationship of a four-way filter, and realizes the pipelining of the algorithm. As a result, the computing resources occupied by the improved CMA algorithm on the FPGA board are about 60% of those of the traditional PCMA algorithm. Figure 5 This is the algorithm performance comparison diagram in an embodiment of the present invention. From Figure 5 the comparison of the average bit error rate of the algorithm, it can be seen that in the actual demodulation of a 10 km mode division multiplexing PAM4 transmission system, the improved CMA algorithm has a performance improvement of about 2 dB compared to using the traditional algorithm.

[0092] Correspondingly to the above method, the present invention further provides a parallel demultiplexing equalizer for multiplexed signals based on FPGA, including: an input data module, configured to receive multiplexed serial signals from a high-speed link, perform oversampling processing on the received multiplexed serial signals, parallelize each oversampled multiplexed serial signal, and input each parallelized signal into a butterfly equalization demultiplexing module; a butterfly equalization demultiplexing module, configured to perform equalization processing on the input with tap coefficients updated periodically, and perform demultiplexing processing on the equalized signal based on the CMA algorithm to obtain an output signal for demultiplexing the received multiplexed signal; a Q proportion error accumulation module, configured to sequentially select the output signals of the butterfly equalization demultiplexing module at a preset proportion at intervals, and calculate a tap coefficient accumulation error vector by combining the selected output signals and corresponding input signals; wherein the preset proportion is the reciprocal of the oversampling processing multiple; a tap coefficient update module, configured to update the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient accumulation error vector according to the iteration step size of the CMA algorithm.

[0093] In some embodiments of the present invention, the parallel demultiplexing equalizer for multiplexed signals based on FPGA further includes: a step size update module, configured to control the iteration step size of the CMA algorithm through an error function; wherein, in the step size control algorithm, the Taylor expansion is used to convert the exponential operation into addition, multiplication or division operations, and the divisor in the division operation is converted into the corresponding power of 2 it is close to.

[0094] In some embodiments of the present invention, the butterfly equalization demultiplexing module includes four sub-filters, wherein the first sub-filter and the second sub-filter are used to independently process the multiplexed signals of the first mode and the second mode respectively, and the third sub-filter and the fourth sub-filter are orthogonal to the first sub-filter and the second sub-filter.

[0095] In order to improve the parallelization and low-complexity processing of the constant modulus algorithm, it is arranged on the FPGA for multi-input multi-output (MIMO) demultiplexing at the receiving end in a high-speed optical communication scenario.

[0096] In summary, the present invention mainly demonstrates a parallel low-complexity MIMO demultiplexing equalizer system model based on FPGA, an explanation of the low-complexity optimization of the equalization algorithm, and the principle of an adaptive step control algorithm for hardware optimization. The present invention is directed to an equalizer for few-mode multiplexed PAM4 signals. On the basis of the original parallel implementation of the CMA algorithm, the improvements include: (1) A new tap coefficient update method is proposed. Without changing the relatively low clock frequency of the FPGA, by setting the filters of different paths to an orthogonal relationship, the update of the tap coefficients of several paths in the demultiplexing is avoided; (2) An adaptive control step method is introduced to improve the global convergence ability and maintain the stability of the algorithm without the increased complexity affecting the hardware implementation; (3) A method of delaying the update of the weights is adopted, enabling the CMA algorithm to be pipelined, reducing the timing pressure inside the FPGA and increasing the calculation speed, so as to meet the requirement of maximizing the data throughput of blind equalization.

[0097] The method proposed by the present invention not only helps to reduce the complexity of implementing the CMA algorithm, but also ensures a good convergence effect at a relatively large convergence step.

[0098] Those of ordinary skill in the art should understand that the various exemplary components, systems, and methods described in connection with the embodiments disclosed herein can be implemented in hardware, software, or a combination of both. Specifically, whether to execute in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, and so on. When implemented in software, the elements of the present invention are programs or code segments used to execute the required tasks. The programs or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or a communication link.

[0099] It should be clear that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, the detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order between the steps after understanding the spirit of the present invention.

[0100] In the present invention, the features described and / or illustrated for one embodiment can be used in the same or a similar manner in one or more other embodiments, and / or combined with the features of other embodiments or replace the features of other embodiments.

[0101] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A parallel demultiplexing method for multiplexed signals based on FPGA, characterized in that, Including: Receiving a multiplexed signal in multiple serials from a high-speed link, performing oversampling processing on the received multiplexed signal in multiple serials, and performing parallelization processing on each oversampled serial multiplexed signal; Inputting each signal after parallelization processing into a butterfly equalization demultiplexing module, performing equalization processing on the input using the tap coefficients periodically updated by the butterfly equalization demultiplexing module, and performing demultiplexing processing on the signal after equalization processing based on the CMA algorithm to obtain an output signal for demultiplexing the received multiplexed signal; Sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, and calculating a tap coefficient cumulative error vector by combining the selected output signals and the corresponding input signals; wherein, the preset ratio is the reciprocal of the oversampling processing multiple; Updating the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient cumulative error vector according to the iteration step of the CMA algorithm.

2. The method according to claim 1, characterized in that, The mode of the multiplexed signal in multiple serials includes a first mode and a second mode; The butterfly equalization demultiplexing module includes four sub-filters, wherein the first sub-filter and the second sub-filter are used to independently process the multiplexed signals in the first mode and the second mode respectively, and the third sub-filter and the fourth sub-filter are orthogonal to the first sub-filter and the second sub-filter.

3. The method according to claim 1, characterized in that, The sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, and calculating a tap coefficient cumulative error vector by combining the selected output signals and the corresponding input signals includes: Sequentially and intermittently selecting the output signals of the butterfly equalization demultiplexing module according to a preset ratio, calculating an error signal based on the selected output signals, and calculating a tap coefficient cumulative error vector by combining the calculated error signal and the corresponding input signals.

4. The method according to claim 1, wherein The updating the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient cumulative error vector according to the iteration step of the CMA algorithm includes: Performing a multiplication operation on the iteration step of the CMA algorithm and the tap coefficient cumulative error vector, and iteratively calculating and updating the tap coefficients of the butterfly equalization demultiplexing module based on the result of the multiplication operation; wherein, the range of the momentum factor of the momentum gradient algorithm is (0, 1).

5. The method according to claim 4, wherein The method further includes: delaying the update of the tap coefficients of the butterfly equalization demultiplexing module.

6. The method according to claim 1, characterized in that, The method further includes: controlling the iteration step of the CMA algorithm through an error function; wherein, in the control step algorithm, the exponential operation is converted into addition, multiplication or division operations by using Taylor expansion, and the divisor in the division operation is converted into the corresponding power of 2 it is close to.

7. The method according to claim 6, wherein The fixed-point relationship setting of the control step algorithm on the FPGA development board is 0.

8. A parallel demultiplexing equalizer for multiplexed signals based on FPGA, characterized in that, Including: An input data module, configured to receive a multiplexed signal in multiple serials from a high-speed link, perform oversampling processing on the received multiplexed signal in multiple serials, perform parallelization processing on each oversampled serial multiplexed signal, and input each signal after parallelization processing into a butterfly equalization demultiplexing module; Butterfly equalization demultiplexing module, which is used to perform equalization processing on the input with periodically updated tap coefficients, and perform demultiplexing processing on the equalized signal based on the CMA algorithm to obtain an output signal for demultiplexing the received multiplexed signal; Q proportion error accumulation module, which sequentially selects the output signals of the butterfly equalization demultiplexing module at intervals according to a preset proportion, and calculates the tap coefficient accumulation error vector by combining the selected output signals and the corresponding input signals; wherein, the preset proportion is the reciprocal of the oversampling processing multiple; Tap coefficient update module, which updates the tap coefficients of the butterfly equalization demultiplexing module based on the tap coefficient accumulation error vector according to the iteration step size of the CMA algorithm.

9. The demultiplexing equalizer according to claim 8, characterized in that, It further includes: Step size update module, which is used to control the iteration step size of the CMA algorithm through an error function; wherein, in the control step size algorithm, the Taylor expansion is used to convert the exponential operation into addition, multiplication or division operations, and the divisor in the division operation is converted into the corresponding power of 2 it is close to.

10. The demultiplexing equalizer according to claim 8 or 9, characterized in that, Four sub-filters are included in the butterfly equalization demultiplexing module, wherein the first sub-filter and the second sub-filter are used to independently process the multiplexed signals of the first mode and the second mode respectively, and the third sub-filter and the fourth sub-filter are orthogonal to the first sub-filter and the second sub-filter.

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