Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region; first and second active patterns on the first and second regions, respectively, of the substrate; a bit line structure extending in a horizontal direction, the bit line structure including: a lower conductive structure having first and second conductive patterns alternately and repeatedly arranged in the horizontal direction, the first conductive pattern including polysilicon doped with first and second impurities, and the second conductive pattern including polysilicon doped with third impurities, and an upper conductive structure on the lower conductive structure and including a third conductive pattern; and a gate structure on the second active pattern, the gate structure including a gate insulating pattern and a fourth conductive pattern sequentially stacked in the vertical direction, the fourth conductive pattern including polysilicon doped with a second impurity.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2024-0009330, filed with the Korean Intellectual Property Office on January 22, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to semiconductor devices, and more particularly, to DRAM devices. Background Art

[0003] A DRAM device may include a bit line structure on a cell region and a gate structure on a peripheral circuit region. The bit line structure and the gate structure may each include a conductive pattern. The electrical characteristics of the bit line structure and the gate structure may vary according to the material of the conductive pattern. Summary of the Invention

[0004] Example embodiments provide a semiconductor device having improved characteristics.

[0005] According to an example embodiment, a semiconductor device may include: a substrate including a first region and a second region; a first active pattern and a second active pattern on the first region and the second region of the substrate, respectively; a bit line structure extending in a horizontal direction substantially parallel to the upper surface of the substrate, the bit line structure including: a lower conductive structure having first conductive patterns and second conductive patterns alternately and repeatedly arranged in the horizontal direction, the first conductive patterns including polysilicon doped with a first impurity and a second impurity, and the second conductive patterns including polysilicon doped with a third impurity, and an upper conductive structure on the lower conductive structure and including a third conductive pattern; a gate structure on the second active pattern, the gate structure including a gate insulating pattern and a fourth conductive pattern sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate, the fourth conductive pattern including polysilicon doped with the second impurity; a contact plug structure on each of the back ends of the first active pattern; and a capacitor on the contact plug structure.

[0006] According to an exemplary embodiment, a semiconductor device may include: a substrate including a first region and a second region; a first active pattern and a second active pattern on the first region and the second region of the substrate, respectively; a bit line structure including: a lower conductive structure extending in a horizontal direction substantially parallel to the upper surface of the substrate, the lower conductive structure contacting an upper surface of a central portion of the first active pattern, a first barrier pattern on the lower conductive structure, and a third conductive pattern on the first barrier pattern; a gate structure on the second active pattern, the gate structure including a gate insulating pattern, a fourth conductive pattern, a second barrier pattern, and a fifth conductive pattern sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate, and an upper surface of the fourth conductive pattern being higher than an upper surface of the lower conductive structure; a contact plug structure on each of opposite ends of the first active pattern; and a capacitor on the contact plug structure.

[0007] According to an exemplary embodiment, a semiconductor device may include: a substrate including a first region and a second region; a first active pattern and a second active pattern on the first region and the second region of the substrate, respectively; a bit line structure including: a lower conductive structure extending in a horizontal direction substantially parallel to the upper surface of the substrate, the lower conductive structure having first conductive patterns and second conductive patterns alternately and repeatedly arranged in the horizontal direction, a corresponding conductive pattern of the second conductive patterns contacting an upper surface of a central portion of the first active pattern, a first barrier pattern on the lower conductive structure, and a third conductive pattern on the first barrier pattern; a gate structure on the second active pattern, the gate structure including a gate insulating pattern, a second barrier pattern, and a fourth conductive pattern sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate; a contact plug structure on each of opposite ends of the first active pattern; and a capacitor on the contact plug structure, and wherein the first barrier pattern and the second conductive pattern and the second barrier pattern and the fourth conductive pattern respectively include substantially the same material.

[0008] In a semiconductor device according to some exemplary embodiments, conductive patterns included in a bit line structure on a cell region and a gate structure on a peripheral circuit region, respectively, may have impurities with a desired concentration. Accordingly, the bit line structure and the gate structure may have improved electrical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 are a plan view and a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0010] Figures 4 to 31 are a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0011] Figure 32 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0012] Figures 33 to 37 The plan view and cross-sectional view illustrate a method of manufacturing a semiconductor device according to an exemplary embodiment. Detailed Description

[0013] From the following detailed description with reference to the accompanying drawings, the above and other aspects and features of a semiconductor device and a method of manufacturing a semiconductor device according to some exemplary embodiments will become readily understood. It will be understood that although the terms "first", "second", and / or "third" may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structures, and / or processes, these various materials, layers, regions, pads, electrodes, patterns, structures, and / or processes should not be limited by these terms. These terms are only used to distinguish one material, layer, region, pad, electrode, pattern, structure, or process from another material, layer, region, pad, electrode, pattern, structure, or process. Thus, "first", "second", and / or "third" may be selectively or interchangeably used for each material, layer, region, electrode, pad, pattern, structure, or process, respectively.

[0014] Hereinafter, two directions among the horizontal directions that are substantially parallel to the upper surface of the substrate 100 and that can be substantially orthogonal to each other may be referred to as a first direction D1 and a second direction D2, respectively, and a direction among the horizontal directions that can have an acute angle with respect to each of the first direction D1 and the second direction D2 may be referred to as a third direction D3. In addition, a direction that is substantially perpendicular to the upper surface of the substrate 100 may be referred to as a vertical direction.

[0015] Although the terms "same", "equal", or "equivalent" are used in the description of the exemplary embodiments, it will be understood that there may be some imprecision. Thus, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0016] When the terms "about", "substantially", or "approximately" are used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operating tolerances (e.g., ±10%) centered on the recited numerical value. In addition, when the word "about", "substantially", or "approximately" is used in connection with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather the tolerance of the shape is within the disclosed range. Further, whether the numerical value or shape is modified with "about" or "substantially", it will be understood that these values and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) centered on the recited numerical value or shape.

[0017] Figure 1 The plan view illustrates a semiconductor device according to an exemplary embodiment. Figure 2 including along Figure 1A cross-sectional view taken along lines A-A' and B-B', and Figure 3 is a cross-sectional view taken along Figure 1 line C-C'.

[0018] Referring to Figures 1 to 3 , the semiconductor device may include a first active pattern 101, a second active pattern 105, a first gate structure 170, a second gate structure 330, a bit line structure 395, a contact plug structure, a wiring 605, a second upper contact plug 607, and a capacitor 670 on a substrate 100.

[0019] The semiconductor device may further include an isolation pattern 110, a first insulating pattern structure 215, a fourth insulating pattern 410, a fifth insulating pattern 420, a spacer structure 465, a fourth spacer 490, a second ohmic contact pattern 501, a fence pattern 480 (see Figure 29 ), a gate spacer 340, a first etch stop layer 360, an insulating intermediate layer 370, a capping layer 380, and a second insulating pattern structure 625.

[0020] The substrate 100 may include silicon, germanium, silicon germanium, or a group III-V compound semiconductor (such as, GaP, GaAs, or GaSb). In some example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0021] A first region I of the substrate 100 may be a cell region on which memory cells are formed, and a second region II of the substrate 100 surrounding the first region I of the substrate 100 may be a peripheral circuit region on which peripheral circuit patterns for driving the memory cells are formed. Figures 1 to 3 A part of the first region I and parts of the second region II adjacent to the first region I in the first direction D1 and the second direction D2 are respectively shown.

[0022] The first active pattern 101 may extend along a third direction D3 on the first region I of the substrate 100, and a plurality of first active patterns 101 may be spaced apart from each other in the first direction D1 and the second direction D2. The second active pattern 105 may be spaced apart from each other in the first direction D1 and the second direction D2 on the second region II of the substrate 100.

[0023] Sidewalls of the first active pattern 101 and the second active pattern 105 may be covered by the isolation pattern 110. The first active pattern 101 and the second active pattern 105 may include substantially the same material as the substrate 100, and the isolation pattern 110 may include an oxide (e.g., silicon oxide).

[0024] With Figure 7 and Figure 8 Refer to togetherFigures 1 to 3 As shown in Figures 1 to 3 , a first gate structure 170 may be formed in a fourth recess 40 that extends in a first direction D1 through an upper portion of a first active pattern 101 and an isolation pattern 110. The first gate structure 170 may include a first gate insulating pattern 120 on a bottom and sidewalls of the fourth recess 40, a first gate electrode on a portion of the first gate insulating pattern 120 that is on the bottom and lower sidewalls of the fourth recess 40, and a first gate mask 160 on the first gate electrode. The first gate electrode may include a first conductive pattern 140 and a second conductive pattern 150 stacked in a vertical direction in sequence, and a first barrier pattern (although not shown) may also be disposed between the first gate insulating pattern 120 and the first conductive pattern 140.

[0025] The first gate insulating pattern 120 may include an oxide (e.g., silicon oxide), the first barrier pattern may include a metal nitride (e.g., titanium nitride, tantalum nitride), the first conductive pattern 140 may include a metal (e.g., tungsten), a metal nitride (e.g., titanium nitride and tantalum nitride), a metal silicide, doped polysilicon, etc., and the first gate mask 160 may include an insulating nitride (e.g., silicon nitride).

[0026] In some example embodiments, the first gate structure 170 may extend in the first direction D1 over a first region I of the substrate 100, and a plurality of first gate structures 170 may be spaced apart from each other in a second direction D2.

[0027] In relation to Figure 14 and Figure 15 in conjunction with Figures 1 to 3 As shown in Figures 1 to 3 , a first opening 230 that extends through the first insulating layer structure 210 and exposes upper surfaces of the first active pattern 101, the isolation pattern 110, and the first gate mask 160 of the first gate structure 170 may be formed, and an upper surface of a central portion of the first active pattern 101 in a third direction D3 may be exposed through the first opening 230.

[0028] In some example embodiments, an area of a bottom of the first opening 230 may be larger than an area of an upper surface of the first active pattern 101. Accordingly, the first opening 230 may also expose an upper surface of a portion of the isolation pattern 110 adjacent to the first active pattern 101. Additionally, the first opening 230 may extend through an upper portion of the first active pattern 101 and a portion of the isolation pattern 110 adjacent to the first active pattern 101, and thus a bottom of the first opening 230 may be lower than upper surfaces of each opposite edge portion of the first active pattern 101 in the third direction D3.

[0029] The bit line structure 395 may include a fifth conductive pattern 243, a sixth conductive pattern 247, a third barrier pattern 255, a seventh conductive pattern 265, a third mask 275, a first etch stop pattern 365, and a capping pattern 385 that are sequentially stacked in a vertical direction on the first opening 230 or the first insulating pattern structure 215. The fifth conductive pattern 243 and the sixth conductive pattern 247 may jointly form a lower conductive structure, the third barrier pattern 255 and the seventh conductive pattern 265 may jointly form an upper conductive structure, and the third mask 275, the first etch stop pattern 365, and the capping pattern 385 may jointly form an insulating structure. In one example, the bit line structure 395 may extend in a horizontal direction (e.g., the second direction D2) substantially parallel to the upper surface of the substrate 100.

[0030] The lower conductive structure may extend in the second direction D2. The fifth conductive pattern 243 of the lower conductive structure may be formed on the first insulating pattern structure 215 outside the first opening 230, and the sixth conductive pattern 247 may be formed on the first opening 230. The fifth conductive pattern 243 and the sixth conductive pattern 247 may be alternately arranged and in contact with each other in the second direction D2.

[0031] In some example embodiments, the lower surface of the sixth conductive pattern 247 may be lower than the lower surface of the fifth conductive pattern 243 and in contact with the upper surface of the central portion of the first active pattern 101.

[0032] The fifth conductive pattern 243 and the sixth conductive pattern 247 may include, for example, polysilicon doped with impurities. The impurities may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0033] In some example embodiments, the fifth conductive pattern 243 may include a first impurity and a second impurity, and the first impurity and the second impurity may be the same as or different from each other. Hereinafter, the doping concentration of the impurities in the fifth conductive pattern 243 (i.e., the sum of the doping concentration of the first impurity and the doping concentration of the second impurity) may be referred to as the first doping concentration.

[0034] In some example embodiments, the sixth conductive pattern 247 may include a third impurity. Hereinafter, the doping concentration of the third impurity in the sixth conductive pattern 247 may be referred to as the third doping concentration.

[0035] In some example embodiments, the third doping concentration of the sixth conductive pattern 247 may be greater than the first doping concentration of the fifth conductive pattern 243.

[0036] The third blocking pattern 255 may include a metal nitride (e.g., titanium nitride), a metal silicon nitride (e.g., titanium silicon nitride), the seventh conductive pattern 265 may include a metal (e.g., tungsten), and each of the third mask 275, the first etch stop pattern 365, and the capping pattern 385 may include an insulating nitride (e.g., silicon nitride).

[0037] In some example embodiments, the bit line structure 395 may extend along a second direction D2 on a first region I of the substrate 100, and a plurality of bit line structures 395 may be spaced apart from each other in a first direction D1.

[0038] The fourth insulating pattern 410 and the fifth insulating pattern 420 may be formed in the first opening 230 and may contact the lower sidewalls of the bit line structure 395. The fourth insulating pattern 410 may include an oxide (e.g., silicon oxide), and the fifth insulating pattern 420 may include an insulating nitride (e.g., silicon nitride).

[0039] The first insulating pattern structure 215 may be formed on the first active pattern 101 and the isolation pattern 110 below the bit line structure 395, and may include a first insulating pattern 185, a second insulating pattern 195, and a third insulating pattern 205 sequentially stacked in a vertical direction. The first insulating pattern 185 and the third insulating pattern 205 may include an oxide (e.g., silicon oxide), and the second insulating pattern 195 may include an insulating nitride (e.g., silicon nitride).

[0040] The spacer structure 465 may include a first spacer 400 covering the sidewalls of the bit line structure 395 and the sidewalls of the third insulating pattern 205, an air spacer 435 on the lower outer sidewalls of the first spacer 400, and a third spacer 450 on the outer sidewalls of the air spacer 435, the sidewalls of the first insulating pattern structure 215, the upper surfaces of the fourth insulating pattern 410, and the upper surfaces of the fifth insulating pattern 420.

[0041] Each of the first spacer 400 and the third spacer 450 may include an insulating nitride (e.g., silicon nitride), and the air spacer 435 may include air.

[0042] The fourth spacer 490 may be formed on the outer sidewalls of a portion of the first spacer 400 on the upper sidewalls of the bit line structure 395, and may cover the upper ends of the air spacer 435 and the upper surfaces of the third spacer 450. The fourth spacer 490 may include an insulating nitride (e.g., silicon nitride).

[0043] The second gate structure 330 may be at least partially stacked with the second active pattern 105 in a vertical direction on a second region II of the substrate 100. Accordingly, a plurality of second gate structures 330 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0044] The second gate structure 330 may include a second gate insulating pattern 280, a third conductive pattern 290, a second blocking pattern 300, a fourth conductive pattern 310, and a second gate mask 320 that are sequentially stacked in a vertical direction, and the third conductive pattern 290, the second blocking pattern 300, and the fourth conductive pattern 310 may commonly form a second gate electrode.

[0045] The second gate insulating pattern 280 of the second gate structure 330 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), etc.

[0046] The third conductive pattern 290, the second blocking pattern 300, the fourth conductive pattern 310, and the second gate mask 320 of the second gate structure 330 may include the same materials as the fifth conductive pattern 243, the third blocking pattern 255, the seventh conductive pattern 265, and the third mask 275 of the bit line structure 395, respectively.

[0047] However, different from the fifth conductive pattern 243 of the bit line structure 395 including polysilicon doped with a first impurity and a second impurity, the third conductive pattern 290 of the second gate structure 330 may include polysilicon doped only with the second impurity among the first impurity and the second impurity. That is, the third conductive pattern 290 of the second gate structure 330 may not include the first impurity.

[0048] In some exemplary embodiments, a first doping concentration of the first impurity and the second impurity included in the fifth conductive pattern 243 may be greater than a second doping concentration of the second impurity included in the third conductive pattern 290. Therefore, among a first doping concentration of the fifth conductive pattern 243 of the bit line structure 395, a second doping concentration of the third conductive pattern 290 of the second gate structure 330, and a third doping concentration of the sixth conductive pattern 247 of the bit line structure 395, the third doping concentration is the largest and the second doping concentration is the smallest.

[0049] In some exemplary embodiments, the first doping concentration may be about 1.4 times to about 5 times the second doping concentration.

[0050] In some exemplary embodiments, an upper surface of the third conductive pattern 290 of the second gate structure 330 may be higher than an upper surface of a lower conductive structure of the bit line structure 395.

[0051] The gate spacer 340 may cover sidewalls of the second gate structure 330. The gate spacer 340 may include an oxide (e.g., silicon oxide) or an insulating nitride (e.g., silicon nitride).

[0052] However, the structures of the spacer structure 465 and the gate spacer 340 are not limited thereto, and each of the spacer structure 465 and the gate spacer 340 may include a single spacer or more than two spacers stacked in sequence.

[0053] The first etch stop layer 360 may be formed on the second region II of the substrate 100 to cover the upper surface of the second gate structure 330, the outer sidewalls of the gate spacer 340, and the upper surface of the second active pattern 105. The first etch stop layer 360 may include the same material as the first etch stop pattern 365.

[0054] The insulating intermediate layer 370 may be formed on the first etch stop layer 360 on the second region II of the substrate 100 to a sufficient height, and the uppermost surface of the insulating intermediate layer 370 may be substantially coplanar with the upper surface of a portion of the first etch stop layer 360 on the second gate structure 330. The insulating intermediate layer 370 may include an oxide (e.g., silicon oxide), and the capping layer 380 may include a nitride (e.g., silicon nitride).

[0055] The capping layer 380 may be disposed on the first etch stop layer 360 and the insulating intermediate layer 370 on the second region II of the substrate 100. The capping layer 380 may include an insulating nitride (e.g., silicon nitride).

[0056] The contact plug structure may include a lower contact plug 475, a first ohmic contact pattern 500, and a first upper contact plug 549 stacked in sequence in the vertical direction on the first active pattern 101 and the isolation pattern 110 on the first region I of the substrate. In some example embodiments, the contact plug structure may be on each of the opposite ends of the first active pattern 101.

[0057] The lower contact plug 475 may contact the upper surface of an edge portion of the first active pattern 101 in the third direction D3. In some example embodiments, a plurality of lower contact plugs 475 may be spaced apart from each other in the second direction D2, and a fence pattern 480 may be formed between adjacent lower contact plugs among the lower contact plugs 475 in the second direction D2. The fence pattern 480 may include an insulating nitride (e.g., silicon nitride).

[0058] The lower contact plug 475 may include, for example, doped polysilicon, and the first ohmic contact pattern 500 may include a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.).

[0059] The first upper contact plug 549 may include a first metal pattern 545 and a fourth barrier pattern 535 covering the lower surface of the first metal pattern 545. The first metal pattern 545 may include a metal (e.g., tungsten), and the fourth barrier pattern 535 may include a metal nitride (e.g., titanium nitride).

[0060] In some example embodiments, a plurality of first upper contact plugs 549 may be spaced apart from each other in a first direction D1 and a second direction D2, and may be arranged in a honeycomb pattern or a lattice pattern in a plan view. In the plan view, each first upper contact plug 549 may have a shape such as a circle, an ellipse, or a polygon.

[0061] The wiring 605 may include a second metal pattern 595 and a fifth barrier pattern 585 covering the lower surface of the second metal pattern 595. In some example embodiments, a plurality of wirings 605 may be spaced apart from each other in a first direction D1 and a second direction D2.

[0062] The second ohmic contact pattern 501 may be formed on the upper surface of the second active pattern 105 adjacent to the second gate structure 330.

[0063] The second upper contact plug 607 may include a third metal pattern 597 and a sixth barrier pattern 587 covering the lower surface of the third metal pattern 597. The second upper contact plug 607 may extend through the capping layer 380, the insulating intermediate layer 370, and the second gate insulating pattern 280 to contact the upper surface of the second ohmic contact pattern 501.

[0064] Each of the second metal pattern 595 and the third metal pattern 597 may include a metal (e.g., tungsten), and each of the fifth barrier pattern 585 and the sixth barrier pattern 587 may include a metal nitride (e.g., titanium nitride). Together with Figure 29 and Figure 30 referring to Figures 1 to 3 , the second insulating pattern structure 625 may include a sixth insulating pattern 610 on the inner wall of the seventh opening 547 and a seventh insulating pattern 620 disposed on the sixth insulating pattern 610 and filling the remaining portion of the seventh opening 547. The seventh opening 547 may extend through the first upper contact plug 549, a part of the insulating structure of the bit line structure 395, and parts of the first spacer 400, the third spacer 450, and the fourth spacer 490, and may surround the first upper contact plug 549 in a plan view. The upper end of the air spacer 435 may be closed by the sixth insulating pattern 610.

[0065] The sixth insulating pattern 610 and the seventh insulating pattern 620 may include an insulating nitride (e.g., silicon nitride).

[0066] The second etch stop layer 630 may be formed on the sixth insulating pattern 610, the seventh insulating pattern 620, the first upper contact plug 549, and the fence pattern 480. The second etch stop layer 630 may include an insulating nitride (e.g., boron nitride silicon, silicon nitride, etc.).

[0067] The capacitor 670 may include a lower electrode 640, a dielectric layer 650, and an upper electrode 660 sequentially stacked, and the lower electrode 640 may extend through the second etch stop layer 630 to contact the upper surface of the first upper contact plug 549. In some example embodiments, the lower electrode 640 may have a shape such as a pillar or a cylinder.

[0068] The lower electrode 640 may include, for example, a metal, a metal nitride, a metal silicide, or polysilicon doped with impurities. The dielectric layer 650 may include, for example, a metal oxide, and the upper electrode 660 may include, for example, a metal, a metal nitride, a metal silicide, or silicon germanium (SiGe) doped with impurities.

[0069] In the semiconductor device, a first doping concentration of a fifth conductive pattern 243 of the bit line structure 395 may be greater than a second doping concentration of a third conductive pattern 290 of the second gate structure 330. Accordingly, while an increase in the threshold voltage of the second gate structure 330 can be prevented, a low resistance of the bit line structure 395 can be maintained.

[0070] In addition, an upper surface of a lower conductive structure of the bit line structure 395 may be lower than an upper surface of the third conductive pattern 290 of the second gate structure 330. Accordingly, an aspect ratio of the bit line structure 395 including the lower conductive structure can be reduced, thereby reducing the difficulty of manufacturing the semiconductor device. In addition, a parasitic capacitance between the bit line structure 395 including the lower conductive structure and the contact plug structure can be reduced.

[0071] Figures 4 to 31 are a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment.

[0072] Specifically, Figure 4 , Figure 7 , Figure 9 , Figure 11 , Figure 14 , Figure 18 , Figure 21 , Figure 25 and Figure 29 are plan views, Figure 5 , Figure 10 , Figures 12 to 13 , Figures 15 to 17 , Figures 19 to 20 , Figures 22 to 24 , Figures 26 to 28 and Figures 30 to 31 include cross-sectional views taken along lines A-A' and B-B' of the corresponding plan views, respectively, and Figure 6 and Figure 8 are cross-sectional views taken along line C-C' of the corresponding plan view.

[0073] Referring to Figures 4 to 6, a first active pattern 101 and a second active pattern 105 can be formed on a substrate 100 including a first region I and a second region II.

[0074] The first active pattern 101 and the second active pattern 105 can be formed by removing an upper portion of the substrate 100 to form a recess structure.

[0075] The recess structure can include a first recess 102, a second recess 104, and a third recess 106. The first recess 102 can be formed between first active patterns in the first active pattern 101 that are spaced apart from each other by a relatively small distance, the second recess 104 can be formed between first active patterns in the first active pattern 101 that are spaced apart from each other by a relatively large distance, and the third recess 106 can be formed on the second region II of the substrate 100 or between the first region I and the second region II of the substrate 100.

[0076] In some example embodiments, the third recess 106 can have a width and / or depth greater than the width and / or depth of the second recess 104, and the second recess 104 can have a width and / or depth greater than the width and / or depth of the first recess 102.

[0077] An isolation pattern 110 can be formed to cover sidewalls of the first active pattern 101 and the second active pattern 105. Accordingly, the first active pattern 101 and the second active pattern 105 with sidewalls covered by the isolation pattern 110 can be defined.

[0078] Referring to Figure 7 and Figure 8 , an etching process can be performed on the first active pattern 101 and the isolation pattern 110 on the first region I of the substrate 100 to form a fourth recess 40 extending in a first direction D1.

[0079] In some example embodiments, during the etching process, due to etching selectivity, the first active pattern 101 including a semiconductor material can be etched less than the isolation pattern 110 including an insulating material. Accordingly, the fourth recess 40 can have a concave upper surface on the upper surface of the first active pattern 101.

[0080] A first gate insulating layer and a first conductive layer can be sequentially stacked on inner walls of the fourth recess 40, the upper surface of the first active pattern 101, the upper surface of the second active pattern 105, and the upper surface of the isolation pattern 110, the first gate insulating layer and the first conductive layer can be planarized until the upper surfaces of the first active pattern 101, the second active pattern 105, and the isolation pattern 110 are exposed, and an upper portion of the first conductive layer can be removed by, for example, a re-etch process.

[0081] The planarization process can include a chemical mechanical polishing (CMP) process and / or a re-etch process.

[0082] Through a planarization process, a first gate insulating pattern 120 can be formed on the inner wall of the fourth recess 40, and through an etch-back process, a first conductive pattern 140 can be formed on the first gate insulating pattern 120 to fill the lower portion of the fourth recess 40.

[0083] A second conductive pattern 150 can be formed on the first conductive pattern 140, a first gate mask layer can be formed on the second conductive pattern 150, the first active pattern 101, the second active pattern 105, and the isolation pattern 110 to fill the fourth recess 40, and the first gate mask layer can be planarized until the upper surfaces of the first active pattern 101, the second active pattern 105, and the isolation pattern 110 are exposed, so that a first gate mask 160 can be formed to fill the upper portion of the fourth recess 40. The first conductive pattern 140 and the second conductive pattern 150 can commonly form a first gate electrode, and a first barrier pattern (although not shown) can also be formed between the first gate insulating pattern 120 and the first conductive pattern 140.

[0084] The first gate insulating pattern 120, the first barrier pattern, the first conductive pattern 140, the second conductive pattern 150, and the first gate mask 160 in the fourth recess 40 can commonly form a first gate structure 170.

[0085] Refer to Figure 9 and Figure 10 As shown in FIGS. and, a first insulating layer structure 210 can be formed on the first region I and the second region II of the substrate 100, and a part of the first insulating layer structure 210 on the second region II of the substrate 100 can be removed.

[0086] The first insulating layer structure 210 can include a first insulating layer to a third insulating layer 180, 190, and 200 stacked in sequence.

[0087] A second gate insulating pattern 280 can be formed on the upper surface of the second active pattern 105 on the second region II of the substrate 100. For example, a thermal oxidation process can be performed on the second active pattern 105 on the second region II of the substrate 100 to form the second gate insulating pattern 280.

[0088] A preliminary third conductive layer 240a can be formed on the third insulating layer 200 on the first region I of the substrate 100 and on the isolation pattern 110 and the second gate insulating pattern 280 on the second region II of the substrate 100. The preliminary third conductive layer 240a can include, for example, undoped polysilicon.

[0089] Refer to Figure 11 and Figure 12, a first mask 241 can be formed to cover a part of the preliminary third conductive layer 240a on the second region II of the substrate 100, and thus, the upper surface of the preliminary third conductive layer 240a on the first region I of the substrate 100 can be exposed.

[0090] The upper part of the exposed preliminary third conductive layer 240a can be removed by, for example, performing an etch-back process, and thus, the upper surface of the preliminary third conductive layer 240a on the first region I of the substrate 100 can be lower than the upper surface of the preliminary third conductive layer 240a on the second region II of the substrate 100.

[0091] A first doping process can be performed on the exposed preliminary third conductive layer 240a to dope the preliminary third conductive layer 240a with a first impurity. The first impurity can include an n-type impurity (e.g., phosphorus (P), arsenic (As), etc.). In some example embodiments, the first doping process can be performed by, for example, an ion implantation (IIP) process, a gas-phase doping (GPD) process, or the like.

[0092] In some example embodiments, an etch-back process can be performed after the first doping process.

[0093] Referring to Figure 13 , after removing the first mask 241, a second doping process can be performed on the preliminary third conductive layer 240a to additionally dope the preliminary third conductive layer 240a with a second impurity. Thus, the preliminary third conductive layer 240a can be converted into the third conductive layer 240.

[0094] The second impurity can include an n-type impurity (e.g., phosphorus (P), arsenic (As), etc.). In some example embodiments, the second impurity can be the same as or different from the first impurity.

[0095] Through the first doping process, compared with the second part of the third conductive layer 240 on the second region II of the substrate 100, the first part of the third conductive layer 240 on the first region I of the substrate 100 can further include the first impurity. Thus, the doping concentration of the first part of the third conductive layer 240 on the first region I of the substrate 100 (i.e., the concentration of the first impurity and the second impurity in the first part of the third conductive layer 240) can be greater than the doping concentration of the second part of the third conductive layer 240 on the second region II of the substrate 100 (i.e., the concentration of the second impurity in the second part of the third conductive layer 240).

[0096] In some example embodiments, the second doping process can be performed by, for example, an ion implantation (IIP) process, a gas-phase doping (GPD) process, or the like.

[0097] Referring to Figure 14 and Figure 15, a second mask 242 may be formed on the third conductive layer 240. The third conductive layer 240, the first insulating layer structure 210, the first active pattern 101, the isolation pattern 110, and the first gate mask 160 of the first gate structure 170 may be etched by an etching process using the second mask 242 as an etching mask to form a first opening 230.

[0098] In some example embodiments, the etched first insulating layer structure 210 may have a circular or elliptical shape in a plan view, and a plurality of first insulating layer structures 210 may be spaced apart from each other along a first direction D1 and a second direction D2 on a first region I of the substrate 100. The first insulating layer structure 210 may be respectively stacked with an end portion of the first active pattern 101 in a third direction D3 in a vertical direction substantially perpendicular to the upper surface of the substrate 100.

[0099] Referring to Figure 16 , a fourth conductive layer 245 may be formed to a sufficient height within the first opening 230, and an etch-back process may be performed on an upper portion of the fourth conductive layer 245.

[0100] In some example embodiments, an upper surface of the fourth conductive layer 245 may be substantially coplanar with an upper surface of the third conductive layer 240.

[0101] In some example embodiments, the fourth conductive layer 245 may be formed by a deposition process using a source gas of a third impurity and a source gas of silicon. Accordingly, the fourth conductive layer 245 may include polysilicon doped with the third impurity. The third impurity may include an n-type impurity (e.g., phosphorus (P), arsenic (As), etc.).

[0102] Referring to Figure 17 , the second mask 242 may be removed, and a first barrier layer 250, a fifth conductive layer 260, and a third mask layer 270 may be sequentially stacked on the third conductive layer 240 and the fourth conductive layer 245 on the first region I and the second region II of the substrate 100.

[0103] The third conductive layer 240, the fourth conductive layer 245, and the fifth conductive layer 260 may jointly form a conductive structure layer.

[0104] In some example embodiments, an upper surface of a part of the third mask layer 270 on the first region I of the substrate 100 and an upper surface of a part of the third mask layer 270 on the second region II of the substrate 100 may be substantially coplanar with each other.

[0105] Referring to Figure 18 and Figure 19 , the conductive structure layer may be patterned to form a second gate structure 330 on the second region II of the substrate 100.

[0106] The second gate structure 330 may include a second gate insulating pattern 280, a third conductive pattern 290, a second blocking pattern 300, a fourth conductive pattern 310, and a second gate mask 320 that are sequentially stacked in a vertical direction, and the third conductive pattern 290, the second blocking pattern 300, and the fourth conductive pattern 310 may commonly form a second gate electrode.

[0107] The second gate structure 330 may at least partially overlap with the second active pattern 105 in a vertical direction on a second region II of the substrate 100.

[0108] A gate spacer 340 may be formed on sidewalls of the second gate structure 330. The gate spacer 340 may be formed by forming a gate spacer layer on the substrate 100 on which the second gate structure 330 is formed, and anisotropically etching the gate spacer layer.

[0109] A first etch stop layer 360 may be conformally formed on the substrate 100 on which a conductive structure layer, the second gate structure 330, the gate spacer 340, and the isolation pattern 110 are formed.

[0110] In some example embodiments, a plurality of second gate structures 330 may be spaced apart from each other in a first direction D1 and a second direction D2.

[0111] Referring to Figure 20 and, an insulating intermediate layer 370 may be formed to a sufficient height on the first etch stop layer 360, the insulating intermediate layer 370 may be planarized until the upper surface of the second gate structure 330 and a part of the upper surface of the first etch stop layer 360 on the conductive structure layer are exposed, and a capping layer 380 may be formed on the insulating intermediate layer 370 and the first etch stop layer 360.

[0112] Therefore, the insulating intermediate layer 370 may fill the space between the gate spacers 340 on the sidewalls of the second gate structure 330.

[0113] Referring to Figure 21 and Figure 22 and, a part of the capping layer 380 on a first region I of the substrate 100 may be etched to form a capping pattern 385, and the first etch stop layer 360, the third mask layer 270, the fifth conductive layer 260, the first blocking layer 250, the fourth conductive layer 245, and the third conductive layer 240 may be sequentially etched using the capping pattern 385 as an etch mask.

[0114] In some example embodiments, the capping pattern 385 may extend in the second direction D2 on the first region I of the substrate 100, and a plurality of capping patterns 385 may be formed to be spaced apart from each other in the first direction D1. The capping layer 380 may remain on the second region II of the substrate 100.

[0115] Through an etching process, on the first region I of the substrate 100, a sixth conductive pattern 247, a third barrier pattern 255, a seventh conductive pattern 265, a third mask 275, a first etch stop pattern 365, and a capping pattern 385 can be sequentially stacked on the first opening 230, and a third insulating pattern 205, a fifth conductive pattern 243, a third barrier pattern 255, a seventh conductive pattern 265, a third mask 275, a first etch stop pattern 365, and a capping pattern 385 can be sequentially stacked on the second insulating layer 190 of the first insulating layer structure 210 outside the first opening 230.

[0116] The fifth conductive pattern 243 and the sixth conductive pattern 247 can jointly form a lower conductive structure, the third barrier pattern 255 and the seventh conductive pattern 265 can jointly form an upper conductive structure, and the third mask 275, the first etch stop pattern 365, and the capping pattern 385 can jointly form an insulating structure. Hereinafter, the lower conductive structure, the upper conductive structure, and the insulating structure can jointly form a bit line structure 395.

[0117] Referring to Figure 23 , a first spacer layer can be formed on the substrate 100 on which the bit line structure 395 and the capping layer 380 are formed, and a fourth insulating layer and a fifth insulating layer can be sequentially formed on the first spacer layer.

[0118] The first spacer layer can also cover the sidewalls of the third insulating pattern 205 below the bit line structure 395 on the second insulating layer 190, and the fifth insulating layer can fill the remaining portion of the first opening 230.

[0119] The fourth insulating layer and the fifth insulating layer can be etched by an etching process. In some example embodiments, the etching process can be a wet etching process using, for example, phosphoric acid (H2PO3), SCl, and hydrofluoric acid (HF) as etchants, and the portions of the fourth insulating layer and the fifth insulating layer other than their portions in the first opening 230 can be removed. Thus, most of the surface of the first spacer layer (i.e., all portions of the surface of the first spacer layer other than a part of its surface in the first opening 230) can be exposed, and the fourth insulating layer and the fifth insulating layer remaining in the first opening 230 can form a fourth insulating pattern 410 and a fifth insulating pattern 420, respectively.

[0120] A second spacer layer can be formed on the exposed surface of the first spacer layer and on the fourth insulating pattern 410 and the fifth insulating pattern 420 in the first opening 230. The second spacer layer can be anisotropically etched to form a second spacer 430 covering the sidewalls of the bit line structure 395 on the surface of the first spacer layer and on the fourth insulating pattern 410 and the fifth insulating pattern 420.

[0121] The capping pattern 385 and the second spacer 430 can be used as an etch mask to perform a dry etching process to form a second opening 440 that exposes the upper surface of the first active pattern 101, and the upper surfaces of the isolation pattern 110 and the first gate mask 160 can also be exposed through the second opening 440.

[0122] Through the dry etching process, portions of the first spacer layer on the upper surface of the capping layer 380, the upper surface of the capping pattern 385, and the upper surface of the second insulating layer 190 can be removed, and thus the first spacer 400 can be formed on the sidewalls of the bit line structure 395.

[0123] Through the dry etching process, the first insulating layer 180 and the second insulating layer 190 can be partially removed to respectively leave the first insulating pattern 185 and the second insulating pattern 195 below the bit line structure 395. The first insulating pattern to the third insulating pattern 185, 195, and 205 stacked sequentially below the bit line structure 395 can form the first insulating pattern structure 215.

[0124] Refer to Figure 24 and a third spacer layer can be formed on the upper surfaces of the capping layer 380 and the capping pattern 385, the outer sidewalls of the second spacer 430, the portions of the upper surfaces of the fourth insulating pattern 410 and the fifth insulating pattern 420, and the upper surfaces of the first active pattern 101, the isolation pattern 110, and the first gate mask 160 exposed through the second opening 440. The third spacer layer can be anisotropically etched to form the third spacer 450 that covers the outer sidewalls of the second spacer 430.

[0125] The first spacer to the third spacer 400, 430, and 450 stacked sequentially on the sidewalls of the bit line structure 395 in the horizontal direction on the first region I of the substrate 100 can be referred to as the preliminary spacer structure 460.

[0126] Refer to Figure 25 and Figure 26 and a preliminary lower contact plug layer can be formed to fill the second opening 440 on the first region I of the substrate 100 to a sufficient height, and the upper portion of the preliminary lower contact plug layer can be planarized until the upper surfaces of the capping layer 380 and the capping pattern 385 are exposed, so as to form the lower contact plug 475 in the second opening 440.

[0127] The lower contact plug 475 can extend in the second direction D2 between adjacent bit line structures in the first direction D1 in the bit line structure 395 on the first region I of the substrate 100, and a plurality of lower contact plugs 475 can be spaced apart from each other in the first direction D1.

[0128] A second mask including a plurality of third openings may be formed on the capping layer 380 and the lower contact plug 475, where each of the plurality of third openings may extend in a first direction D1 and be spaced apart from each other in a second direction D2, and the lower contact plug 475 may be etched using the second mask as an etching mask to form a fourth opening.

[0129] In some example embodiments, each third opening may be stacked with the first gate structure 170 in the vertical direction. Through an etching process, a fourth opening may be formed to expose the upper surface of the first gate mask 160 of the first gate structure 170. Accordingly, the lower contact plug 475 may be divided into a plurality of portions spaced apart from each other in the second direction D2. Each lower contact plug 475 may contact the upper surface of an end portion of the first active pattern 101 extending in a third direction D3 in the vertical direction.

[0130] After removing the etching mask, a fence pattern 480 may be formed to fill the fourth opening. The plurality of fence patterns 480 may be spaced apart from each other in the second direction D2 between the bit line structures 395.

[0131] As described above, the lower contact plug 475 and the fence pattern 480 that may be alternately and repeatedly arranged in the second direction D2 may be formed by the following steps: forming a preliminary lower contact plug layer extending in the second direction D2 between the bit line structures 395, planarizing the preliminary lower contact plug layer to form the lower contact plug 475, forming fourth openings spaced apart from each other in the second direction D2 through the lower contact plug 475, and filling the fourth openings with the fence pattern 480. However, the inventive concept is not limited thereto.

[0132] In some example embodiments, the lower contact plug 475 and the fence pattern 480 that may be alternately and repeatedly arranged in the second direction D2 may be formed by the following steps: forming a fence layer extending in the second direction D2 between the bit line structures 395, forming fifth openings spaced apart from each other in the second direction D2 through the fence layer to divide the fence layer into the fence patterns 480, forming a preliminary lower contact plug layer on the fence layer to fill the fifth openings, and planarizing the lower contact plug layer to form the lower contact plug 475.

[0133] In some example embodiments, the lower contact plug 475 and the fence pattern 480 that may be alternately and repeatedly arranged in the second direction D2 may be formed by the following steps: forming a sacrificial layer including an oxide (e.g., silicon oxide) and extending in the second direction D2 between the bit line structures 395, forming the fence patterns 480 spaced apart from each other in the second direction D2 through the sacrificial layer, removing the sacrificial layer to form a sixth opening, forming a preliminary lower contact plug layer to fill the sixth opening, and planarizing the preliminary lower contact plug layer to form the lower contact plug 475.

[0134] Reference Figure 27 The upper portion of the lower contact plug 475 can be removed to expose the upper portion of the preliminary spacer structure 460 on the sidewall of the bit line structure 395, and the upper portions of the second spacer 430 and the third spacer 450 of the exposed preliminary spacer structure 460 can be removed.

[0135] The upper portion of the lower contact plug 475 can be additionally removed. Accordingly, the upper surface of the lower contact plug 475 can be lower than the upper surfaces of the second spacer 430 and the third spacer 450.

[0136] A fourth spacer layer can be formed on the bit line structure 395, the preliminary spacer structure 460, the fence pattern 480, and the lower contact plug 475, and the fourth spacer layer can be anisotropically etched to form a fourth spacer 490 covering the upper portion of the preliminary spacer structure 460 on the sidewall of the bit line structure 395, and the upper surface of the lower contact plug 475 can be exposed through an etching process. Additionally, the insulating intermediate layer 370 and the capping layer 380 can be etched to form contact holes exposing the upper surface of the second active pattern 105 adjacent to the second gate structure 330. In some example embodiments, a plurality of contact holes can be formed to be spaced apart from each other in a first direction D1 and a second direction D2.

[0137] A first ohmic contact pattern 500 can be formed on the exposed upper surface of the lower contact plug 475, and a second ohmic contact pattern 501 can be formed on the exposed upper surface of the second active pattern 105. In some example embodiments, the first ohmic contact pattern 500 and the second ohmic contact pattern 501 can be formed by the following steps: forming a first metal layer on the capping pattern 385, the fourth spacer 490, the lower contact plug 475, and the second active pattern 105, performing a heat treatment on the first metal layer, and removing the unreacted portion of the first metal layer.

[0138] The first ohmic contact pattern 500 can be formed only on the exposed upper surface of the lower contact plug 475, but the inventive concept is not limited thereto. That is, during the heat treatment process, the metal of the first metal layer can diffuse in the horizontal direction such that the first ohmic contact pattern 500 can also be formed on the upper surface of the lower contact plug 475 covered by the fourth spacer 490.

[0139] Reference Figure 28 A second barrier layer 530 can be formed on the capping pattern 385, the fence pattern 480, the fourth spacer 490, the first ohmic contact pattern 500, and the lower contact plug 475 in the first region I of the substrate 100 and on the capping layer 380, the inner sidewalls of the contact holes, and the second ohmic contact pattern 501 in the second region II of the substrate 100, and a second metal layer 540 can be formed on the second barrier layer 530 to fill the space between the bit line structure 395 and the contact holes.

[0140] Referring to Figure 29 and Figure 30 , the second metal layer 540 and the second barrier layer 530 can be patterned.

[0141] Accordingly, a first upper contact plug 549 can be formed on the first region I of the substrate 100, and a wiring 605 and a second upper contact plug 607 can be formed on the second region II of the substrate 100. A seventh opening 547 can be formed between the first upper contact plug 549, the wiring 605, and the second upper contact plug 607.

[0142] The seventh opening 547 can be formed by partially removing not only the second metal layer 540 and the second barrier layer 530 but also a capping pattern 385, a first etch stop pattern 365, a third mask 275, a fourth spacer 490, a fence pattern 480, and a preliminary spacer structure 460 on the first region I of the substrate 100, as well as a capping layer 380 on the second region II of the substrate 100. The seventh opening 547 can expose the upper surface of the second spacer 430.

[0143] When the seventh opening 547 is formed, the second metal layer 540 and the second barrier layer 530 can be respectively converted into a first metal pattern 545 that "collectively forms the first upper contact plug 549 on the first region I of the substrate 100" and a fourth barrier pattern 535 that covers the lower surface of the first metal pattern 545.

[0144] The lower contact plug 475, the first ohmic contact pattern 500, and the first upper contact plug 549 sequentially stacked on the first region I of the substrate 100 can collectively form a contact plug structure.

[0145] The second metal layer 540 and the second barrier layer 530 that are not stacked with the contact hole in the vertical direction can be respectively converted into a second metal pattern 595 that "collectively forms the wiring 605 on the second region II of the substrate 100" and a fifth barrier pattern 585 that covers the lower surface of the second metal pattern 595.

[0146] The second metal layer 540 and the second barrier layer 530 that are stacked with the contact hole in the vertical direction can be respectively converted into a third metal pattern 597 that "collectively forms the second upper contact plug 607 on the second region II of the substrate 100" and a sixth barrier pattern 587 that covers the lower surface of the third metal pattern 597.

[0147] Referring to Figure 31 , the second spacer 430 can be removed to form an air gap connected to the seventh opening 547. The second spacer 430 can be removed by, for example, a wet etching process.

[0148] In some example embodiments, not only the first portion of the second spacer 430 directly exposed by the seventh opening 547 on the sidewall of the bit line structure 395 can be removed, but also the second portion of the second spacer 430 parallel to the first portion in the horizontal direction can be removed. That is, not only the portion of the second spacer 430 exposed by the seventh opening 547 and not covered by the first upper contact plug 549 can be removed, but also the portion of the second spacer 430 covered by the first upper contact plug 549 can be removed.

[0149] A second insulating pattern structure 625 can be formed to fill the seventh opening 547.

[0150] In some example embodiments, the second insulating pattern structure 625 can include a sixth insulating pattern 610 and a seventh insulating pattern 620 stacked in sequence. The sixth insulating pattern 610 can include a material with poor gap filling characteristics, and thus the air gap may not be filled with the sixth insulating pattern 610 but may be retained, which can be referred to as the air spacer 435. The first spacer 400, the third spacer 450, and the air spacer 435 can jointly form a spacer structure 465. The air spacer 435 can be a spacer including air. The seventh insulating pattern 620 can include an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride).

[0151] Referring back to Figures 1 to 3 , a capacitor 670 can be formed to contact the upper surface of the first upper contact plug 549.

[0152] For example, a second etch stop layer 630 and a molding layer can be sequentially formed on the first upper contact plug 549, the second insulating pattern structure 625, and the wiring 605, and the second etch stop layer 630 and the molding layer can be partially etched to form an eighth opening that partially exposes the upper surface of the first upper contact plug 549.

[0153] A lower electrode layer can be formed on the exposed upper surface of the first upper contact plug 549 and the molding layer to fill the eighth opening, and the lower electrode layer can be planarized until the upper surface of the molding layer is exposed to form a lower electrode 640 having a column shape. In some example embodiments, the lower electrode 640 can be formed to have a cylindrical shape. The molding layer can be removed by, for example, a wet etching process.

[0154] A dielectric layer 650 can be formed on the upper surface of the lower electrode 640 and the upper surface of the second etch stop layer 630, and an upper electrode 660 can be formed on the dielectric layer 650 to form a capacitor 670 including the lower electrode 640, the dielectric layer 650, and the upper electrode 660 on the first region I of the substrate 100.

[0155] Contact plugs and upper wirings may also be formed on the substrate 100 to be electrically connected to the capacitor 670, the bit line structure 395, and the wiring 605, so that the manufacturing of the semiconductor device can be completed.

[0156] As shown above, a third conductive layer 240 may be formed on the substrate 100 including the first region I and the second region II. A first mask 241 may be formed to cover a second portion of the third conductive layer 240 on the second region II of the substrate 100. A first doping process may be performed on a first portion of the third conductive layer 240 on the first region I of the substrate 100 that is not covered by the first mask 241. The first mask 241 may be removed, and a second doping process may be performed on the first portion and the second portion of the third conductive layer 240. Therefore, the doping concentration of impurities in the first portion of the third conductive layer 240 on the first region I may be greater than the doping concentration of impurities in the second region II of the third conductive layer 240. And thus, the first doping concentration of impurities in the fifth conductive pattern 243 obtained from the first portion of the third conductive layer 240 on the first region I may be greater than the second doping concentration of impurities obtained from the second portion of the third conductive layer 240 on the second region II.

[0157] If the first doping process is not performed on the third conductive layer 240, the doping concentration of impurities in each of the fifth conductive pattern 243 of the bit line structure 395 and the third conductive pattern 290 of the second gate structure 330 may be determined only by the second doping process. Therefore, the doping concentration of impurities in the fifth conductive pattern 243 and the third conductive pattern 290 cannot be independently adjusted based on the electrical characteristics of each of the bit line structure 395 and the second gate structure 330. For example, when the doping concentration of impurities is increased during the second doping process to reduce the resistance of the bit line structure 395, the doping concentration of impurities in the third conductive pattern 290 of the second gate structure 330 may also increase, resulting in an increase in the threshold voltage of the second gate structure 330.

[0158] However, in the method of manufacturing a semiconductor device according to some example embodiments, not only the second doping process performed on the first portion and the second portion of the third conductive layer 240 may be executed, but also the first doping process selectively performed only on the first portion of the third conductive layer 240 on the first region I of the substrate 100 may be executed. Therefore, through the first doping process, the first doping concentration of impurities in the fifth conductive pattern 243 of the bit line structure 395 and the second doping concentration of impurities in the third conductive pattern 290 of the second gate structure 330 can be independently adjusted. And thus, the electrical characteristics of the semiconductor device can be improved.

[0159] In addition, after forming a first mask 241 that covers a second portion on a second region II of the substrate 100 and covers the third conductive layer 240, an upper portion of a first portion of the third conductive layer 240 that is not covered by the first mask 241 on the first region I of the substrate 100 can be removed. Accordingly, the height of the fifth conductive pattern 243 can be reduced to decrease the aspect ratio of the bit line structure 395 including the fifth conductive pattern 243, thereby reducing the overall process difficulty. In addition, as the aspect ratio of the bit line structure 395 decreases, the parasitic capacitance between the bit line structure 395 and the contact plug structure can also be reduced.

[0160] Figure 32 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0161] Except for the second gate structure 330 including the third gate insulating pattern 285 instead of the second gate insulating pattern 280, the semiconductor device can be substantially the same as or similar to Figures 1 to 3 the semiconductor device.

[0162] Referring to Figure 32 , the second gate structure 330 can include a third gate insulating pattern 285, a third conductive pattern 290, a second barrier pattern 300, a fourth conductive pattern 310, and a second gate mask 320.

[0163] In some exemplary embodiments, the third gate insulating pattern 285 can include a high-k material (such as a metal oxide having a high dielectric constant (e.g., hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), etc.)).

[0164] In one exemplary embodiment, an upper surface of the fourth conductive pattern 310 of the second gate structure 330 and an upper surface of the seventh conductive pattern 265 of the bit line structure 395 can be substantially coplanar with each other. In one exemplary embodiment, the third barrier pattern 255 and the seventh conductive pattern 265 can include substantially the same materials as the second barrier pattern 300 and the fourth conductive pattern 310, respectively.

[0165] Figures 33 to 37 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment. Specifically, Figure 34 is a plan view, and Figure 33 and Figures 35 to 37 include cross-sectional views taken along lines A-A' and B-B' of the corresponding plan view, respectively. The method can include processes substantially the same as or similar to the processes shown in reference to Figures 4 to 31 and Figures 1 to 3 , and thus repeated explanations thereof are omitted herein.

[0166] Referring to Figure 33 , processes can be performed similar to those in reference to Figures 4 to 10The processes shown are basically the same or similar processes.

[0167] That is, a first insulating layer structure 210 may be formed on a first region I and a second region II of the substrate 100, and a part of the first insulating layer structure 210 on the second region II of the substrate 100 may be removed. However, different from the processes described with reference to Figure 9 and Figure 10 a third conductive layer 240 may be formed on the first insulating layer structure 210 on the first region I of the substrate 100 and on the second active pattern 105 and the isolation pattern 110 on the second region II of the substrate 100. The third conductive layer 240 may include, for example, polysilicon doped with an n-type impurity (e.g., phosphorus (P), arsenic (As), etc.).

[0168] In one exemplary embodiment, the third conductive layer 240 may be formed by forming a preliminary third conductive layer 240a including undoped polysilicon and performing an IIP process and / or a GPD process on it. In another exemplary embodiment, the third conductive layer 240 may be formed by performing a deposition process using a source gas of silicon and a source gas of an n-type impurity.

[0169] With reference to Figure 34 and Figure 35 , a fourth mask 244 may be formed on a first portion of the third conductive layer 240 on the first region I of the substrate 100, and a second portion of the third conductive layer 240 on the second region II of the substrate 100 may be removed.

[0170] Accordingly, the upper surfaces of the second active pattern 105 and the isolation pattern 110 on the second region II of the substrate 100 may be exposed.

[0171] With reference to Figure 36 , a third gate insulating pattern 285 may be formed on the first region I and the second region II of the substrate 100, and a part of the third gate insulating pattern 285 on the first region I of the substrate 100 may be removed.

[0172] The third gate insulating pattern 285 may include a metal oxide having a high dielectric constant (e.g., hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), etc.). In some exemplary embodiments, the third gate insulating pattern 285 may be formed by a deposition process.

[0173] With reference to Figure 37 , after removing the fourth mask 244, a first barrier layer 250, a fifth conductive layer 260, and a third mask layer 270 may be sequentially formed on the third conductive layer 240 and the third gate insulating pattern 285.

[0174] Thereafter, by performing the same as that with reference to Figures 18 to 31 andFigures 1 to 3 The manufacturing of semiconductor devices is accomplished by processes that are substantially the same as or similar to the processes shown.

[0175] Although some example embodiments have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, comprising: A substrate, including a first region and a second region; A first active pattern and a second active pattern, respectively on the first region and the second region of the substrate; A bit line structure, extending in a horizontal direction parallel to the upper surface of the substrate, the bit line structure comprising: A lower conductive structure, having first conductive patterns and second conductive patterns alternately and repeatedly arranged in the horizontal direction, the first conductive patterns comprising polysilicon doped with a first impurity and a second impurity, and the second conductive patterns comprising polysilicon doped with a third impurity, and An upper conductive structure, on the lower conductive structure and including a third conductive pattern; A gate structure, on the second active pattern, the gate structure including a gate insulating pattern and a fourth conductive pattern sequentially stacked in a vertical direction perpendicular to the upper surface of the substrate, the fourth conductive pattern comprising polysilicon doped with the second impurity; A contact plug structure, on each of the opposite ends of the first active pattern; and A capacitor, on the contact plug structure.

2. The semiconductor device according to claim 1, wherein A first doping concentration is greater than a second doping concentration of the second impurity of the fourth conductive pattern, the first doping concentration being the sum of the doping concentration of the first impurity and the doping concentration of the second impurity of the first conductive pattern.

3. The semiconductor device according to claim 2, wherein, The first doping concentration is 1.4 times to 5 times the second doping concentration.

4. The semiconductor device according to claim 2, wherein, A third doping concentration of the third impurity of the second conductive pattern is greater than the first doping concentration.

5. The semiconductor device according to claim 1, wherein, The first impurity and the second impurity are different from each other.

6. The semiconductor device according to claim 1, wherein, The first impurity and the second impurity are the same as each other.

7. The semiconductor device according to claim 1, wherein, The lower surface of the second conductive pattern contacts the upper surface of the central portion of the first active pattern and is lower than the lower surface of the first conductive pattern.

8. The semiconductor device according to claim 1, wherein, The upper conductive structure includes a first barrier pattern on the lower conductive structure and a third conductive pattern on the first barrier pattern, Wherein, the gate structure includes a second barrier pattern and a fifth conductive pattern on the fourth conductive pattern, and Wherein, the first barrier pattern and the third conductive pattern respectively comprise the same materials as the second barrier pattern and the fifth conductive pattern.

9. A semiconductor device, comprising: A substrate, including a first region and a second region; A first active pattern and a second active pattern, respectively on the first region and the second region of the substrate; A bit line structure, comprising: A lower conductive structure, extending in a horizontal direction parallel to the upper surface of the substrate, the lower conductive structure contacting the upper surface of the central portion of the first active pattern, A first barrier pattern, on the lower conductive structure, and A third conductive pattern, on the first barrier pattern; A gate structure, on the second active pattern, the gate structure including a gate insulating pattern, a fourth conductive pattern, a second barrier pattern and a fifth conductive pattern sequentially stacked in a vertical direction perpendicular to the upper surface of the substrate, and the upper surface of the fourth conductive pattern is higher than the upper surface of the lower conductive structure; A contact plug structure, on each of the opposite ends of the first active pattern; and A capacitor, on the contact plug structure.

10. The semiconductor device according to claim 9, wherein, The lower conductive structure has first conductive patterns and second conductive patterns alternately and repeatedly arranged in the horizontal direction, and the second conductive pattern contacts the upper surface of the central portion of the first active pattern.

11. The semiconductor device according to claim 10, wherein, The lower surface of the second conductive pattern is lower than the lower surface of the first conductive pattern.

12. The semiconductor device according to claim 10, wherein, The first conductive pattern, the second conductive pattern, and the fourth conductive pattern contain n-type impurities, and a first doping concentration of the n-type impurities in the first conductive pattern is greater than a second doping concentration of the n-type impurities in the fourth conductive pattern.

13. The semiconductor device according to claim 12, wherein, The first doping concentration is 1.4 times to 5 times the second doping concentration.

14. The semiconductor device according to claim 12, wherein, A third doping concentration of the n-type impurities in the second conductive pattern is greater than the first doping concentration.

15. The semiconductor device according to claim 9, wherein, The first blocking pattern and the third conductive pattern respectively contain the same material as the second blocking pattern and the fifth conductive pattern.

16. A semiconductor device, comprising: a substrate including a first region and a second region; a first active pattern and a second active pattern respectively on the first region and the second region of the substrate; a bit line structure, comprising: a lower conductive structure extending in a horizontal direction parallel to an upper surface of the substrate, the lower conductive structure having the first conductive pattern and the second conductive pattern alternately and repeatedly arranged in the horizontal direction, the second conductive pattern contacting an upper surface of a central portion of the first active pattern; a first blocking pattern on the lower conductive structure; and a third conductive pattern on the first blocking pattern; a gate structure on the second active pattern, the gate structure including a gate insulating pattern, a second blocking pattern, and a fourth conductive pattern sequentially stacked in a vertical direction perpendicular to the upper surface of the substrate; a contact plug structure on each of opposite ends of the first active pattern; and a capacitor on the contact plug structure; and wherein the first blocking pattern and the third conductive pattern respectively contain the same material as the second blocking pattern and the fourth conductive pattern.

17. The semiconductor device according to claim 16, wherein, The gate insulating pattern contains a high-k dielectric material.

18. The semiconductor device according to claim 16, wherein, Each of the first blocking pattern and the second blocking pattern contains a metal nitride or a metal silicon nitride.

19. The semiconductor device according to claim 16, wherein, An upper surface of the third conductive pattern and an upper surface of the fourth conductive pattern are coplanar with each other.

20. The semiconductor device according to any one of claims 16 to 19, wherein, A lower surface of the second conductive pattern is lower than a lower surface of the first conductive pattern.

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