Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes at least one memory cell. The memory cell includes a first electrode layer, a second electrode layer spaced apart from the first electrode layer, and a memory layer interposed between the first electrode layer and the second electrode layer. The first electrode layer includes a first amorphous carbon layer and a first graphene-containing layer interposed between the memory layer and the first amorphous carbon layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0008718, filed with the Korean Intellectual Property Office on January 19, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to semiconductor technology, and more particularly, to semiconductor devices including memory cells having graphene - containing layers, and methods for manufacturing such semiconductor devices. Background Art

[0004] In recent years, the trends of miniaturization, low power consumption, high performance, and diversification of electronic devices have required semiconductor devices capable of storing data in various electronic devices such as computers, portable communication devices, etc. Researchers and the industry are studying and developing such semiconductor devices. Such semiconductor devices include semiconductor devices that can store data by utilizing the property of switching between different resistance states according to an applied voltage or current, such as resistive random access memory (RRAM), phase - change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses. Summary of the Invention

[0005] Embodiments of the present disclosure relate to semiconductor devices that can improve the characteristics of memory cells, and methods for manufacturing such semiconductor devices.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes at least one memory cell. The memory cell includes a first electrode layer, a second electrode layer spaced apart from the first electrode layer, and a memory layer interposed between the first electrode layer and the second electrode layer. The first electrode layer includes a first amorphous carbon layer and a first graphene - containing layer interposed between the memory layer and the first amorphous carbon layer.

[0007] According to another embodiment of the present disclosure, a semiconductor device includes at least one memory cell. The memory cell includes: a first electrode layer including a first amorphous carbon layer; a memory layer disposed on the first electrode layer; and a second electrode layer disposed on the memory layer and including a second amorphous carbon layer and a graphene - containing layer interposed between the second amorphous carbon layer and the memory layer. The top surface of the first amorphous carbon layer directly contacts the memory layer. Brief Description of the Drawings

[0008] Figure 1 is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 is along Figure 1The cross-sectional view taken along line A-A' and line B-B' shown in the figure.

[0010] Figure 3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0011] Figure 4 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0012] Figure 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0013] Figure 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0014] Figure 7 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 8 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure. Detailed Description of the Embodiments

[0016] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0017] Some embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the various embodiments of the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the embodiments of the present disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same components in multiple figures and embodiments of the present disclosure.

[0018] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where there is one or more intermediate layers between the first layer and the second layer or the substrate. As used herein (including in the claims), the "or" in a list of items (e.g., a list of items expressed in phrases such as "at least one of... " or "one or more of... " or "both one or two of... ") represents an inclusive list. For example, a list of at least one of A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0019] Figure 1 is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.Figure 2 is a cross-sectional view taken along the lines A-A' and B-B' shown in Figure 1 .

[0020] Referring to Figure 1 and Figure 2 , a semiconductor device according to an embodiment of the present disclosure may include a substrate 100, a plurality of first wires 110 formed on the substrate 100 and extending along a first direction D1, a plurality of second wires 120 formed on the first wires 110 to be spaced apart from the first wires 110 and extending along a second direction D2 intersecting the first direction D1, and memory cells MC disposed between the first wires 110 and the second wires 120 and overlapping at cross regions between the first wires 110 and the second wires 120, respectively. Here, both the first direction D1 and the second direction D2 may correspond to horizontal directions substantially parallel to the top surface of the substrate 100. A direction substantially perpendicular to the top surface of the substrate 100 will be referred to as a third direction D3 hereinafter.

[0021] The substrate 100 may include a semiconductor material, such as silicon. The substrate 100 may include a given lower structure (not shown) formed therein. For example, the substrate 100 may include a driving circuit (not shown) electrically connected to the first wires 110 and / or the second wires 120 and controlling them.

[0022] Each of the first wires 110 and the second wires 120 may include one or more conductive materials, such as metals (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), etc.), metal nitrides (such as titanium nitride (TiN) and tantalum nitride (TaN), etc.), or a combination thereof. The first wires 110 and the second wires 120 may be respectively coupled to the bottom and the top of the memory cell MC and transmit a voltage or a current to the memory cell MC, so that the memory cell MC can operate. For example, a write operation for storing data in the memory cell MC, a read operation for reading data stored in the memory cell MC, etc. may be performed. When the first wire 110 is used as a word line, the second wire 120 may be used as a bit line. Conversely, when the first wire 110 is used as a bit line, the second wire 120 may be used as a word line.

[0023] The memory cell MC may be a device that stores different data according to a voltage or a current applied through the first wires 110 and the second wires 120. The memory cell MC may have a cylindrical shape overlapping at the intersection between the first wires 110 and the second wires 120. Although the memory cell MC is shown as having a cylindrical shape in Figure 1 , embodiments of the present disclosure are not limited thereto. The shape of the memory cell MC may be variously modified into a square column, an elliptical column, etc.

[0024] According toFigure 2 In this embodiment, the memory cell MC may include a memory layer 135 that performs the function of storing data, a first electrode layer 131 between the memory layer 135 and the first wire 110, and a second electrode layer 139 between the memory layer 135 and the second wire 120. The first electrode layer 131 may include a first amorphous carbon layer 131A and a first graphene-containing layer 131B between the memory layer 135 and the first amorphous carbon layer 131A. The second electrode layer 139 may include a second amorphous carbon layer 139A and a second graphene-containing layer 139B between the memory layer 135 and the second amorphous carbon layer 139A.

[0025] The memory layer 135 can store data in various ways. For example, the memory layer 135 can store different data by having variable resistance characteristics (i.e., characteristics of switching between different resistance states according to the applied voltage or current). The memory layer 135 can have a single-layer structure or a multi-layer structure, and the single-layer structure or multi-layer structure includes various materials for resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), and magnetic random access memory (MRAM), etc. For example, metal oxides (such as transition metal oxides and perovskite-based materials, etc.), phase change materials (such as chalcogenide-based materials), ferroelectric materials, and ferromagnetic materials, etc.

[0026] In addition, the memory layer 135 may not only have variable resistance characteristics of switching between different resistance states according to the applied voltage or current but also have characteristics of a selector that is turned on or off based on a predetermined threshold voltage. The memory layer 135 can be called a self-selective memory layer. Since the self-selective memory layer has different threshold voltages in different resistance states, the functions of a memory and a selector can be realized simultaneously. The memory layer 135 may include, for example, a chalcogenide-based material, and the switching between the high resistance state and the low resistance state can be performed according to the migration of a predetermined chalcogen element in the chalcogenide-based material. Here, the threshold voltage in the high resistance state and the threshold voltage in the low resistance state may be different from each other.

[0027] The first electrode layer 131 may be interposed between the first wire 110 and the storage layer 135, and may serve to physically separate them from each other and electrically connect them to each other. The first electrode layer 131 may include a first amorphous carbon layer 131A. When a conventional metal-containing material is used as the first electrode layer 131, the metal of the metal-containing material diffuses into the storage layer 135 during the operation of the memory cell MC, thereby having a negative impact on the characteristics of the storage layer 135. In contrast, when the first amorphous carbon layer 131A is used as the first electrode layer 131, diffusion of the metal into the storage layer 135 can be fundamentally prevented. However, when the first electrode layer 131 includes only the first amorphous carbon layer 131A, a specific constituent element among the constituent elements of the storage layer 135 diffuses into the first amorphous carbon layer 131A during the operation of the memory cell MC. Specifically, when the storage layer 135 includes a chalcogenide-based material (such as a self-selective storage layer), a specific chalcogen element (such as selenium) in the chalcogenide-based material may diffuse into the first amorphous carbon layer 131A. In this case, since a specific constituent element of the storage layer 135 may be lost and thus the composition of the storage layer 135 may change, deterioration of the characteristics of the storage layer 135 may occur. To solve this problem, according to an embodiment of the present disclosure, a first graphene-containing layer 131B may be used. In other words, the first electrode layer 131 includes the first amorphous carbon layer 131A to prevent diffusion of the metal from a conventional metal-containing electrode into the storage layer 135. The first electrode layer 131 further includes the first graphene-containing layer 131B to substantially prevent one or more elements of the storage layer 135 from diffusing into the first amorphous carbon layer 131A, as will be described in more detail below.

[0028] The first graphene-containing layer 131B may be interposed between the storage layer 135 and the first amorphous carbon layer 131A, and may serve to physically separate them from each other and electrically connect them to each other. The first graphene-containing layer 131B may include single-layer graphene or graphite in which graphene is stacked into multiple layers. Since the first graphene-containing layer 131B has a two-dimensional planar crystal structure, it can effectively prevent the migration of elements in the direction perpendicular to the crystal plane (e.g., in the third direction D3). Therefore, the first graphene-containing layer 131B can be used to prevent and / or reduce the diffusion of specific constituent elements of the storage layer 135 into the first amorphous carbon layer 131A during the operation of the memory cell MC. In other words, the first graphene-containing layer 131B can be used as a diffusion barrier in the out-of-plane direction (e.g., the third direction D3) perpendicular to its in-plane direction. Specifically, when the storage layer 135 includes a chalcogenide-based material (such as a self-selective storage layer), it can prevent and / or reduce the diffusion of a predetermined chalcogen element (such as selenium) of the chalcogenide-based material into the first amorphous carbon layer 131A. In addition, since the first graphene-containing layer 131B has a two-dimensional planar crystal structure, it can prevent and / or reduce the heat generated during the operation of the memory cell MC from being transmitted to the outside in the direction perpendicular to the crystal plane (e.g., in the third direction D3). In this case, the operating power of the memory cell MC can be reduced due to the thermal insulation effect on the memory cell MC. In other words, the first graphene-containing layer 131B has a relatively low thermal conductivity in the out-of-plane direction (e.g., the third direction D3), thereby increasing the thermal resistance in the out-of-plane direction. Therefore, the first graphene-containing layer 131B serves as a thermal insulator, which significantly reduces the heat transmitted from the memory cell MC to its outside in the out-of-plane direction during the operation of the memory cell MC. Therefore, according to an embodiment of the present disclosure, using the first electrode layer 131 including the first graphene-containing layer 131B can reduce the power required for the operation of the memory cell MC.

[0029] When the first electrode layer 131 includes a stacked structure of a first amorphous carbon layer 131A and a first graphene-containing layer 131B, the characteristics required for the first electrode layer 131, such as desired electrical conductivity and thermal conductivity, can be easily obtained. The thermal conductivity and electrical conductivity of the first graphene-containing layer 131B can be lower than those of the first amorphous carbon layer 131A. Specifically, the thermal conductivity and electrical conductivity of the first graphene-containing layer 131B in the out-of-plane direction (or out-of-plane thermal conductivity and out-of-plane electrical conductivity) can be lower than the thermal conductivity and electrical conductivity of the first amorphous carbon layer 131A, respectively. Therefore, at least one of the electrical conductivity or thermal conductivity of the first electrode layer 131 can be adjusted by controlling the thickness of the first amorphous carbon layer 131A and the thickness of the first graphene-containing layer 131B. Specifically, the thickness of the first amorphous carbon layer 131A and the thickness of the first graphene-containing layer 131B can be lengths in a direction corresponding to the out-of-plane direction of the first graphene-containing layer 131B (e.g., the third direction D3). For example, when it is determined that the electrical conductivity of the first electrode layer 131 (e.g., the electrical conductivity in the third direction D3) is lower than the target level, the electrical conductivity of the first electrode layer 131 can be increased by increasing the thickness of the first amorphous carbon layer 131A to be greater than the thickness of the first graphene-containing layer 131B. In other words, the first amorphous carbon layer 131A can be used together with the first graphene-containing layer 131B as the first electrode layer 131 to compensate for the low electrical conductivity of the first graphene-containing layer 131B. For example, when it is determined that the thermal conductivity of the first electrode layer 131 is higher than the target level and thus the operating power increases, the thickness of the first graphene-containing layer 131B can be increased to be greater than the thickness of the first amorphous carbon layer 131A to reduce the thermal conductivity of the first electrode layer 131. In some embodiments, the thickness of the first graphene-containing layer 131B can be about 30% to about 70% of the total thickness of the first electrode layer 131. When the thickness of the first graphene-containing layer 131B is less than about 30% of the total thickness of the first electrode layer 131, the first graphene-containing layer 131B may not be able to properly function as a thermal insulator to sufficiently reduce the power required for the operation of the memory cell MC, or may not be able to properly function as a diffusion barrier to effectively prevent one or more elements of the storage layer 135 from diffusing into the first amorphous carbon layer 131A, or may not be able to properly function as both. When the thickness of the first graphene-containing layer 131B is greater than about 70% of the total thickness of the first electrode layer 131, the first amorphous carbon layer 131A may not be sufficient to compensate for the low electrical conductivity of the first graphene-containing layer 131B.

[0030] The second electrode layer 139 may be interposed between the second wire 120 and the storage layer 135 to physically separate them from each other and electrically connect them to each other. The second electrode layer 139 may include a second amorphous carbon layer 139A and a second graphene-containing layer 139B. When the second amorphous carbon layer 139A is used as the second electrode layer 139, diffusion of metal into the storage layer 135 can be fundamentally blocked. The second graphene-containing layer 139B may be interposed between the storage layer 135 and the second amorphous carbon layer 139A to physically separate them from each other and electrically connect them to each other. The second graphene-containing layer 139B may include single-layer graphene or graphite in which graphene is stacked in multiple layers. The second graphene-containing layer 139B may be used to prevent and / or reduce the diffusion and loss of specific constituent elements of the storage layer 135 into the second amorphous carbon layer 139A during the operation of the memory cell MC. In addition, the second graphene-containing layer 139B may block and / or reduce the transfer of heat generated during the operation of the memory cell MC to the outside.

[0031] When the second electrode layer 139 includes a stacked structure of the second amorphous carbon layer 139A and the second graphene-containing layer 139B, the conductivity and thermal conductivity of the second electrode layer 139 can be adjusted by adjusting the relative thicknesses of the second amorphous carbon layer 139A and the second graphene-containing layer 139B.

[0032] According to this embodiment of the present disclosure, the first electrode layer 131 and the second electrode layer 139 may be substantially symmetric with respect to the storage layer 135 interposed therebetween. Accordingly, the thickness of the first amorphous carbon layer 131A and the thickness of the second amorphous carbon layer 139A may be substantially the same, and the thickness of the first graphene-containing layer 131B and the thickness of the second graphene-containing layer 139B may be substantially the same. However, embodiments of the present disclosure are not limited thereto, and if necessary, the first electrode layer 131 and the second electrode layer 139 may be implemented asymmetrically. For example, the thickness of the first amorphous carbon layer 131A and the thickness of the second amorphous carbon layer 139A may be different from each other, or the thickness of the first graphene-containing layer 131B and the thickness of the second graphene-containing layer 139B may be different from each other, or both. For example, either the first graphene-containing layer 131B or the second graphene-containing layer 139B may be omitted, which will be described later with reference to Figure 3 and Figure 4 will be described.

[0033] Examples of methods for manufacturing the above semiconductor device in Figure 1 and Figure 2 will be described below.

[0034] The conductive material layer for forming the first wire 110 and the material layer for forming the memory cell MC can be deposited on the substrate 100, and by selectively etching the conductive material layer and the material layer, a linear first wire 110 extending along the first direction D1 and an initial memory cell having a linear shape substantially the same as that of the first wire 110 above the first wire 110 can be formed. Subsequently, the spaces between the first wires 110 and the spaces between the initial memory cells can be filled with a dielectric material, and the conductive material layer for forming the second wire 120 can be deposited on the initial memory cells and the dielectric material, and by selectively etching the conductive material layer, a linear second wire 120 extending along the second direction D2 can be formed. Subsequently, the initial memory cells and the dielectric material exposed by the second wire 120 can be selectively etched to form columnar memory cells MC.

[0035] In addition, depending on the polarity of the voltage applied to each of the first wire 110 and the second wire 120 during the operation of the memory cell MC, a specific constituent element of the storage layer 135 can diffuse into both the first amorphous carbon layer 131A and the second amorphous carbon layer 139A, or into either the first amorphous carbon layer 131A or the second amorphous carbon layer 139A. When the specific constituent element of the storage layer 135 diffuses into both the first amorphous carbon layer 131A and the second amorphous carbon layer 139A, as Figure 2 shown in the embodiment of, the first graphene-containing layer 131B and the second graphene-containing layer 139B can be used simultaneously. In addition, when the specific constituent element of the storage layer 135 diffuses into either the first amorphous carbon layer 131A or the second amorphous carbon layer 139A, the corresponding one of the first graphene-containing layer 131B and the second graphene-containing layer 139B can be used.

[0036] Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. Parts substantially the same as those in the above embodiment of the present disclosure will be denoted by the same reference numerals, and detailed descriptions thereof may be omitted for simplicity.

[0037] Refer to Figure 3, a semiconductor device according to this embodiment of the present disclosure may include a substrate 100, a plurality of first wires 110 formed on the substrate 100 and extending along a first direction D1, a plurality of second wires 120 formed on the first wires 110 and spaced apart from the first wires 110 and extending along a second direction D2 intersecting the first direction D1, and memory cells MC disposed between the first wires 110 and the second wires 120 and overlapping at the intersection regions between the first wires 110 and the second wires 120, respectively. Here, each memory cell MC may include a storage layer 135, a first electrode layer 131 between the storage layer 135 and the first wire 110, and a second electrode layer 139 between the storage layer 135 and the second wire 120. The first electrode layer 131 may include an amorphous carbon layer. The second electrode layer 139 may include a second amorphous carbon layer 139A and a second graphene-containing layer 139B between the storage layer 135 and the second amorphous carbon layer 139A.

[0038] When a positive voltage is mainly applied to the top of the memory cell MC (i.e., the second wire 120), chalcogen elements (such as selenium) in the storage layer 135 may migrate to the second electrode layer 139, and hardly any migration to the first electrode layer 131 occurs. In this case, the second graphene-containing layer 139B may prevent and / or reduce the diffusion of selenium elements into the second amorphous carbon layer 139A. In addition, a graphene-containing layer between the first electrode layer 131 and the storage layer 135 may be omitted.

[0039] In addition, since the first electrode layer 131 is in an amorphous state, the top surface roughness of the first electrode layer 131 may be lower than that of a crystalline material. Since the storage layer 135 is disposed on the first electrode layer 131 and directly contacts the top surface of the first electrode layer 131 having a relatively low roughness, the characteristics of the storage layer 135 may be further improved according to this embodiment of the present disclosure.

[0040] Figure 4 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0041] Reference Figure 4, the semiconductor device according to this embodiment of the present disclosure may include a substrate 100, a plurality of first wires 110 formed on the substrate 100 and extending along a first direction D1, a plurality of second wires 120 formed on the first wires 110 and spaced apart from the first wires 110 and extending along a second direction D2 intersecting the first direction D1, and memory cells MC disposed between the first wires 110 and the second wires 120 and overlapping at the crossing regions between the first wires 110 and the second wires 120, respectively. Herein, each memory cell MC may include a storage layer 135, a first electrode layer 131 interposed between the storage layer 135 and the first wire 110, and a second electrode layer 139 interposed between the storage layer 135 and the second wire 120. The first electrode layer 131 may include a first amorphous carbon layer 131A and a first graphene-containing layer 131B interposed between the storage layer 135 and the first amorphous carbon layer 131A. The second electrode layer 139 may include an amorphous carbon layer.

[0042] When a positive voltage is mainly applied to the bottom of the memory cell MC (i.e., applied to the first wire 110), the chalcogen element (such as selenium) in the storage layer 135 may migrate to the first electrode layer 131, and hardly any migration to the second electrode layer 139 occurs. In this case, the first graphene-containing layer 131B can prevent and / or reduce the diffusion of selenium elements into the first amorphous carbon layer 131A. In addition, the graphene-containing layer between the second electrode layer 139 and the storage layer 135 can be omitted. Therefore, the bottom surface of the second electrode layer 139 can directly contact the storage layer 135 and has a relatively low roughness.

[0043] Figure 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0044] Reference Figure 5, a semiconductor device according to this embodiment of the present disclosure may include a substrate 100, a plurality of first conductive lines 110 formed on the substrate 100 and extending along a first direction D1, a plurality of second conductive lines 120 formed on the first conductive lines 110 and spaced apart from the first conductive lines 110 and extending along a second direction D2 intersecting the first direction D1, and memory cells MC disposed between the first conductive lines 110 and the second conductive lines 120 and overlapping at the crossing regions between the first conductive lines 110 and the second conductive lines 120, respectively. Here, each memory cell MC may include a storage layer 135, a first electrode layer 131 between the storage layer 135 and the first conductive line 110, a second electrode layer 139 between the storage layer 135 and the second conductive line 120, a first additional electrode layer 133 between the first conductive line 110 and the first electrode layer 131, and a second additional electrode layer 137 between the second conductive line 120 and the second electrode layer 139. The first electrode layer 131 may include a first amorphous carbon layer 131A and a first graphene-containing layer 131B between the storage layer 135 and the first amorphous carbon layer 131A. The second electrode layer 139 may include a second amorphous carbon layer 139A and a second graphene-containing layer 139B between the storage layer 135 and the second amorphous carbon layer 139A.

[0045] Each of the first additional electrode layer 133 and the second additional electrode layer 137 may include a metal-containing material, for example, a metal (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), etc.), a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof. When it is difficult to compensate for the low conductivity of the first graphene-containing layer 131B with only the first amorphous carbon layer 131A, the first additional electrode layer 133 may be used to further increase the conductivity. The conductivity of the first additional electrode layer 133 may be higher than the conductivity of the first amorphous carbon layer 131A. When it is difficult to compensate for the low conductivity of the second graphene-containing layer 139B with only the second amorphous carbon layer 139A, the second additional electrode layer 139 may be used to further increase the conductivity. The conductivity of the second additional electrode layer 139 may be higher than the conductivity of the second amorphous carbon layer 139A.

[0046] Even though the first additional electrode layer 133 and the second additional electrode layer 137 contain a metal, since the first electrode layer 131 is between the first additional electrode layer 133 and the storage layer 135, and the second additional electrode layer 139 is between the second additional electrode layer 137 and the storage layer 135, it is possible to prevent and / or reduce the diffusion of the metal in the first additional electrode layer 133 and the second additional electrode layer 137 into the storage layer 135. The thickness of the first additional electrode layer 133 may be less than the thickness of the first electrode layer 131, and the thickness of the second additional electrode layer 137 may be less than the thickness of the second electrode layer 139.

[0047] According to this embodiment of the present disclosure, the first additional electrode layer 133 and the second additional electrode layer 137 may be substantially symmetric with respect to the storage layer 135 therebetween. Accordingly, the thicknesses of the first additional electrode layer 133 and the second additional electrode layer 137 may be substantially the same. However, embodiments of the present disclosure are not limited thereto, and if necessary, the first additional electrode layer 133 and the second additional electrode layer 137 may be implemented asymmetrically. For example, the thickness of the first additional electrode layer 133 and the thickness of the second additional electrode layer 137 may be different from each other, or either the first additional electrode layer 133 or the second additional electrode layer 137 may be omitted.

[0048] In addition, according to this embodiment of the present disclosure, a case where the first additional electrode layer 133 and the second additional electrode layer 137 are added to Figure 2 the semiconductor device of the illustrated embodiment is described, but embodiments of the present disclosure are not limited thereto. According to another embodiment of the present disclosure, at least one of the first additional electrode layer 133 or the second additional electrode layer 137 may be added to Figure 3 the semiconductor device of the illustrated embodiment, Figure 4 the semiconductor device of the illustrated embodiment, and Figures 6 to 8 any one of the semiconductor devices to be described later.

[0049] In addition, the above embodiments of the present disclosure all correspond to the case where the memory cell MC includes the storage layer 135 and does not include a selector layer. For example, when the storage layer 135 is a self-selective storage layer, it may also be used as a selector. Accordingly, a separate selector layer may be omitted. However, when the storage layer 135 only has a data storage function and does not have a selector function, a separate selector layer may be included. These embodiments will be described with reference to Figure 6 and Figure 7 .

[0050] Figure 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0051] Referring to Figure 6, a semiconductor device according to this embodiment of the present disclosure may include a substrate 100, a plurality of first conductors 110 formed on the substrate 100 and extending along a first direction D1, a plurality of second conductors 120 formed on the first conductors 110 and spaced apart from the first conductors 110 and extending along a second direction D2 intersecting the first direction D1, and memory cells MC disposed between the first conductors 110 and the second conductors 120 and overlapping in the crossing regions between the first conductors 110 and the second conductors 120, respectively. Here, each memory cell MC may include a storage layer 135, a selector layer 141, a first electrode layer 131 interposed between the storage layer 135 and the first conductor 110, a second electrode layer 139 interposed between the storage layer 135 and the selector layer 141, and a third electrode layer 143 interposed between the selector layer 141 and the second conductor 120. The memory layer 135, the first electrode layer 131, and the second electrode layer 139 may form a memory unit MU, while the selector layer 141, the second electrode layer 139, and the third electrode layer 143 may form a selector unit SU. The second electrode layer 139 may be a common electrode of the memory unit MU and the selector unit SU. According to this embodiment of the present disclosure, the selector unit SU may be disposed on the memory unit MU.

[0052] According to this embodiment of the present disclosure, the storage layer 135 may only have a data storage function and may not have a selector function. Thus, the memory cell MC may further include a selector layer 141 electrically coupled to the storage layer 135 through the second electrode layer 139.

[0053] The selector layer 141 may be used to prevent or reduce leakage current that may occur between memory cells MC sharing the first conductor 110 or the second conductor 120 when controlling access to the storage layer 135. To this end, the selector layer 141 may have a threshold switching characteristic, that is, it blocks current or makes the current hardly flow when the voltage levels supplied to the top and bottom of the selector layer 141 are lower than a predetermined threshold voltage level, and releases current to make it flow rapidly when the voltage levels supplied to the top and bottom of the selector layer 141 are equal to or higher than the threshold voltage level. In other words, the selector layer 141 may conduct at a level equal to or higher than the threshold voltage level and turn off at a level lower than the threshold voltage level.

[0054] The selector layer 141 may include a two-terminal threshold switch (OTS) material (such as a diode and a chalcogenide-based material), a mixed ionic electronic conductor (MIEC) material (such as a metal-containing chalcogenide-based material), a metal insulator transition (MIT) material (such as NbO2 and VO2), or a tunneling dielectric material having a relatively wide bandgap (such as SiO2, and Al2O3, etc.).

[0055] In addition, the selector layer 141 may include a dielectric material containing dopants implanted by ion implantation. Here, the dielectric material may include silicon-containing dielectric materials (such as silicon oxide, silicon nitride, and silicon oxynitride, etc.), dielectric metal oxides, dielectric metal nitrides, and combinations thereof. The dopants can be used to create trap sites that capture conductive carriers migrating in the dielectric material, or to provide channels for the recapture of conductive carriers to migrate again. To form trap sites, various elements that generate potential energy capable of receiving conductive carriers in the dielectric material can be used as dopants. For example, when the dielectric material includes a silicon-containing dielectric material, the dopants may include metals with valences different from that of silicon, such as aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), or combinations thereof. In addition, when the dielectric material includes a dielectric metal oxide or a dielectric metal nitride, the dopants may include metals with valences different from that of the metal in the metal oxide or metal nitride, or silicon. For example, the selector layer 141 may include silicon dioxide (SiO2) implanted with arsenic (As) by an ion implantation method. When a voltage equal to or higher than the threshold voltage is applied to the selector layer 141, conductive carriers can migrate through the trap sites, thereby achieving a conducting state in which current flows through the selector layer 141. When the voltage applied to the selector layer 141 is reduced to a level lower than the threshold voltage, the conductive carriers do not migrate, thereby achieving a non-conducting state in which no current flows.

[0056] The third electrode layer 143 may be interposed between the second wire 120 and the selector layer 141, and may serve to physically separate them from each other and electrically connect them to each other. The third electrode layer 143 may include a metal-containing material, for example, a metal (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), etc.), a metal nitride (such as titanium nitride (TiN) and tantalum nitride (TaN), etc.), or a combination thereof. In addition, the third electrode layer 143 may include an amorphous carbon layer.

[0057] Figure 7 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0058] Reference Figure 7, a semiconductor device according to this embodiment of the present disclosure may include a substrate 100, a plurality of first conductors 110 formed on the substrate 100 and extending along a first direction D1, a plurality of second conductors 120 formed on the first conductors 110 and spaced apart from the first conductors 110 and extending along a second direction D2 intersecting the first direction D1, and memory cells MC disposed between the first conductors 110 and the second conductors 120 and overlapping at the crossing regions between the first conductors 110 and the second conductors 120 respectively. Here, each memory cell MC may include a storage layer 135, a selector layer 141, a second electrode layer 139 between the storage layer 135 and the second conductor 120, a first electrode layer 131 between the storage layer 135 and the selector layer 141, and a third electrode layer 143 between the selector layer 141 and the first conductor 110. The storage layer 135, the first electrode layer 131, and the second electrode layer 139 may form a memory unit MU, while the selector layer 141, the first electrode layer 131, and the third electrode layer 143 may form a selector unit SU. The first electrode layer 131 may be a common electrode of the memory unit MU and the selector unit SU. According to this embodiment of the present disclosure, the selector unit SU may be disposed below the memory unit MU.

[0059] According to this embodiment of the present disclosure, the storage layer 135 may only have a data storage function and may not have a selector function. Thus, the memory cell MC may further include a selector layer 141 electrically connected to the storage layer 135 through the first electrode layer 131.

[0060] In addition, according to the above embodiment of the present disclosure, the first conductors 110 and the second conductors 120 are spaced apart from each other in the vertical direction and extend in corresponding horizontal directions. However, the spacing direction and the extending direction of the first conductors 110 and the second conductors 120 may be changed in various ways, and the memory cells MC may be disposed between the first conductors 110 and the second conductors 120 to overlap at the crossing regions between the first conductors 110 and the second conductors 120. One of these embodiments will be described below with reference to Figure 8 Describe one of these embodiments.

[0061] Figure 8 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0062] Reference Figure 8, the semiconductor device according to this embodiment of the present disclosure may include: a plurality of first wires 210 arranged in a first direction D1 and having a cylindrical shape extending in a third direction D3; a plurality of second wires 220 formed to be spaced apart from the first wires 210 in a second direction D2 and extending in the first direction D1; and a memory cell MC', which is disposed between the first wire 210 and the second wire 220 to overlap at the crossing region between the first wire 210 and the second wire 220, respectively. The second wires 220 may be stacked in the third direction D3, and although not shown, a dielectric layer may be formed between the second wires 220 adjacent to each other in the third direction D3. The third direction D3 may correspond to a vertical direction substantially perpendicular to the top surface of a substrate (not shown), and the first direction D1 and the second direction D2 may correspond to horizontal directions substantially parallel to the top surface of the substrate.

[0063] Each memory cell MC' may include a storage layer 235, a first electrode layer 231 interposed between the storage layer 235 and the first wire 210, and a second electrode layer 239 interposed between the storage layer 235 and the second wire 220. The first electrode layer 231 may include a first amorphous carbon layer 231A and a first graphene-containing layer 231B interposed between the storage layer 235 and the first amorphous carbon layer 231A. The second electrode layer 239 may include a second amorphous carbon layer 239A and a second graphene-containing layer 239B interposed between the storage layer 235 and the second amorphous carbon layer 239A. According to this embodiment of the present disclosure, the layers 231, 235, and 239 forming the memory cell MC' may not be stacked in the third direction D3, but may be arranged in the second direction D2.

[0064] According to an embodiment of the present disclosure, a semiconductor device and a manufacturing method thereof that can improve the characteristics of a memory cell may be provided.

[0065] Although some specific embodiments of the present disclosure have been described herein, various changes and modifications can be made.

Claims

1. A semiconductor device, comprising: At least one memory cell, Wherein, the memory cell comprises: A first electrode layer; A second electrode layer spaced apart from the first electrode layer; and A storage layer interposed between the first electrode layer and the second electrode layer, and Wherein, the first electrode layer comprises: A first amorphous carbon layer; and A first graphene-containing layer interposed between the storage layer and the first amorphous carbon layer.

2. The semiconductor device according to claim 1, wherein, The second electrode layer comprises a second amorphous carbon layer.

3. The semiconductor device according to claim 2, wherein, The second electrode layer further comprises a second graphene-containing layer interposed between the storage layer and the second amorphous carbon layer.

4. The semiconductor device according to claim 3, wherein, The storage layer comprises: constituent elements that migrate during operation of the memory cell, and Wherein, the first graphene-containing layer prevents or reduces diffusion of the constituent elements into the first amorphous carbon layer, and Wherein, the second graphene-containing layer prevents or reduces diffusion of the constituent elements into the second amorphous carbon layer.

5. The semiconductor device according to claim 3, wherein, At least one of the thermal conductivity or electrical conductivity of the second electrode layer is adjusted based on the thickness of the second amorphous carbon layer and the thickness of the second graphene-containing layer.

6. The semiconductor device according to claim 2, wherein, The second amorphous carbon layer is in direct contact with the storage layer.

7. The semiconductor device according to claim 1, wherein, The memory cell further comprises a first additional electrode layer, and Wherein, the first amorphous carbon layer is disposed between the first additional electrode layer and the first graphene-containing layer.

8. The semiconductor device according to claim 7, wherein, The electrical conductivity of the first additional electrode layer is higher than that of the first amorphous carbon layer.

9. The semiconductor device according to claim 7, wherein, The first additional electrode layer comprises a metal-containing material.

10. The semiconductor device according to claim 7, wherein, The memory cell further comprises a second additional electrode layer, and Wherein, the second amorphous carbon layer is disposed between the second additional electrode layer and the second graphene-containing layer.

11. The semiconductor device according to claim 10, wherein, The electrical conductivity of the second additional electrode layer is higher than that of the second amorphous carbon layer.

12. The semiconductor device according to claim 10, wherein, The second additional electrode layer comprises a metal-containing material.

13. The semiconductor device according to claim 1, wherein, The storage layer comprises: constituent elements that migrate towards the first electrode layer during operation of the memory cell, and Wherein, the first graphene-containing layer prevents or reduces diffusion of the constituent elements into the first amorphous carbon layer.

14. The semiconductor device according to claim 1, wherein, At least one of the thermal conductivity or electrical conductivity of the first electrode layer is adjusted based on the thickness of the first amorphous carbon layer and the thickness of the first graphene-containing layer.

15. The semiconductor device according to claim 1, further comprising: A plurality of first wires extending in a first direction; And A plurality of second wires extending in a second direction intersecting the first direction and spaced apart from the first wires in a third direction intersecting the first direction and the second direction, Wherein, the memory cells are arranged between the first wires and the second wires to overlap at the intersection regions between the first wires and the second wires respectively.

16. The semiconductor device according to claim 15, further comprising a substrate disposed below the first wires, the second wires, and the memory cells, Among them, The first direction and the second direction are parallel to the top surface of the substrate, and the third direction is perpendicular to the top surface of the substrate.

17. The semiconductor device according to claim 15 further includes a substrate disposed under the first wire, the second wire, and the memory cell, Among them, wherein the first direction is perpendicular to the top surface of the substrate, and the second direction and the third direction are parallel to the top surface of the substrate.

18. A semiconductor device includes: at least one memory cell, wherein the memory cell includes: a first electrode layer including a first amorphous carbon layer; a storage layer disposed on the first electrode layer; and a second electrode layer disposed on the storage layer and including a second amorphous carbon layer and a graphene-containing layer interposed between the second amorphous carbon layer and the storage layer, and wherein the top surface of the first amorphous carbon layer directly contacts the storage layer.

19. The semiconductor device according to claim 18, wherein, The storage layer includes constituent elements that migrate to the second electrode layer during operation of the memory cell.

20. The semiconductor device according to claim 18, wherein, The memory cell further includes an additional electrode layer, and wherein the second amorphous carbon layer is disposed between the additional electrode layer and the graphene-containing layer.

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