Semiconductor structure and forming method thereof

Abstract

The method includes depositing a multilayer stack including a plurality of sacrificial layers and a plurality of semiconductor layers positioned alternately. The plurality of sacrificial layers includes a bottom sacrificial layer having a first thickness and an upper sacrificial layer over the bottom sacrificial layer. The upper sacrificial layer has a second thickness less than the first thickness. The method further includes patterning the multilayer stack to form protruding fins; forming a dummy gate stack on the protruding fin; forming a source / drain region alongside the dummy gate stack; removing the dummy gate stack and the plurality of sacrificial layers in the protruding fins to leave grooves; and forming a replacement gate stack in the recess. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Technological advancements in integrated circuit (IC) materials and design have produced multiple generations of ICs, with each generation having smaller and more complex circuits than the previous one. During the development of ICs, the functional density (e.g., the number of interconnect devices per chip area) generally increases while the geometric dimensions have decreased. Such scaling processes typically provide benefits by increasing production efficiency and reducing associated costs.

[0003] Such scaling also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advancements. For example, gate-all-around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods of manufacturing GAA transistors are being developed. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor structure, including: depositing a multi-layer stack including a plurality of sacrificial layers and a plurality of semiconductor layers alternately positioned, wherein the plurality of sacrificial layers include: a bottom sacrificial layer having a first thickness; and an upper sacrificial layer located above the bottom sacrificial layer, wherein the upper sacrificial layer has a second thickness less than the first thickness; patterning the multi-layer stack to form a first protruding fin; forming a first pseudo-gate stack on the first protruding fin; forming a first source / drain region beside the first pseudo-gate stack; removing the plurality of sacrificial layers in the first pseudo-gate stack and the first protruding fin to leave a first groove; and forming a first replacement gate stack in the first groove.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a semiconductor strip; a first isolation region and a second isolation region located on opposite sides of the semiconductor strip; a plurality of semiconductor nanostructures overlapping with the semiconductor strip, wherein the upper plurality of semiconductor nanostructures overlap with the corresponding lower plurality of semiconductor nanostructures; a gate stack including: a bottom portion having a first height, wherein the bottom portion is located between the semiconductor strip and the plurality of semiconductor nanostructures; and an upper portion located between adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion has a second height less than the first height; and a semiconductor region located beside the plurality of semiconductor nanostructures and contacting the plurality of semiconductor nanostructures.

[0006] Some additional embodiments of the present application provide a semiconductor structure, comprising: a plurality of semiconductor nanostructures, wherein the upper plurality of semiconductor nanostructures overlap with the corresponding lower plurality of semiconductor nanostructures; a gate stack, comprising: a bottom portion, located below the bottommost semiconductor nanostructure of the plurality of semiconductor nanostructures, wherein the bottom portion comprises: a first work function layer; and a second work function layer, surrounded by the first work function layer, wherein all layers in the bottom portion have a first total number; and an upper portion, located between two adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion comprises the second work function layer, and wherein all layers in the upper portion have a second total number less than the first total number; and a semiconductor region, located beside the plurality of semiconductor nanostructures and in contact with the plurality of semiconductor nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 to 4 and Figure 5A-1 、 Figure 5A-2 、 Figure 5B-1 、 Figures 5B-2 to 12A-1 、 Figure 12A-2 、 Figure 12B-1 and Figure 12B-2 show views of intermediate stages in the formation of a gate-all-around (GAA) transistor in accordance with some embodiments.

[0009] Figure 13 show a process flow for forming a transistor in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, for ease of description, this document may use spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the figures. Except for the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be correspondingly interpreted in the same manner.

[0012] A gate-all-around (GAA) transistor is formed, and the GAA transistor can be a nanosheet transistor and / or a nanowire transistor. According to some embodiments, the bottom spacing between the bottom nanostructure and the underlying semiconductor strip (sub-channel) is greater than the upper spacing between the adjacent (semiconductor) nanostructures above. Thus, it is possible to fill the bottom spacing with a first work function layer and a second work function layer on the first work function layer. The second work function layer has the function of increasing the threshold voltage of the sub-transistor including the sub-channel. The upper spacing can be filled with a portion of the gate stack and does not include the second work function layer. Thus, when the GAA transistor is turned off, the leakage current through the sub-channel is reduced accordingly.

[0013] The embodiments discussed herein are provided to give examples of the subject matter capable of being made or used in the embodiments of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0014] Figures 1 to 12A-1 、 Figure 12A-2 、 Figure 12B-1 and Figure 12B-2 shows a cross-sectional view of an intermediate stage in the formation of a gate-all-around (GAA) transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in the process flow shown in Figure 13 .

[0015] Referring to Figure 1 , a perspective view of a wafer 10 is shown. The wafer 10 includes a multi-layer structure, and the multi-layer structure includes a multi-layer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which can be a silicon substrate, a silicon germanium (SiGe) substrate, etc., and other substrates and / or structures such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc. may be used. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0016] According to some embodiments, a multi-layer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are shown as the process 202 in the process flow 200 shown in Figure 13 According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0017] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc.

[0018] Once the first layer 22A has been deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, etc., where the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0019] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B can also be formed to a thickness different from that of the first layer 22A. According to some embodiments, the first layer 22A is formed to a first thickness in the range between about 9 nm and about 10 nm. However, any suitable thickness can be utilized while remaining within the scope of the embodiments.

[0020] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 has been formed.

[0021] According to some embodiments, the bottommost layer 22A (denoted as 22A-1) has a thickness T1, and the upper layer 22A (denoted as 22A-2) has a thickness T2. The thicknesses T2 of the upper layers 22A-2 can be the same or different from each other. The thickness T1 is greater than the thickness T2. The ratio T1 / T2 can be in the range between about 1.2 and about 2.0, and can be in the range between about 1.5 and 1.8. According to some embodiments, the thickness T1 can be in the range between about 13.5 nm and about 15 nm, and the thickness T2 can be in the range between about 9 nm and about 10 nm. The second layer 22B can also have the same thickness or a different thickness from the first layer 22A-2. According to some embodiments, the first layer 22A is removed in a subsequent process and is optionally referred to as the sacrificial layer 22A throughout the description.

[0022] According to some embodiments, there can be some pad oxide layers and hard mask layers (not shown) formed above the multi-layer stack 22. These layers are patterned and are used for subsequent patterning of the multi-layer stack 22.

[0023] Reference Figure 2 , in an etching process, portions of the multi-layer stack 22 and the underlying substrate 20 are patterned to form trenches 23. The corresponding process is shown as Figure 13 process 204 in the process flow 200 shown in. The trenches 23 extend into the substrate 20. The remaining portion of the multi-layer stack is hereinafter referred to as the multi-layer stack 22'. The underlying multi-layer stack 22' leaves some portions of the substrate 20, and is hereinafter referred to as the semiconductor strip 20'. The multi-layer stack 22' includes semiconductor layers 22A and 22B. The semiconductor layer 22A is optionally referred to as the sacrificial layer, and the semiconductor layer 22B is optionally referred to as the nanostructure hereinafter. The portions of the multi-layer stack 22' and the underlying semiconductor strip 20' are collectively referred to as the semiconductor strip 24.

[0024] In the above embodiments, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more lithography processes, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch smaller than that achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a lithography process. Spacers are formed beside the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the remaining spacers can be used to pattern the GAA structure.

[0025] Figure 3Illustrates the formation of isolation region 26, which is also referred to as a shallow trench isolation (STI) region throughout the description. The corresponding process is shown as Figure 13 Process 206 in process flow 200 shown in. The STI region 26 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The pad oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material above the pad oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. Then, a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process may be implemented to make the top surface of the dielectric material flush, and the remaining portion of the dielectric material is the STI region 26.

[0026] Then, the STI region 26 is recessed such that the top portion of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top portion of the multi-layer stack 22' and the semiconductor strip 20'. The recessing of the STI region 26 may be implemented by a dry etching process, where, for example, NF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is implemented by a wet etching process. For example, the etching chemical may include HF.

[0027] Next, Figure 4 Illustrates two device regions 100A and 100B in the same wafer 10 and the same device die, both of which are used to form GAA transistors, which may be nanosheet transistors or nanowire transistors. The structures formed in the device regions 100A and 100B may share the same formation process, including as Figures 1 to 3 shown in the process. The width of the multi-layer stack 22' in the device region 100A may be equal to, greater than, or less than the width of the multi-layer stack 22' in the device region 100B.

[0028] According to some embodiments, device region 100A is an n-type device region (wherein n-type transistors will be formed), and device region 100B is a p-type device region (wherein p-type transistors will be formed). According to alternative embodiments, device region 100A is a p-type device region, and device region 100B is an n-type device region. According to still other alternative embodiments, both device regions 100A and 100B are n-type device regions, or both device regions 100A and 100B are p-type device regions. In the examples discussed below, it may be assumed that device regions 100A and 100B are an n-type device region and a p-type device region, respectively, while each of device regions 100A and 100B may be any combination of the other type of device region.

[0029] As Figure 4 shown, a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (projecting) fin 28. The corresponding process is shown as Figure 13 process 208 in process flow 200 shown. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the projecting fin 28 to form an oxide layer or by depositing a dielectric layer such as a silicon oxide layer. For example, polysilicon or amorphous silicon may be used to form the dummy gate electrode 34, and other materials such as amorphous carbon may also be used.

[0030] Each of the dummy gate stacks 30 may also include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, or a multi-layer thereof. The dummy gate stack 30 may span over a single or multiple projecting fins 28 and the STI region 26 between the projecting fins 28. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the projecting fin 28. The formation of the dummy gate stack 30 includes: forming a dummy gate dielectric layer; depositing a dummy gate electrode layer above the dummy gate dielectric layer; depositing one or more hard mask layers; and then patterning the formed layers through a patterning process.

[0031] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxynitride (SiOCN), etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include: depositing one or more dielectric layers; and then performing an anisotropic etching process on the dielectric layers. The remaining portion of the dielectric layer is the gate spacer 38.

[0032] Figure 5A-1 and Figure 5A-2 shows a cross-sectional view of the structure after the subsequent formation of source / drain regions and the overlying dielectric layer in the device region 100A in Figure 4 . Figure 5B-1 and Figure 5B-2 shows a cross-sectional view of the structure after the subsequent formation of source / drain regions and the overlying dielectric layer in the device region 100B in Figure 4 . Throughout the description, the figures with reference numerals including "A-1" or "A-2" are obtained from the device region 100A and from the cross-sections GL-GL and CL-CL, respectively. The figures with reference numerals including "B-1" or "B-2" are obtained from Figure 4 the device region 100B and from the cross-sections GL-GL and CL-CL, respectively. For example, Figure 5A-1 shows Figure 4 the reference cross-section GL-GL (where "GL" represents the gate length) in Figure 5A-2 which is parallel to the gate longitudinal direction. Figure 4 shows the reference cross-section CL-CL (where "CL" represents the channel length) in

[0033] which cuts through the protruding fin 28. Figure 5A-2 Figure 5B-2 Referring to Figure 4 and Figure 13 , the portions of the protruding fin 28 that are not directly under the dummy gate stack 30 and the gate spacers 38 (

[0034] ) are recessed by an etching process to form grooves (occupied by regions 48A and 48B). The corresponding process is shown as process 210 in process flow 200 shown in Figure 13 . For example, a dry etching process can be implemented using a mixture of C2F6, CF4, SO2, HBr, Cl2, and O2, a mixture of HBr, Cl2, O2, and CH2F2, etc., to etch the multi-layer semiconductor stack 22' and the underlying semiconductor strip 20'. The bottom of the groove is at least flush with the bottom of the multi-layer semiconductor stack 22' or can be lower than the bottom of the multi-layer semiconductor stack 22'. The etching can be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the groove are vertical and straight.

[0035] Figure 5A-2It is also shown that source / drain regions 48A are formed in the device region 100A, and Figure 5B-2 it is also shown that source / drain regions 48B are formed in the device region 100B. The source / drain regions may refer to the source or the drain, individually or jointly depending on the context. The corresponding process is shown as Figure 13 process 214 in the process flow 200 shown in. The source / drain regions 48A and 48B may extend to a distance within a range of about 50 nm to about 55 nm lower than the bottom nanostructure 22B.

[0036] The source / drain regions 48A and 48B (when being n-type regions) may include silicon or SiC and an n-type dopant, such as As, P, Sb, etc. or a combination thereof. For example, the source / drain regions 48A and 48B (when being n-type) may include SiAs, SiP, SiCP, SiAsP, SiSb, etc. The source / drain regions 48A and 48B (when being p-type regions) may include silicon, SiGe or Ge, and also include a p-type dopant, such as boron, indium or a combination thereof. For example, the source / drain regions 48A and 48B (when being p-type) may include SiGeB, GeB, etc.

[0037] The formation of the source / drain regions 48A and 48B may be implemented by an epitaxial process. In addition, when the source / drain regions 48A and 48B have the same conductivity type, the source / drain regions 48A and 48B may be epitaxially grown by the same epitaxial process. In an exemplary embodiment where the device regions 100A and 100B are an n-type device region and a p-type device region respectively, the source / drain region 48A is an n-type region, and the source / drain region 48B is a p-type region.

[0038] Figure 5A-1 、 Figure 5A-2 、 Figure 5B-1 and Figure 5B-2 It is also shown that a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52 are formed. The corresponding process is shown as Figure 13 process 216 in the process flow 200 shown in. The CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. The ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD or any other suitable deposition method. The ILD 52 may be formed of an oxygen-containing dielectric material, which may be silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0039] A planarization process such as a CMP process or a mechanical polishing process is performed to make the top surface of the ILD 52 flush. According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, or may stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or the hard mask 36), the gate spacers 38, and the ILD 52 are flush within the process variation range.

[0040] Refer to Figure 6A-1 , Figure 6A-2 , Figure 6B-1 and Figure 6B-2 , in one or more etching processes, the dummy gate electrode 34 (and the hard mask 36, if remaining) and the dummy gate dielectric 32 in the device regions 100A and 100B are removed, thereby forming grooves 58A and 58B (collectively referred to as grooves 58) in the device regions 100A and 100B, respectively. The corresponding process is shown as Figure 13 Process 218 in the process flow 200 shown in

[0041] Refer to Figure 7A-1 , Figure 7A-2 , Figure 7B-1 and Figure 7B-2 , by etching through the removal of the sacrificial layer 22A, the grooves 58A and 58B extend downward between the nanostructures 22B. As can be recognized from Figure 6A-1 and Figure 6B-1 , after the removal of the dummy gate dielectric 32 and the dummy gate electrode 34, the sidewalls of the sacrificial layer 22A are exposed, and thus the sacrificial layer 22A can be removed. The corresponding process is shown as Figure 13 Process 220 in the process flow 200 shown in

[0042] Due to the difference between the thicknesses T1 and T2 of the bottom sacrificial layer 22A-1 and the upper sacrificial layer 22A-2 ( Figure 1 ), the spacing S1 between the semiconductor strip 20' and the bottommost nanostructure 22B above is equal to the thickness T1 or slightly different from the thickness T1 (due to the etching process). The spacing S2 between adjacent nanostructures 22B is equal to the thickness T2 or slightly different from the thickness T2 (due to the etching process), and the thickness T2 is less than the thickness T1. According to some embodiments, the ratio S1 / S2 may be in the range of about 1.2 and 2.0.

[0043] Refer to Figure 8A-1 , Figure 8A-2 , Figure 8B-1 and Figure 8B-2 , a gate dielectric 62 is formed. The corresponding process is shown as Figure 13Process 222 in process flow 200 as shown. According to some embodiments, each of the gate dielectrics 62 includes an interface layer 64 and a high-k dielectric layer 66 on the interface layer 64. The interface layer 64 may have a thickness in the range between about 1 nm and about 1.5 nm. The thickness of the interface layer 64 may also be less than 1 / 3 of the spacer S2 ( Figure 7A-1 and Figure 7B-1 ). According to some embodiments, the gate dielectrics 62 in the device regions 100A and 100B are formed using a common formation process. The interface layer 64 may be formed of or include silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD. The interface layer 64 may also be formed by an oxidation process.

[0044] According to some embodiments, the high-k dielectric layer 66 includes one or more dielectric layers. For example, the high-k dielectric layer 66 may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The high-k dielectric layer 66 may also be deposited by a conformal deposition process such as ALD or CVD. The high-k dielectric layer 66 may have a thickness in the range between about 1 nm and about 1.5 nm, which may be substantially the same as the thickness of the interface layer 64.

[0045] Referring Figure 9B-1 and Figure 9B-2 , Figure 9B-1 and Figure 9B-2 show a view in the device region 100B where a first work function layer 68B is formed. The corresponding process is shown as Figure 13 process 224 in process flow 200 as shown. According to some embodiments of forming a p-type transistor in the device region 100B, the work function layer 68B may be a p-type work function layer having a work function higher than the mid-gap work function (about 4.5 eV to about 4.6 eV). For example, the work function of the work function layer 68B may be in the range between about 4.6 eV and about 5.2 eV. According to some embodiments, the work function layer 68B may be formed of or include TiN, TiC, TiCN, etc.

[0046] According to an alternative embodiment, the work function layer 68B may have a mid-gap work function, for example, in the range between about 4.5 eV and about 4.6 eV. The corresponding work function layer 68B may include tungsten. The formation process may include ALD, CVD, etc.

[0047] According to some embodiments, the work function layer 68B is conformally deposited on the high-k dielectric layer 66. The thickness T3 of the work function layer 68B may be greater than T2 / 2 and less than T1 / 2 ( Figure 1)。For example, the thickness of the work function layer 68B can be in the range between about 3 nm and about 4.5 nm. Thus, the resulting work function layers 68B deposited on adjacent semiconductor nanostructures 22B merge with each other, with no gap left between them. On the other hand, a gap is left between the bottom nanostructure 22B and the semiconductor strip 20'. According to some embodiments, the spacer S1 (which is equal to the thickness T1 in Figure 1 is greater than about 13.5 nm and can be in the range between about 13.5 nm and about 15 nm. The remaining spacer S3 can be greater than about 1 nm and can be in the range between about 1 nm and about 3 nm.

[0048] Figure 9A-1 and Figure 9A-2 illustrate the structure shown in the device region 100A after the formation of the work function layer 68B. The high-k dielectric layer 66 can be exposed. According to some embodiments, the formation of the work function layer 68B can include a blanket conformal deposition process such that the work function layer 68B is also deposited into the device region 100A when it is deposited into the device region 100B. An etch mask (not shown) can then be formed to cover the device region 100B, followed by an etching process to remove the work function layer 68B from the device region 100A and thus re-expose the high-k dielectric layer 66. The etch mask is then removed.

[0049] Figure 10A-1 、 Figure 10A-2 、 Figure 10B-1 and Figure 10B-2 illustrate the deposition of the work function layer 68A. The corresponding process is shown as process 226 in process flow 200 shown in Figure 13 The thickness of the work function layer 68A can be in the range between about 6 nm and about 7 nm. According to some embodiments of forming an n-type transistor in the device region 100A, the work function layer 68A can have a work function lower than the mid-gap work function and can be in the range between about 4.0 eV and about 4.5 eV. According to some embodiments, the work function layer 68B can be formed of or include an aluminum-containing material such as TiAl, TiAlC, TiAlN, TaAl, TaAlC, TaAlN, etc.

[0050] According to an alternative embodiment, the work function layer 68A can have a mid-gap work function, for example, in the range between about 4.5 eV and about 4.6 eV. The corresponding work function layer 68A can include tungsten. The formation process can include ALD, CVD, etc. Other materials such as Si, Ti, etc. can also be used.

[0051] Figure 10A-1 、 Figure 10A-2 、 Figure 10B-1 and Figure 10B-2The formation of the upper layer of the gate electrode is also shown. The corresponding process is shown as Figure 13 Process 228 in process flow 200 shown in. According to some embodiments, a silicon layer 70 is deposited, and the silicon layer 70 includes elemental silicon (rather than a compound of silicon). The deposition can be achieved, for example, by immersing the wafer 10 in a silicon-containing precursor such as silane, disilane, etc. The thickness of the silicon layer 70 can be in the range between about 1 nm and about 2 nm. A glue layer 72 is deposited on the silicon layer 70, and the glue layer 72 can include TiN. The glue layer 72 can be formed by a deposition process such as CVD, ALD, etc. The thickness of the glue layer 72 can be in the range between about 1 nm and about 3 nm, and can be in the range between about 1 nm and about 2 nm, or in the range between about 2.5 nm and about 3 nm.

[0052] A filling metal region 74 that completely fills the remaining grooves is also deposited on the glue layer 72. The deposition thickness of the filling metal region 74 can be in the range between about 3 nm and about 4 nm. Then, a planarization process such as a CMP process or a mechanical polishing process is implemented to leave gate electrodes 76A and 76B in device regions 100A and 100B, respectively.

[0053] In device region 100A, the gate dielectric 62 and the gate electrode 76A together form a gate stack 78A. In device region 100B, the gate dielectric 62 and the gate electrode 76B together form a gate stack 78B. The height of the gate stacks 78A and 78B can be in the range between about 12 nm and about 14 nm. Thus, GAA transistors 110A and 110B are formed in device regions 100A and 100B, respectively.

[0054] In device region 100A, according to some embodiments, the work function layer 68A completely fills the bottom gap between the nanostructure 22B1 and the semiconductor strip 20', and the upper layers such as the silicon layer 70 and the glue layer 72 do not fill into the bottom gap. According to an alternative embodiment, in addition to the work function layer 68B, some other layers such as the silicon layer 70 or both the silicon layer 70 and the glue layer 72 fill into the bottom gap, and the upper gap is completely filled by the work function layer 68A.

[0055] In the device region 100B, according to some embodiments, the work function layers 68A and 68B completely fill the bottom gap between the nanostructures 22B1 and the semiconductor strip 20', and upper layers such as the silicon layer 70 and the glue layer 72 do not fill into the bottom gap. According to alternative embodiments, some other layers such as the silicon layer 70 or both the silicon layer 70 and the glue layer 72 fill into the bottom gap, while the upper gap is completely filled by the work function layer 68B. A dielectric hard mask 80 is formed over the gate stacks 78A and 78B. The forming process may include: recessing the gate stacks 78A and 78B by etching; and filling the resulting grooves with a dielectric material. Then a planarization process is implemented to make the top surface of the dielectric hard mask 80 flush with the top surface of the ILD 52.

[0056] Figure 11A-1 , Figure 11A-2 , Figure 11B-1 and Figure 11B-2 and Figure 12A-1 , Figure 12A-2 , Figure 12B-1 and Figure 12B-2 illustrates the formation of the upper components. According to some embodiments, as Figure 11A-1 , Figure 11A-2 , Figure 11B-1 and Figure 11B-2 shown, a source / drain silicide layer 82 is formed over the source / drain regions 48A and 48B, and source / drain contact plugs 84 are formed in the ILD 52. An etch stop layer 86 and an ILD 88 are further formed, and source / drain contact plugs 92 are formed in the etch stop layer 86 and the ILD 88. The formation of the source / drain contact plugs 92 includes a planarization process such as a CMP process. Figure 12A-1 , Figure 12A-2 , Figure 12B-1 and Figure 12B-2 illustrates the formation of the gate contact plug 90, which penetrates the dielectric hard mask 80 to electrically connect to the gate electrode.

[0057] In the device region 100A, as Figure 12A-1 and Figure 12A-2 shown, the work function layer 68A completely fills the gap between adjacent semiconductor nanostructures 22B, and completely fills the gap between the bottom semiconductor nanostructure 22B and the semiconductor strip 20'. Thus, both the channel and the sub-channel 20' formed by the semiconductor nanostructures 22B are controlled by the gate stacks with the work function layer 68A.

[0058] It can be considered that the nanosheet transistor 110A includes two types of sub-transistors. The first sub-transistor 110A-1 includes the sub-channel 20' as its channel, the gate stack portion between the sub-channel 20' and the semiconductor nanostructure 22B1 as its gate stack, and the source / drain region 48A as its source / drain region. The second sub-transistor 110A-2 includes a plurality of semiconductor nanostructures 22B1 and 22B2 as channels, and the corresponding upper portion of the gate stack 78A as its gate stack, and also includes the source / drain region 48A as their source / drain region. The sub-transistors 110A-1 and 110A-2 are connected in parallel to form the transistor 110A. The sub-transistors 110A-1 and 110A-2 can have the same threshold voltage.

[0059] In the device region 100B, on the other hand, as Figure 11B-1 and Figure 11B-2 shown, the work function layer 68B completely fills the gap between adjacent semiconductor nanostructures 22B2. Therefore, the corresponding work function layer is the work function layer 68B. On the other hand, the work function layers 68B and 68A (collectively referred to as the work function layer 68B') jointly fill the bottom gap between the bottom semiconductor nanostructure 22B1 and the semiconductor strip 20'.

[0060] It can be considered that the nanosheet transistor 110B also includes two types of sub-transistors. The first sub-transistor 110B-1 includes the sub-channel 20' as its channel, the gate stack portion 78B between the sub-channel 20' and the bottom semiconductor nanostructure 22B1 as its gate stack, and the source / drain region 48B as its source / drain region. The second sub-transistor 110B-2 includes a plurality of semiconductor nanostructures 22B1 and 22B2 as channels, and the corresponding upper portion of the gate stack 78B as their gate stack, and the source / drain region 48B as their gate stack. The sub-transistors 110B-1 and 110B-2 are connected in parallel to form the transistor 110B.

[0061] According to some embodiments in which the work function layer 68B has a p-type work function (e.g., work function WF68B), the work function layer 68A has a work function WF68A that is lower than the work function WF68B. Therefore, assuming that the transistor 110B is a p-type transistor, the effective work function of the gate electrode of the first sub-transistor 110B-1 is lower than the individual work function WF68B. Therefore, the threshold voltage Vt68B1 of the sub-transistor 110B-1 is higher than the threshold voltage Vt68B2 of the sub-transistor 110B-2.

[0062] It should be understood that the sub-channel 20' is prone to leakage, especially when the width of the nanosheet increases. According to some embodiments, by adjusting the work function layer of the gate stack portion for the sub-channel 20', when the transistor 110B is turned off, since the threshold voltage Vt68B1 of the sub-transistor 110B-1 is higher than the threshold voltage Vt68B2 of the sub-transistor 110B-2, the sub-channel 20' is better turned off, and the leakage current through the sub-channel 20' is reduced.

[0063] According to some exemplary embodiments discussed above, the transistor 110A is an n-type transistor, and the transistor 110B is a p-type transistor. Accordingly, the work function layer 68B is a p-type work function layer or a mid-gap work function layer, and the work function layer 68A has a lower work function than the work function layer 68B (which can be a p-type work function, a mid-gap work function, or an n-type work function) to increase the threshold voltage of the sub-transistor 100B-1.

[0064] According to an alternative embodiment, the transistor 110A is a p-type transistor, and the transistor 110B is an n-type transistor. Accordingly, the work function layer 68B is an n-type work function layer or a mid-gap work function layer, and the work function layer 68A has a higher work function than the work function layer 68B (which can be an n-type work function, a mid-gap work function, or a p-type work function) to increase the threshold voltage of the sub-transistor 100B-1.

[0065] According to still some alternative embodiments, both the transistors 110A and 110B are p-type transistors. Accordingly, the work function layer 68B is a p-type work function layer or a mid-gap work function layer, and the work function layer 68A has a lower work function than the work function layer 68B (which can be an n-type work function or a mid-gap work function) to increase the threshold voltage of the sub-transistor 100B-1.

[0066] According to still some alternative embodiments, both the transistors 110A and 110B are n-type transistors. Accordingly, the work function layer 68B is an n-type work function layer or a mid-gap work function layer, and the work function layer 68A has a higher work function than the work function layer 68B (which can be a p-type work function or a mid-gap work function) to increase the threshold voltage of the sub-transistor 100B-1.

[0067] Embodiments of the present disclosure have some advantageous features. By forming multiple work function layers for the bottom portion of the gate stack of the GAA transistor, the threshold voltage of the bottom sub-transistor is increased, and the leakage through the sub-channel is reduced.

[0068] According to some embodiments of the present disclosure, the method includes: depositing a multi-layer stack including a plurality of sacrificial layers and a plurality of semiconductor layers alternately positioned, wherein the plurality of sacrificial layers includes: a bottom sacrificial layer having a first thickness; and an upper sacrificial layer located above the bottom sacrificial layer, wherein the upper sacrificial layer has a second thickness less than the first thickness; patterning the multi-layer stack to form a first protruding fin; forming a first pseudo-gate stack on the first protruding fin; forming a first source / drain region beside the first pseudo-gate stack; removing the plurality of sacrificial layers in the first pseudo-gate stack and the first protruding fin to leave a first groove; and forming a first replacement gate stack in the first groove.

[0069] In an embodiment, the ratio of one of the first thickness to the second thickness is greater than about 1.2. In an embodiment, the first groove includes: a bottom groove located below the bottommost semiconductor layer of the plurality of semiconductor layers in the first protruding fin, wherein forming the first replacement gate stack includes depositing a first work function layer and depositing a second work function layer into the bottom groove; and an upper groove above the bottommost semiconductor layer, wherein the first replacement gate stack includes the first work function layer in the upper groove. In an embodiment, depositing the first work function layer fills the entirety of one of the upper grooves.

[0070] In an embodiment, the first work function layer and the second work function layer include different materials. In an embodiment, the first source / drain region is included in a p-type transistor, and wherein the second work function layer has a lower work function than the first work function layer. In an embodiment, the first work function layer has a p-type work function, and the second work function layer has an n-type work function. In an embodiment, the first work function layer has a first p-type work function, and the second work function layer has a second p-type work function lower than the first p-type work function.

[0071] In an embodiment, the first source / drain region is included in an n-type transistor, and wherein the second work function layer has a higher work function than the first work function layer. In an embodiment, the first work function layer has an n-type work function, and the second work function layer has a p-type work function. In an embodiment, the first work function layer has a first n-type work function, and the second work function layer has a second n-type work function higher than the first n-type work function.

[0072] In an embodiment, patterning the multi-layer stack further forms a second protruding fin, and the method further includes: forming a second pseudo-gate stack on the second protruding fin; forming a second source / drain region beside the second pseudo-gate stack; removing the plurality of sacrificial layers in the second pseudo-gate stack and the second protruding fin to leave a second groove; and forming a second replacement gate stack in the second groove, wherein all the second grooves are filled with the same work function layer.

[0073] According to some embodiments of the present disclosure, a structure includes: a semiconductor strip; a first isolation region and a second isolation region located on opposite sides of the semiconductor strip; a plurality of semiconductor nanostructures overlapping the semiconductor strip, wherein an upper plurality of semiconductor nanostructures overlap corresponding lower plurality of semiconductor nanostructures; a gate stack including: a bottom portion having a first height, wherein the bottom portion is located between the semiconductor strip and the plurality of semiconductor nanostructures; and an upper portion located between adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion has a second height less than the first height; and a semiconductor region located beside and in contact with the plurality of semiconductor nanostructures.

[0074] In an embodiment, the upper portions of the gate stack have the same height. In an embodiment, the bottom portion of the gate stack includes: a first work function layer; and a second work function layer surrounded by the first work function layer, wherein the upper portion of the gate stack includes the first work function layer and does not include the second work function layer. In an embodiment, the bottom portion further includes a silicon layer surrounded by the second work function layer. In an embodiment, a ratio of one of the first height to the second height is greater than about 1.2.

[0075] According to some embodiments of the present disclosure, a structure includes: a plurality of semiconductor nanostructures, wherein an upper plurality of semiconductor nanostructures overlap corresponding lower plurality of semiconductor nanostructures; a gate stack including: a bottom portion located below the bottommost semiconductor nanostructure of the plurality of semiconductor nanostructures, wherein the bottom portion includes: a first work function layer; and a second work function layer surrounded by the first work function layer, wherein all layers in the bottom portion have a first total number; and an upper portion located between two adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion includes the second work function layer, and wherein all layers in the upper portion have a second total number less than the first total number; and a semiconductor region located beside and in contact with the plurality of semiconductor nanostructures. In an embodiment, the upper portion of the gate stack does not include the second work function layer. In an embodiment, a first height of the bottom portion is higher than a second height of the upper portion.

[0076] Some embodiments of the present application provide a method of forming a semiconductor structure, including: depositing a multi-layer stack including a plurality of sacrificial layers and a plurality of semiconductor layers alternately positioned, wherein the plurality of sacrificial layers include: a bottom sacrificial layer having a first thickness; and an upper sacrificial layer located above the bottom sacrificial layer, wherein the upper sacrificial layer has a second thickness less than the first thickness; patterning the multi-layer stack to form a first protruding fin; forming a first dummy gate stack on the first protruding fin; forming a first source / drain region beside the first dummy gate stack; removing the plurality of sacrificial layers in the first dummy gate stack and the first protruding fin to leave a first groove; and forming a first replacement gate stack in the first groove.

[0077] In some embodiments, a ratio of one of the first thickness to the second thickness is greater than about 1.2. In some embodiments, the first groove includes: a bottom groove located below a bottommost semiconductor layer of the plurality of semiconductor layers in the first protruding fin, wherein forming the first replacement gate stack includes depositing a first work function layer and depositing a second work function layer into the bottom groove; and an upper groove above the bottommost semiconductor layer, wherein the first replacement gate stack includes the first work function layer in the upper groove. In some embodiments, depositing the first work function layer causes an entirety of one of the upper grooves to be filled. In some embodiments, the first work function layer and the second work function layer include different materials. In some embodiments, the first source / drain region includes in a p-type transistor, and wherein the second work function layer has a lower work function than the first work function layer. In some embodiments, the first work function layer has a p-type work function, and the second work function layer has an n-type work function. In some embodiments, the first work function layer has a first p-type work function, and the second work function layer has a second p-type work function lower than the first p-type work function. In some embodiments, the first source / drain region includes in an n-type transistor, and wherein the second work function layer has a higher work function than the first work function layer. In some embodiments, the first work function layer has an n-type work function, and the second work function layer has a p-type work function. In some embodiments, the first work function layer has a first n-type work function, and the second work function layer has a second n-type work function higher than the first n-type work function. In some embodiments, patterning the multi-layer stack further causes a second protruding fin to be formed, and the method further includes: forming a second dummy gate stack on the second protruding fin; forming a second source / drain region beside the second dummy gate stack; removing the plurality of sacrificial layers in the second dummy gate stack and the second protruding fin to leave a second groove; and forming a second replacement gate stack in the second groove, wherein all of the second grooves are filled with the same work function layer.

[0078] Some other embodiments of the present application provide a semiconductor structure, including: a semiconductor strip; a first isolation region and a second isolation region located on opposite sides of the semiconductor strip; a plurality of semiconductor nanostructures overlapping with the semiconductor strip, wherein the upper plurality of semiconductor nanostructures overlap with the corresponding lower plurality of semiconductor nanostructures; a gate stack including: a bottom portion having a first height, wherein the bottom portion is located between the semiconductor strip and the plurality of semiconductor nanostructures; and an upper portion located between adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion has a second height less than the first height; and a semiconductor region located beside and in contact with the plurality of semiconductor nanostructures.

[0079] In some embodiments, the upper portion of the gate stack has the same height. In some embodiments, the bottom portion of the gate stack includes: a first work function layer; and a second work function layer surrounded by the first work function layer, wherein the upper portion of the gate stack includes the first work function layer and does not include the second work function layer. In some embodiments, the bottom portion further includes a silicon layer surrounded by the second work function layer. In some embodiments, the ratio of one of the first height to the second height is greater than about 1.2.

[0080] Some further embodiments of the present application provide a semiconductor structure, including: a plurality of semiconductor nanostructures, wherein the upper plurality of semiconductor nanostructures overlap with the corresponding lower plurality of semiconductor nanostructures; a gate stack including: a bottom portion located below the bottommost semiconductor nanostructure of the plurality of semiconductor nanostructures, wherein the bottom portion includes: a first work function layer; and a second work function layer surrounded by the first work function layer, wherein all layers in the bottom portion have a first total number; and an upper portion located between two adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion includes the second work function layer, and wherein all layers in the upper portion have a second total number less than the first total number; and a semiconductor region located beside and in contact with the plurality of semiconductor nanostructures.

[0081] In some embodiments, the upper portion of the gate stack does not include the second work function layer. In some embodiments, the first height of the bottom portion is higher than the second height of the upper portion.

[0082] The features of several embodiments are outlined above, enabling those skilled in the art to better understand various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can readily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent constructs do not depart from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: Depositing a multi-layer stack including a plurality of sacrificial layers and a plurality of semiconductor layers positioned alternately, wherein the plurality of sacrificial layers include: A bottom sacrificial layer having a first thickness; and An upper sacrificial layer positioned above the bottom sacrificial layer, wherein the upper sacrificial layer has a second thickness less than the first thickness; Patterning the multi-layer stack to form a first protruding fin; Forming a first dummy gate stack on the first protruding fin; Forming a first source / drain region beside the first dummy gate stack; Removing the plurality of sacrificial layers in the first dummy gate stack and the first protruding fin to leave a first groove; and Forming a first replacement gate stack in the first groove.

2. The method according to claim 1, wherein The ratio of one of the first thickness to the second thickness is greater than 1.

2.

3. The method according to claim 1, wherein The first groove includes: A bottom groove positioned below the bottommost semiconductor layer of the plurality of semiconductor layers in the first protruding fin, wherein forming the first replacement gate stack includes depositing a first work function layer and depositing a second work function layer into the bottom groove; and An upper groove above the bottommost semiconductor layer, wherein the first replacement gate stack includes the first work function layer in the upper groove.

4. The method according to claim 3, wherein, Depositing the first work function layer such that it fills the entirety of one of the upper grooves.

5. The method according to claim 3, wherein, The first work function layer and the second work function layer include different materials.

6. The method according to claim 5, wherein, The first source / drain region is included in a p-type transistor, and wherein the second work function layer has a lower work function than the first work function layer.

7. The method according to claim 6, wherein, The first work function layer has a p-type work function, and the second work function layer has an n-type work function.

8. The method according to claim 6, wherein The first work function layer has a first p-type work function, and the second work function layer has a second p-type work function lower than the first p-type work function.

9. A semiconductor structure, comprising: A semiconductor strip; A first isolation region and a second isolation region positioned on opposite sides of the semiconductor strip; A plurality of semiconductor nanostructures overlapping with the semiconductor strip, wherein the upper plurality of semiconductor nanostructures overlap with corresponding lower plurality of semiconductor nanostructures; A gate stack, comprising: A bottom portion having a first height, wherein the bottom portion is positioned between the semiconductor strip and the plurality of semiconductor nanostructures; and An upper portion positioned between adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion has a second height less than the first height; and A semiconductor region positioned beside the plurality of semiconductor nanostructures and in contact with the plurality of semiconductor nanostructures.

10. A semiconductor structure, comprising: A plurality of semiconductor nanostructures, wherein the upper plurality of semiconductor nanostructures overlap with corresponding lower plurality of semiconductor nanostructures; A gate stack, comprising: A bottom portion positioned below the bottommost semiconductor nanostructure of the plurality of semiconductor nanostructures, wherein the bottom portion includes: A first work function layer; and A second work function layer surrounded by the first work function layer, wherein all layers in the bottom portion have a first total number; The upper portion, located between two adjacent ones of the plurality of semiconductor nanostructures, wherein the upper portion includes the second work function layer, and wherein all layers in the upper portion have a second total number less than the first total number; and The semiconductor region, located beside the plurality of semiconductor nanostructures and in contact with the plurality of semiconductor nanostructures.

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