Semiconductor structure processing method and semiconductor process equipment

Abstract

The invention discloses a semiconductor structure processing method and semiconductor process equipment, and belongs to the technical field of semiconductor processing, the processing method comprises the steps that a to-be-etched part is provided, the to-be-etched part comprises a target etching layer, a patterned mask layer and a dielectric structure, the target etching layer is provided with a plurality of isolation grooves, the patterned mask layer is located above the target etching layer, and the dielectric structure is located above the patterned mask layer; the patterned mask layer and the isolation grooves are filled with the dielectric structure, the top surface of the dielectric structure is flush with the top surface of the patterned mask layer, and the patterned mask layer is used as a mask structure in the process of forming the multiple isolation grooves in the target etching layer; removing the part, filled in the patterned mask layer, in the dielectric structure; removing the patterned mask layer; and removing a part of the remaining dielectric structure to a preset depth. According to the processing method, the problems that in the current shallow trench isolation process, when the layer structure above the fin-shaped structure is removed, the fin-shaped structure is prone to fracture, the performance of the device is reduced, and the yield is reduced can be solved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor processing technology, and particularly relates to a processing method for a semiconductor structure and a semiconductor process device. Background Art

[0002] In the process of semiconductor processing, the reduction of feature size is the current technological development trend. However, after the feature size is reduced to the processing limit of the lithography machine, if further reduction of the feature size is required, auxiliary technologies need to be used to increase the pattern density. Among common auxiliary technologies, since the double patterning process requires two lithography processes, it requires high alignment accuracy and does not have the ability to continuously double the pattern density. Therefore, the self-aligned multiple patterning technology is usually used to form a FinFET structure (Fin Field-Effect Transistor). However, during the STI (Shallow Trench Isolation) process, when the chemical mechanical polishing process is used to remove the dielectric structure, due to the relatively small width of the fin-shaped structure on the substrate, it is easy to be damaged during the grinding process, and even the fin-shaped structure breaks, resulting in a decrease in device performance and a reduction in yield. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a processing method for a semiconductor structure and a semiconductor process device to solve the problem that during the shallow trench isolation process, when removing the layer structure above the fin-shaped structure, the fin-shaped structure is prone to breakage, resulting in a decrease in device performance and a reduction in yield.

[0004] In a first aspect, this application discloses a processing method for a semiconductor structure, which includes: Providing an etching target, wherein the etching target includes a target etching layer, a patterned mask layer, and a dielectric structure. The target etching layer has a plurality of isolation grooves. The patterned mask layer is located above the target etching layer. The dielectric structure fills the patterned mask layer and each of the isolation grooves, and the top surface of the dielectric structure is flush with the top surface of the patterned mask layer. The patterned mask layer is used as a mask structure during the process of forming the plurality of isolation grooves on the target etching layer; Removing a part of the dielectric structure filled in the patterned mask layer; Removing the patterned mask layer; Removing a part of the remaining dielectric structure to a preset depth.

[0005] In a second aspect, the present application discloses a semiconductor process equipment, which includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor. When the program or instruction is executed by the processor, the steps of the processing method described above are implemented.

[0006] The embodiment of the present application discloses a processing method for a semiconductor structure. First, a workpiece to be etched needs to be provided. In the workpiece to be etched, the target etching layer has a plurality of isolation grooves, and a patterned mask layer is provided above the target etching layer. At the same time, the dielectric structure of the workpiece to be etched fills the patterned mask layer and each isolation groove, and the top surface of the dielectric structure is flush with the top surface of the patterned mask layer. And in the process of processing a plurality of isolation grooves on the substrate to form the target etching layer, the mask structure of the target etching layer is formed into a patterned mask layer. In order to remove the patterned mask layer, in the embodiment of the present application, first, the part of the dielectric structure filled in the patterned mask layer is removed, so that the patterned mask layer is integrally exposed outside the target etching layer. After that, the patterned mask layer is removed. Then, a part of the remaining dielectric structure is removed to a preset depth to expose the fin structure again. Since the patterned mask layer and the target etching layer are formed independently, the connection reliability between the two is relatively low. Furthermore, in the process of removing the patterned mask layer, the force acting on the patterned mask layer is difficult to be transmitted to the fin structure below it, which can reduce the probability of damage to the fin structure and improve the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings: Figure 1 is a schematic diagram of the process flow for removing the layer structure above the target etching layer in the current technology; Figure 2 is a schematic diagram of the process flow for removing the layer structure above the target etching layer by using the processing method disclosed in the embodiment of the present application; Figure 3 is a flowchart of the processing method disclosed in the embodiment of the present application; Figure 4 is a schematic diagram of a film layer structure required to form a workpiece to be etched in the processing method disclosed in the embodiment of the present application; Figures 5a - 5m is a schematic diagram of the intermediate structure at different nodes during the formation process of the patterned mask layer in the processing method disclosed in the embodiment of the present application; Figures 6a - 6c is a schematic diagram of the intermediate structure at different nodes during the formation process of the workpiece to be etched in the processing method disclosed in the embodiment of the present application.

[0008] Reference numerals: 10 - target etching layer, 11 - fin structure, 12 - isolation groove, 20 - patterned mask layer, 30 - dielectric structure, 30' - dielectric covering layer, 40 - patterned transition layer, 50 - patterned pattern transfer layer 101 - substrate, 102 - transition layer, 103 - second mask layer, 104 - pattern transfer layer, 105 - second axis layer, 106 - first mask layer, 107 - etch stop layer, 108 - first axis layer, 109 - SOC layer, 110 - BARC layer, 111 - photoresist layer, 112 - deposition layer, 113 - sidewall, 114 - second deposition layer, 115 - second sidewall. Detailed implementation manners

[0009] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0010] The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. generally belong to the same category, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally means an "or" relationship between the associated objects before and after.

[0011] As Figure 3 shown, an embodiment of the present application discloses a processing method for a semiconductor structure, which is applied to a shallow trench isolation process, and is particularly suitable for the shallow trench isolation process of Fin FET. Before performing the shallow trench isolation process, it is usually necessary to first form a fin structure 11 (i.e., a Fin structure). In order to ensure electrical isolation between adjacent Fin FETs, a shallow trench isolation structure needs to be formed between two adjacent fin structures. Specifically, by etching the substrate, an isolation groove 12 can be formed between any two adjacent fin structures 11 to provide electrical isolation for the two adjacent fin structures 11 by using the isolation groove 12. Among them, after the above process, the device formed on the substrate, which has multiple isolation grooves and includes multiple fin structures 11, is the target etching layer 10.

[0012] Moreover, in order to ensure relatively good subsequent graphic quality, after forming isolation grooves with a depth dimension meeting requirements on the target etching layer 10, i.e., the substrate, there is still a part of the mask layer directly serving as the target etching layer 10 remaining. Therefore, in the embodiments of the present application, the workpiece to be etched includes a target etching layer 10 and a patterned mask layer 20. Among them, during the process of etching the substrate to form the target etching layer 10, the patterned mask layer 20 serves as a mask structure.

[0013] In addition, in order to ensure relatively good isolation effect, during the process, it is necessary to perform dielectric filling on multiple isolation grooves formed on the target etching layer 10. Furthermore, in the embodiments of the present application, the workpiece to be etched further includes a dielectric structure 30, and the dielectric structure 30 is filled in each isolation groove. And, in order to improve the electrical isolation effect of the isolation grooves, during the process of forming the dielectric structure 30, it is necessary to make each isolation groove be filled with the dielectric structure as much as possible. For this purpose, the dielectric structure can be in an overfilled state in the isolation groove, that is, the upper surface of the dielectric structure exceeds the upper surface of the target etching layer. At the same time, in order to ensure that the pattern can be transferred normally, the mask layer directly serving as the substrate has been patterned, and the pattern of the patterned mask layer corresponds to the isolation grooves of the target etching layer. In the case where the upper surface of the dielectric structure exceeds the upper surface of the target etching layer, the dielectric structure naturally fills in the pattern of the patterned mask layer. That is, in the embodiments of the present application, the dielectric structure is filled in each isolation groove of the target etching layer and each patterned mask layer.

[0014] Furthermore, in order to ensure relatively high consistency in the removal of the dielectric material at different positions in the pattern of the patterned mask layer when removing the part of the dielectric structure filled in the patterned mask layer, in the embodiments of the present application, the top surface of the dielectric structure 30 can be flush with the top surface of the patterned mask layer 20, so as to ensure that when removing the dielectric structure 30, the thickness of the dielectric material at different positions in the pattern of the patterned mask layer 20 is the same, so as to make the removal thickness (or depth) of the dielectric material at different positions in the pattern of the patterned mask layer 20 equal as much as possible within the same time, thereby facilitating the removal of the patterned mask layer.

[0015] Based on the above situation, as Figure 2 shown, in the embodiments of the present application, the processing method includes: A to-be-etched component is provided. The to-be-etched component includes a target etching layer 10, a patterned mask layer 20, and a dielectric structure 30. The target etching layer 10 has a plurality of isolation grooves, and the target etching layer 10 includes a plurality of fin structures. In the target etching layer 10, any isolation groove is used to electrically isolate two adjacent fin structures. The patterned mask layer 20 is located above the target etching layer 10. The dielectric structure 30 fills the patterned mask layer 20 and each isolation groove, and the top surface of the dielectric structure 30 is flush with the top surface of the patterned mask layer 20. Additionally, as described above, during the process of forming a plurality of isolation grooves on the substrate to form the target etching layer 10, the patterned mask layer 20 serves as a mask structure of the substrate.

[0016] After that, it is necessary to remove the part of the dielectric structure 30 located above the target etching layer 10 and the patterned mask layer 20. In the related art, as Figure 1 shown, usually, the patterned mask layer 20 is first removed by etching. After that, the part of the dielectric structure 30 located above the target etching layer 10 is removed by chemical mechanical polishing to expose the target etching layer 10. However, since the width of the fin structure is relatively small, and the dielectric material in the isolation groove of the target etching layer 10 and the dielectric material above the target etching layer 10 are formed in the same process stage, the integrity of the dielectric materials at two positions, one in the pattern of the patterned mask layer 20 and the other in the isolation groove, of the dielectric structure 30 is relatively strong. This makes it easy for the shear force received by the dielectric structure 30 to be transmitted to the fin structure when removing the dielectric material above the target etching layer 10 by chemical mechanical polishing, making the fin structure easy to be damaged or even broken.

[0017] Therefore, in the processing method disclosed in the embodiments of the present application, as Figure 2 shown, a technical solution is given to first remove the part of the dielectric structure 30 filled in the patterned mask layer 20, and then remove the patterned mask layer 20. In the case of adopting this technical solution, after removing the part of the dielectric structure 30 filled in the patterned mask layer 20, the patterned mask layer 20 is integrally exposed. Compared with the connection reliability between the parts of the dielectric structure 30 filled in the isolation groove and the pattern of the patterned mask layer respectively, since the two-layer structures of the patterned mask layer 20 and the target etching layer 10 are independently formed, the connection reliability between the patterned mask layer 20 and the target etching layer 10 is relatively low. Furthermore, during the process of removing the patterned mask layer 20, the force acting on the patterned mask layer 20 is difficult to be transmitted to the fin structure below it. Thus, compared with the above-mentioned related art, the technical solution disclosed in the present application can reduce the probability of damage to the fin structure when removing the layer structure above the fin structure during the shallow trench isolation process and improve the yield of the product.

[0018] Specifically, after the above step S1, as Figure 3 shown, in combination with Figure 2 , the processing method disclosed in the embodiments of the present application further includes: S2. Removing a part of the medium structure 30 filled in the patterned mask layer 20; S3. Removing the patterned mask layer 20.

[0019] Of course, after step S3, generally, a part of the dielectric material filled in each isolation groove can be further removed by etching or the like to expose the fin structure.

[0020] That is, in the embodiments of the present application, the processing method further includes: S4. Removing a part of the remaining medium structure to a preset depth. Of course, in this process, the removal depth of the remaining medium structure can be flexibly selected according to actual needs. For example, the aforementioned depth can correspond to the height of the fin structure, and this is not limited herein.

[0021] The embodiments of the present application disclose a processing method for a semiconductor structure. First, a workpiece to be etched needs to be provided. In the workpiece to be etched, the target etching layer 10 has a plurality of isolation grooves, and a patterned mask layer 20 is provided above the target etching layer 10. At the same time, the medium structure 30 of the workpiece to be etched is filled in the patterned mask layer 20 and each isolation groove. The top surface of the medium structure 30 is flush with the top surface of the patterned mask layer 20, and during the process of processing a plurality of isolation grooves on the substrate to form the target etching layer 10, the mask structure of the substrate is formed into the patterned mask layer 20. In order to remove the patterned mask layer 20, in the embodiments of the present application, first, a part of the medium structure 30 filled in the patterned mask layer 20 is removed, so that the patterned mask layer 20 is integrally exposed outside the target etching layer 10. Then, the patterned mask layer 20 is removed. Then, a part of the remaining medium structure 30 is removed to a preset depth to expose the fin structure again. Since the patterned mask layer 20 and the target etching layer 10 are independently formed, the connection reliability between the two is relatively low. Furthermore, during the process of removing the patterned mask layer 20, the force acting on the patterned mask layer 20 is difficult to transfer to the fin structure below it, which can reduce the probability of damage to the fin structure and improve the yield of the product.

[0022] Further, in a specific embodiment of the present application, an etching method can be adopted to remove a part of the medium structure 30 filled in the patterned mask layer 20. Of course, in this process, the etching gas needs to be correspondingly selected according to the specific materials of the target etching layer 10, the mask layer, and the medium structure respectively, so as to ensure that the medium structure 30 has a relatively high selectivity to the mask layer during the etching process. That is to say, in the embodiment of the present application, the processing method includes: removing a part of the medium structure filled in the patterned mask layer through the first etching step, that is, stopping the etching of the medium structure at a position flush with the bottom of the patterned mask layer. More specifically, by controlling the etching time of the first etching step, the medium structure 30 is etched to a position flush with the bottom of the patterned mask layer 20, so as to completely expose the patterned mask layer 20 for removal in subsequent steps.

[0023] In a specific embodiment of the present application, a deposition method can be adopted to form a medium structure. For this purpose, in the processing method disclosed in the embodiment of the present application, as Figures 6a - 6c shown, the steps of providing the workpiece to be etched include: forming a patterned mask layer on the substrate 101, as Figure 6a shown; etching the substrate by using the patterned mask layer, and forming a plurality of fin structures and isolation grooves on the substrate to form a target etching layer, as Figure 6b shown, wherein the isolation grooves are used to electrically isolate two adjacent fin structures; forming a medium structure between the target etching layer 10 and the patterned mask layer 20 through a deposition step.

[0024] Specifically, during the process of forming the medium structure by deposition, the medium material gradually fills each isolation groove 12 of the target etching layer 10, and as the deposition process continues, the height of the medium material filled in the isolation groove gradually increases until it is flush with the top surface of the target etching layer 10, filling the isolation groove with the medium material. In order to make the flatness of the medium material at the top of the isolation groove relatively better, it is necessary to make the medium material in an overfilled state relative to the isolation groove. For this purpose, in the embodiment of the present application, the medium material can be further deposited and filled in the patterns of the patterned mask layer.

[0025] Optionally, during the process of filling the medium material in the patterns of the patterned mask layer, when the filling height of the medium material is flush with the upper surface of the patterned mask layer, the deposition process can be stopped, that is, the upper surface of the medium material is flush with the upper surface of the patterned mask layer, which can form the above-mentioned workpiece to be etched.

[0026] In order to further improve the top flatness of the dielectric material in the isolation trench to enhance the performance of semiconductor devices, in another embodiment of the present application, when depositing the dielectric material on the target etching layer and the patterned mask layer through the deposition step, the dielectric material can be gradually deposited to a position where the upper surface exceeds the upper surface of the patterned mask layer, so that the dielectric material is also formed above the patterned mask layer.

[0027] That is, in the embodiment of the present application, the above-mentioned formation of the dielectric structure between the target etching layer and the patterned mask layer through the deposition step includes: Through the deposition step, a dielectric covering layer 30' is formed on the target etching layer and the patterned mask layer, wherein the upper surface of the dielectric covering layer 30' is higher than the upper surface of the patterned mask layer 20, as Figure 6c shown; After that, it further includes: chemically mechanically polishing the dielectric covering layer 30' until the patterned mask layer is exposed to form the dielectric structure 30. In this case, the etched part required in the embodiment of the present application can also be obtained, that is, Figure 2 the first figure ( Figure 2 the structure located in the upper left corner in

[0028] That is, in the embodiment of the present application, when forming the dielectric structure 30, first, through over-deposition, after the dielectric material has been filled in the patterned mask layer 20, the deposition process continues, so that the upper part of the patterned mask layer is integrally covered with the dielectric material, and the dielectric covering layer 30' is formed. After that, the part of the dielectric covering layer 30' located above the patterned mask layer is gradually removed by chemical mechanical polishing. During the above process, the flatness of the upper surface of the dielectric material can be gradually improved. Furthermore, when polished to a position flush with the patterned mask layer and the etched part is formed, it is ensured that the flatness of the upper surface of the dielectric structure is relatively high to enhance the performance of the subsequent formed semiconductor device. It should be noted that during the process of chemically mechanically polishing the dielectric covering layer, its upper surface is not a fixed surface but continuously changing.

[0029] Furthermore, between the step of forming the dielectric covering layer and the step of chemically mechanically polishing the dielectric covering layer, the processing method disclosed in the embodiment of the present application may further include: Annealing the dielectric covering layer.

[0030] In the case of adopting the technical solution of the present application, the densification of the dielectric material in the dielectric covering layer can be improved by annealing, which makes the electrical isolation effect provided by the dielectric material stronger and further improves the electrical isolation effect of the isolation trench on the adjacent two fin structures.

[0031] As described above, the processing method disclosed in the embodiments of the present application includes removing a part of the remaining dielectric structure to a preset depth. Different from the removal method of the part of the dielectric structure located above the patterned mask layer, in the embodiments of the present application, an etching method can be used to further remove the part of the dielectric structure located between two adjacent fin structures to prevent damage to the fin structures during the above removal process.

[0032] That is, the above step S4 includes: Through a second etching step, a part of the remaining dielectric structure is removed to a preset depth to expose the fin structures.

[0033] In addition, in order to further prevent damage to the fin structures during the process of removing the patterned mask layer 20, in a specific embodiment of the present application, an etching method can also be used to remove the patterned mask layer 20. Compared with the method of removing the patterned mask layer by chemical mechanical polishing, the method disclosed in the embodiments of the present application enables the patterned mask layer 20 to hardly be affected by shear force during the process of removing the patterned mask layer 20, thereby greatly reducing the probability of damage to the fin structures due to external forces. Of course, during the process of removing the patterned mask layer 20 by etching, the etching gas needs to be selected corresponding to the materials of the mask layer and the target etching layer 10 respectively to ensure that the mask layer has a high selectivity ratio relative to the target etching layer 10.

[0034] Based on the above embodiments, in order to reduce the etching control difficulty of the mask layer and prevent over-etching during the process of etching to remove the patterned mask layer and damage the target etching layer, in the embodiments of the present application, the workpiece to be etched can also include a patterned transition layer 40, and the patterned transition layer 40 is located between the fin structures 11 and the patterned mask layer 20. Of course, similar to the patterned mask layer 20, the patterned transition layer 40 is formed after the transition layer is etched and the pattern is transferred. The pattern structure formed on the transition layer is the same as the pattern structure formed on the mask layer. That is, during the process of etching the substrate to form the target etching layer 10 with multiple isolation grooves, the pattern structure is first transferred to the mask layer to form the patterned mask layer 20, and then transferred to the transition layer to form the patterned transition layer 40, and finally transferred to the substrate to form the target etching layer 10. During the etching process, the transition layer is used to provide the function of balancing internal stress. In the case where the target etching layer is formed of a silicon substrate, optionally, the transition layer is formed of materials such as silicon oxide. In addition, in the case where the workpiece to be etched includes a patterned transition layer, during the process of forming the dielectric structure, a part of the dielectric structure fills the pattern of the patterned transition layer.

[0035] In an embodiment of the present application, the patterned transition layer 40 can also have a selectivity ratio with respect to the patterned mask layer 20, that is, the selectivity ratio of the transition layer to the mask layer is greater than 1. In this case, when the patterned mask layer 20 is removed by etching, the transition layer 40 can also provide a certain etching stop function. Thus, during the process of etching and removing the patterned mask layer 20, after the lower edge of the patterned mask layer 20 is basically completely etched away, since the part to be continuously etched is the patterned transition layer, the end point of the aforementioned etching process can be judged more accurately and quickly from parameters such as the etching rate, thereby reducing the process difficulty and preventing the target etched layer 10 from being etched during this process.

[0036] Of course, in the case of adopting the above technical solution, after the patterned mask layer is etched and removed, in order to achieve the purpose of etching the part between any two adjacent fin structures in the dielectric structure, it is necessary to remove the patterned transition layer. Therefore, in the processing method disclosed in the embodiment of the present application, after removing the patterned mask layer, it further includes: removing the patterned transition layer and the part of the dielectric structure filled in the patterned transition layer. More specifically, the etching selectivity ratio of the transition layer and the dielectric material can be made equivalent, or the dielectric material can have a high selectivity ratio with respect to the transition layer, so that during the process of etching the dielectric structure, when the patterned transition layer is removed or basically removed, the part between any two adjacent fin structures in the dielectric structure (i.e., the remaining part in the dielectric structure) can be etched to a preset depth.

[0037] Furthermore, in the embodiment of the present application, a self-aligned multiple patterning technique can be adopted to form the patterned mask layer.

[0038] Specifically, during the process of etching a plurality of isolation grooves on the substrate to form the workpiece to be etched, a film layer structure can be formed first, such as Figure 4As shown, the film layer structure may sequentially include, from bottom to top: a substrate 101, a transition layer 102, a second mask layer 103, a pattern transfer layer 104, a second core layer 105, a first mask layer 106, an etch stop layer 107, a first core layer 108, a SOC (Spin-On Carbon) layer 109, a BARC (Bottom Anti-Reflective Coating) layer 110, and a photoresist layer 111. Among them, the second mask layer 103 is used to form a patterned mask layer in the component to be etched. Based on the foregoing film layer structure, after processes such as etching and deposition, a required patterned mask layer 20 can be formed on the substrate 101, and the patterned mask layer 20 has a relatively high pattern density. It should be noted that this embodiment only takes the self-aligned quadruple patterning (SAQP) technology as an example, however, the present invention is not limited thereto, and other methods for forming a patterned mask layer are feasible.

[0039] As Figure 5a shown, based on the foregoing film layer structure, through exposure and development processing, the photoresist layer 111 can be formed into a patterned photoresist layer, as Figure 5b and Figure 5c shown. By using the etching method, the pattern of the photoresist layer 111 can be sequentially transferred to the BARC layer 110, the SOC layer 109, and the first core layer 108, and is stopped by the etch stop layer 107. After that, as Figure 5d shown, through deposition and other methods, a deposition layer 112 can be formed on the outer wall of the patterned first core layer, and as Figure 5e shown, by using the etching method, the part of the deposition layer 112 located at the top of the patterned first core layer is removed to form sidewalls 113 on both sides of each structure in the patterned first core layer. After that, as Figure 5f shown, the patterned first core layer is removed to achieve the purpose of reducing the graphic size and increasing the pattern density. After that, as Figure 5g shown, by using the etching method, the pattern (i.e., the sidewalls 113) after doubling the pattern density is transferred to the first mask layer 106, as Figures 5h - 5j shown. After further etching, the pattern of the patterned first mask layer is transferred to the second core layer 105 to form a patterned second core layer, and as Figure 5k and Figure 5l shown, by using the deposition method in sequence, a second deposition layer 114 is formed on the outside of each structure in the patterned core layer. After etching, the part of the second deposition layer 114 located at the top of the patterned second core layer is removed, so as to form second sidewalls 115 on both sides of the patterned second core layer, as Figure 5mAs shown, after removing the patterned second axis layer, the pattern density can be further doubled, making the pattern density four times the initial pattern density. After that, using the second sidewall 115 as a mask structure, the pattern can be sequentially transferred to the pattern transfer layer 104 and the second mask layer 103. In the case where the transition layer 102 is provided, the pattern can be further transferred to the transition layer 102. During the above process, as Figure 5m shown, the pattern formed above the pattern transfer layer 104 can be transferred to the second mask layer 103 to form the patterned mask layer 20. Based on this, using the patterned mask layer as a mask structure to etch the substrate 101, a plurality of isolation grooves 12 can be formed on the substrate 101, thereby forming the target etched layer 10.

[0040] During the process of forming the patterned mask layer using the self-aligned multiple patterning technique, in order to further improve the pattern quality, when a plurality of isolation grooves 12 with a preset depth have been formed on the substrate 101, part of the pattern transfer layer 104 can still remain. That is, when the target etched layer 10 is formed, the thickness of the patterned pattern transfer layer 50 is still greater than 0. In other words, in the embodiments of the present application, as Figure 6b shown, when the pattern is transferred to the mask layer 103 and after the etching work of the isolation grooves 13 on the substrate 101 has been completed, at least part of the patterned pattern transfer layer 50 still remains, which can further improve the pattern quality formed on the target etched layer 10.

[0041] Based on any of the above processing methods, the embodiments of the present application also disclose a semiconductor structure formed by using any of the above processing methods.

[0042] The embodiments of the present application also provide a semiconductor process device, including a processor, a memory, a program or instruction stored on the memory and executable on the processor. When the program or instruction is executed by the processor, it realizes each process of the above processing method embodiment and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0043] The embodiments of the present application also provide a storage medium storing a program or instruction. When the program or instruction is executed by the processor, it realizes each process of the processing method embodiment provided in any of the above embodiments and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0044] Among them, the processor is the processor in the semiconductor process device in the above embodiment. The storage medium includes computer storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc.

[0045] It should be noted that in this article, the terms "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such a process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0046] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. A method for processing a semiconductor structure, characterized in that, Including: Providing an etching target, wherein the etching target includes a target etching layer, a patterned mask layer, and a dielectric structure. The target etching layer has a plurality of isolation grooves. The patterned mask layer is located above the target etching layer. The dielectric structure fills the patterned mask layer and each of the isolation grooves, and the top surface of the dielectric structure is flush with the top surface of the patterned mask layer. The patterned mask layer is used as a mask structure during the process of forming the plurality of isolation grooves on the target etching layer; Removing the part of the dielectric structure that fills the patterned mask layer; Removing the patterned mask layer; Removing part of the remaining dielectric structure to a preset depth.

2. The processing method according to claim 1, characterized in that, The removing the part of the dielectric structure that fills the patterned mask layer includes: By controlling the etching time of the first etching step, the etching of the dielectric structure is stopped at a position flush with the bottom of the patterned mask layer.

3. The processing method according to claim 1, characterized in that, The providing the etching target includes: Forming the patterned mask layer on a substrate; Using the patterned mask layer to etch the substrate, and forming a plurality of fin structures and isolation grooves on the substrate to form a target etching layer. The isolation grooves are used to electrically isolate two adjacent fin structures; Through a deposition step, forming a dielectric structure between the target etching layer and the patterned mask layer.

4. The processing method according to claim 3, wherein The through the deposition step, forming a dielectric structure between the target etching layer and the patterned mask layer includes: Through a deposition step, forming a dielectric covering layer on the target etching layer and the patterned mask layer. The upper surface of the dielectric covering layer is higher than the upper surface of the patterned mask layer; Chemically mechanically polishing the dielectric covering layer until the patterned mask layer is exposed to form a dielectric structure.

5. The processing method according to claim 4, characterized in that, Between the step of forming the dielectric covering layer and the step of chemically mechanically polishing the dielectric covering layer, there is also included: Annealing the dielectric covering layer.

6. The processing method according to claim 3, characterized in that, The removing part of the remaining dielectric structure to a preset depth includes: Through a second etching step, removing part of the remaining dielectric structure to a preset depth to expose the fin structures.

7. The processing method according to claim 3, characterized in that, The etching target further includes a patterned transition layer, and the patterned transition layer is located between the fin structures and the patterned mask layer.

8. According to the processing method described in claim 3, characterized in that Using a self-aligned multiple patterning technique to form the patterned mask layer.

9. The processing method according to claim 8, characterized in that, On the side of the patterned mask layer facing away from the target etching layer, there is also provided a pattern transfer layer. When the substrate is formed with a plurality of isolation grooves with a preset depth, the thickness of the pattern transfer layer is greater than 0.

10. A semiconductor process equipment, characterized in that, Including a processor, a memory, and a program or instruction stored on the memory and executable on the processor. When the program or instruction is executed by the processor, the steps of the processing method described in any one of claims 1 to 9 are implemented.

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