Gallium nitride device and method for preparing the same

Abstract

The present application provides a gallium nitride device and a method for preparing the same, relating to the field of semiconductor device technology. The device is capable of improving the withstand voltage of a buffer layer of the gallium nitride device and enhancing the dynamic electrical properties of the gallium nitride device. The gallium nitride device comprises: a silicon substrate, an insulating layer, and a buffer layer stacked along a first direction, the insulating layer being located between the silicon substrate and the buffer layer, separating the silicon substrate and the buffer layer, the insulating layer and the buffer layer being in contact with each other, the insulating layer comprising a first portion and a second portion, the first portion and the second portion being adjacently arranged in a second direction, the first portion having a thickness less than the second portion along the first direction, and the second direction being perpendicular to the first direction. The gallium nitride device introduces an insulating layer between the silicon substrate and the buffer layer to separate the silicon substrate and the buffer layer, thereby preventing background electrons from being captured by defects in the buffer layer, thereby improving the on-resistance of the buffer layer, improving the withstand voltage of the buffer layer, and improving the dynamic electrical properties of the gallium nitride device.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a gallium nitride device and a method for preparing the gallium nitride device. Background Art

[0002] Gallium nitride (GaN) is a new semiconductor material used in the development of microelectronics and optoelectronics. Along with other semiconductor materials such as silicon carbide (SiC) and diamond, it is considered a third-generation semiconductor material. Due to the lack of large-scale GaN substrates, GaN is typically grown via heteroepitaxial growth on sapphire, silicon carbide, and silicon substrates. Silicon substrates, due to their advantages such as large size, low cost, and adjustable conductivity, are widely used as epitaxial materials for GaN microelectronics and optoelectronics, enabling the fabrication of silicon-based GaN devices.

[0003] To improve the vertical breakdown voltage of GaN-on-Si devices, a high-resistance buffer layer is typically formed above the silicon substrate. For example, a buffer layer with a high aluminum (Al) content can be grown to increase the breakdown voltage per unit thickness, or a thicker GaN buffer layer can be grown. However, during the epitaxial growth of GaN on a silicon substrate, a high amount of background electrons is generated, reducing the on-resistance of the buffer layer and thus affecting the dynamic electrical properties of the GaN-on-Si device. Summary of the Invention

[0004] The embodiments of the present disclosure provide a gallium nitride device and a method for manufacturing the gallium nitride device, which can improve the withstand voltage level of the buffer layer of the gallium nitride device and enhance the dynamic electrical properties of the gallium nitride device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a gallium nitride device is provided. The gallium nitride device comprises: a silicon substrate, an insulating layer, and a buffer layer stacked along a first direction, the insulating layer being located between the silicon substrate and the buffer layer, separating the silicon substrate and the buffer layer, and being in contact with the buffer layer; the insulating layer comprising a first portion and a second portion, the first portion and the second portion being adjacently arranged in a second direction; the first portion being thinner than the second portion along the first direction, and the second direction being perpendicular to the first direction.

[0007] The gallium nitride device provided in the embodiments of the present disclosure introduces an insulating layer between the silicon substrate and the buffer layer to separate the silicon substrate and the buffer layer, thereby providing electrical isolation and blocking the electrical coupling between the silicon substrate and the buffer layer. This prevents background electrons injected into the buffer layer from being captured by defects in the buffer layer, thereby increasing the on-resistance of the buffer layer, improving the withstand voltage of the buffer layer, reducing the off-state leakage current, and further improving the dynamic on-resistance stability of the gallium nitride device, thereby improving the dynamic electrical properties and reliability of the gallium nitride device.

[0008] In the gallium nitride device provided by the embodiments of the present disclosure, the insulating layer includes a first portion and a second portion arranged adjacent to each other in a second direction. Along the first direction, the thickness of the first portion is less than that of the second portion, forming an alternating thin-thick structure. This alternating thin-thick structure is achieved by a secondary epitaxial growth process for the insulating layer. This secondary epitaxial growth ensures the crystal continuity of the insulating layer, reduces defects in the insulating layer, and forms a coherent insulating layer, thereby stably separating the silicon substrate and the buffer layer.

[0009] In some embodiments, the plurality of first portions and the plurality of second portions together constitute a first surface of the insulating layer, the first surface is in contact with the buffer layer, and the first surface has first protrusions and first recesses alternately arranged along the second direction.

[0010] In some embodiments, there are multiple first portions and multiple second portions; along the second direction, the multiple first portions and the multiple second portions are alternately arranged.

[0011] In some embodiments, along the first direction, a thickness difference between the first portion and the second portion ranges from 100 nm to 1000 nm.

[0012] In some embodiments, along the second direction, a length of each first portion is 200 nm to 10000 nm.

[0013] In some embodiments, along the second direction, the length of the plurality of second portions accounts for 30% to 70% of the length of the insulating layer.

[0014] In some embodiments, the thickness of the insulating layer is 50 nm to 1500 nm.

[0015] In some embodiments, the thermal expansion coefficient of the insulating layer is less than and / or, the difference between the thermal expansion coefficient of the insulating layer and the thermal expansion coefficient of the silicon substrate is less than .

[0016] In some embodiments, the material of the insulating layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0017] In some embodiments, the buffer layer includes a first buffer layer and a second buffer layer stacked along a first direction, and the second buffer layer is located between the first buffer layer and the insulating layer.

[0018] In some embodiments, the second buffer layer includes a third portion and a fourth portion arranged along the first direction, the third portion is located between the fourth portion and the first portion, and the third portion and the second portion are arranged in the second direction.

[0019] In some embodiments, the gallium nitride device further includes a nucleation layer, the nucleation layer is located between the silicon substrate and the insulating layer, the insulating layer is located between the nucleation layer and the buffer layer, and the insulating layer separates the nucleation layer and the buffer layer.

[0020] In some embodiments, the gallium nitride device further includes a channel layer, a barrier layer, and a cap layer stacked along a first direction, the buffer layer is located between the channel layer and the insulating layer, and the barrier layer is located between the channel layer and the cap layer.

[0021] On the other hand, a method for preparing a gallium nitride device is provided, comprising: providing a silicon substrate; forming an insulating layer and a buffer layer; wherein the silicon substrate, the insulating layer, and the buffer layer are stacked along a first direction, the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer separates the silicon substrate and the buffer layer, and the insulating layer and the buffer layer are in contact with each other; the insulating layer comprises a first portion and a second portion, the first portion and the second portion are arranged adjacent to each other in a second direction; along the first direction, the thickness of the first portion is less than the thickness of the second portion, and the second direction is perpendicular to the first direction.

[0022] In some embodiments, forming an insulating layer and a buffer layer includes: forming an insulating dielectric layer, wherein a silicon substrate and the insulating dielectric layer are stacked along a first direction; removing a portion of the insulating dielectric layer to form a first hole, wherein the remaining insulating dielectric layer includes a first portion of the insulating layer; forming a second portion of the insulating layer in the first hole; and forming a buffer layer.

[0023] In some embodiments, a second portion of an insulating layer is formed in a first hole, including: forming a third portion of a second buffer layer, the third portion and the first portion are stacked along a first direction, the first portion is located between the third portion and the silicon substrate, and a second hole facing the first hole is provided between adjacent third portions; filling with insulating material so that the insulating material covers the first hole, the second hole and the third portion; and grinding the insulating material to expose the third portion.

[0024] In some embodiments, forming the buffer layer includes: forming a fourth portion of the second buffer layer, where the fourth portion covers the third portion and the second portion; and forming the first buffer layer, where the second buffer layer is located between the first buffer layer and the insulating layer.

[0025] It is understandable that the beneficial effects achieved by the method for preparing the gallium nitride device provided in the above embodiments of the present disclosure can be referred to the beneficial effects of the gallium nitride device described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure.

[0027] Figure 1 A schematic structural diagram of a gallium nitride device provided in one embodiment of the present application;

[0028] Figure 2 A schematic structural diagram of a gallium nitride device provided in yet another embodiment of the present application;

[0029] Figure 3 A schematic structural diagram of a gallium nitride device provided in another embodiment of the present application;

[0030] Figure 4 A schematic structural diagram of a gallium nitride device provided in yet another embodiment of the present application;

[0031] Figure 5 A schematic flow chart of a method for preparing a gallium nitride device according to one embodiment of the present application;

[0032] Figure 6 A schematic structural diagram of a silicon substrate provided in one embodiment of the present application;

[0033] Figure 7 A schematic diagram of a process for forming an insulating layer and a buffer layer according to an embodiment of the present application;

[0034] Figure 8 A schematic structural diagram of a first portion of forming an insulating layer on a silicon substrate according to an embodiment of the present application;

[0035] Figure 9 A schematic diagram of a structure for forming a nucleation layer on a silicon substrate according to an embodiment of the present application;

[0036] Figure 10 A schematic structural diagram of a first portion of forming an insulating layer on a nucleation layer according to an embodiment of the present application;

[0037] Figure 11 A schematic diagram of a process for forming a second part of an insulating layer in a first hole according to an embodiment of the present application;

[0038] Figure 12 A schematic diagram of a structure for forming a first nitride layer and a second nitride layer according to an embodiment of the present application;

[0039] Figure 13 A schematic structural diagram of a third portion for forming a second buffer layer according to an embodiment of the present application;

[0040] Figure 14 A schematic diagram of a structure for forming a third nitride layer according to an embodiment of the present application;

[0041] Figure 15 A schematic structural diagram of a third portion for forming a second buffer layer provided in another embodiment of the present application;

[0042] Figure 16A schematic diagram of the structure of the filling insulation material provided in one embodiment of the present application;

[0043] Figure 17 A schematic structural diagram of a filling insulating material provided in another embodiment of the present application;

[0044] Figure 18 A schematic diagram of a structure for forming an insulating layer according to an embodiment of the present application;

[0045] Figure 19 A schematic diagram of a structure for forming an insulating layer provided in another embodiment of the present application;

[0046] Figure 20 A schematic diagram of a process for forming a buffer layer according to an embodiment of the present application;

[0047] Figure 21 A schematic structural diagram of a fourth portion for forming a second buffer layer according to an embodiment of the present application;

[0048] Figure 22 A schematic structural diagram of a fourth portion for forming a second buffer layer provided in another embodiment of the present application;

[0049] Figure 23 A schematic diagram of a structure for forming a first buffer layer according to an embodiment of the present application;

[0050] Figure 24 A schematic structural diagram of forming a first buffer layer according to another embodiment of the present application;

[0051] Figure 25 A schematic diagram of a structure for forming a channel layer according to an embodiment of the present application;

[0052] Figure 26 A schematic diagram of a structure for forming a barrier layer and a cap layer according to an embodiment of the present application;

[0053] Figure 27 A schematic structural diagram of forming a channel layer provided in another embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0057] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C,” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] Gallium nitride (GaN) is a new semiconductor material for the development of microelectronics and optoelectronics. Along with other semiconductor materials such as silicon carbide (SiC) and diamond, it is considered a third-generation semiconductor material. Due to the lack of large-scale GaN substrates, GaN is typically grown via heteroepitaxial growth on sapphire, silicon carbide, and silicon substrates. Silicon (Si) substrates are widely used as epitaxial materials for GaN microelectronics and optoelectronics due to their advantages such as large size, low cost, and adjustable conductivity.

[0061] However, epitaxial growth of GaN thin films on silicon substrates is limited by the significant thermal and lattice mismatch between the silicon substrate and the GaN material. The significant thermal mismatch between the silicon substrate and the GaN material refers to the significant difference in thermal expansion coefficients between GaN and silicon. When cooled, GaN contracts faster than silicon, causing tensile stress in the GaN epitaxial layer, which can easily lead to cracks or warping. The lattice mismatch between the silicon substrate and the GaN material refers to the mismatch in the lattice constants of GaN and silicon. This leads to a high dislocation density in the GaN epitaxial layer, which affects the electrical performance of the fabricated GaN device (such as leakage current and reduced breakdown voltage). To address these issues, the performance of GaN devices can be improved by optimizing the GaN epitaxial structure and substrate parameters (such as thickness and resistivity).

[0062] For example, a low-resistivity silicon substrate with a resistance of less than 1 Ω·cm (ohm·cm) can be used as the substrate for GaN device epitaxy to reduce the substrate's on-resistance. Alternatively, the overall resistivity of the substrate can be reduced by increasing the substrate thickness, thereby mitigating warping caused by thermal stress. However, low-resistivity silicon itself cannot withstand high voltages. The high voltage withstand of silicon-based GaN devices in the vertical direction (referring to the first direction in the following embodiments) is primarily achieved by a high-resistance buffer layer above the silicon substrate. For example, the breakdown voltage per unit thickness can be increased by growing a high-aluminum (Al) buffer layer (Al>50%) above the silicon substrate. For example, a high-Al content AlN (aluminum nitride) or AlGaN (aluminum gallium nitride) superlattice buffer layer can be used, increasing the thickness of the AlGaN buffer layer and increasing the Al content in the AlGaN. Alternatively, a thicker GaN buffer layer can be grown to distribute stress, reduce cracking, and simultaneously improve the voltage withstand capability in the vertical direction.

[0063] During the epitaxial growth of GaN on silicon substrates, aluminum nitride (AlN) is typically used as a nucleation layer before the buffer layer is epitaxially grown on the silicon substrate. This layer mitigates the lattice mismatch between GaN and silicon and provides a starting template for heteroepitaxial growth. However, due to lattice and thermal mismatch, the interface between silicon and AlN is prone to the generation of numerous dislocation defects (such as threading dislocations). Furthermore, background electrons are easily generated at the AlN / Si interface, forming unintentionally doped conductive channels that can lead to leakage current or unstable dynamic resistance. If background electrons are trapped by buffer layer defects, they can reduce the on-resistance of the buffer layer, thereby affecting the dynamic electrical properties of the resulting GaN-on-silicon device.

[0064] Figure 1 A schematic diagram of the structure of a gallium nitride device provided in one embodiment of the present application. In order to solve the above problems, in some embodiments, combined with Figure 1 As shown, the present application provides a gallium nitride device 1, comprising a silicon substrate 10, an insulating layer 30, and a buffer layer 40 stacked along a first direction. The insulating layer 30 is located between the silicon substrate 10 and the buffer layer 40, separating the silicon substrate 10 and the buffer layer 40, and the insulating layer 30 and the buffer layer 40 are in contact with each other.

[0065] In this embodiment, an insulating layer 30 is introduced between the silicon substrate 10 and the buffer layer 40 to separate the silicon substrate 10 and the buffer layer 40, thereby providing electrical isolation and blocking the electrical coupling between the silicon substrate 10 and the buffer layer 40. This prevents background electrons from being injected into the buffer layer 40 and captured by defects in the buffer layer 40, thereby increasing the on-resistance of the buffer layer 40, increasing the withstand voltage of the buffer layer 40, reducing the off-state leakage current, and further improving the dynamic on-resistance stability of the gallium nitride device 1, thereby improving the dynamic electrical properties and reliability of the gallium nitride device 1.

[0066] In some embodiments, along the first direction, the thickness of the insulating layer 30 is 50 nm to 1500 nm. Exemplarily, the thickness of the insulating layer 30 is 50 nm, 300 nm, 650 nm, 800 nm, 1000 nm, 1250 nm, or 1500 nm.

[0067] When the thickness of the insulating layer 30 approaches 50 nm along the first direction, it is beneficial to reduce the size of the GaN device 1 along the first direction. When the thickness of the insulating layer 30 approaches 1500 nm along the first direction, it is beneficial to enhance the electrical isolation effect of the insulating layer 30, further improving the dynamic on-resistance stability of the GaN device 1.

[0068] In some embodiments, the thermal expansion coefficient of the insulating layer 30 is less than (per Kelvin); and / or, the difference between the thermal expansion coefficient of the insulating layer 30 and the thermal expansion coefficient of the silicon substrate 10 is less than .

[0069] In this embodiment, the thermal expansion coefficient of the insulating layer 30 is defined as less than Alternatively, the difference between the thermal expansion coefficient of the insulating layer 30 and the thermal expansion coefficient of the silicon substrate 10 is less than , so that the thermal expansion coefficient of the insulating layer 30 is closer to that of the silicon substrate 10 than that of AlN (the thermal expansion coefficient of the silicon substrate 10 is approximately ), which is more synchronized with the contraction behavior of silicon during cooling. In this embodiment, the insulating layer 30 acts as a "stress transition layer," gradually absorbing the sudden change in the thermal expansion coefficient between silicon and the buffer layer 40, thereby preventing stress from concentrating in the thermal expansion coefficient.

[0070] In some embodiments, the material of the insulating layer 30 includes one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

[0071] Among them, the thermal expansion coefficient of silicon nitride is , the thermal expansion coefficient of silicon oxide is , the thermal expansion coefficient of silicon oxynitride is usually between to The specific value depends on the chemical ratio of nitrogen (N) and oxygen (O) and the preparation process. In this embodiment, the thermal expansion coefficients of silicon nitride, silicon oxide and silicon oxynitride are all less than , the difference in thermal expansion coefficient with the silicon substrate 10 is less than When one or more of silicon nitride, silicon oxide, and silicon oxynitride are used to prepare the insulating layer 30, the insulating layer 30 can play an electrical isolation role and serve as a "stress transition layer" to alleviate the thermal mismatch between the silicon substrate 10 and the gallium nitride material.

[0072] Figure 2 A schematic diagram of the structure of a gallium nitride device provided in another embodiment of the present application. In some embodiments, combined with Figure 2 As shown, the insulating layer 30 includes a first portion 301 and a second portion 302, which are adjacent to each other in the second direction. Along the first direction, the thickness of the first portion 301 is smaller than the thickness of the second portion 302, and the second direction is perpendicular to the first direction.

[0073] In this embodiment, the first portion 301 and the second portion 302 contact in the second direction, so that the first portion 301 and the second portion 302 together form a continuous insulating layer 30, thereby separating the silicon substrate 10 from the buffer layer 40. Along the first direction, the thickness of the first portion 301 is less than the thickness of the second portion 302, forming an alternating thin and thick structure. This alternating thin and thick structure is achieved by the secondary epitaxial growth process of the insulating layer 30. The secondary epitaxial growth of the insulating layer 30 ensures the crystal continuity of the insulating layer 30, reduces defects in the insulating layer 30, and forms a continuous insulating layer 30, thereby stably separating the silicon substrate 10 from the buffer layer 40.

[0074] In some embodiments, combined Figure 2 As shown, there are multiple first parts 301 and multiple second parts 302. Along the second direction, the multiple first parts 301 and the multiple second parts 302 are alternately arranged.

[0075] In this embodiment, the insulating layer 30 includes a first portion 301 and a second portion 302 arranged adjacent to each other in the second direction. Along the first direction, the thickness of the first portion 301 is less than that of the second portion 302. Multiple first portions 301 and second portions 302 can be present, alternating with each other to form a periodic alternating structure. This periodic alternating structure is achieved by a secondary epitaxial growth process for the insulating layer 30. A first epitaxial growth process begins by growing a uniformly thin insulating layer. Then, through photolithography, an opening is created in the area where the thickness is to be increased (i.e., the second portion 302). A mask is retained in the area of ​​the first portion 301, forming the first portion 301 of the insulating layer 30. A second epitaxial growth process selectively grows a thicker insulating layer in the opening area, forming the second portion 302 of the insulating layer 30. This secondary epitaxial growth of the insulating layer 30 ensures the crystal continuity of the insulating layer 30, reduces defects in the insulating layer 30, and forms a coherent insulating layer 30, thereby stably separating the silicon substrate 10 from the buffer layer 40.

[0076] In some embodiments, combined Figure 2 As shown, the plurality of first portions 301 and the plurality of second portions 302 together constitute the first surface 303 of the insulating layer 30 . The first surface 303 is in contact with the buffer layer 40 . The first surface 303 has first protrusions 304 and first recesses 305 alternately arranged along the second direction.

[0077] In this embodiment, the periodic alternating structure formed by the alternating arrangement of multiple first portions 301 and multiple second portions 302 results in the first surface 303 of the insulating layer 30 having first protrusions 304 and first recesses 305 arranged alternately along the second direction. The first protrusions 304 and first recesses 305 are achieved by the secondary epitaxial growth process of the insulating layer 30. The secondary epitaxial growth of the insulating layer 30 ensures the crystal continuity of the insulating layer 30, thereby stably separating the silicon substrate 10 and the buffer layer 40.

[0078] In some embodiments, along the first direction, the thickness difference between the first portion 301 and the second portion 302 ranges from 100 nm to 1000 nm. Figure 2 As shown, along the first direction, the thickness difference between the first portion 301 and the second portion 302 is h, and the value of h can be 100 nm, 300 nm, 500 nm, 700 nm, 900 nm or 1000 nm.

[0079] When the thickness difference between the first portion 301 and the second portion 302 along the first direction approaches 100 nm, it is beneficial to reduce the size of the GaN device 1 along the first direction. When the thickness difference between the first portion 301 and the second portion 302 along the first direction approaches 1000 nm, it is beneficial to increase the thickness of the buffer layer 40, thereby further dispersing stress, reducing cracks, and improving the withstand voltage of the GaN device 1 along the first direction.

[0080] In some embodiments, along the second direction, the length of each first portion 301 ranges from 200 nm to 10,000 nm. Figure 2 As shown, along the second direction, the length of a first portion 301 is y, and the value of y can be 200 nm, 1500 nm, 2800 nm, 4000 nm, 5100 nm, 6300 nm, 7500 nm, 8800 nm or 10000 nm.

[0081] When the length of the first portion 301 along the second direction approaches 200 nm, epitaxial growth of GaN is facilitated, thereby improving the quality of the GaN epitaxially grown crystal. When the length of the first portion 301 along the second direction approaches 10,000 nm, the fabrication process is simplified, facilitating fabrication of the GaN device 1.

[0082] In some embodiments, along the second direction, the length of the plurality of second portions 302 accounts for 30% to 70% of the length of the insulating layer 30. For example, Figure 2As shown, along the second direction, the length of one second portion 302 is f, and the length of the plurality of second portions 302 is f×m, where m represents the number of second portions 302. Let K be the ratio of the length of the plurality of second portions 302 to the length of the insulating layer 30, then K=(f×m) / r, where r represents the length of the insulating layer 30. The value of K can be 30%, 40%, 50%, 60%, or 70%.

[0083] When the length of the plurality of second portions 302 along the second direction approaches 30% of the length of the insulating layer 30, the fabrication process is simplified, facilitating fabrication of the gallium nitride device 1. When the length of the plurality of second portions 302 along the second direction approaches 70% of the length of the insulating layer 30, gallium nitride epitaxial growth is facilitated, improving the quality of the gallium nitride epitaxially grown crystal.

[0084] In the above embodiment, the specific values ​​of the thickness difference between the first portion 301 and the second portion 302 in the first direction, as well as the length of each first portion 301 and the length of the plurality of second portions 302 in the second direction, need to be set according to the actual requirements of the gallium nitride device 1 and the manufacturing process requirements, and are not specifically limited in this application.

[0085] In some embodiments, combined Figure 2 As shown, the buffer layer 40 includes a first buffer layer 400 and a second buffer layer 410 stacked along a first direction, and the second buffer layer 410 is located between the first buffer layer 400 and the insulating layer 30. The first buffer layer 400 includes a high resistance buffer layer, and the second buffer layer 410 includes a nitride buffer layer.

[0086] In this embodiment, the second buffer layer 410 is located between the first buffer layer 400 and the insulating layer 30, and the second buffer layer 410 is in contact with the insulating layer 30. The second buffer layer 410 includes a nitride buffer layer, and the material of the nitride buffer layer includes GaN and / or AlGaN. The first buffer layer 400 includes a high-resistance buffer layer, and the material of the high-resistance buffer layer includes iron (Fe) / carbon (C) doped GaN and / or, high Al content AlGaN, and the resistivity of the high-resistance buffer layer is greater than Ω·cm.

[0087] In this embodiment, the second buffer layer 410 serves as a high-quality epitaxial template, improving the quality of the subsequent epitaxially grown crystal, while also providing a low-resistance lateral path for lateral current expansion. The first buffer layer 400 utilizes its high resistance to expand the depletion region laterally, reducing the longitudinal electric field strength while blocking leakage paths caused by substrate defects, thereby improving the vertical withstand voltage of the GaN device 1.

[0088] In some embodiments, along the first direction, the thickness of the second buffer layer 410 ranges from 300 nm to 1500 nm. For example, the thickness of the second buffer layer 410 is 300 nm, 600 nm, 900 nm, 1200 nm, or 1500 nm.

[0089] When the thickness of the second buffer layer 410 along the first direction approaches 300 nm, it is beneficial to reduce the size of the gallium nitride device 1 along the first direction. When the thickness of the second buffer layer 410 along the first direction approaches 1500 nm, it can further disperse stress, reduce cracks, and improve the withstand voltage level of the gallium nitride device 1 along the first direction.

[0090] In some embodiments, along the first direction, the thickness of the first buffer layer 400 ranges from 1000 nm to 5000 nm. For example, the thickness of the first buffer layer 400 is 1000 nm, 2000 nm, 3000 nm, 4000 nm, or 5000 nm.

[0091] When the thickness of the first buffer layer 400 along the first direction approaches 1000 nm, it is beneficial to reduce the size of the gallium nitride device 1 along the first direction. When the thickness of the first buffer layer 400 along the first direction approaches 5000 nm, it can further disperse stress, reduce cracks, and improve the withstand voltage of the gallium nitride device 1 along the first direction.

[0092] In the above embodiment, the thickness of the first buffer layer 400 and the second buffer layer 410 in the first direction needs to be set according to the actual requirements of the gallium nitride device 1 and the manufacturing process requirements, and is not specifically limited in this application.

[0093] In some embodiments, combined Figure 2 As shown, the second buffer layer 410 includes a third portion 411 and a fourth portion 412 arranged along the first direction, the third portion 411 is located between the fourth portion 412 and the first portion 301 , and the third portion 411 and the second portion 302 are arranged in the second direction.

[0094] In this embodiment, the third portion 411 and the fourth portion 412 are in contact with each other in the second direction, so that the third portion 411 and the fourth portion 412 together constitute a continuous second buffer layer 410 , thereby reducing internal defects of the second buffer layer 410 .

[0095] In some embodiments, combined Figure 2As shown, there are multiple third portions 411, and the multiple third portions 411 are arranged at intervals along the second direction. Along the first direction, one third portion 411 is in contact with one first portion 301. Along the second direction, the multiple third portions 411 and the multiple second portions 302 are arranged alternately.

[0096] In this embodiment, the second buffer layer 410 includes a third portion 411 and a fourth portion 412 arranged along the first direction. The third portion 411 may be multiple, and the multiple third portions 411 are spaced apart along the second direction to form a periodic structure. This periodic structure is achieved by the secondary epitaxial growth process of the second buffer layer 410. The secondary epitaxial growth of the second buffer layer 410 ensures the crystal continuity of the second buffer layer 410 and improves the crystal quality of the second buffer layer 410.

[0097] In some embodiments, combined Figure 2 As shown, the fourth portion 412 and the plurality of third portions 411 together constitute the second surface 413 of the second buffer layer 410 . The second surface 413 is in contact with the insulating layer 30 , and has second protrusions 414 and second recesses 415 alternately arranged along the second direction.

[0098] In this embodiment, the periodic structure formed by the multiple third portions 411 arranged at intervals along the second direction results in the second surface 413 of the second buffer layer 410 having second protrusions 414 and second depressions 415 arranged alternately along the second direction. The second protrusions 414 and second depressions 415 are achieved by the secondary epitaxial growth process of the second buffer layer 410. The secondary epitaxial growth of the second buffer layer 410 ensures the crystal continuity of the second buffer layer 410 and improves the crystal quality of the second buffer layer 410.

[0099] In the above embodiment, the second surface 413 of the second buffer layer 410 is in contact with the first surface 303 of the insulating layer 30 , the first protrusion 304 is in contact with the second recess 415 , and the first recess 305 is in contact with the second protrusion 414 .

[0100] Figure 3 A schematic diagram of the structure of a gallium nitride device provided in another embodiment of the present application. In some embodiments, combined with Figure 3 As shown, the gallium nitride device 1 further includes a nucleation layer 20. Along a first direction, the nucleation layer 20 is located between the silicon substrate 10 and the insulating layer 30. The insulating layer 30 is located between the nucleation layer 20 and the buffer layer 40. The insulating layer 30 separates the nucleation layer 20 and the buffer layer 40. The material of the nucleation layer 20 includes AlN, or AlN and GaN.

[0101] In this embodiment, a nucleation layer 20 is provided between the silicon substrate 10 and the insulating layer 30 to alleviate the lattice mismatch and thermal stress between the silicon substrate 10 and GaN. The lattice constants of silicon and GaN are quite different, and direct growth will result in high density dislocations (greater than ). The nucleation layer 20 can partially compensate for the lattice mismatch and reduce the dislocation density by providing an intermediate transition layer. The thermal expansion coefficients of silicon and GaN are significantly different. During the cooling process after growth, the nucleation layer 20 absorbs thermal stress through elastic or plastic deformation, which can reduce cracks or film peeling caused by thermal mismatch. In addition, the nucleation layer 20 forms nanoscale crystal nuclei (such as AlN island structures) on the silicon surface, and these nanoscale crystal nuclei are merged into a continuous mask by controlling the growth conditions (such as temperature and pressure). During lateral epitaxial overgrowth, the design of the nucleation layer 20 (such as the AlN mask) can guide the lateral growth of GaN, further reduce threading dislocations, and improve crystal quality.

[0102] Figure 4 A schematic diagram of the structure of a gallium nitride device provided in another embodiment of the present application. In some embodiments, combined with Figure 4 As shown, the gallium nitride device 1 further includes a channel layer 500 , a barrier layer 510 and a cap layer 520 stacked along a first direction. Along the first direction, the buffer layer 40 is located between the channel layer 500 and the insulating layer 30 , and the barrier layer 510 is located between the channel layer 500 and the cap layer 520 .

[0103] In this embodiment, combined Figure 4 As shown, the channel layer 500, barrier layer 510, and cap layer 520 together constitute the device layer 50 of the GaN device 1 and determine its performance. The channel layer 500 is the primary path for current flow, allowing electrons to move rapidly within the channel layer 500, enabling high-speed electron transport. The barrier layer 510 induces a two-dimensional electron gas (2DEG) within the channel layer 500 through a polarization effect. The barrier layer 510 also provides a potential barrier, preventing electrons from leaking from the channel layer 500 to other areas. The cap layer 520 protects the structure of the GaN device 1, improves surface properties, and adjusts electrical performance.

[0104] In some embodiments, the material of the channel layer 500 includes GaN, the material of the barrier layer 510 includes AlGaN, and the material of the cap layer 520 includes one or a combination of GaN, SiN, and p-type GaN (p-GaN).

[0105] In some embodiments, along the first direction, the thickness of the channel layer 500 ranges from 50 nm to 500 nm. For example, the thickness of the channel layer 500 is 50 nm, 150 nm, 275 nm, 375 nm, or 500 nm.

[0106] In some embodiments, along the first direction, the thickness of the barrier layer 510 ranges from 10 nm to 30 nm. For example, the thickness of the barrier layer 510 is 10 nm, 20 nm, or 30 nm.

[0107] In some embodiments, the cap layer 520 is made of GaN and / or SiN, and has a thickness ranging from 1 nm to 5 nm along the first direction. Exemplarily, the cap layer 520 has a thickness of 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.

[0108] In some embodiments, the cap layer 520 is made of p-GaN, and along the first direction, the thickness of the cap layer 520 ranges from 50 nm to 100 nm. For example, the thickness of the cap layer 520 is 50 nm, 67 nm, 75 nm, 87 nm, or 100 nm.

[0109] In some embodiments, the present application provides a method for preparing a gallium nitride device, which is used to prepare the gallium nitride device described in the above embodiments. Figure 5 A schematic diagram of a process for preparing a gallium nitride device according to an embodiment of the present application. Figure 5 As shown, the method for preparing a gallium nitride device includes:

[0110] S51, providing a silicon substrate.

[0111] In this step, a silicon substrate is provided such as Figure 6 As shown, Figure 6 A schematic structural diagram of a silicon substrate provided in one embodiment of the present application.

[0112] S52, forming an insulating layer and a buffer layer, wherein the silicon substrate, the insulating layer and the buffer layer are stacked along a first direction, the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer separates the silicon substrate and the buffer layer, the insulating layer and the buffer layer are in contact and connected, the insulating layer includes a first part and a second part, the first part and the second part are adjacently arranged in a second direction, along the first direction, the thickness of the first part is less than the thickness of the second part, and the second direction is perpendicular to the first direction.

[0113] In this embodiment, the gallium nitride device 1 described in the above embodiment can be formed by forming a stacked insulating layer 30 and a buffer layer 40 on a provided silicon substrate 10 along a first direction. Therefore, the beneficial effects achievable by the method for preparing the gallium nitride device provided in this embodiment can be referred to the beneficial effects of the gallium nitride device 1 described above, and will not be further described here.

[0114] In some embodiments, as Figure 7 As shown, Figure 7A schematic diagram of a process for forming an insulating layer and a buffer layer according to an embodiment of the present application is provided. Step S52, forming the insulating layer and the buffer layer, includes:

[0115] S521 , forming an insulating dielectric layer, wherein the silicon substrate and the insulating dielectric layer are stacked along a first direction.

[0116] Figure 8 A schematic diagram of the structure of the first part of forming an insulating layer on a silicon substrate according to an embodiment of the present application. Figure 8 As shown, a layer of silicon nitride, silicon oxide or silicon oxynitride can be deposited on the silicon substrate 10 by PECVD (Plasma Enhance Chemical Vapor Deposition) process with a thickness ranging from 50nm to 2000nm to form an insulating dielectric layer 306, thereby realizing the insulating layer 30 in the above embodiment (see Figures 1 to 4 The first epitaxial growth of the middle insulating layer 30).

[0117] In one example, combining Figure 8 As shown, a 250 nm thick silicon oxide film can be grown on the silicon substrate 10 by a PECVD process to form an insulating dielectric layer 306 .

[0118] In some embodiments, the gallium nitride device 1 includes a nucleation layer 20. The specific location of the nucleation layer 20 in the gallium nitride device 1 is described in the above embodiments. To form the gallium nitride device 1 including the nucleation layer 20, before forming the insulating dielectric layer, in step S21, the gallium nitride device manufacturing method further includes: forming the nucleation layer, wherein the silicon substrate, the nucleation layer, and the insulating dielectric layer are stacked along a first direction, with the nucleation layer located between the silicon substrate and the insulating dielectric layer.

[0119] Figure 9 A schematic diagram of a structure for forming a nucleation layer on a silicon substrate according to an embodiment of the present application. Figure 9 As shown, a nitride film (such as an aluminum nitride film, or an aluminum nitride and gallium nitride film) can be deposited on a silicon substrate 10 using an MOCVD (Metal-Organic Chemical Vapor Deposition) process to form a nucleation layer 20. The deposition temperature of the nucleation layer 20 ranges from 800°C to 1200°C. The temperature is then lowered to room temperature to obtain an epitaxial wafer having the silicon substrate 10 and the nucleation layer 20 stacked along a first direction.

[0120] In one example, combining Figure 9As shown, a 200nm AlN film and a 100nm GaN film can be grown on a silicon substrate 10 by an MOCVD process after heating to 1150°C to form a nucleation layer 20, and then cooled to room temperature to obtain an epitaxial wafer having a silicon substrate 10 and a nucleation layer 20 stacked along a first direction.

[0121] Figure 10 A schematic structural diagram of the first part of forming an insulating layer on a nucleation layer according to an embodiment of the present application. Figure 10 As shown, in this embodiment, it is possible to Figure 9 A layer of silicon nitride, silicon oxide or silicon oxynitride is deposited on the epitaxial wafer by a PECVD process to form an insulating dielectric layer 306 .

[0122] In one example, combining Figure 10 As shown, this can be done by Figure 9 A first silicon nitride layer with a thickness of 300 nm is deposited on the epitaxial wafer by a PECVD process to form an insulating dielectric layer 306 .

[0123] S522 , removing a portion of the insulating dielectric layer to form a first hole, with the remaining insulating dielectric layer including the first portion of the insulating layer.

[0124] In this step, combine Figure 8 and Figure 10 As shown, a portion of the insulating dielectric layer 306 can be removed by photolithography and etching to expose the surface of the silicon substrate 10 or the surface of the nucleation layer 20 below the insulating dielectric layer 306. Figure 8 As shown, when the nucleation layer 20 is not included, after removing part of the insulating dielectric layer 306, the surface of the silicon substrate 10 below the insulating dielectric layer 306 is exposed; Figure 10 As shown, when the nucleation layer 20 is included, a portion of the insulating dielectric layer 306 is removed to expose the surface of the nucleation layer 20 below the insulating dielectric layer 306. Alternatively, CMP (Chemical Mechanical Polishing) can be performed on the insulating dielectric layer 306 to remove a portion of the insulating dielectric until the underlying silicon substrate 10 or the nucleation layer 20 is exposed, thereby forming the first hole 307. The remaining insulating dielectric layer 306 includes the first portion 301 of the insulating layer 30, thereby forming a periodic pattern mask layer.

[0125] In the periodic pattern mask layer, the period length of the pattern mask (i.e., the length of each first portion 301 in the above embodiment) ranges from 200 nm to 10,000 nm, and the pattern opening ratio ranges from 30% to 70% (i.e., the ratio K of the length of the plurality of second portions 302 to the length of the insulating layer 30 in the above embodiment). After forming the periodic pattern mask layer, the epitaxial wafer with the periodic pattern mask layer is cleaned and dried for later use.

[0126] In one example, the gallium nitride device 1 does not include the nucleation layer 20. Figure 8 As shown, a portion of the insulating dielectric layer 306 is etched to expose the surface of the silicon substrate 10. The period of the etched pattern (i.e., the length of each first portion 301 in the above embodiment) is 800 nm, and the aperture ratio of the pattern mask (i.e., the length of the plurality of first holes 307 along the second direction as a percentage of the total length of the periodic pattern mask layer in the above embodiment) is 50%, thereby forming a periodic pattern mask layer. Subsequently, the epitaxial wafer with the pattern mask is cleaned and dried.

[0127] In another example, the gallium nitride device 1 includes a nucleation layer 20. Figure 10 As shown, a portion of the insulating dielectric layer 306 can be removed through photolithography and etching to expose the underlying nucleation layer 20, thereby forming a periodic patterned mask layer. The period length of the patterned mask (i.e., the length of each first portion 301 in the above embodiment) is 1000 nm, and the aperture ratio of the patterned mask (i.e., the ratio K of the length of the plurality of second portions 302 to the length of the insulating layer 30 in the above embodiment) is 60%. The epitaxial wafer with the patterned mask is then cleaned and dried.

[0128] S523 , forming a second portion of the insulating layer in the first hole.

[0129] S524, forming a buffer layer.

[0130] In some embodiments, Figure 11 A schematic diagram of the process of forming the second part of the insulating layer in the first hole according to an embodiment of the present application. Figure 11 As shown, step S523, forming a second portion of the insulating layer in the first hole, includes:

[0131] S5231, forming a third portion of the second buffer layer, wherein the third portion and the first portion are stacked along a first direction, the first portion is located between the third portion and the silicon substrate, and a second hole facing the first hole is provided between adjacent third portions.

[0132] Figure 12 A schematic diagram of the structure for forming a first nitride layer and a second nitride layer provided in one embodiment of the present application. Figure 13 A schematic diagram of the structure of the third part of forming the second buffer layer provided in one embodiment of the present application. Figure 8 、 Figure 12 and Figure 13As shown, in some embodiments, when the nucleation layer 20 is not included, step S5231, forming the third part of the second buffer layer, includes: forming a first nitride layer 416 in the first hole 307, the material of the first nitride layer 416 includes aluminum nitride; forming a second nitride layer 417, the second nitride layer 417 covering the first nitride layer 416 and the first part 301, the material of the second nitride layer 417 includes gallium nitride; removing part of the second nitride layer 417 and the first nitride layer 416 facing the first hole 307 to form a second hole 418 facing the first hole 307 in the second nitride layer 417, and the remaining second nitride layer 417 includes the third part 411 of the second buffer layer 410.

[0133] In this embodiment, combined Figure 12 As shown, the MOCVD process can be used to Figure 8 The epitaxial wafer with the periodic pattern mask layer shown is first grown with a first nitride layer 416 (the first nitride layer 416 includes an aluminum nitride film), and then grown with a second nitride layer 417 (the second nitride layer 417 includes a gallium nitride film). The growth temperature of the first nitride layer 416 and the second nitride layer 417 is 800°C to 1200°C. In the first direction, the total thickness of the first nitride layer 416 and the second nitride layer 417 is 300nm to 1500nm, and the second nitride layer 417 is merged to form a continuous film above the periodic pattern mask layer, so that the second nitride layer 417 covers both the first nitride layer 416 and the first portion 301, thereby realizing the second buffer layer 410 in the above-mentioned embodiment (refer to Figures 2 to 4 The first epitaxial growth of the second buffer layer 410 in FIG.

[0134] Further, combined with Figure 13 As shown, it can be removed by photolithography and etching Figure 12 The first nitride layer 416 in the window area (i.e., within the first hole 307) of the periodic pattern mask layer in the epitaxial wafer and the portion of the second nitride layer 417 facing the first hole 307 are shown, thereby exposing the silicon substrate 10 below the insulating dielectric layer 306. At this time, the second nitride layer 417 forms a second hole 418 facing the first hole 307, and the remaining second nitride layer 417 forms the third portion 411 of the second buffer layer 410.

[0135] In one example, if Figure 12 As shown, the temperature is raised to 1100℃ and the MOCVD process is used. Figure 8 A 200nm thick AlN layer is sequentially grown on the epitaxial wafer with the periodic pattern mask layer to form a first nitride layer 416, and a 500nm thick GaN layer is then grown to form a second nitride layer 417. The GaN layer is then merged onto the first nitride layer 416 and the first portion 301 by lateral epitaxy to form a continuous thin film. Figure 13 As shown, the Figure 12 In the epitaxial wafer shown, the first nitride layer 416 grown in the first hole 307 faces a portion of the second nitride layer 417 of the first hole 307, exposing the silicon substrate 10, and only retaining a portion of the second nitride layer 417 above the first portion 301 to form a third portion 411 of the second buffer layer 410.

[0136] Figure 14 A schematic structural diagram of forming a third nitride layer according to an embodiment of the present application. Figure 15 A schematic structural diagram of the third portion of the second buffer layer provided in another embodiment of the present application. Figure 10 、 Figure 14 and Figure 15 As shown, in some embodiments, when the nucleation layer 20 is included, step S5231, forming the third part of the second buffer layer, includes: forming a third nitride layer 420 in the first hole 307, the material of the third nitride layer 420 includes gallium nitride, and the third nitride layer 420 covers the first part 301; removing the portion of the third nitride layer 420 located in the first hole 307 and facing the first hole 307 to form a second hole 418 facing the first hole 307, and the remaining third nitride layer 420 includes the third part 411 of the second buffer layer 410.

[0137] In this embodiment, combined Figure 14 As shown, the MOCVD process can be used to Figure 10 A third nitride layer 420 is grown on the epitaxial wafer with the periodic pattern mask layer shown. The growth temperature of the third nitride layer 420 is 800°C to 1200°C. In the first direction, the third nitride layer 420 is 300nm to 1500nm, and the third nitride layer 420 is merged to form a continuous film above the periodic pattern mask layer, so that the third nitride layer 420 covers the first portion 301, thereby achieving the second buffer layer 410 in the above embodiment (refer to Figures 2 to 4 The first epitaxial growth of the second buffer layer 410 in FIG.

[0138] Further, combined with Figure 15 As shown, it can be removed by photolithography and etching Figure 14 The epitaxial wafer shown in the figure shows a portion of the third nitride layer 420 in the window region (located within and facing the first hole 307) in the periodic pattern mask layer, exposing the nucleation layer 20 beneath the insulating dielectric layer 306. At this point, a second hole 418 is formed facing the first hole 307, and the remaining third nitride layer 420 forms the third portion 411 of the second buffer layer 410.

[0139] In one example, if Figure 14As shown, the temperature is raised to 1000℃ and the MOCVD process is used. Figure 8 A 600 nm GaN film is grown on the epitaxial wafer with the periodic pattern mask layer shown to form a third nitride layer 420. The third nitride layer 420 is merged to form a continuous film on the first portion 301. Figure 15 As shown, the Figure 14 The portion of the third nitride layer 420 grown in and facing the first hole 307 exposes the nucleation layer 20 , and only the portion of the third nitride layer 420 above the first portion 301 is retained to form the third portion 411 of the second buffer layer 410 .

[0140] S5232, filling the insulating material so that the insulating material covers the first hole, the second hole and the third portion.

[0141] Figure 16 A schematic structural diagram of the filling insulating material provided in one embodiment of the present application. Figure 17 A schematic diagram of the structure of the filling insulating material provided in another embodiment of the present application. Figure 16 and Figure 17 As shown, in this step, an insulating material 419 (such as silicon nitride, silicon oxide or silicon oxynitride) can be deposited in the epitaxial wafer formed in step S5231 by a PECVD process to fill the insulating material 419. The deposition thickness of the insulating material 419 is 50nm to 2000nm. The insulating material 419 covers the first hole 307, the second hole 418 and the third portion 411, forming a continuous mask in the second direction to realize the insulating layer 30 (refer to FIG. Figures 1 to 4 The second epitaxial growth of the insulating layer 30) in the embodiment of the present invention is performed.

[0142] In one example, the second hole 418 is formed by removing a portion of the second nitride layer 417. Figure 16 As shown, the PECVD process can be used to Figure 13 Silicon oxide is deposited on the epitaxial wafer to a thickness of 800 nm, connecting the silicon oxide with the remaining insulating dielectric layer 306 in the second direction to form a transversely penetrating thin film. The resulting thin film covers the first hole 307, the second hole 418, and the remaining second nitride layer 417, thereby covering the first hole 307, the second hole 418, and the third portion 411.

[0143] In another example, the second hole 418 is formed by removing a portion of the third nitride layer 420. Figure 17 As shown, the PECVD process can be used to Figure 15Silicon nitride is deposited on the epitaxial wafer to a thickness of 600 nm, connecting the silicon nitride with the remaining insulating dielectric layer 306 in the second direction to form a transversely penetrating thin film. The resulting thin film covers the first hole 307, the second hole 418, and the remaining third nitride layer 420, thereby covering the first hole 307, the second hole 418, and the third portion 411.

[0144] S5233, remove part of the insulating material to expose the third portion.

[0145] Figure 18 A schematic diagram of a structure for forming an insulating layer provided in one embodiment of the present application. Figure 19 This is a schematic diagram of the structure of forming an insulating layer provided in another embodiment of the present application. In this step, Figure 18 and Figure 19 As shown, insulating material 419 can be partially etched using photolithography and etching methods, or CMP can be performed on insulating material 419 to remove a portion of insulating material 419, thereby exposing third portion 411. After exposing third portion 411, the epitaxial wafer with exposed third portion 411 is cleaned and dried for later use. At this point, the remaining insulating material 419 includes insulating material 419 located within first hole 307 and second hole 418, forming second portion 302. First portion 301 and second portion 302 together constitute insulating layer 30, achieving the formation of insulating layer 30 through secondary epitaxial growth.

[0146] In one example, the third portion 411 is formed by the remaining second nitride layer 417, as shown in FIG. Figure 18 As shown, the insulating material 419 can be subjected to CMP to remove the remaining insulating material 419 above the second nitride layer 417 , thereby exposing the third portion 411 , and then the obtained epitaxial wafer is cleaned and dried.

[0147] In another example, the third portion 411 is formed by the remaining third nitride layer 420, as shown in FIG. Figure 19 As shown, the insulating material 419 can be subjected to CMP to remove the remaining insulating material 419 above the third nitride layer 420 , thereby exposing the third portion 411 , and then the obtained epitaxial wafer is cleaned and dried.

[0148] Figure 20 A schematic diagram of a process for forming a buffer layer according to an embodiment of the present application is provided. In some embodiments, as Figure 20 As shown, S524, forming a buffer layer includes:

[0149] S5241 , forming a fourth portion of the second buffer layer, wherein the fourth portion covers the third portion and the second portion.

[0150] Figure 21A schematic structural diagram of the fourth part for forming the second buffer layer provided in one embodiment of the present application. Figure 22 This is a schematic structural diagram of the fourth part of forming the second buffer layer provided in another embodiment of the present application. Figure 21 and Figure 22 As shown, a fourth nitride layer can be further grown on the epitaxial wafer formed in step S23, i.e., the epitaxial wafer with the third portion 411 exposed, through the MOCVD process. The growth temperature of the fourth nitride layer is in the range of 800°C to 1200°C, the thickness of the fourth nitride layer is in the range of 300nm to 1500nm, and the material of the fourth nitride layer includes gallium nitride. The fourth nitride layer is combined to form a continuous thin film above the third portion 411 and the second portion 302, forming the fourth portion 412 of the second buffer layer 410, thereby achieving a second epitaxial growth of the second buffer layer 410. The fourth portion 412 covers the third portion 411 and the second portion 302. The fourth portion 412 and the third portion 411 together constitute the second buffer layer 410, thereby achieving the second epitaxial growth of the second buffer layer 410.

[0151] In one example, the third portion 411 is formed by the remaining second nitride layer 417, as shown in FIG. Figure 21 As shown, the temperature can be raised to 1000℃ and the MOCVD process can be used to Figure 16 A GaN film is continuously grown on the epitaxial wafer. The thickness of the GaN film is 500 nm, so that the GaN film is merged over the third portion 411 and the second portion 302 , thereby forming the fourth portion 412 of the second buffer layer 410 .

[0152] In another example, the third portion 411 is formed by the remaining third nitride layer 420, as shown in FIG. Figure 22 As shown, the temperature can be raised to 1050℃ and the MOCVD process can be used to Figure 17 A GaN film is continuously grown on the epitaxial wafer. The thickness of the GaN film is 800 nm, so that the GaN film is merged over the third portion 411 and the second portion 302 , thereby forming the fourth portion 412 of the second buffer layer 410 .

[0153] S5242 , forming a first buffer layer, wherein the second buffer layer is located between the first buffer layer and the insulating layer.

[0154] Figure 23 A schematic structural diagram of forming a first buffer layer according to an embodiment of the present application. Figure 24 This is a schematic diagram of the structure of forming the first buffer layer provided in another embodiment of the present application. Figure 23 and Figure 24As shown, a high-resistance buffer layer can be continuously grown on the second buffer layer 410 to form a first buffer layer 400. The temperature range for forming the first buffer layer 400 is 800° C. to 1200° C., the thickness range of the first buffer layer 400 is 1000 nm to 5000 nm, and the material of the first buffer layer 400 includes Fe / C-doped GaN and / or high-Al content AlGaN.

[0155] In one example, combining Figure 23 As shown, when the reaction chamber temperature is reduced to 900℃, Figure 21 A 50 nm AlN layer is further grown on the surface of the epitaxial wafer shown, and then the temperature is raised to 1020° C. to grow a 2000 nm AlGaN layer and a 1000 nm carbon-doped GaN layer to form a 3050 nm high-resistance buffer layer, thereby forming a first buffer layer 400 .

[0156] In another example, combining Figure 24 As shown, when the reaction chamber temperature is 1000℃, Figure 22 An AlN layer, an AlGaN layer and a carbon-doped GaN layer are sequentially grown on the surface of the epitaxial wafer to form a 2500 nm high-resistance buffer layer, thereby forming a first buffer layer 400 .

[0157] After forming the buffer layer in step S524, the gallium nitride device fabrication method further includes: forming a channel layer; forming a barrier layer; and forming a cap layer. In the first direction, the buffer layer is located between the channel layer and the insulating layer, and the barrier layer is located between the channel layer and the cap layer.

[0158] Figure 25 A schematic diagram of a structure for forming a channel layer provided in one embodiment of the present application. Figure 26 A schematic diagram of the structure for forming a barrier layer and a cap layer provided in one embodiment of the present application. Figure 27 A schematic diagram of a structure for forming a channel layer is provided for another embodiment of the present application. In this embodiment, Figure 4 ,as well as Figures 25 to 27As shown, a channel layer 500 can be further grown on the epitaxial wafer formed in step S24, that is, the epitaxial wafer with the buffer layer 40 formed thereon, wherein the material of the channel layer 500 includes GaN, the growth temperature range of the channel layer 500 is 1000°C to 1200°C, and the thickness of the channel layer 500 along the first direction is 50nm to 500nm; then, a barrier layer 510 is grown on the channel layer 500, wherein the material of the barrier layer 510 includes AlGaN, the growth temperature range of the barrier layer 510 is 1000°C to 1200°C, and the thickness of the barrier layer 510 along the first direction is 10nm to 30nm; and then, a cap layer 520 is grown on the barrier layer 510, wherein the growth temperature range of the cap layer 520 is 900°C to 1200°C, and along the first direction, the cap layer 520 can be a GaN layer / SiN layer with a thickness of 1nm to 5nm, or a p-GaN layer with a thickness of 50nm to 100nm. In this embodiment, the channel layer 500 , the barrier layer 510 and the cap layer 520 together constitute the device layer 50 of the gallium nitride device 1 .

[0159] In one example, if Figure 25 As shown, it can be Figure 23 A GaN layer is grown on the first buffer layer 400 of the epitaxial wafer shown in FIG. 4 to form a channel layer 500. The growth temperature of the channel layer 500 is 1080° C., and the thickness of the channel layer 500 is 200 nm. Figure 26 As shown, then Figure 25 The AlGaN layer is further grown on the channel layer 500 of the epitaxial wafer to form a barrier layer 510. The growth temperature of the barrier layer 510 is 1060°C and the thickness of the barrier layer 510 is 20nm. Figure 26 As shown, a GaN layer is continuously grown on the barrier layer 510 to form a cap layer 520. The growth temperature of the cap layer 520 is 1060°C, and the thickness of the cap layer 520 is 3 nm.

[0160] In yet another example, Figure 27 As shown, it can be Figure 24 The GaN layer is grown on the first buffer layer 400 of the epitaxial wafer to form a channel layer 500. The growth temperature of the channel layer 500 is 1100°C and the thickness of the channel layer 500 is 150nm. Figure 27 The AlGaN layer is continuously grown on the channel layer 500 of the epitaxial wafer to form a barrier layer 510, as shown in FIG. Figure 4 As shown. The growth temperature of the barrier layer 510 is 1100°C and the thickness of the barrier layer 510 is 20nm. Figure 4 As shown, a p-GaN layer is continuously grown on the barrier layer 510 to form a cap layer 520 . The growth temperature of the cap layer 520 is 980° C., and the thickness of the cap layer 520 is 100 nm.

[0161] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A gallium nitride device, characterized in that: include: A silicon substrate, an insulating layer, and a buffer layer stacked along a first direction, wherein the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer is a continuous structure, the insulating layer separates the silicon substrate and the buffer layer, and the insulating layer and the buffer layer are in contact and connected; The insulating layer includes a first portion and a second portion, wherein the first portion and the second portion are adjacently arranged in a second direction; Along the first direction, a thickness of the first portion is smaller than a thickness of the second portion, and the second direction is perpendicular to the first direction.

2. The gallium nitride device according to claim 1, characterized in that The plurality of first portions and the plurality of second portions together constitute a first surface of the insulating layer. The first surface is in contact with the buffer layer and has first protrusions and first recesses alternately arranged along the second direction.

3. The gallium nitride device according to claim 1 or 2, characterized in that: The number of the first parts is plural, and the number of the second parts is plural; Along the second direction, a plurality of the first portions and a plurality of the second portions are alternately arranged.

4. The gallium nitride device according to claim 3, characterized in that Along the first direction, a thickness difference between the first portion and the second portion ranges from 100 nm to 1000 nm; and / or, Along the second direction, the length of each first portion is 200 nm to 10000 nm; and / or, Along the second direction, the length of the plurality of second portions accounts for 30% to 70% of the length of the insulating layer; and / or, The thickness of the insulating layer is 50 nm to 1500 nm.

5. The gallium nitride device according to claim 1 or 2, characterized in that: The material of the insulating layer includes one or a combination of silicon nitride, silicon oxide and silicon oxynitride.

6. The gallium nitride device according to claim 1 or 2, characterized in that: The buffer layer includes a first buffer layer and a second buffer layer stacked along the first direction, and the second buffer layer is located between the first buffer layer and the insulating layer.

7. The gallium nitride device according to claim 6, characterized in that: The second buffer layer includes a third portion and a fourth portion arranged along the first direction, the third portion is located between the fourth portion and the first portion, and the third portion and the second portion are arranged in the second direction.

8. The gallium nitride device according to claim 1 or 2, characterized in that: The gallium nitride device further includes a nucleation layer, wherein the nucleation layer is located between the silicon substrate and the insulating layer, the insulating layer is located between the nucleation layer and the buffer layer, and the insulating layer separates the nucleation layer and the buffer layer.

9. A method for preparing a gallium nitride device, characterized in that: include: providing a silicon substrate; forming an insulating layer and a buffer layer; The silicon substrate, the insulating layer, and the buffer layer are stacked along a first direction, the insulating layer is located between the silicon substrate and the buffer layer, the insulating layer is a continuous structure, the insulating layer separates the silicon substrate and the buffer layer, and the insulating layer and the buffer layer are in contact and connected; the insulating layer includes a first portion and a second portion, and the first portion and the second portion are adjacently arranged in a second direction; Along the first direction, a thickness of the first portion is smaller than a thickness of the second portion, and the second direction is perpendicular to the first direction.

10. The preparation method according to claim 9, characterized in that The forming of the insulating layer and the buffer layer comprises: forming an insulating dielectric layer, wherein the silicon substrate and the insulating dielectric layer are stacked along the first direction; removing a portion of the insulating dielectric layer to form a first hole, with the remaining insulating dielectric layer including the first portion of the insulating layer; forming the second portion of the insulating layer in the first hole; A buffer layer is formed.

11. The preparation method according to claim 10, characterized in that: The forming of the second portion of the insulating layer in the first hole includes: forming a third portion of a second buffer layer, wherein the third portion and the first portion are stacked along the first direction, the first portion is located between the third portion and the silicon substrate, and a second hole facing the first hole is provided between adjacent third portions; filling the insulating material so that the insulating material covers the first hole, the second hole and the third portion; The insulating material is ground to expose the third portion.

12. The preparation method according to claim 11, characterized in that The forming of the buffer layer comprises: forming a fourth portion of the second buffer layer, wherein the fourth portion covers the third portion and the second portion; A first buffer layer is formed, and the second buffer layer is located between the first buffer layer and the insulating layer.

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