Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a base, an insulating layer located on the surface of the base, and a semiconductor layer located on the surface of the insulating layer, and the semiconductor layer comprises a channel region; the gate structure is located in the semiconductor layer and located on the surface of the insulating layer, the gate structure makes contact with the side wall of the channel region, and the gate structure and the channel region are arranged in the first direction parallel to the surface of the substrate; the source-drain doping layer is located in the semiconductor layer and located on the surface of the insulating layer, the source-drain doping layer makes contact with the side walls of the two opposite sides of the channel region, the source-drain doping layer and the channel region are arranged in the second direction parallel to the surface of the substrate, and the second direction is different from the first direction; when the gate electrode, the source electrode and the drain electrode are led out by forming plugs subsequently, part of the insulating layer does not need to be removed like a traditional process, the flexibility of device design is improved, meanwhile, the area of a device region is reduced, the preparation cost is reduced, the preparation period is shortened, and the application range is wide.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] As the advanced semiconductor manufacturing process has fully shifted to below 28 nanometers, the device feature size is too small and the gate oxide layer is extremely thin in the traditional process, making it very easy to occur short-channel effect and gate leakage problems. Two major routes have been developed in modern semiconductor manufacturing processes: FINFET and FDSOI (fully depleted silicon-on-insulator) technology. FDSOI is a process technology that continues to be based on the planar transistor structure: an ultra-thin buried oxide (box) layer is introduced into the bulk silicon as an insulating layer, and an ultra-thin top silicon layer is used to fabricate a fully depleted transistor channel. The biggest feature of FDSOI is that it can achieve chip area reduction, energy consumption saving, performance improvement and function expansion under Moore's Law without comprehensively modifying the equipment structure and production process. FDSOI ensures various key attributes of the transistor with an extremely thin top layer. Compared with the traditional bulk CMOS, the FD wafer can save up to 35% power consumption while maintaining the same performance. Based on different design optimizations, the peak performance of the processor based on the fully depleted wafer is increased by 50%. Due to its small drain / source parasitic capacitance, lower device delay and dynamic power consumption, and the threshold voltage not depending on the gate bias, it is more suitable for low-power applications.

[0003] In current chip manufacturing processes, different circuit modules on a chip are fabricated on the same substrate according to the manufacturing process, and then the electrical connections and packaging of these circuit modules are carried out to form the final product. However, as the functions of chips continue to increase, the number of circuit modules in the chips is also increasing. For example, it integrates a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM), multiple input / output (I / O) ports, etc. In addition, the FD-SOI technology can not only obtain all the benefits that FinFET fully depleted transistors bring to planar traditional technologies, but also achieve advanced negative bias technology that the latter cannot reach. Compared with bulk silicon-based MOS transistors or FinFETs, FD-SOI transistors can greatly improve chip performance due to their flexible and adjustable back bias. However, the back bias control terminal of the FD-SOI transistor is led out from the top of the wafer, and is in the same plane as the gate, source, and drain. It is necessary to remove part of the SOI layer, and prepare bias connections and pure planar process devices in the SOI layer removal area, and thus has to face a large height difference in the structure between circuit modules. At the same time, FD-SOI is commonly used in the pre-gate or post-gate process and both use dual in-situ doped epitaxy, and additional protection processes are required in the partial SOI layer removal area during the manufacturing process. Therefore, the existing FD-SOI manufacturing process is both complex and costly.

[0004] Therefore, how to simplify the FD-SOI manufacturing process and effectively reduce the manufacturing cycle and cost is a technical problem that urgently needs to be solved at present. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate, the substrate includes: a base, an insulating layer on the surface of the base, and a semiconductor layer on the surface of the insulating layer, the semiconductor layer includes a channel region; a gate structure located in the semiconductor layer and on the surface of the insulating layer, the gate structure is in contact with the sidewalls of the channel region, and the gate structure and the channel region are arranged along a first direction parallel to the surface of the base; source-drain doping layers located in the semiconductor layer and on the surface of the insulating layer, the source-drain doping layers are respectively in contact with the sidewalls on the opposite sides of the channel region, and the source-drain doping layers and the channel region are arranged along a second direction parallel to the surface of the base, and the second direction is different from the first direction.

[0007] Optionally, it further includes: a well region located in the substrate.

[0008] Optionally, it further includes: a first conductive plug connected to the source-drain doping layer.

[0009] Optionally, it further includes: a second conductive plug connected to the gate structure.

[0010] Optionally, the gate structure includes a gate oxide layer in contact with the sidewall surfaces of the channel region, a gate dielectric layer on the surface of the gate oxide layer, and a gate layer on the surface of the gate dielectric layer.

[0011] Optionally, it further includes a second isolation layer within the substrate, which isolates the substrate from the source / drain doping layer and isolates the substrate from the gate structure.

[0012] Optionally, the material of the source / drain doping layer includes one or more combinations of silicon germanium, silicon carbide, and silicon, and the source / drain doping layer is doped with N-type ions or P-type ions.

[0013] Optionally, it further includes: a well doping region within the semiconductor layer; a first isolation layer between the well doping region, the channel region, and the source / drain doping layer.

[0014] Optionally, it further includes: a third conductive plug connected to the well doping region.

[0015] Correspondingly, the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a base, an insulating layer on the surface of the base, and a semiconductor layer on the surface of the insulating layer, the semiconductor layer includes a channel region; forming a first groove within the semiconductor layer that exposes the surface of the insulating layer and part of the sidewall surfaces of the channel region, the first groove and the channel region are arranged along a first direction parallel to the surface of the base; forming a gate structure within the first groove; forming a second groove within the semiconductor layer that exposes the surface of the insulating layer, the second groove and the channel region are arranged along a second direction parallel to the surface of the base, and the second groove exposes opposite sidewalls of the channel region, and the second direction is different from the first direction; forming a source / drain doping layer within the second groove.

[0016] Optionally, the semiconductor layer further includes a well doping region, the well doping region and the channel region are arranged along the first direction; the gate structure and the well doping region are respectively located on both sides of the channel region.

[0017] Optionally, it further includes: forming a third groove that exposes the insulating layer between the well doping region and the channel region; forming a first isolation layer within the third groove.

[0018] Optionally, the first isolation layer is also located between the source / drain doping layer and the well doping region.

[0019] Optionally, it further includes: performing P-type doping or N-type doping on the well doping region; forming a third conductive plug on the surface of the well doping region.

[0020] Optionally, the method for forming the gate structure includes: forming a gate oxide layer on the bottom and sidewalls of the first groove, forming a gate dielectric layer on the surface of the gate oxide layer; forming a gate layer on the surface of the gate dielectric layer.

[0021] Optionally, the material of the gate layer is polysilicon doped with N-type ions or P-type ions.

[0022] Optionally, after forming the gate layer, planarization of the gate layer is further included to form a gate structure.

[0023] Optionally, the material of the source-drain doping layer includes one or more combinations of silicon germanium, silicon carbide, and silicon; the forming method of the source-drain doping layer includes: forming an initial source-drain doping layer on the bottom and sidewalls of the second groove, and the initial source-drain doping layer is doped with N-type ions or P-type ions; planarizing the initial source-drain doping layer to form the source-drain doping layer; the process of doping the initial source-drain doping layer with N-type ions or P-type ions includes an ion implantation process or an in-situ doping process.

[0024] Optionally, it further includes: forming a first conductive plug on the surface of the source-drain doping layer; forming a second conductive plug on the surface of the gate structure.

[0025] Optionally, it further includes: forming a second isolation layer in the semiconductor layer, and the second isolation layer is located between the source-drain doping layer and the semiconductor layer, and between the gate structure and the semiconductor layer.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the semiconductor structure of the technical solution of the present invention, the gate structure and the channel region are arranged along a first direction parallel to the surface of the substrate, the source-drain doping layer and the channel region are arranged along a second direction parallel to the surface of the substrate, and the first direction is different from the second direction. When forming plugs to lead out the gate, source, and drain subsequently, it is not necessary to remove part of the insulating layer like in the traditional process, which increases the flexibility of device design, reduces the device area, and lowers the manufacturing cost and cycle, and has a wide range of applications. Description of the Drawings

[0028] Figures 1 to 12 It is a schematic diagram of the structures of each step of a semiconductor structure and its forming method in an embodiment of the present invention. Detailed Embodiments

[0029] As in the background art, the performance of the existing semiconductor structure is poor.

[0030] On this basis, the present invention provides a semiconductor structure, in which the gate structure and the channel region are arranged along a first direction parallel to the surface of the substrate, the source-drain doping layer and the channel region are arranged along a second direction parallel to the surface of the substrate, and the first direction is different from the second direction. While reducing the device area, it increases the flexibility of device design, and can reduce the manufacturing cost and cycle, and has a wide range of applications.

[0031] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0032] Figures 1 to 12 These are schematic diagrams of the structures of each step of a semiconductor structure and a method for forming the same in an embodiment of the present invention.

[0033] First, please refer to FIGS. 1 and Figure 2 , and provide a substrate 100.

[0034] Figure 1 FIG. Figure 2 is a cross-sectional view taken along line A-A, Figure 2 and FIG. Figure 1 is a top view of

[0035] In this embodiment, the substrate 100 includes a base 101, an insulating layer 102 on the surface of the base 101, and a semiconductor layer 103 on the surface of the insulating layer 102. The semiconductor layer 103 includes a channel region 104.

[0036] In this embodiment, the material of the base 101 is silicon.

[0037] In other embodiments, the material of the base 101 may also be materials such as silicon germanium.

[0038] In this embodiment, the material of the insulating layer 102 is silicon oxide.

[0039] In other embodiments, the material of the insulating layer 102 may also be silicon oxycarbide, etc.

[0040] In this embodiment, the material of the semiconductor layer 103 is silicon.

[0041] In other embodiments, the semiconductor layer 103 may also be materials such as silicon germanium.

[0042] In this embodiment, the semiconductor layer 103 further includes a well doping region 105, and the well doping region 105 and the channel region 104 are arranged along a first direction.

[0043] In this embodiment, a third groove 106 exposing the insulating layer 102 is formed between the well doping region 105 and the channel region 104; a first isolation layer 107 is formed in the third groove 106.

[0044] In this embodiment, the material of the first isolation layer 107 is silicon oxide.

[0045] In this embodiment, the first direction is defined as the Y direction, and the second direction is defined as the X direction, but it is not limited to the definitions in this embodiment.

[0046] Please refer to Figure 3 and Figure 4, a first groove 108 is formed in the semiconductor layer 103, exposing the surface of the insulating layer 102 and the sidewall surfaces of a part of the channel region 104. The first groove 108 and the channel region 104 are arranged along a first direction Y parallel to the surface of the substrate 101.

[0047] Figure 3 is Figure 4 a cross-sectional view taken at A-A, Figure 4 is Figure 3 a top view of.

[0048] In this embodiment, the process of forming the first groove 108 is a dry etching process.

[0049] In other embodiments, the process of forming the first groove 108 can also be a wet etching process.

[0050] Please refer to Figure 5 , and a gate structure 109 is formed in the first groove 108.

[0051] Figure 5 The view direction of Figure 3 is the same as the view direction of

[0052] In this embodiment, the gate structure 109 and the well doping region 105 are respectively located on both sides of the channel region 104.

[0053] In this embodiment, the method of forming the gate structure 109 includes: forming a gate oxide layer 109a on the bottom and sidewalls of the first groove 108, forming a gate dielectric layer 109b on the surface of the gate oxide layer 109a; forming a gate layer 109c on the surface of the gate dielectric layer 109b.

[0054] In this embodiment, the material of the gate layer 109c is polysilicon doped with N-type ions or P-type ions.

[0055] In this embodiment, after forming the gate layer 109c, it further includes planarizing the gate layer 109c to form the gate structure 109.

[0056] In this embodiment, it further includes forming a second isolation layer 110 in the semiconductor layer 103, and the second isolation layer 110 is located between the gate structure 109 and the semiconductor layer 103.

[0057] In this embodiment, the material of the second isolation layer 110 is silicon oxide.

[0058] Please refer to Figure 6 and Figure 7, a second groove 111 exposing the surface of the insulating layer 102 is formed in the semiconductor layer 103. The second groove 111 and the channel region 104 are arranged along a second direction X parallel to the surface of the substrate 101, and the second groove 111 exposes the sidewalls on opposite sides of the channel region 104. The second direction X is different from the first direction Y.

[0059] Figure 6 is Figure 7 a cross-sectional view taken at A-A, Figure 7 is Figure 6 a top view of

[0060] In this embodiment, the process of forming the second groove 111 is a dry etching process.

[0061] In other embodiments, the process of forming the second groove 111 can also be a wet etching process.

[0062] Please refer to Figure 8 and Figure 9 , a source / drain doping layer 112 is formed in the second groove 111.

[0063] Figure 8 is Figure 9 a cross-sectional view taken at A-A, Figure 9 is Figure 8 a top view of

[0064] In this embodiment, the material of the source / drain doping layer 112 includes one or more combinations of silicon germanium, silicon carbide, and silicon.

[0065] In this embodiment, the method of forming the source / drain doping layer 112 includes: forming an initial source / drain doping layer on the bottom and sidewalls of the second groove 111, and the initial source / drain doping layer is doped with N-type ions or P-type ions; planarizing the initial source / drain doping layer to form the source / drain doping layer 112; the process of doping the initial source / drain doping layer with N-type ions or P-type ions includes an ion implantation process or an in-situ doping process.

[0066] In this embodiment, continuing to refer to Figure 9 , the first isolation layer 107 is also located between the source / drain doping layer 112 and the well doping region 105.

[0067] In this embodiment, there is also a second isolation layer 110 between the source / drain doping layer 112 and the semiconductor layer 103.

[0068] Please refer to Figures 10 to 12 , further including: forming a first conductive plug 114 on the surface of the source / drain doping layer 112; forming a second conductive plug 115 on the surface of the gate structure 109, and performing P-type doping or N-type doping on the well doping region 105; forming a third conductive plug 113 on the surface of the well doping region 105.

[0069] Figure 10 For Figure 12 Cross-sectional view taken along line A-A; Figure 11 Figure 12 Cross-sectional view taken along line B-B, Figure 12 is a top view.

[0070] In this embodiment, the materials of the third conductive plug 113, the first conductive plug 114, and the second conductive plug 115 include metal, and the metal includes one or a combination of more than one of copper, tungsten, aluminum, and titanium nitride.

[0071] In this embodiment, the first conductive plug 114 leads out the source / drain doping layer 112, the second conductive plug 115 leads out the gate structure 109, and the third conductive plug 113 leads out the well doping layer 105. There is a second isolation layer 110 between the source / drain doping layer 112 and the semiconductor layer 103, and between the gate structure 109 and the semiconductor layer 103. There is a first isolation layer 107 between the well doping region 105 and the channel region 104. The setting of this structure can enhance the flexibility of device design, reduce the device area, lower the manufacturing cost and cycle, improve the device performance and reduce the device power consumption, and has a wide range of applications.

[0072] Using the above method, the present invention also provides a semiconductor structure. Please refer to Figure 12 , which includes: a substrate 100, the substrate 100 includes: a base 101, an insulating layer 102 located on the surface of the base 101, and a semiconductor layer 103 located on the surface of the insulating layer 102. The semiconductor layer 103 includes a channel region 104; a gate structure 109 located in the semiconductor layer 103 and on the surface of the insulating layer 102, the gate structure 109 is in contact with the sidewalls of the channel region 104, and the gate structure 109 and the channel region 104 are arranged along a first direction Y parallel to the surface of the base 101; a source / drain doping layer 112 located in the semiconductor layer 103 and on the surface of the insulating layer 102, the source / drain doping layer 112 is in contact with the sidewalls on opposite sides of the channel region 104 respectively, and the source / drain doping layer 112 and the channel region 104 are arranged along a second direction X parallel to the surface of the base 101, and the second direction X is different from the first direction Y.

[0073] In this embodiment, it further includes: a well region located in the substrate 100.

[0074] In this embodiment, it further includes: a first conductive plug 114 connected to the source / drain doping layer 112.

[0075] In this embodiment, it further includes: a second conductive plug 115 connected to the gate structure 109.

[0076] In this embodiment, the gate structure 109 includes a gate oxide layer 109a in contact with the sidewall surfaces of the channel region 104, a gate dielectric layer 109b on the surface of the gate oxide layer 109a, and a gate layer 109c on the surface of the gate dielectric layer 109b.

[0077] In this embodiment, a second isolation layer 110 is included within the substrate 100, and the second isolation layer 110 isolates the substrate 100 from the source / drain doping layer 112 and isolates the substrate 100 from the gate structure 109.

[0078] In this embodiment, the material of the source / drain doping layer 112 includes one or more combinations of silicon germanium, silicon carbide, and silicon, and the source / drain doping layer 112 is doped with N-type ions or P-type ions.

[0079] In this embodiment, it further includes: a well doping region 105 within the semiconductor layer 103; a first isolation layer 107 between the well doping region 105, the channel region 104, and the source / drain doping layer 112.

[0080] In this embodiment, it further includes: a third conductive plug 113 connected to the well doping region 105.

[0081] In this embodiment, the first conductive plug 114 leads out the source / drain doping layer 112, the second conductive plug 115 leads out the gate structure 109, and the third conductive plug 113 leads out the well doping layer 105. There is a second isolation layer 110 between the source / drain doping layer 112 and the semiconductor layer 103, and between the gate structure 109 and the semiconductor layer 103. There is a first isolation layer 107 between the well doping region 105 and the channel region 104. The setting of this structure can enhance the flexibility of device design, reduce the device area, lower the manufacturing cost and cycle, improve the device performance and reduce the device power consumption, and has a wide range of applications.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate comprising: a base, an insulating layer on the surface of the base, and a semiconductor layer on the surface of the insulating layer, the semiconductor layer comprising a channel region; A gate structure within the semiconductor layer and on the surface of the insulating layer, the gate structure in contact with the sidewalls of the channel region, and the gate structure and the channel region arranged along a first direction parallel to the surface of the base; Source-drain doping layers within the semiconductor layer and on the surface of the insulating layer, the source-drain doping layers respectively in contact with the sidewalls on opposite sides of the channel region, and the source-drain doping layers and the channel region arranged along a second direction parallel to the surface of the base, the second direction being different from the first direction.

2. The semiconductor structure according to claim 1, wherein Further comprising: A well region within the substrate.

3. The semiconductor structure according to claim 1, wherein Further comprising: A first conductive plug connected to the source-drain doping layer.

4. The semiconductor structure according to claim 1, wherein Further comprising: A second conductive plug connected to the gate structure.

5. The semiconductor structure according to claim 1, wherein The gate structure includes a gate oxide layer in contact with the surface of the sidewalls of the channel region, a gate dielectric layer on the surface of the gate oxide layer, and a gate electrode layer on the surface of the gate dielectric layer.

6. The semiconductor structure according to claim 1, wherein Further comprising: A second isolation layer within the substrate, the second isolation layer isolating the substrate and the source-drain doping layer and isolating the substrate and the gate structure.

7. The semiconductor structure according to claim 1, wherein The material of the source-drain doping layer includes one or more combinations of silicon germanium, silicon carbide, and silicon, and the source-drain doping layer is doped with N-type ions or P-type ions.

8. The semiconductor structure according to claim 7, wherein, Further comprising: A well doping region within the semiconductor layer; A first isolation layer between the well doping region, the channel region, and the source-drain doping layer.

9. The semiconductor structure according to claim 8, wherein, Further comprising: A third conductive plug connected to the well doping region.

10. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate comprising a base, an insulating layer on the surface of the base, and a semiconductor layer on the surface of the insulating layer, the semiconductor layer comprising a channel region; Forming a first groove within the semiconductor layer exposing the surface of the insulating layer and a portion of the surface of the sidewalls of the channel region, the first groove and the channel region arranged along a first direction parallel to the surface of the base; Forming a gate structure within the first groove; Forming a second groove within the semiconductor layer exposing the surface of the insulating layer, the second groove and the channel region arranged along a second direction parallel to the surface of the base, and the second groove exposing the sidewalls on opposite sides of the channel region, the second direction being different from the first direction; Forming source-drain doping layers within the second groove.

11. The method for forming a semiconductor structure as described in claim 10, wherein, The semiconductor layer further includes a well doping region, the well doping region and the channel region arranged along the first direction; the gate structure and the well doping region are respectively located on both sides of the channel region.

12. The method for forming a semiconductor structure according to claim 11, wherein, Further comprising: Forming a third groove between the well doping region and the channel region exposing the insulating layer; Forming a first isolation layer within the third groove.

13. The method for forming a semiconductor structure according to claim 12, wherein, The first isolation layer is also located between the source-drain doping layer and the well doping region.

14. The method for forming a semiconductor structure according to claim 11, wherein Further comprising: Performing P-type doping or N-type doping on the well doping region; Forming a third conductive plug on the surface of the well doping region.

15. The method for forming a semiconductor structure according to claim 10, wherein, The method for forming the gate structure includes: forming a gate oxide layer on the bottom and sidewalls of the first groove, and forming a gate dielectric layer on the surface of the gate oxide layer; forming a gate layer on the surface of the gate dielectric layer.

16. The method for forming a semiconductor structure according to claim 15, wherein, The material of the gate layer is polysilicon doped with N-type ions or P-type ions.

17. The method for forming a semiconductor structure according to claim 15, wherein, After forming the gate layer, it further includes planarizing the gate layer to form the gate structure.

18. The method for forming a semiconductor structure according to claim 10, wherein, The material of the source / drain doped layer includes one or more combinations of silicon germanium, silicon carbide, and silicon; the method for forming the source / drain doped layer includes: forming an initial source / drain doped layer on the bottom and sidewalls of the second groove, and the initial source / drain doped layer is doped with N-type ions or P-type ions; planarizing the initial source / drain doped layer to form the source / drain doped layer; the process of doping the initial source / drain doped layer with N-type ions or P-type ions includes an ion implantation process or an in-situ doping process.

19. The method for forming a semiconductor structure according to claim 10, wherein, It further includes: forming a first conductive plug on the surface of the source / drain doped layer; forming a second conductive plug on the surface of the gate structure.

20. The method for forming a semiconductor structure according to claim 10, wherein, It further includes: forming a second isolation layer in the semiconductor layer, and the second isolation layer is located between the source / drain doped layer and the semiconductor layer, and between the gate structure and the semiconductor layer.

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