Treatment of reinforcing material structures

Abstract

A method of forming a semiconductor structure, the method including performing a pre-treatment process including annealing a surface of a substrate in a hydrogen (H2) environment; performing an interface forming process including thermally oxidizing a pre-treated surface of the substrate to form an interface layer; and performing a post-treatment process including annealing a surface of the formed interface layer in an ammonia (NH3) environment.

Description

Technical Field

[0001] This application claims priority to U.S. Provisional Application Serial No. 63 / 438,160, filed on January 10, 2023, the entire content of which is incorporated herein by reference.

[0002] Embodiments described herein generally relate to semiconductor device manufacturing, and more particularly, to systems and methods for forming high-quality high-k dielectric layers in semiconductor structures. Background Art

[0003] As the dimensions of metal-oxide-semiconductor field-effect transistors (MOSFETs) are reduced to achieve high device performance and low power consumption, the thickness of conventional silicon dioxide (SiO2) gate dielectrics has been reduced to its physical limit. Therefore, to enable further miniaturization, it is inevitable to replace the silicon dioxide gate dielectric with a high-k dielectric material. Among various high-k dielectric materials, hafnium oxide (HfO2) has been used since the 45nm MOSFET technology node due to its high dielectric constant and excellent thermal stability on silicon substrates. However, to further reduce the equivalent oxide thickness (EOT) for 32nm MOSFET technology nodes and below, simply reducing the thickness of the high-k dielectric layer is problematic because the leakage current through the high-k dielectric layer increases.

[0004] Therefore, a system and method are needed that can be used to form a thin (e.g., EOT less than 1nm) high-k dielectric layer with a controllable chemical structure to ensure desired structural and electrical properties. Summary of the Invention

[0005] Embodiments of the present disclosure provide a method of forming a semiconductor structure. The method includes performing a pre-treatment process that includes annealing the surface of a substrate in a hydrogen (H2) environment; performing an interface formation process that includes thermally oxidizing the pre-treated surface of the substrate to form an interface layer; and performing a post-treatment process that includes annealing the surface of the formed interface layer in an ammonia (NH3) environment.

[0006] Embodiments of the present disclosure also provide a method of forming a semiconductor structure. The method includes performing a pre-cleaning process, including etching a surface of a substrate through a dry etching process using nitrogen trifluoride (NF3) gas and a wet etching process using a hydrochloric acid (HCl) solution and / or a dilute hydrofluoric acid (DHF) solution, performing an interface layer module process to form an interface layer on the pre-cleaned surface of the substrate, wherein the interface layer module process includes performing a pre-treatment process, including annealing the pre-cleaned surface of the substrate in a hydrogen (H2) environment; performing an interface formation process, including thermally oxidizing the pre-treated surface of the substrate to form an interface layer, and performing a post-treatment process, including annealing the surface of the formed interface layer in an ammonia (NH3) environment, performing a hydration process, including annealing the surface of the interface layer in an ammonia (NH3) and water (H2O) environment, and performing a deposition process, including depositing a high-k dielectric layer on the hydrated surface of the interface layer.

[0007] Embodiments of the present disclosure also provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, a fifth processing chamber, a sixth processing chamber, and a system controller configured to perform a pre-cleaning process in the first processing chamber, including a dry etching process using nitrogen trifluoride (NF3) gas and a wet etching process using a hydrochloric acid (HCl) solution and / or a dilute hydrofluoric acid (DHF) solution, perform a pre-treatment process in the second processing chamber, including annealing the pre-cleaned surface of the substrate in a hydrogen (H2) environment, perform an interface formation process in the third processing chamber, including thermally oxidizing the pre-treated surface of the substrate to form an interface layer, perform a post-treatment process in the fourth processing chamber, including annealing the surface of the formed interface layer in an ammonia (NH3) environment, perform a hydration process in the fifth processing chamber, including annealing the surface of the interface layer in an ammonia (NH3) and water (H2O) environment, and perform a deposition process in the sixth processing chamber, including depositing a high-k dielectric layer on the hydrated surface of the interface layer. The pre-treatment process, the interface formation process, the post-treatment process, the hydration process, and the deposition process are performed in the processing system without breaking vacuum. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to be able to understand the above features of the present disclosure in detail, the present disclosure briefly summarized above can be described more specifically with reference to the embodiments, some of which are shown in the drawings. However, it should be noted that the drawings only show the general embodiments of the present disclosure and should not be regarded as limiting its scope, since the present disclosure may allow other equally effective embodiments.

[0009] Figure 1 is a schematic top view of an exemplary multi-chamber processing system according to one embodiment.

[0010] Figure 2 is a process flow diagram of a method of forming a semiconductor structure according to one embodiment.

[0011] Figure 3A , 3B and 3C are schematic diagrams of a semiconductor structure according to one embodiment.

[0012] Figure 4 is a process flow diagram of an interface layer (IL) module process according to one embodiment.

[0013] For ease of understanding, where possible, the same reference numerals are used to denote the same elements common to the drawings. It should be considered that the elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation. Detailed Description

[0014] As gate structures are scaled down to smaller dimensions, new material structures are sought to provide improvements. Compared to traditional gate structures that utilize materials such as silicon oxide, the use of high-k dielectric materials increases the dielectric constant of the gate structure. However, similar to silicon oxide, as the thickness of the gate structure decreases, the leakage current increases. For example, gate leakage increases as the effective oxide thickness decreases. Thus, the inverse relationship between gate leakage and effective oxide thickness may impose limitations on the performance of transistors and the components produced.

[0015] High-k dielectric materials can provide a higher channel carrier concentration than silicon oxide at similar thicknesses. As the industry continues to seek lower effective oxide thicknesses without increasing gate leakage, efforts to maximize the dielectric constant (also referred to as the "k-value") of known high-k materials have reached a limit due to morphological characteristics. Traditional techniques have been attempting to overcome the natural characteristics of high-k materials, which may set an upper limit on the k-value and subsequent device modifications to attempt to incorporate new films.

[0016] The embodiments described herein provide systems and methods for improving the characteristics of high-k dielectric materials. By creating a high-quality thin interface layer between a substrate and a high-k dielectric layer, a higher dielectric constant can be achieved and subsequent device performance can be improved.

[0017] Figure 1is a schematic top view of an example of a multi-chamber processing system 100 in accordance with some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 can be processed in the respective chambers and transferred between the respective chambers without exposing the wafers to the ambient environment external to the processing system 100 (e.g., an atmospheric ambient environment such as may exist in a laboratory). For example, wafers can be processed in the respective chambers and transferred between the respective chambers in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment between the various processes performed on the wafers in the processing system 100 to prevent contamination from moisture, organic or inorganic trace substances. Accordingly, the processing system 100 can provide an integrated solution for some wafer processing.

[0018] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include or integrated processing systems, or other suitable processing systems available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing systems (including those from other manufacturers) may be suitable to benefit from the aspects described herein.

[0019] In Figure 1 the example shown, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate wafer transfer. The docking station 140 is configured to receive one or more front-opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally includes blades 148 disposed at one end of the respective factory interface robot 142 and is configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0020] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. The ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 can be, for example, slit valve openings with slit valves for the transfer of wafers therethrough by the transfer robots 112, 114 and for providing a seal between the respective chambers to prevent the passage of gas between the respective chambers. Generally, any port is open for the transfer of wafers therethrough. Otherwise, the port is closed.

[0021] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the respective chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 144 through the port 150 or 152 to the load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low pressure or vacuum environment (which can include an inert gas). Thus, the pumping down of the load lock chamber 104 or 106 facilitates the passage of the wafer between the atmospheric environment of, for example, the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0022] When the wafer is in the evacuated load lock chamber 104 or 106, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 through the access ports 154 or 156 into the transfer chamber 108. The transfer robot 112 can then transfer the wafer through the corresponding access ports 162, 164 to any one and / or between the processing chambers 120, 122 for processing, and transfer the wafer through the corresponding access ports 158, 160 to any one and / or between the holding chambers 116, 118 to wait for further transfer. Similarly, the transfer robot 114 can access the wafers in the holding chambers 116 or 118 through the access ports 166 or 168, and can transfer the wafers through the corresponding access ports 170, 172, 174, 176 to any one and / or between the processing chambers 124, 126, 128, 130 for processing, and transfer the wafers through the corresponding access ports 166, 168 to any one and / or between the holding chambers 116, 118 to wait for further transfer. The transfer and holding of the wafer within and between the various chambers can be carried out in a low pressure or vacuum environment provided by the gas and pressure control system.

[0023] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing wafers. In some examples, the processing chamber 122 can perform a cleaning process, the processing chamber 120 can perform an etching process, and the processing chambers 124, 126, 128, 130 can perform corresponding epitaxial growth processes. The processing chamber 122 can be a SiCoNi TM pre-cleaning chamber. The processing chamber 120 can be a Selectra TM etching chamber available from Applied Materials of Santa Clara, California.

[0024] The system controller 190 is coupled to the processing system 100 for controlling the processing system 100 or its components. For example, the system controller 190 can use direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100, or control the operation of the processing system 100 by controlling the controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. In operation, the system controller 190 can collect data and feedback from the individual chambers to coordinate the performance of the processing system 100.

[0025] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuitry 196. The CPU 192 can be in any form of a general-purpose processor for use in an industrial setting. The memory 194 or non-transitory computer-readable medium can be accessed by the CPU 192 and can be one or more of memories such as random access memory (RAM), read-only memory (ROM), disk drives, hard disks, or any other form of local or remote digital storage. The support circuitry 196 is coupled to the CPU 192 and can include a cache, frequency circuitry, an input / output subsystem, a power supply, etc. The various methods disclosed herein can generally be implemented under the control of the CPU 192 by the CPU 192 executing computer instruction codes stored in the memory 194 (or in the memory of a particular processing chamber), for example, as software routines. When the CPU 192 executes the computer instruction codes, the CPU 192 controls the chamber to perform processing according to the various methods.

[0026] Other processing systems can have other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, there can be more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) as the transfer device in the processing system.

[0027] Figure 2 is a flow chart of a method 200 of forming a semiconductor structure 300 in accordance with one or more instances of the present disclosure. Figure 3A 、 3B and 3C are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of the method 200. Understand Figure 3A 、 3B and 3C only show partial schematic views of the semiconductor structure 300, and the semiconductor structure 300 may include any number of transistor segments and additional materials having aspects as shown. It should also be understood that although Figure 2 the method steps shown are described sequentially, other processing sequences including one or more method steps that have been omitted and / or added and / or have been rearranged in another desired order also fall within the scope of the embodiments of the present disclosure provided herein.

[0028] The method 200 begins with a pre-clean process in block 210 to pre-clean the surface 302A of the substrate 302, as Figure 3AAs shown. The substrate 302 may include, for example, crystalline silicon (e.g., Si<100> or Si<111>), doped or undoped silicon wafers, patterned or unpatterned silicon wafers, strained silicon, silicon germanium, doped or undoped polysilicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 302 may include a stack of silicon (Si) layers and silicon germanium (SiGe) layers formed alternately and repeatedly on the surface 302A of the substrate 302, such as the structure in a gate-all-around (GAA) field-effect transistor (FET).

[0029] The pre-cleaning process may include a dry etching process, such as SiConi TM A remote plasma-assisted dry etching process partially removes the silicon germanium (SiGe) layer, where the surface 302A of the substrate 302 is exposed to nitrogen trifluoride (NF3) gas, nitrogen (N2) gas, or ammonia (NH3) gas, and then the surface 302A of the substrate 302 is etched through a wet etching process using an etching solution, such as hydrochloric acid (HCl) solution and / or dilute hydrofluoric acid (DHF) solution, to remove oxide-containing contaminants (e.g., native oxide layer). The surface 302A of the substrate 302 pre-cleaned with the DHF solution may be hydrophobic (e.g., not adhesive to moisture) and have a large surface roughness, such as 5 angstroms to 8 angstroms.

[0030] The pre-cleaning process can be performed in a pre-cleaning chamber, such as Clarion TM or Siconi TM chamber, which can be obtained from Applied Materials, Inc. located in Santa Clara, California. The pre-cleaning process can be performed without breaking the vacuum environment in a multi-chamber processing system (such as Figure 1 the multi-chamber processing system 100 shown) to prevent contamination from moisture, organic, or inorganic trace substances.

[0031] In block 220, an interface layer (IL) module process is performed to form an interface layer 304 on the pre-cleaned surface of the substrate 302, as Figure 3B shown. The interface layer 304 formed in block 220 is a thin silicon oxide (SiO2) layer with a thickness between about 3 angstroms and about 8 angstroms, such as about 4 angstroms, corresponding to one or more monolayers of silicon oxide. The interface layer 304 can act as a nucleation layer for the high-k dielectric layer 306 ( Figure 3C shown therein) to be deposited thereon and improve the quality of the interface between the substrate 302 and the high-k dielectric layer 306 (e.g., such as interface state density, cumulative capacitance, frequency dispersion, and leakage current).

[0032] Since the surface 302A of the substrate 302 is hydrophobic and has a large surface roughness, the IL module process includes a pre-treatment process to smooth the surface 302A of the substrate 302 before forming the interface layer, and a post-treatment process after forming the interface layer 304 to form surface ligands on the surface 304A of the interface layer 304 (e.g., silicon oxide (SiO2)), as discussed in more detail below. A high-quality conformal thin interface layer 304 can be formed on the smooth surface of the substrate 302, and its thickness can be precisely controlled.

[0033] In block 230, a hydration process is performed to passivate the surface 304A of the interface layer 304 formed in block 220 with hydroxide (-OH), while catalyzing the binding of the surface 304A of the interface layer 304 with a metal-containing precursor for forming a high-k dielectric layer 306 on the surface 304A of the interface layer in the deposition process in block 240 ( Figure 3C as shown).

[0034] The hydration process may include exposing the substrate 302 to an ammonia (NH3) and water (H2O) environment in a processing chamber, such as a Clarion TM chamber available from Applied Materials, Inc. of Santa Clara, California. The hydration process can be performed without breaking the vacuum environment in a multi-chamber processing system (e.g., Figure 1 the multi-chamber processing system 100 as shown) to prevent contamination from moisture, organic, or inorganic trace substances.

[0035] The rapid thermal annealing process can be performed at a temperature between about 15°C and about 60°C and a pressure between about 5 Torr and 300 Torr.

[0036] In block 240, a deposition process is performed to deposit a high-k dielectric layer 306 on the hydrated surface 304A of the interface layer 304, as Figure 3C shown. The high-k dielectric layer 306 can be formed of a high-k dielectric material, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), ytterbium oxide (Y2O3), or aluminum oxide (Al2O3).

[0037] The deposition process can include an atomic layer deposition (ALD) process, where a metal-containing precursor and an oxygen-containing precursor are alternately delivered to an exposed surface of the semiconductor structure 300. In some embodiments, the metal-containing precursor is cleaned before delivering the oxygen-containing precursor. The metal can be a transition metal, such as hafnium (Hf), zirconium (Zr), or titanium (Ti), a rare earth metal, such as lanthanum (La), ytterbium (Yb), or yttrium (Y), an alkaline earth metal, such as strontium (Sr), or other metals, such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal can be used. For example, the oxygen-containing precursor can be or include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen- and oxygen-containing precursor, plasma-enhanced oxygen (including locally or remotely enhanced oxygen), or any other material, including oxygen that can bind to the metal to produce a layer of metal oxide on the substrate 302. In one example, the metal-containing precursor is hafnium tetrachloride (HfCl4) and the oxidant is deionized water (H2O) to form a hafnium dioxide (HfO2) layer. The ALD process can be performed at a temperature between about 200 °C and about 400 °C, such as about 270 °C. The high-k dielectric layer 306 deposited through the ALD process can be amorphous and have a thickness between about 10 Å and about 30 Å.

[0038] The deposition process can be performed in a processing chamber, such as Figure 1 the processing chambers 120, 122, 124, 126, 128, or 130 shown. The deposition process can be performed without breaking the vacuum environment in a multi-chamber processing system, such as Figure 1 the multi-chamber processing system 100 shown, to prevent contamination from moisture, organic, or inorganic trace substances.

[0039] In block 250, an optional plasma nitridation process is performed to insert nitrogen atoms into the vacancies and defects in the high-k dielectric layer 306. The plasma nitridation process can be a decoupled plasma nitridation (DPN) process, performed in a DPN chamber, such as available from Applied Materials, Inc. of Santa Clara, California. the DPN chamber of a DPN chamber.

[0040] The plasma nitridation process exposes the deposited high-k dielectric layer 306 to a nitrogen plasma, allowing nitrogen radicals or nitrogen atoms to be incorporated throughout the thickness of the high-k dielectric layer 306. During the plasma nitridation process, nitrogen atoms can form metastable bonds with oxygen (O). The gases that can be used for plasma processing include nitrogen-containing gases, such as nitrogen gas (N2), ammonia gas (NH3), or a mixture thereof. In one example, the nitrogen gas is ammonia gas (NH3) mixed with about 3% to about 8% nitrogen gas (N2). Due to the incorporation of nitrogen into the vacancies and defects of the deposited high-k dielectric layer 306, the plasma nitridation process does not change the thickness of the high-k dielectric layer 306.

[0041] The plasma nitridation process can be carried out at a temperature between about 0 °C and about 500 °C for between about 10 seconds and about 300 seconds.

[0042] In block 260, an optional post-nitridation annealing process is performed to passivate the remaining chemical bonds in the high-k dielectric layer 306 that has been plasma nitrided.

[0043] The post-nitridation annealing process can include a spike thermal annealing process in a nitrogen (N2) and argon (Ar) environment, and is carried out in, for example, a rapid thermal processing (RTP) chamber such as the RadOx TM chamber that can be obtained from Applied Materials, Inc. located in Santa Clara, California.

[0044] The spike thermal annealing process can be carried out at a temperature between about 700 °C and about 900 °C and at a pressure between about 0.5 Torr and 780 Torr for between about 1 second and about 30 seconds.

[0045] Figure 4 is a process flow diagram of the IL module processing shown in block 220 of method 200 according to one or more examples of the present disclosure.

[0046] The IL module processing begins with a pre-treatment process in block 410 to reduce the surface roughness of the surface 302A of the substrate 302. The surface 302A of the substrate 302 that has been pre-cleaned by the etching process in block 210 can be rough. Before the interface layer 304 is formed on the surface 302A of the substrate 302, the pre-treatment process can reduce the surface roughness of the surface 302A of the substrate.

[0047] The pre-treatment process can include a spike thermal annealing process in a hydrogen (H2) environment to induce the migration of silicon (Si) atoms on the surface 302A of the substrate 302 and enhance the smoothness of the surface 302A of the substrate 302. The spike thermal annealing process can be carried out at a temperature between about 500 °C and about 900 °C and at a pressure between about 5 Torr and 80 Torr for between about 10 seconds and about 100 seconds.

[0048] The pre-treatment process can be carried out in a rapid thermal processing (RTP) chamber such as the RadOx TM chamber that can be obtained from Applied Materials, Inc. located in Santa Clara, California. The pre-treatment process can be carried out without breaking the vacuum environment in a multi-chamber processing system (such as Figure 1 the multi-chamber processing system 100 shown) to prevent contamination from moisture, organic or inorganic trace substances.

[0049] In block 420, an interface formation process is performed to form an interface layer 304 on the pre-treated surface 302A of the substrate 302, as Figure 3Aas shown

[0050] The interface formation process may include a suitable thermal oxidation process to oxidize the surface 302A of the substrate 302, such as an enhanced in-situ steam generation (eISSG) process using nitrous oxide (N2O) gas and hydrogen (H2) gas at a temperature between about 500 °C and about 800 °C and a pressure between 1 Torr and about 30 Torr. In some embodiments, the interface layer 304 may be formed by a rapid thermal oxidation (RTO) process using O2 gas at a temperature between about 500 °C and about 800 °C. The interface layer 304 formed at a high temperature in block 420 may be tight and will not increase its thickness during subsequent processing.

[0051] The interface formation process may be performed in a processing chamber, such as Figure 1 the processing chambers 120, 122, 124, 126, 128, or 130 as shown. The interface formation process may be performed without breaking the vacuum environment in a multi-chamber processing system (such as Figure 1 the multi-chamber processing system 100 as shown) to prevent contamination from moisture, organic, or inorganic trace substances.

[0052] In block 430, a post-treatment process is performed to form surface ligands on the surface 304A of the interface layer 304, which catalyzes the binding of the surface 304A of the interface layer 304 with the metal precursor used to form the high-k dielectric layer 306 on the surface 304A of the interface layer in the deposition process in block 240. In one example, for the hafnium tetrachloride (HfCl4) precursor for forming a hafnium dioxide (HfO2) layer, NH2 ligands are formed to enhance the nucleation of hafnium tetrachloride (HfCl4) on the surface 304A of the interface layer 304, and the silicon (Si) dangling bonds at the surface 304A of the substrate 302 are terminated by the NH2 ligands. The proper nucleation of hafnium tetrachloride (HfCl4) on the surface 304A of the interface layer 304 results in the formation of a defect-free high-k dielectric layer 306. The proper nucleation of other metal-containing precursors of metal halides (such as chlorides, fluorides, bromides), such as zirconium tetrachloride (ZrCl4) and titanium tetrachloride (TiCl4) on the surface 304A of the interface layer 304, can be similarly enhanced by terminating the silicon (Si) dangling bonds with NH2 ligands.

[0053] The post-treatment process may include a spike thermal annealing process in an ammonia (NH3) environment to form surface NH2 ligands on the surface 304A of the interface layer 304. The spike thermal annealing process may be performed at a temperature between about 500 °C and about 800 °C and a pressure between about 2 Torr and about 50 Torr for between about 15 seconds and about 60 seconds.

[0054] The post-treatment process may be performed in a rapid thermal processing (RTP) chamber. It may be performed without breaking the vacuum environment in a multi-chamber processing system (such asFigure 1 Perform post-disposal processing in a vacuum environment in the multi-chamber processing system 100 shown in FIG. to prevent contamination from moisture, organic or inorganic trace substances.

[0055] In the embodiments described herein, a system and method for forming a high-quality thin high-k dielectric layer are provided. The properties of such high-k dielectric layers can be well controlled. For example, the nitridation process in block 260 can be controlled to provide nitrogen incorporation between about 3 atomic % and about 20 atomic % in the high-k dielectric layer 306 to achieve a higher k value than higher nitrogen incorporation and to inhibit the formation of grains having a size greater than about 20 angstroms in the high-k dielectric layer 306.

[0056] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be derived without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A method of forming a semiconductor structure, the method comprising: Performing a pre-treatment process, the pre-treatment process comprising annealing the surface of a substrate in a hydrogen (H2) environment; Performing an interface formation process, the interface formation process comprising thermally oxidizing the pre-treated surface of the substrate to form an interface layer; And Performing a post-treatment process, the post-treatment process comprising annealing the surface of the formed interface layer in an ammonia (NH3) environment.

2. The method according to claim 1, wherein the pre-treatment process, the interface formation process, and the post-treatment process are performed in a processing system without breaking vacuum.

3. The method according to claim 1, wherein the substrate comprises silicon (Si) and the interface layer comprises silicon dioxide (SiO2).

4. The method according to claim 3, wherein The interface formation process comprises: thermally oxidizing the substrate using nitrous oxide (N2O) gas and hydrogen (H2) gas.

5. The method according to claim 3, wherein the interface layer has a thickness between 3 Å and 8 Å.

6. The method according to claim 1, wherein the pre-treatment process is performed at a temperature between 500 °C and 900 °C and at a pressure between 5 Torr and 80 Torr for between 30 seconds and 100 seconds.

7. The method according to claim 1, wherein the post-treatment process is performed at a temperature between 500 °C and 800 °C and at a pressure between 2 Torr and 50 Torr for between 15 seconds and 60 seconds.

8. A method of forming a semiconductor structure, the method comprising: Performing a pre-cleaning process, the pre-cleaning process comprising etching the surface of a substrate through a dry etching process using nitrogen trifluoride (NF3) gas and a wet etching process using hydrochloric acid (HCl) solution and / or dilute hydrofluoric acid (DHF) solution; Performing an interface layer module process to form an interface layer on the pre-cleaned surface of the substrate, wherein the interface layer module process comprises: Performing a pre-treatment process, the pre-treatment process comprising annealing the pre-cleaned surface of the substrate in a hydrogen (H2) environment; Performing an interface formation process, the interface formation process comprising thermally oxidizing the pre-treated surface of the substrate to form the interface layer; And Performing a post-treatment process, the post-treatment process comprising annealing the surface of the formed interface layer in an ammonia (NH3) environment; Performing a hydration process, the hydration process comprising annealing the surface of the interface layer in an ammonia (NH3) and water (H2O) environment; And Performing a deposition process, the deposition process comprising depositing a high-k dielectric layer on the hydrated surface of the interface layer.

9. The method according to claim 8, wherein the interface layer module process, the hydration process, and the deposition process are performed in a processing system without breaking vacuum.

10. The method according to claim 8, wherein The substrate comprises silicon (Si) and the interface layer comprises silicon dioxide (SiO2) having a thickness between 3 Å and 8 Å, and The interface formation process includes: thermally oxidizing the substrate using nitrous oxide (N2O) gas and hydrogen (H2) gas.

11. The method according to claim 8, wherein the pre-treatment process is performed at a temperature between 500 °C and 900 °C and at a pressure between 10 Torr and [missing value] Torr for between 30 seconds and 100 seconds.

12. The method according to claim 8, wherein the post-treatment process is performed at a temperature between 500 °C and 800 °C and at a pressure between 2 Torr and 50 Torr for between 15 seconds and 60 seconds.

13. The method according to claim 8, wherein the high-k dielectric layer comprises hafnium dioxide (HfO2).

14. The method according to claim 8, the method further comprising: performing a plasma nitridation process, the plasma nitridation process comprising exposing the deposited high-k dielectric layer to a nitrogen plasma using a mixture of nitrogen (N2) and ammonia (NH3) gases; and performing a post-nitridation annealing process, the post-nitridation annealing process comprising annealing the surface of the plasma nitrided high-k dielectric layer at a temperature between 700 °C and 900 °C in a nitrogen (N2) and argon (Ar) environment.

15. A processing system, the processing system comprising: a first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; a fifth processing chamber; a sixth processing chamber; and a system controller configured to perform: performing a pre-cleaning process in the first processing chamber, the pre-cleaning process comprising etching the surface of the substrate by a dry etching process using nitrogen trifluoride (NF3) gas and a wet etching process using hydrochloric acid (HCl) solution and / or dilute hydrofluoric acid (DHF) solution; performing a pre-treatment process in the second processing chamber, the pre-treatment process comprising annealing the pre-cleaned surface of the substrate in a hydrogen (H2) environment; performing an interface formation process in the third processing chamber, the interface formation process comprising thermally oxidizing the pre-treated surface of the substrate to form an interface layer; performing a post-treatment process in the fourth processing chamber, the post-treatment process comprising annealing the surface of the formed interface layer in an ammonia (NH3) environment; performing a hydration process in the fifth processing chamber, the hydration process comprising annealing the surface of the interface layer in an ammonia (NH3) and water (H2O) environment; and performing a deposition process in the sixth processing chamber, the deposition process comprising depositing a high-k dielectric layer on the hydrated surface of the interface layer; wherein the pre-treatment process, the interface formation process, the post-treatment process, the hydration process, and the deposition process are performed in the processing system without breaking vacuum.

16. The processing system according to claim 15, wherein the substrate comprises silicon (Si) and the interface layer comprises silicon dioxide (SiO2) having a thickness between 3 Å and 8 Å, and The interface formation process includes thermally oxidizing the substrate using nitrous oxide (N2O) gas and hydrogen (H2) gas.

17. The processing system according to claim 15, wherein the pre-treatment process is carried out at a temperature between 500 °C and 900 °C and at a pressure between 10 Torr and [Torr] for between 30 seconds and 100 seconds.

18. The processing system according to claim 15, wherein the post-treatment process is carried out at a temperature between 500 °C and 800 °C and at a pressure between 2 Torr and 50 Torr for between 15 seconds and 60 seconds.

19. The processing system according to claim 15, wherein the high-k dielectric layer comprises hafnium dioxide (HfO2).

20. The processing system according to claim 15, the processing system further comprising: a seventh processing chamber; and an eighth processing chamber, wherein the system controller is further configured to perform: performing a plasma nitridation process in the seventh processing system, the plasma nitridation process comprising exposing the deposited high-k dielectric layer to a nitrogen plasma using a mixture of nitrogen (N2) and ammonia (NH3) gases; and performing a post-nitridation annealing process in the eighth processing system, the post-nitridation annealing process comprising annealing the surface of the plasma nitridation of the high-k dielectric layer at a temperature between 700 °C and 850 °C in a nitrogen (N2) and argon (Ar) environment.

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