High gain low power phase detector and loop filter for phase locked loop (PLL)

Abstract

An apparatus includes a phase locked loop (PLL) including a phase detector and loop filter (PD / LF), the phase detector and loop filter (PD / LF) including a phase / frequency detector including a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and an output configured to generate an output signal based on the reference signal and the feedback signal; a first capacitor; and a charge pump, the charge pump including: a charging path configured to generate a charging current to charge the first capacitor based on the output signal; and a discharge path including a first resistor configured to discharge the first capacitor.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to pending U.S. non - provisional application Ser. No. 18 / 086,565, filed on Dec. 21, 2022, which is assigned to the assignee of the present application and is hereby incorporated by reference in its entirety as if set forth in full herein and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure generally relate to phase - locked loops (PLLs), and more particularly to high - gain, low - power phase detectors and loop filters (PD / LFs) for PLLs. Background Art

[0004] A phase - locked loop (PLL) can be used in a wireless communication system to generate a clock signal or a local oscillator (LO) signal for controlling the transmission and / or reception of data signals. It may be necessary to generate a clock or LO signal with specific low reference spurious and phase noise requirements to ensure the successful transmission and / or reception of data signals. In some PLLs, the low reference spurious and phase noise requirements can be met by employing a phase detector and loop filter (PD / LF) with a relatively high phase - detection (PD) gain. Summary of the Invention

[0005] The following presents a simplified summary of one or more specific implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations and is not intended to identify key or critical elements of all implementations nor to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more specific implementations in a simplified form as a prelude to the more detailed description that follows.

[0006] One aspect of the present disclosure relates to an apparatus. The apparatus includes: a phase - locked loop (PLL) that includes: a phase detector and loop filter (PD / LF) that includes: a phase / frequency detector that includes a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and an output configured to generate an output signal based on the reference signal and the feedback signal; a first capacitor; and a charge pump that includes: a charging path configured to generate a charging current based on the output signal to charge the first capacitor; and a discharging path that includes a first resistor configured to discharge the first capacitor.

[0007] Another aspect of the present disclosure relates to a method for generating a frequency control signal for a voltage controlled oscillator (VCO). The method includes: generating a phase difference signal based on a reference signal and a feedback signal, where the feedback signal is based on a VCO signal generated by the VCO; partially discharging a first capacitor from a first voltage to a second voltage higher than the ground potential during a discharge phase; and charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, where the frequency control signal is based on the third voltage.

[0008] Another aspect of the present disclosure relates to an apparatus for generating a frequency control signal for a voltage controlled oscillator (VCO). The apparatus includes: means for generating a phase difference signal based on a reference signal and a feedback signal, where the feedback signal is based on a VCO signal generated by the VCO; means for partially discharging a first capacitor from a first voltage to a second voltage higher than the ground potential during a discharge phase; and means for charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, where the frequency control signal is based on the third voltage.

[0009] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a phase locked loop (PLL) coupled to the one or more signal processing cores. The PLL further includes a phase detector and a loop filter (PD / LF), and the phase detector and the loop filter (PD / LF) include: a phase / frequency detector including a first input configured to receive a reference signal, a second input configured to receive a feedback signal, and an output configured to generate an output signal based on the reference signal and the feedback signal; a first capacitor; and a charge pump including: a charging path configured to generate a charging current based on the output signal to charge the first capacitor; and a discharging path including a first resistor configured to discharge the first capacitor.

[0010] To achieve the foregoing and related purposes, one or more specific embodiments include the features that are fully described hereinafter and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative aspects of one or more specific embodiments. However, these aspects are merely indicative of the various ways in which the principles of the various specific embodiments may be employed, and the specification of the specific embodiments is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A block diagram of an example phase-locked loop (PLL) in accordance with one aspect of the present disclosure is illustrated.

[0012] Figure 2A A block diagram / schematic diagram of an example phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure is illustrated.

[0013] Figure 2B An example is illustrated depicting signals related to the example operation of a phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure and Figure 2A thereof.

[0014] Figure 3A A block diagram / schematic diagram of another example phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure is illustrated.

[0015] Figure 3B An example is illustrated depicting signals related to the example operation of a phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure and Figure 3A thereof.

[0016] Figure 4 A block diagram of another example phase-locked loop (PLL) in accordance with another aspect of the present disclosure is illustrated.

[0017] Figure 5A A block diagram / schematic diagram of another example phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure is illustrated.

[0018] Figure 5B An example is illustrated depicting signals related to the example operation of a phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure and Figure 5A thereof.

[0019] Figure 6A A block diagram / schematic diagram of another example phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure is illustrated.

[0020] Figure 6B An example is illustrated depicting signals related to the example operation of a phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure and Figure 6A thereof.

[0021] Figure 7 A block diagram / schematic diagram of another example phase detector and loop filter (PD / LF) in accordance with another aspect of the present disclosure is illustrated.

[0022] Figure 8A flowchart illustrating an example method for generating a frequency control signal for a voltage controlled oscillator (VCO) in accordance with another aspect of the present disclosure.

[0023] Figure 9 A block diagram illustrating an example wireless communication device in accordance with another aspect of the present disclosure. Detailed Description

[0024] The following detailed description presented in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0025] Figure 1 A block diagram illustrating an example phase locked loop (PLL) 100 in accordance with one aspect of the present disclosure. PLL 100 includes a first divider 110, a phase detector and loop filter 120 (collectively referred to herein as "PD / LF"), a voltage controlled oscillator (VCO) 130, a buffer 140, a second divider 150, and a lock detector 160. It should be understood that the specific implementation of PLL 100 may vary significantly depending on the specifications and performance requirements.

[0026] Divider 110 is configured to receive an input reference (clock) signal N·f ref (e.g., a substantially periodic signal), and divide the reference signal N·f ref by a division ratio N to generate a reference signal f ref , where the division ratio N may be an integer. PD / LF 120 is configured to receive the reference signal f ref and a feedback signal f fb at respective first and second inputs, compare the phase / frequency of the reference signal f ref and the feedback signal f fb , and generate a frequency control signal vco_vctrl based on the phase / frequency difference between the reference signal f ref and the feedback signal f ref . VCO 130 is configured to generate a VCO (clock) signal f vco based on the frequency control signal vco_vctrl; the VCO signal f vco is output by buffer 140.

[0027] Second divider 150 is configured to receive the VCO signal f vcoand divides the VCO signal f by a division ratio L vco to generate a feedback signal f fb , where the division ratio L can also be an integer or a fraction. The lock detector 160 is configured to generate a set pll_lock_det signal when the PLL 100 is in a locked state (and a reset pll_lock_det signal when the PLL 100 is not in a locked state). That is, in the locked state, the PD / LF 120 generates a frequency control signal vco_vctrl such that (based on the VCO signal f vco and the division ratio L generated (e.g., f fb = f vco / L)) the feedback signal f fb has a phase / frequency that is substantially the same as or locked to the phase / frequency of the reference signal f ref .

[0028] The PLL 100 can be implemented with different transfer functions depending on the specific implementation of the loop filter. For example, the PLL 100 can be implemented as a type IPLL, where the transfer function includes one integrator provided by the VCO. Alternatively, the PLL 100 can be implemented as a type IIPLL, where the transfer function includes two integrators provided by the VCO and a charge pump with a loop filter. The type IPLL has a higher bandwidth than the type IIPLL and can be able to reduce phase noise better than the type IIPLL. Additionally, the type IIPLL typically requires a larger capacitor, which is difficult to implement in an integrated circuit (IC) and is typically implemented as an off-chip capacitor. However, the capacitance requirements of the type IPLL are much smaller, and the loop filter capacitor can be implemented on-chip.

[0029] The type IPLL typically requires a higher phase detector (PD) gain to achieve good phase noise performance. As further discussed herein, two PD / LF architectures have been used to implement a high PD gain to increase the loop gain.

[0030] Figure 2A Illustrates a block diagram / schematic diagram of an example phase detector and loop filter (PD / LF) 200 according to another aspect of the present disclosure. The PD / LF 200 can be an example implementation of the PD / LF 120 of the PLL 100. Specifically, the PD / LF 200 includes a phase / frequency detector 210, a control circuit 220, a charge pump 230 including a current source Icp, a first switching device SW1, and a second switching device SW2, a first capacitor C1, a second capacitor C2, and a third switching device SW3. The phase / frequency detector 210 includes being configured to receive a reference signal V ref and a feedback signal V fbinput, and configured to generate an output of an up-signal based on a phase / frequency difference between a reference signal V ref and a feedback signal V fb between them.

[0031] Regarding the charge pump 230, a current source Icp, a first switching device SW1, and a second switching device SW2 are serially coupled between an upper voltage rail Vdd and a lower voltage rail (e.g., ground or another negative voltage compared to the supply voltage on the upper voltage rail, which may be referred to as "ground" hereinafter). The current source Icp and the first switching device SW1 constitute a charging path of the charge pump 230, and the second switching device SW2 constitutes a discharging path of the charge pump 230. The on / off (e.g., closed / open) state of the first switching device SW1 is controlled by the up-signal generated by the phase / frequency detector 210. A control circuit 220 may be included and configured to receive a reference signal V ref and a feedback signal V fb at corresponding inputs, and is configured to generate a control signal φrst for controlling the on / off (e.g., closed / open) state of the second switching device SW2 based on the reference signal V ref .

[0032] A first capacitor C1 is coupled between a first node n1 (between the first switching device SW1 and the second switching device SW2 of the charge pump 230) and ground. A third switching device SW3 is coupled between the first node n1 and a second node n2. The control circuit 220 is configured to generate a control signal φh for controlling the on / off (e.g., closed / open) state of the third switching device SW3 based on the feedback signal V fb . A second capacitor C2 is coupled between the second node n2 and ground. As further discussed herein, a sampled signal or voltage vsmp is generated at the first node n1, and a frequency control signal or voltage vco_vctrl is generated at the second node n2. The operation of the PD / LF 200 is discussed below:

[0033] Figure 2B Illustrates a graph depicting signals related to an example operation of the PD / LF 200 according to another aspect of the present disclosure. The x-axis or horizontal axis represents time. The y-axis or vertical axis represents the voltage levels of the reference signal V ref , the feedback signal V fb , the up-signal, the control signal φh, the control signal φrst, the sampled signal vsmp, and the frequency control signal vco_vctrl from top to bottom.

[0034] Referring to the reference signal V ref and the feedback signal V fb in the top two sections of the graph, the reference signal V ref and the feedback signal Vfb The phase difference between is visualized, where the reference signal V ref presents a rising edge at time t1, and the feedback signal V fb presents a rising edge at time t2. Thus, the time interval t1 - t2 is related to the phase difference between the reference signal V ref and the feedback signal V fb The phase / frequency detector 210 detects the phase difference by setting the upper signal (e.g., to a high logic level) between time t1 and time t2. In response to the set upper signal, the first switching device SW1 is turned on to couple the current source Icp to the first capacitor C1 to charge the first capacitor (e.g., enable the charging path). Additionally, in response to the reference signal V ref going high at time t1, the control circuit 220 resets the control signal φrst (e.g., to a low logic level) to turn off the second switching device SW2 (e.g., disable the discharging path). Thus, when the phase / frequency detector 210 resets the upper signal due to both the reference signal V ref and the feedback signal V fb being at the same logic level or a high logic level, the sampled signal vsmp increases from 0 V at time t1 to the peak voltage Vpk at time t2.

[0035] Subsequently, at time t2, when the feedback signal V fb presents a rising edge and the upper signal becomes reset, the control circuit 220 sets the control signal φh (e.g., to a high logic level) to turn on the third switching device SW3, and distributes the charge accumulated on the first capacitor C1 between the first capacitor C1 and the second capacitor C2 during the charging phase to form / adjust the frequency control signal or voltage vco_vctrl across both the capacitor C1 and the capacitor C2; and the first switching device SW1 is turned off in response to the upper signal becoming reset. Subsequently, at time t3 (e.g., a defined time after time t2 when the charge is sufficiently distributed between the capacitor C1 and the capacitor C2), the control circuit 220 resets the control signal φh to disconnect the third switching device SW3 and sets the control signal φh to close the second switching device SW2 (e.g., enable the discharging path). The closing of the second switching device SW2 fully discharges the capacitor C1, causing the sampled signal vsmp to decrease to substantially zero (0) volts (V). This resets the capacitor C1 for the next charging phase.

[0036] The PD gain of the PD / LF 200 can be defined as the peak Vpk of the sampled signal vsamp and the reference signal V ref and the feedback signal V fbThe ratio of the phase difference as indicated by the time interval t1 - t2 (e.g., PD gain = Vpk / (t1 - t2)). The peak voltage Vpk is directly related to the charging current Icp. Thus, in the PD / LF 200, one way to increase the PD gain to improve the phase noise performance of the VCO 130 is to increase the charging current Icp.

[0037] Figure 3A A block / schematic diagram of another exemplary phase detector and loop filter (PD / LF) 300 in accordance with another aspect of the present disclosure is illustrated. The PD / LF 300 may be another exemplary implementation of the PD / LF 120 of the PLL 100. Specifically, the PD / LF 300 includes an exclusive-NOR (XNOR) gate 310 serving as a phase / frequency detector, a non-overlapping clock generator 320, a charge pump 330 including a first field-effect transistor (FET) MP1 (e.g., a p-channel metal-oxide-semiconductor FET or PMOS FET), a second FET MN1 (e.g., an n-channel metal-oxide-semiconductor FET or NMOS FET), a first switching device SW1 and a second switching device SW2, and a first capacitor C1 and a second capacitor C2.

[0038] The XNOR gate 310 is configured to generate / output a signal xnor based on the phase difference between a reference signal V ref and a feedback signal V fb received at its respective inputs. The charge pump 330 includes an input coupled to the output of the XNOR gate 310 to receive the xnor signal from the output. The FET MP1 and the FET MN1 are serially coupled between an upper voltage rail Vdd and a lower voltage rail (e.g., ground). That is, the FET MP1 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the output of the XNOR gate 310, and a drain coupled to the drain of the FET MN1 at a first node n1 (e.g., the output of the charge pump 330). The FET MN1 includes a gate coupled to the output of the XNOR gate 310 (e.g., the coupled gates of the FET MP1 and MN1 serve as the input of the charge pump 330) and a source coupled to ground.

[0039] The first switching device SW1 is coupled between the first node n1 and a second node n2. The first capacitor C1 is coupled between the second node n2 and ground. The second switching device SW2 is coupled between the second node n2 and a third node n3. The non-overlapping clock generator 320, which may include an input configured to receive the feedback signal V fb is configured to generate complementary clock signals φ1 and φ2 for use based on the feedback signal V fbto separately control the on / off (e.g., closed / open) states of the first switching device SW1 and the second switching device SW2. As further discussed herein, the sampled signal vsmp is generated at the second node n2, and the frequency control signal or voltage vco_vctrl is generated at the third node n3. The operation of the PD / LF 300 is discussed below:

[0040] Figure 3B Illustrated is a graph depicting signals related to an example operation of the PD / LF 300 in accordance with another aspect of the present disclosure. The x-axis or horizontal axis represents time. The y-axis or vertical axis represents the voltage levels of the reference signal V ref and the feedback signal V fb from top to bottom, the xnor signal, the non-complementary clock signal φ1, the complementary clock signal φ2, the sampled signal vsmp, and the frequency control signal vco_vctrl.

[0041] According to the discharge phase between time t1 and time t2, the non-overlapping clock generator 320 generates the non-complementary clock signal φ1 and the complementary clock signal φ2 at a set (e.g., high) logic level and a reset (e.g., low) logic level, respectively. The high clock signal φ1 turns on the first switching device SW1 to discharge the first capacitor C1, and the low clock signal φ2 turns off the second switching device SW2 to isolate the discharge phase of the second capacitor C2 from the first capacitor C1. Additionally, between time t1 and time t2, in response to the reference signal V ref and the feedback signal V fb both being at the same (e.g., high) logic level, the XNOR gate 310 generates an xnor signal at a high logic level. The high xnor signal turns off the FET MP1 (e.g., disables the charging path) and turns on the FET MN1 to couple the upper end of the first capacitor C1 at the node n2 to ground (e.g., enables the discharge path) via the first switching device SW1, so as to fully discharge the first capacitor C1. As illustrated in the graph, the sampled voltage vsmp starts to discharge to 0V at time t1.

[0042] Referring to the reference signal V ref and the feedback signal V fb in the top two sections of the graph, the phase difference between the reference signal V ref and the feedback signal V fb is visualized, where the reference signal V ref presents a falling edge at time t2, and the reference signal V fb presents a falling edge at time t3. Thus, the time interval t2 - t3 is related to the reference signal V ref and the feedback signal V fbis related to the phase difference therebetween. The XNOR gate 310 detects the phase difference by setting the xnor signal to a set (e.g., low) logic level between time t2 and time t3. In response to the low logic signal xnor, the FET MP1 is turned on (e.g., enabling the charging path), and the FET MN1 is turned off (e.g., disabling the discharging path). The turned-on FET MP1 couples the upper voltage rail Vdd to the first capacitor C1 to charge the first capacitor. Thus, when the XNOR gate 310 detects that both the reference signal V ref and the feedback signal V fb are at the same (e.g., low) logic level, the sampled signal vsmp increases from 0V at time t2 to the peak voltage Vpk at time t3 and generates an xnor signal at a reset (e.g., high) logic level.

[0043] Subsequently, at time t3, when the clock signals φ1 and φ2 become reset (e.g., low) and set (e.g., high) respectively, the first switching device SW1 and the second switching device SW2 are turned off and on respectively. The turned-on second switching device SW2 distributes the charge accumulated on the first capacitor C1 during the charging phase between the first capacitor C1 and the second capacitor C2 to form / adjust the frequency control signal or voltage vco_vctrl across both the capacitor C1 and the capacitor C2. In response to the high xnor signal at time t3, the turned-off first switching device SW1 isolates the capacitor C1 and the capacitor C2 from the ground via the turned-on FET MN1.

[0044] Similarly, the PD gain of the PD / LF 300 can be defined as the ratio of the peak Vpk of the sampled signal vsamp to the phase difference indicated by the time interval t2 - t3 between the reference signal V ref and the feedback signal V fb (e.g., PD gain = Vpk / (t2 - t3)). The peak voltage Vpk is directly related to the supply voltage Vdd, the on-resistance of the FET MP1, and the resistance of the turned-on first switching device SW1. Since Vdd can be constant and the on-resistance of the first switching device SW1 can have a substantially small resistance, in the PD / LF 300, one way to increase the PD gain to improve the phase noise performance of the VCO 130 is to increase the size of the FET MP1 to reduce its on-resistance.

[0045] Figure 4A block diagram of another exemplary phase-locked loop (PLL) 400 is illustrated in accordance with another aspect of the present disclosure. The PLL 400 includes a phase detector and loop filter (PD / LF) 430, a voltage-controlled oscillator (VCO) 440, and other PLL components 450 (such as buffers, dividers (e.g., integer dividers or fractional dividers), Σ-Δ modulators, lock detectors, etc.). The PD / LF 430 includes inputs configured to receive a reference signal V ref and a feedback signal V fb , and to generate a frequency control signal vco_vctrl based on a phase difference between the reference signal V ref and the feedback signal V fb . The VCO 440 is configured to generate a VCO signal V vco based on the frequency control signal vco_vctrl. The other PLL components 450 may include a buffer for outputting the VCO signal V vco , and at least one divider configured to generate the feedback signal V vco based on the VCO signal V fb (e.g., by dividing the VCO signal).

[0046] To supply power to the PD / LF 430 and the VCO 440, the PLL 400 further includes or is associated with the following: a power supply 410 and a first low-dropout (LDO) regulator 415, a second low-dropout (LDO) regulator 420, and a third low-dropout (LDO) regulator 425. The power supply 410, which may be implemented as a power management integrated circuit (PMIC), is configured to generate a first supply voltage Vdd1. The first LDO regulator 415 is configured to generate a second supply voltage Vdd2 based on the first supply voltage Vdd1. The second LDO regulator 420 is configured to generate a third supply voltage Vdd3 for the PD / LF 430 based on the second supply voltage Vdd2. Similarly, the third LDO regulator 425 is configured to generate a fourth supply voltage Vdd4 for the VCO 440 based on the second supply voltage Vdd2.

[0047] As discussed with reference to the PD / LF 200 and 300, a higher PD gain generally improves the phase noise characteristics of the VCO 440. Additionally, as previously mentioned, implementing a higher PD gain in the PD / LF 200 and 300 generally involves increasing the charging current, such as by increasing the current supplied by the current source Icp in the PD / LF 200 or increasing the size of the FET MP1 in the PD / LF 300.

[0048] However, increasing the charging current in PD / LFs 200 and 300 typically generates a voltage ripple on the corresponding power supply Vdd3, for example, as represented by a triangular waveform juxtaposed with the third supply voltage Vdd3. As discussed, the voltage ripple is the result of the first capacitor C1 being periodically charged and discharged to generate a frequency control signal vco_vctrl based on the phase difference between the reference signal V ref and the feedback signal V fb .

[0049] Typically, the second LDO regulator 420 is not ideal; and thus, the voltage ripple generated in the third supply voltage Vdd3 propagates to the second supply voltage Vdd2, as indicated by the dashed arrow line. Similarly, the third LDO regulator 425 is also not ideal; and thus, the voltage ripple that has propagated to the second supply voltage Vdd2 propagates to the fourth supply voltage Vdd4 for the VCO 440, also as indicated by the dashed arrow line. The voltage ripple on the VCO supply voltage Vdd4 adversely affects the reference spurious and phase noise characteristics of the VCO 440. Therefore, any VCO characteristic benefit achieved by increasing the charging current to increase the PD gain in PD / LF 430 may have an adverse effect on the VCO characteristics due to the increased voltage ripple resulting from the higher charging current.

[0050] Figure 5A A block diagram / schematic illustration of another exemplary phase detector and loop filter (PD / LF) 500 in accordance with another aspect of the present disclosure is shown. As discussed further in more detail herein, compared to PD / LFs 200 and 300 that improve the phase detection (PD) gain based on the charging phase of the first capacitor C1, PD / LF 500 improves the PD gain based on the discharging phase of the first capacitor C1. However, it should be understood that PD / LF 500 can improve the PD gain based on both the charging phase and the discharging phase of the first capacitor C1.

[0051] Specifically, PD / LF 500 is a variant of the previously discussed PD / LF 300 and includes many of the same / similar components, such as: an XNOR gate 510 configured to generate an xnor signal based on the phase difference between the reference signal V ref and the feedback signal V fb ; a non-overlapping clock generator 520 configured to generate non-overlapping clock signals based on the feedback signal V fbto generate complementary clock signals φ1 and φ2; a first switching device SW1, the on / off state of which is controlled by the non-complementary clock signal φ1, and which is coupled between a first node n1 and a second node n2; a first capacitor C1, which is coupled between the second node n2 and a lower voltage rail (e.g., ground); a second switching device SW2, the on / off state of which is controlled by the complementary clock signal φ2, and which is coupled between the second node n2 and a third node n3; and a second capacitor C2, which is coupled between the third node n3 and ground. The sampled signal vsmp and the frequency control signal vco_vctrl are generated at the nodes n2 and n3, respectively.

[0052] As discussed above, the PD / LF 500 improves the PD gain based on the discharge phase of the first capacitor C1. In this regard, the PD / LF 500 includes a charge pump 530, which includes a first FET MP1 (e.g., a PMOS FET), a resistor R1 (which may be a variable resistor), and a second FET MN1 (e.g., an NMOS FET) that are coupled in series between the upper voltage rail Vdd and ground. That is, the first FET MP1 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the output of the XNOR gate 510, and a drain coupled to the node n1 (e.g., the output of the charge pump 530). Thus, the FET MP1 constitutes the charging path of the charge pump 530. The resistor R1 is coupled between the node n1 and the drain of the FET MN1. Thus, the resistor R1 and the FET MN1 constitute the discharging path of the charge pump 530. The FET MN1 includes a gate that is also coupled to the output of the XNOR gate 510 and that serves as an input to the charge pump 530 together with the gate of the FET MP1. The FET MN1 includes a source coupled to ground.

[0053] As discussed in more detail with reference to the signal timing diagram discussed below, the resistor R1 can cause the first capacitor C1 to partially discharge during the discharge phase. In doing so, the sampled voltage vsmp at the top of the first capacitor C1 (at the node n2) does not discharge all the way to ground (0V), but discharges to a voltage Vst that is higher than ground. Thus, in the next charging phase, the sampled voltage vsmp starts at the voltage Vst and rises according to the charging current to produce a sampled voltage vsmp with a higher peak Vpk. Since the PD gain of the PD / LF 500 is directly related to the peak Vpk of the sampled voltage vsmp, a higher PD gain can be achieved by controlling the discharge of the first capacitor C1 via the variable resistor R1.

[0054] Figure 5BIllustrates a graph depicting signals related to an example operation of the PD / LF 500 in accordance with another aspect of the present disclosure. The x-axis or horizontal axis represents time. The y-axis or vertical axis represents the voltage levels of the reference signal V ref , the feedback signal V fb , the xnor signal, the non-complementary clock signal φ1, the complementary clock signal φ2, the sampled signal vsmp, and the frequency control signal vco_vctrl.

[0055] During the discharge phase between time t1 and time t2, the non-overlapping clock generator 520 generates the non-complementary clock signal φ1 and the complementary clock signal φ2 at a set (e.g., high) logic level and a reset (e.g., low) logic level, respectively. The high clock signal φ1 turns on the first switching device SW1 to discharge the first capacitor C1, and the low clock signal φ2 turns off the second switching device SW2 to isolate the second capacitor C2 from the discharge phase of the first capacitor C1. Additionally, between time t1 and time t2, in response to the reference signal V ref and the feedback signal V fb both being at the same (e.g., high) logic level, the XNOR gate 510 generates an xnor signal at a high logic level. The high xnor signal turns off the FET MP1 (e.g., disables the charging path) and turns on the FET MN1 to couple the upper end of the first capacitor C1 at node n2 to ground (e.g., enables the discharge path) via the first switching device SW1 and the resistor R1.

[0056] As illustrated in the graph, the sampled voltage vsmp starts to discharge at time t1. In this case (e.g., in contrast to the operation of the PD / LF 300), the resistor R1 reduces the discharge rate of the first capacitor C1 such that the sampled signal vsmp does not discharge all the way to ground but discharges to a starting voltage Vst above ground (e.g., Vst > 0V). Thus, as discussed below, when the charging phase begins, the sampled signal vsmp is at Vst, which achieves a higher peak voltage Vpk for the sampled signal vsmp. The resistor R1 can be variable to set the starting voltage Vst.

[0057] For example, referring to the reference signal V ref and the feedback signal V fb in the top two segments of the graph, the phase difference between the reference signal V ref and the feedback signal V fb is visualized, where the reference signal V ref presents a falling edge at time t2, and the reference signal V fb presents a falling edge at time t3. Thus, the time interval t2 - t3 is related to the reference signal V ref and the feedback signal V fbis related to the phase difference therebetween. The XNOR gate 510 detects the phase difference by setting the xnor signal to a set (e.g., low) logic level between time t2 and time t3. In response to the low logic signal xnor, the FET MP1 is turned on (e.g., enabling the charge path), and the FET MN1 is turned off (e.g., disabling the discharge path). The turned-on FET MP1 couples the upper voltage rail Vdd to the first capacitor C1 to charge the first capacitor. Thus, when the XNOR gate 510 detects that both the reference signal V ref and the feedback signal V fb are at the same (e.g., low) logic level, the sampled signal vsmp increases from Vst at time t2 to the peak voltage Vpk at time t3 and a xnor signal at a reset (e.g., high) logic level is generated.

[0058] Subsequently, at time t3, when the clock signals φ1 and φ2 respectively become reset (e.g., low) and set (e.g., high), the first switching device SW1 and the second switching device SW2 are respectively turned off and on. The turned-on second switching device SW2 distributes the charge accumulated on the first capacitor C1 during the charging phase between the first capacitor C1 and the second capacitor C2 to form / adjust the frequency control signal or voltage vco_vctrl across both the capacitor C1 and the capacitor C2. In response to the high xnor signal at time t3, the turned-off first switching device SW1 isolates the capacitor C1 and the capacitor C2 from the ground via the turned-on FET MN1.

[0059] Therefore, by partially discharging the capacitor C1 during the discharge phase between time t1 and time t2, the subsequent charging phase between time t2 and time t3 starts with the sampled voltage vsmp, which starts with a voltage Vst higher than the ground potential (0V). This allows for achieving a higher peak voltage Vpk, which produces a higher PD gain (e.g., Vpk / (t2 - t3)) for reducing reference spurs and phase noise in the VCO signal Vvco. Additionally, since the increase in the PD gain is not due to an increase in the charging current, it may not have an adverse effect on the voltage ripple in the supply rail Vdd4 of the VCO 440, thus not affecting the reference spur and phase noise characteristics of the VCO 440. Furthermore, since the charging current does not need to increase and can even be reduced, the PD / LF 500 consumes significantly less power while achieving a higher PD gain.

[0060] Figure 6AA block diagram / schematic diagram of another exemplary phase detector and loop filter (PD / LF) 600 in accordance with another aspect of the present disclosure is illustrated. The PD / LF 600 may be an exemplary embodiment of the PD / LF 120 of the PLL 100. Similar to the PD / LF 500, compared with the PD / LF 200 and 300 that improve the phase detection (PD) gain based on the charging phase of the first capacitor C1, the PD / LF 600 improves the PD gain based on the discharging phase of the first capacitor C1. However, it should be understood that the PD / LF 600 may improve the PD gain based on both the charging phase and the discharging phase of the first capacitor C1.

[0061] Specifically, the PD / LF 600 includes a phase / frequency detector 610, a control circuit 620, and a charge pump 530 including a current source Icp, a first switching device SW1, a second switching device SW2, and a resistor R1 (e.g., which may be a variable resistor). The PD / LF 600 further includes a third switching device SW3, as well as a first capacitor C1 and a second capacitor C2. The phase / frequency detector 610 includes inputs configured to receive a reference signal V ref and a feedback signal V fb respectively, and an output for generating an up signal based on the phase / frequency difference between the reference signal V ref and the feedback signal V fb .

[0062] Regarding the charge pump 230, the current source Icp, the first switching device SW1, the resistor R1, and the second switching device SW2 are serially coupled between an upper voltage rail Vdd and a lower voltage rail (e.g., ground). The current source Icp and the first switching device SW1 constitute a charging path of the current source 630, and the resistor R1 and the second switching device SW2 constitute a discharging path of the current source 630. The on / off (e.g., closed / open) state of the first switching device SW1 is controlled by the up signal generated by the phase / frequency detector 610. The control circuit 620, which may include corresponding inputs configured to receive the reference signal V ref and the feedback signal V fb , is configured to generate a control signal φrst for controlling the on / off (e.g., closed / open) state of the second switching device SW2 based on the reference signal V ref .

[0063] The first capacitor C1 is coupled between a first node n1 (between the first switching device SW1 of the charge pump 630 and the resistor R1) and ground. The third switching device SW3 is coupled between the first node n1 and a second node n2. The control circuit 620 is configured to be based on the feedback signal V fbto generate a control signal φh for controlling the on / off (e.g., closed / open) state of the third switching device SW3. The second capacitor C2 is coupled between the second node n2 and ground. As further discussed herein, the sampled signal or voltage vsmp is generated at the first node n1, and the frequency control signal or voltage vco_vctrl is generated at the second node n2. The operation of the PD / LF 600 is discussed below:

[0064] Figure 6B A graph is illustrated depicting example signals related to an example operation of the PD / LF 600 according to another aspect of the present disclosure. The x-axis or horizontal axis represents time. The y-axis or vertical axis represents the voltage levels of the reference signal V ref 、feedback signal V fb 、upper signal, control signal φh, control signal φrst, sampled signal vsmp, and frequency control signal vco_vctrl from top to bottom.

[0065] Referring to the reference signal V ref and feedback signal V fb in the top two sections of the reference graph, the phase difference between the reference signal V ref and the feedback signal V fb is visualized, where the reference signal V ref presents a rising edge at time t1, and the reference signal V fb presents a rising edge at time t2. Thus, the time interval t1 - t2 is related to the phase difference between the reference signal V ref and the feedback signal V fb The phase / frequency detector 610 detects the phase difference by setting the upper signal (e.g., to a high logic level) between time t1 and time t2. In response to the set upper signal, the first switching device SW1 is turned on to couple the current source Icp to the first capacitor C1 to charge the first capacitor (e.g., enable the charging path). Further, in response to the reference signal V ref becoming high at time t1, the control circuit 620 resets the signal φrst (e.g., to a low logic level) to turn off the second switching device SW2 (e.g., disable the discharging path). Thus, when the phase / frequency detector 610 resets the upper signal due to both the reference signal V ref and the feedback signal V fb being at the same logic level or high logic level, the sampled signal vsmp increases from the starting voltage Vst at time t1 (e.g., Vst > 0V) to the peak voltage Vpk at time t2.

[0066] Subsequently, at time t2, when the feedback signal V fbWhen a rising edge is presented and the up signal becomes reset, the control circuit 620 sets the control signal φh (e.g., to a high logic level) to turn on the third switching device SW3 and distributes the charge accumulated on the first capacitor C1 between the first capacitor C1 and the second capacitor C2 during the charging phase to form / adjust a frequency control signal or voltage vco_vctrl across both the capacitor C1 and the capacitor C2; and the first switching device SW1 is turned off in response to the up signal becoming reset. Subsequently, at time t3 (e.g., a defined time after time t2 at which the charge is sufficiently distributed between the capacitor C1 and the capacitor C2), the control circuit 620 resets the control signal φh to turn off the third switching device SW3 and sets the control signal φh to close the second switching device SW2 (e.g., enabling a discharge path). The closing of the second switching device SW2 partially discharges the capacitor C1 via the variable resistor R1 such that the sampled signal vsmp is reduced to the starting voltage Vst. The resistor R1 can be variable to set the starting voltage Vst.

[0067] Thus, by partially discharging the capacitor C1 during the discharge phase, the charging phase between time t1 and time t2 starts with the sampled voltage vsmp, which starts at a starting voltage Vst higher than the ground potential (0V). This allows for achieving a higher peak voltage Vpk, which results in a higher PD gain (e.g., Vpk / (t1 - t2)) for reducing reference spurs and phase noise in the VCO signal Vvco. Additionally, since the increase in PD gain is not due to an increase in the charging current, it may not have an adverse effect on the voltage ripple in the supply rail Vdd4 of the VCO 440, thus not affecting the reference spur and phase noise characteristics of the VCO 440. Further, since the charging current does not need to increase and can even be reduced, the PD / LF 600 can consume significantly less power while achieving a higher PD gain.

[0068] Figure 7 A block diagram / schematic illustration of another exemplary phase detector and loop filter (PD / LF) 700 in accordance with another aspect of the present disclosure is shown. The PD / LF 700 is a variant of the previously discussed PD / LF 500, where the PD / LF 700 further includes a resistor in the charge path to reduce PD gain variations due to the non - linear on - resistance of the FET MP1.

[0069] Specifically, the PD / LF 700 includes: an XNOR gate 710 configured to generate an xnor signal based on the phase difference between a reference signal V ref and a feedback signal V fb ; a non - overlapping clock generator 720 configured to generate non - overlapping clock signals based on the feedback signal Vfb to generate complementary clock signals φ1 and φ2; a first switching device SW1, the on / off state of which is controlled by the non-complementary clock signal φ1, and which is coupled between a first node n1 and a second node n2; a first capacitor C1, which is coupled between the second node n2 and a lower voltage rail (e.g., ground); a second switching device SW2, the on / off state of which is controlled by the complementary clock signal φ2, and which is coupled between the second node n2 and a third node n3; and a second capacitor C2, which is coupled between the third node n3 and ground. A sampled signal vsmp and a frequency control signal vco_vctrl are generated at nodes n2 and n3, respectively.

[0070] As discussed above, the PD / LF 700 controls the PD gain based on the charging and discharging phases of the first capacitor C1. In this regard, the PD / LF 700 includes a charge pump 730, which includes a first FET MP1 (e.g., a PMOS FET) serially coupled between an upper voltage rail Vdd and ground, a first resistor R1 (which may be a variable resistor), a second resistor R2 (which may also be a variable resistor), and a second FET MN1 (e.g., an NMOS FET). That is, the first FET MP1 includes a source coupled to the upper voltage rail Vdd and a gate coupled to an input of the XNOR gate 710. The first resistor R1 is coupled between the drain of the first FET MP1 and the node n1 (e.g., the output of the charge pump 730). The second resistor R2 is coupled between the node n1 and the drain of the FET MN1. The FET MN1 includes a gate, which is also coupled to the output of the XNOR gate 710 and which, together with the gate of the FET MP1, serves as an input to the charge pump 730. The FET MN1 includes a source coupled to ground.

[0071] The first resistor R1 may be variable to control the charging phase of the first capacitor C1. The second resistor R2 may partially discharge the first capacitor C1 during the discharging phase. In doing so, the sampled voltage vsmp at the top of the first capacitor C1 (at node n2) does not discharge all the way to ground (0V), but discharges to a certain voltage Vst above ground. Thus, in the next charging phase, the sampled voltage vsmp starts at the voltage Vst and rises according to the charging current to produce a sampled voltage vsmp with a higher peak Vpk. Since the PD gain of the PD / LF 700 is directly related to the peak Vpk of the sampled voltage vsmp, a higher PD gain can be achieved by controlling the discharging of the first capacitor C1 via the variable resistor R2. The resistor R2 may be variable to set the starting voltage Vst.

[0072] Figure 8A flowchart illustrating an example method 800 of generating a control signal for a voltage controlled oscillator (VCO) in accordance with another aspect of the present disclosure is shown. The method 800 includes generating a phase difference signal based on a reference signal and a feedback signal, where the feedback signal is based on a VCO signal generated by the VCO (block 810). Examples of components for generating a signal based on the phase difference between the reference signal and the feedback signal include any of the phase / frequency detectors 210, 310, 510, 610, and 710 described herein.

[0073] The method 800 further includes partially discharging a first capacitor from a first voltage to a second voltage above ground potential during a discharge phase (block 820). Examples of components for partially discharging a first capacitor from a first voltage to a second voltage above ground potential during a discharge phase include the discharge paths of charge pumps 530, 630, and 730.

[0074] Additionally, the method 800 includes charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, where a frequency control signal is based on the third voltage (block 830). Examples of components for charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase include the charge paths of charge pumps 530, 630, and 730, where the frequency control signal is based on the third voltage.

[0075] Although not explicitly illustrated, the method 800 may include using a second capacitor to distribute the charge on the first capacitor to form a fourth voltage across the first capacitor and the second capacitor when the first capacitor is charged to the third voltage, where the frequency control signal is based on the third voltage. Examples of components for using a second capacitor to distribute the charge on the first capacitor to form a fourth voltage across the first capacitor and the second capacitor when the first capacitor is charged to the third voltage include the switching device SW2 of PD / LF 500 and 700 and the switching device SW3 of PD / LF 600.

[0076] Additionally, method 800 may include controlling partial discharge of the first capacitor, including controlling the resistance of the discharge path between the first capacitor and ground. Examples of components for controlling the resistance of the discharge path between the first capacitor and ground include variable resistor R1 in PD / LF 500 and 600 and variable resistor R2 in PD / LF 700. Method 800 may also include controlling charging of the first capacitor, including controlling the resistance of the charge path between the upper voltage rail and the first capacitor. Examples of components for controlling charging of the first capacitor include variable resistor R1 of PD / LF 700, and this control includes controlling the resistance of the charge path between the upper voltage rail and the first capacitor. Additionally, method 800 may include controlling partial discharge of the first capacitor based on a phase difference signal. Examples of components for controlling partial discharge of the first capacitor based on a phase difference signal include XNOR gates 510 and 710.

[0077] Figure 9 A block diagram of an example wireless communication device 900 in accordance with another aspect of the present disclosure is illustrated. The wireless communication device 900 may be a smart phone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (such as a wireless watch), and other types of wireless devices.

[0078] Specifically, the wireless communication device 900 includes an integrated circuit (IC) 910, which may be implemented as a system-on-chip (SOC). The IC 910 includes one or more signal processing cores 920 configured to generate transmit (Tx) baseband (BB) signals and process receive (Rx) baseband (BB) signals. The IC 910 also includes a baseband (BB) phase-locked loop (PLL) 930 configured to provide a clock signal to the one or more signal processing cores 920 for controlling transmission and reception of the Tx BB signal and the Rx BB signal, respectively. The PLL 930 may be implemented as described herein.

[0079] The wireless communication device 900 may also include a transceiver 950 and at least one antenna 960 (such as an antenna array). The transceiver 950 is coupled to the one or more signal processing cores 920 to receive the Tx BB signal from the one or more signal processing cores and provide the Rx BB signal to the one or more signal processing cores. The transceiver 950 is configured to convert the Tx BB signal into a transmit (Tx) radio frequency (RF) signal and convert the receive (Rx) RF signal into an Rx BB signal. The transceiver 950 is coupled to the at least one antenna 960 to provide the Tx RF signal to the at least one antenna for electromagnetic radiation into the wireless medium for wireless transmission, and receive the Rx RF signal electromagnetically picked up by the at least one antenna 960 from the wireless medium.

[0080] The following provides an overview of aspects of the present disclosure:

[0081] Aspect 1: A device, the device comprising: a phase-locked loop (PLL), the phase-locked loop (PLL) comprising: a phase detector and a loop filter (PD / LF), the phase detector and the loop filter (PD / LF) comprising: a phase / frequency detector, the phase / frequency detector comprising a first input configured to receive a reference signal and a second input configured to receive a feedback signal, and an output configured to generate an output signal based on the reference signal and the feedback signal; a first capacitor; and a charge pump, the charge pump comprising: a charging path configured to generate a charging current based on the output signal to charge the first capacitor; and a discharging path, the discharging path comprising a first resistor configured to discharge the first capacitor.

[0082] Aspect 2: The device according to aspect 1, wherein the first resistor comprises a variable resistor.

[0083] Aspect 3: The device according to aspect 1 or 2, wherein the discharging path is configured to partially discharge the first capacitor during a discharging phase.

[0084] Aspect 4: The device according to any one of aspects 1 to 3, wherein: the charging path comprises a first field effect transistor (FET) coupled between an upper voltage rail and a first node; and the discharging path comprises the first resistor and a second FET coupled in series between the first node and a lower voltage rail, wherein the gates of the first FET and the second FET are coupled to the output of the phase / frequency detector.

[0085] Aspect 5: The device according to aspect 4, wherein the charging path further comprises a second resistor coupled between the first FET and the first node.

[0086] Aspect 6: The device according to aspect 5, wherein the second resistor comprises a variable resistor.

[0087] Aspect 7: The device according to any one of aspects 4 to 6, wherein the PD / LF further comprises: a first switching device coupled between the first node and a second node, wherein the first capacitor is coupled between the second node and the lower voltage rail.

[0088] Aspect 8: The device according to aspect 7, wherein the PD / LF further comprises: a second switching device coupled between the second node and a third node; and a second capacitor coupled between the third node and the lower voltage rail.

[0089] Aspect 9: The apparatus according to aspect 8, wherein the PD / LF further includes a non-overlapping clock generator configured to generate: a non-complementary clock signal based on the feedback signal, wherein the non-complementary clock signal controls the on / off state of the first switching device; and a complementary clock signal based on the feedback signal, wherein the complementary clock signal controls the off / on state of the second switching device.

[0090] Aspect 10: The apparatus according to aspect 8 or 9, further comprising a voltage controlled oscillator (VCO) coupled to the third node.

[0091] Aspect 11: The apparatus according to aspect 10, wherein the PLL further includes a frequency divider configured to generate the feedback signal based on the VCO signal generated by the VCO.

[0092] Aspect 12: The apparatus according to any one of aspects 1 to 11, wherein the phase / frequency detector includes an exclusive-NOR gate.

[0093] Aspect 13: The apparatus according to any one of aspects 1 to 3, wherein: the charging path includes a current source and a first switching device coupled in series between an upper voltage rail and a first node, wherein the on / off state of the first switching device is controlled by the output signal of the phase / frequency detector; and the discharging path includes the first resistor and a second switching device coupled in series between the first node and a lower voltage rail.

[0094] Aspect 14: The apparatus according to aspect 13, wherein the first capacitor is coupled between the first node and the lower voltage rail.

[0095] Aspect 15: The apparatus according to aspect 14, wherein the PD / LF further includes: a third switching device coupled between the first node and a second node; and a second capacitor coupled between the second node and the lower voltage rail.

[0096] Aspect 16: The apparatus according to aspect 15, wherein: the PD / LF further includes a control circuit configured to generate a first control signal and a second control signal, wherein the first control signal and the second control signal are based on the reference signal; the on / off state of the second switching device is controlled by the first control signal; and the on / off state of the third switching device is controlled by the second control signal.

[0097] Aspect 17: The apparatus according to aspect 15 or 16, wherein the PLL further includes a voltage controlled oscillator (VCO) coupled to the second node.

[0098] Aspect 18: The apparatus according to aspect 17, wherein the PLL further includes a frequency divider configured to generate the feedback signal based on the VCO signal generated by the VCO.

[0099] Aspect 19: A method of generating a frequency control signal for a voltage controlled oscillator (VCO), the method comprising: generating a phase difference signal based on a reference signal and a feedback signal, wherein the feedback signal is based on the VCO signal generated by the VCO; partially discharging a first capacitor from a first voltage to a second voltage above ground potential during a discharge phase; and charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, wherein the frequency control signal is based on the third voltage.

[0100] Aspect 20: The method according to aspect 19, the method further comprising distributing the charge on the first capacitor using a second capacitor to form a fourth voltage across the first capacitor and the second capacitor when the first capacitor is charged to the third voltage, wherein the frequency control signal is based on the fourth voltage.

[0101] Aspect 21: The method according to aspect 19 or 20, the method further comprising controlling the partial discharge of the first capacitor, including controlling the resistance of the discharge path between the first capacitor and ground.

[0102] Aspect 22: The method according to any one of aspects 19 to 21, the method further comprising controlling the charging of the first capacitor, including controlling the resistance of the charge path between the upper voltage rail and the first capacitor.

[0103] Aspect 23: The method according to any one of aspects 19 to 22, the method further comprising controlling the partial discharge of the first capacitor based on the phase difference signal.

[0104] Aspect 24: An apparatus for generating a frequency control signal for a voltage controlled oscillator (VCO), the apparatus comprising: means for generating a phase difference signal based on a reference signal and a feedback signal, wherein the feedback signal is based on the VCO signal generated by the VCO; means for partially discharging a first capacitor from a first voltage to a second voltage above ground potential during a discharge phase; and means for charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, wherein the frequency control signal is based on the third voltage.

[0105] Aspect 25: The apparatus according to aspect 24, the apparatus further comprising means for using a second capacitor to distribute the charge on the first capacitor to form a fourth voltage across the first capacitor and the second capacitor when the first capacitor is charged to the third voltage, wherein the frequency control signal is based on the fourth voltage.

[0106] Aspect 26: The apparatus according to aspect 24 or 25, the apparatus further comprising means for controlling partial discharge of the first capacitor, the control including controlling the resistance of a discharge path between the first capacitor and ground.

[0107] Aspect 27: The apparatus according to any one of aspects 24 to 26, the apparatus further comprising means for controlling the charging of the first capacitor, the control including controlling the resistance of a charging path between an upper voltage rail and the first capacitor.

[0108] Aspect 28: The apparatus according to any one of aspects 24 to 27, the apparatus further comprising means for controlling the partial discharge of the first capacitor based on the phase difference signal.

[0109] Aspect 29: A wireless communication device, the wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a phase-locked loop (PLL) coupled to the one or more signal processing cores. The PLL further comprises a phase detector and a loop filter (PD / LF), the phase detector and loop filter (PD / LF) comprising: a phase / frequency detector including a first input configured to receive a reference signal, a second input configured to receive a feedback signal, and an output configured to generate an output signal based on the reference signal and the feedback signal; a first capacitor; and a charge pump including: a charging path configured to generate a charging current based on the output signal to charge the first capacitor; and a discharge path including a first resistor configured to discharge the first capacitor.

[0110] Aspect 30: The wireless communication device according to aspect 29, wherein the discharge path is configured to partially discharge the first capacitor during a discharge phase.

[0111] The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: A phase - locked loop (PLL), the phase - locked loop (PLL) comprising: A phase detector and loop filter (PD / LF), the phase detector and loop filter (PD / LF) comprising: A phase / frequency detector, the phase / frequency detector comprising a first input configured to receive a reference signal, a second input configured to receive a feedback signal, and an output configured to generate an output signal based on the reference signal and the feedback signal; A first capacitor; and A charge pump, the charge pump comprising: A charging path configured to generate a charging current based on the output signal to charge the first capacitor; and A discharging path, the discharging path comprising a first resistor configured to discharge the first capacitor.

2. The apparatus according to claim 1, wherein the first resistor comprises a variable resistor.

3. The apparatus according to claim 1, wherein the discharging path is configured to partially discharge the first capacitor during a discharging phase.

4. The apparatus according to claim 1, wherein: The charging path comprises a first field - effect transistor (FET) coupled between an upper voltage rail and a first node; and The discharging path comprises the first resistor and a second FET coupled in series between the first node and a lower voltage rail, wherein the gates of the first FET and the second FET are coupled to the output of the phase / frequency detector.

5. The apparatus according to claim 4, wherein the charging path further comprises a second resistor coupled between the first FET and the first node.

6. The apparatus according to claim 5, wherein the second resistor comprises a variable resistor.

7. The apparatus according to claim 4, wherein the PD / LF further comprises: A first switching device coupled between the first node and a second node, wherein the first capacitor is coupled between the second node and the lower voltage rail.

8. The apparatus according to claim 7, wherein the PD / LF further comprises: A second switching device coupled between the second node and a third node; And A second capacitor coupled between the third node and the lower voltage rail.

9. The apparatus according to claim 8, wherein the PD / LF further comprises a non - overlapping clock generator configured to generate: A non - complementary clock signal based on the feedback signal, wherein the non - complementary clock signal controls the on / off state of the first switching device; and A complementary clock signal based on the feedback signal, wherein the complementary clock signal controls the off / on state of the second switching device.

10. The apparatus according to claim 8, wherein the PLL further comprises a voltage - controlled oscillator (VCO) coupled to the third node.

11. The apparatus according to claim 10, wherein the PLL further comprises a frequency divider configured to generate the feedback signal based on a VCO signal generated by the VCO.

12. The apparatus according to claim 1, wherein the phase / frequency detector comprises an exclusive-NOR gate.

13. The apparatus according to claim 1, wherein: the charging path comprises a current source and a first switching device serially coupled between an upper voltage rail and a first node, wherein an on / off state of the first switching device is controlled by the output signal of the phase / frequency detector; and the discharging path comprises the first resistor and a second switching device serially coupled between the first node and a lower voltage rail.

14. The apparatus according to claim 13, wherein the first capacitor is coupled between the first node and the lower voltage rail.

15. The apparatus according to claim 14, wherein the PD / LF further comprises: a third switching device coupled between the first node and a second node; and a second capacitor coupled between the second node and the lower voltage rail.

16. The apparatus according to claim 15, wherein: the PD / LF further comprises a control circuit configured to generate a first control signal and a second control signal, wherein the first control signal and the second control signal are based on the reference signal; the on / off state of the second switching device is controlled by the first control signal; and the on / off state of the third switching device is controlled by the second control signal.

17. The apparatus according to claim 15, wherein the PLL further comprises a voltage controlled oscillator (VCO) coupled to the second node.

18. The apparatus according to claim 17, wherein the PLL further comprises a frequency divider configured to generate the feedback signal based on a VCO signal generated by the VCO.

19. A method for generating a frequency control signal for a voltage controlled oscillator (VCO), the method comprising: generating a phase difference signal based on a reference signal and a feedback signal, wherein the feedback signal is based on a VCO signal generated by the VCO; partially discharging a first capacitor from a first voltage to a second voltage higher than a ground potential during a discharging phase; and charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, wherein the frequency control signal is based on the third voltage.

20. The method according to claim 19, the method further comprising, when the first capacitor is charged to the third voltage, using a second capacitor to distribute the charge on the first capacitor to form a fourth voltage across the first capacitor and the second capacitor, wherein the frequency control signal is based on the fourth voltage.

21. The method according to claim 19, the method further comprising controlling the partial discharging of the first capacitor, including controlling a resistance of a discharging path between the first capacitor and the ground.

22. The method according to claim 19, the method further comprising controlling the charging of the first capacitor, including controlling a resistance of a charging path between an upper voltage rail and the first capacitor.

23. The method according to claim 19, the method further comprising controlling the partial discharge of the first capacitor based on the phase difference signal.

24. An apparatus for generating a frequency control signal for a voltage controlled oscillator (VCO), the apparatus comprising: means for generating a phase difference signal based on a reference signal and a feedback signal, wherein the feedback signal is based on a VCO signal generated by the VCO; means for partially discharging a first capacitor from a first voltage to a second voltage above ground potential during a discharge phase; and means for charging the first capacitor from the second voltage to a third voltage based on the phase difference signal during a charging phase, wherein the frequency control signal is based on the third voltage.

25. The apparatus according to claim 24, the apparatus further comprising means for distributing the charge on the first capacitor using a second capacitor to form a fourth voltage across the first capacitor and the second capacitor when the first capacitor is charged to the third voltage, wherein the frequency control signal is based on the fourth voltage.

26. The apparatus according to claim 24, the apparatus further comprising means for controlling the partial discharge of the first capacitor, the control including controlling the resistance of the discharge path between the first capacitor and ground.

27. The apparatus according to claim 24, the apparatus further comprising means for controlling the charging of the first capacitor, the control including controlling the resistance of the charging path between the upper voltage rail and the first capacitor.

28. The apparatus according to claim 24, the apparatus further comprising means for controlling the partial discharge of the first capacitor based on the phase difference signal.

29. A wireless communication device, the wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a phase locked loop (PLL) coupled to the one or more signal processing cores, wherein the PLL comprises: a phase detector and loop filter (PD / LF), the phase detector and loop filter (PD / LF) comprising: a phase / frequency detector comprising a first input configured to receive a reference signal, a second input configured to receive a feedback signal, and an output configured to generate an output signal based on the reference signal and the feedback signal; a first capacitor; and a charge pump, the charge pump comprising: a charging path configured to generate a charging current based on the output signal to charge the first capacitor; and a discharging path comprising a first resistor configured to discharge the first capacitor.

30. The wireless communication device according to claim 29, wherein the discharging path is configured to partially discharge the first capacitor during a discharge phase.

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