Chip control method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a chip control method and device, electronic equipment, a chip and a storage medium, and relates to the field of chip control, and the method comprises the steps: obtaining the working temperature of the chip; according to the working temperature, determining target energy needing to be consumed by an on-chip storage unit in the chip under various dormancy strategies; according to target energy needing to be consumed under the multiple dormancy strategies, a target dormancy strategy is determined from the multiple dormancy strategies; and executing the target sleep strategy on the on-chip storage unit. Therefore, according to the working temperature of the chip, the energy requirements of the on-chip storage unit under the multiple dormancy strategies are calculated, the most energy-saving target dormancy strategy is selected, it can be ensured that the chip can achieve the optimal energy efficiency under various working conditions, unnecessary energy waste is reduced, and the energy efficiency of the chip is improved. The service life of the battery can be obviously prolonged or the overall power consumption of the system is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip control technology, and in particular, to a chip control method, device, electronic device, chip and storage medium. Background Art

[0002] By reasonably allocating different types of storage units, the multi-level storage architecture can find the best balance among performance, power consumption and cost, thereby improving the overall efficiency and flexibility of the system. When a chip adopting the multi-level storage architecture enters the sleep mode, in order to further reduce the sleep power consumption of the on-chip storage units (such as on-chip random access memory (Random Access Memory, abbreviated as RAM), registers, etc.) integrated inside the chip, some special sleep strategies can be adopted to achieve the maximum energy saving without affecting the system performance. Summary of the Invention

[0003] The present application aims to solve at least one of the technical problems in the related art to some extent.

[0004] To this end, the present application proposes a chip control method, device, electronic device, chip and storage medium to achieve reducing energy waste, extending battery life or reducing the overall power consumption of the system; better protecting the on-chip storage units and reducing potential damage caused by thermal stress, thereby improving the stability and reliability of the system.

[0005] An embodiment of one aspect of the present application proposes a chip control method, including:

[0006] Obtaining the operating temperature of the chip;

[0007] Determining the target energy required for the on-chip storage units inside the chip under multiple sleep strategies according to the operating temperature;

[0008] Determining a target sleep strategy from the multiple sleep strategies according to the target energy required under the multiple sleep strategies;

[0009] Executing the target sleep strategy on the on-chip storage units.

[0010] An embodiment of another aspect of the present application proposes a chip control device, including:

[0011] An obtaining module, configured to obtain the operating temperature of the chip;

[0012] A determining module, configured to determine the target energy required for the on-chip storage units inside the chip under multiple sleep strategies according to the operating temperature;

[0013] A selection module, configured to select a target sleep strategy from the multiple sleep strategies according to the target energy required to be consumed under the multiple sleep strategies;

[0014] An execution module, configured to execute the target sleep strategy on the on-chip storage unit.

[0015] Another embodiment of this application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the chip control method described in the foregoing aspect is implemented.

[0016] Another embodiment of this application provides a chip, which includes an interface circuit and a processing circuit that are coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to execute the chip control method described in the foregoing aspect.

[0017] Another embodiment of this application provides a non-transitory computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the chip control method described in the foregoing aspect is implemented.

[0018] Another embodiment of this application provides a computer program product, on which a computer program is stored. When the program is executed by a processor, the chip control method described in the foregoing aspect is implemented.

[0019] The chip control method, device, electronic device, chip, and storage medium provided by this application calculate the energy requirements of the on-chip storage unit under multiple sleep strategies according to the operating temperature of the chip, and select the most energy-efficient target sleep strategy, which can ensure that the chip can achieve the best energy efficiency under various working conditions. This not only reduces unnecessary energy waste, but also significantly extends the battery life or reduces the overall power consumption of the system. In addition, selecting a suitable sleep strategy according to different temperature conditions can not only better protect the on-chip storage unit and reduce potential damage caused by thermal stress, thereby improving the stability and reliability of the system, but also optimize the wake-up time, enabling the chip to recover from the sleep state to the working state faster and shortening the response delay.

[0020] The additional aspects and advantages of this application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of this application. Description of the Drawings

[0021] The above and / or additional aspects and advantages of this application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0022] Figure 1 It is a schematic diagram of the multi-level storage architecture of the chip;

[0023] Figure 2 Schematic diagram of the low-power state or off state entered by the on-chip storage unit when executing different sleep strategies;

[0024] Figure 3 Schematic diagram of the energy consumed by the on-chip storage unit under different sleep strategies;

[0025] Figure 4 Schematic flowchart of the first chip control method provided by the embodiments of the present application;

[0026] Figure 5 Schematic flowchart of the second chip control method provided by the embodiments of the present application;

[0027] Figure 6 Schematic flowchart of the third chip control method provided by the embodiments of the present application;

[0028] Figure 7 Schematic flowchart of the fourth chip control method provided by the embodiments of the present application;

[0029] Figure 8 Schematic diagram of the implementation principle of any embodiment of the present application;

[0030] Figure 9 Schematic diagram of the structure of a chip control device provided by the embodiments of the present application;

[0031] Figure 10 Schematic diagram of the structure of an electronic device provided by the embodiments of the present application;

[0032] Figure 11 Schematic diagram of the structure of a chip proposed by the embodiments of the present application. Detailed implementation manners

[0033] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation to the present application.

[0034] Taking the chip as the Central Processing Unit (CPU) as an example, the multi-level storage architecture of the chip can be as Figure 1 shown, where Figure 1 mainly includes the following components:

[0035] 1. CPU: Central Processing Unit, responsible for executing computing tasks.

[0036] 2. L1 Cache: The first-level cache, located inside the CPU, has the fastest access speed and relatively small capacity.

[0037] 3. L2 Cache: The second-level cache, usually located on the CPU or motherboard, is larger than the L1 cache and has a slightly slower access speed. Among them, both L1 Cache and L2 Cache belong to on-chip storage units.

[0038] 4. OCRAM, short for On-Chip RAM: On-chip memory, integrated inside the chip, has a fast access speed but limited capacity.

[0039] 5. DDR, short for Double Data Rate Synchronous Dynamic Random Access Memory: Off-chip storage unit outside the chip, has a large capacity and a relatively slow access speed.

[0040] 6. Main Interconnect: The main communication bus inside the chip, connecting various main modules, emphasizing high performance and high bandwidth.

[0041] 7. Central Interconnect: The centralized communication hub inside the chip, responsible for managing and scheduling the communication between various modules, emphasizing centralized management and efficient routing.

[0042] In related technologies, when the chip enters the sleep mode, there are mainly the following two low-power sleep modes: Retainment Mode and Data Migration Mode (used to migrate the stored data in the on-chip storage unit to the off-chip storage unit).

[0043] Among them, in the Retainment Mode, the on-chip storage unit (including OCRAM and each level of cache) still retains the stored data, and a certain amount of power consumption is required to maintain the stored data without loss. Among them, the advantages of the Retainment Mode include: Since there is no need to reload the stored data, the wake-up time is relatively short; the disadvantages of the Retainment Mode include: continuous power consumption, not suitable for long-term sleep states.

[0044] Among them, in the Data Migration Mode, the stored data in the on-chip storage unit will be migrated to the off-chip storage unit (such as off-chip DDR), and then the on-chip storage unit is turned off to save power. Among them, the advantages of the Data Migration Mode include: significantly reducing power consumption, suitable for long-term sleep states; the disadvantages of the Data Migration Mode include: when the chip wakes up, it needs to recover data from the off-chip storage unit, increasing the wake-up time and power consumption.

[0045] That is, when a chip with a multi-level storage architecture enters the sleep period, to reduce the sleep power consumption, based on the data retention mode, the on-chip storage unit can be controlled to enter the low-power state, or, according to the data migration mode, the on-chip storage unit can be controlled to enter the off state.

[0046] In the related art, the chip will select one of the above two sleep modes, specifically depending on the expected sleep duration and power consumption budget. If the expected sleep duration is relatively short, the data retention mode is more appropriate because it can wake up the chip faster. On the contrary, if the expected sleep duration is relatively long, the data migration mode is more appropriate because it can significantly reduce the power consumption during sleep.

[0047] As an example, the data migration mode corresponds to Figure 2 Strategy 1 (i.e., the data migration strategy) in Figure 2 . Under Strategy 1, the on-chip storage unit is powered off and enters the off state, and the stored data in the on-chip storage unit is migrated to the off-chip storage unit; the data retention mode corresponds to

[0048] Strategy 2 (i.e., the data retention strategy) in Figure 3 . Under Strategy 2, the on-chip storage unit is not powered off, enters the low-power state, and keeps the stored data continued to be stored in the on-chip storage unit.

[0048] In the related art, the selection of the sleep strategy for the on-chip storage unit is mainly based on a static energy consumption model. Specifically, first, in the way shown in Figure 3 , the energy consumption of the on-chip storage unit under two sleep strategies (the data migration strategy and the data retention strategy) can be calculated. For the data migration strategy, the sum of the data storage energy E save and the data recovery energy E restore is calculated, while for the data retention strategy, the data retention energy E retention is calculated. Then, according to the magnitude relationship between (E save + E restore ) and E retention , which sleep strategy to adopt is determined. Exemplarily, if (E save + E restore ) is greater than E retention , the data retention strategy is adopted; if (E save + E restore ) is less than E retention , the data migration strategy is adopted.

[0049] However, this static energy model based on fixed temperature conditions has significant limitations. Especially in high-temperature environments, for example, when the chip is set in a vehicle communication module and the vehicle communication module is located on the roof of the vehicle, the ambient temperature at which the chip operates may reach 90°C. Under such extreme conditions, the current characteristics of the on-chip memory cells will change significantly, thereby affecting their performance. In particular, E retention changes with the increase in temperature, which makes the existing static energy model inaccurate and may lead to the following problems:

[0050] 1. Inaccurate energy consumption estimation: In a high-temperature environment, the actual energy consumption of the data retention strategy may be much higher than the estimated value at normal temperature, resulting in unnecessary energy waste.

[0051] 2. Decreased reliability: Since the influence of temperature on current characteristics is not fully considered, the selected sleep strategy may not effectively protect the on-chip memory cells, increasing the risk of thermal stress damage and reducing the stability and lifespan of the system.

[0052] 3. Increased response delay: Incorrect energy estimation may lead to the selection of a non-optimal sleep strategy, prolonging the wake-up time and thus increasing the system response delay.

[0053] Therefore, in view of at least one of the problems existing in the above related technologies, the present application proposes a chip control method, device, electronic device, chip, and storage medium.

[0054] The chip control method, device, electronic device, chip, and storage medium according to the embodiments of the present application will be described below with reference to the accompanying drawings.

[0055] Figure 4 It is a schematic flowchart of the first chip control method provided by the embodiments of the present application.

[0056] It should be noted that the chip control method of the embodiments of the present application can be applied to a chip control device. In some possible embodiments, the chip control device can be configured in an electronic device, a vehicle, or a chip so that the electronic device, the vehicle, or the chip can perform the chip control function. Additionally, in some possible embodiments, the chip control device can also be software in an electronic device or a vehicle, etc.

[0057] In any embodiment of the present application, the chip can be integrated into an electronic device or a vehicle. The chip includes a Central Processing Unit (CPU), an Image Signal Processing (ISP), an Application-Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a System On A Chip (SOC), a Reduced Instruction Set Computer (RISC), etc., which will not be listed one by one here.

[0058] As Figure 4 shown, the chip control method may include the following steps S401 to S404:

[0059] Step S401, obtain the operating temperature of the chip.

[0060] In an embodiment of the present application, when the chip enters the sleep mode or receives a sleep instruction, the operating temperature (or ambient temperature) collected by the temperature sensor on the chip can be obtained.

[0061] In an embodiment of the present application, obtaining the operating temperature of the chip includes obtaining the instantaneous temperature of the chip at a certain moment (such as the current moment) or the average temperature within a certain period of time.

[0062] Step S402, determine the target energy consumption required by the on-chip storage unit inside the chip under various sleep strategies according to the operating temperature.

[0063] Among them, the on-chip storage unit includes but is not limited to: on-chip RAM, caches at all levels, registers, etc.

[0064] Among them, the sleep strategies include but are not limited to: data retention strategy, data migration strategy, etc. Under the data retention strategy, the on-chip storage unit still retains the stored data and consumes a certain amount of power to maintain the stored data without loss; under the data migration strategy, the stored data in the on-chip storage unit can be migrated to an off-chip storage unit outside the chip.

[0065] Among them, the off-chip storage unit includes but is not limited to: DDR, Flash, hard disk, magnetic disk, optical disc, etc.

[0066] In the embodiments of the present application, the energy required for the on-chip storage unit under multiple sleep strategies can be calculated according to the working temperature, which is denoted as the target energy in the present application.

[0067] Step S403: Determine the target sleep strategy from multiple sleep strategies according to the target energy required under multiple sleep strategies.

[0068] In the embodiments of the present application, based on the target energy required for the on-chip storage unit under multiple sleep strategies, the target sleep strategy to be executed by the on-chip storage unit can be determined from multiple sleep strategies.

[0069] As an example, in order to minimize energy consumption, the sleep strategy with the lowest target energy can be used as the target sleep strategy to be executed by the on-chip storage unit.

[0070] Step S404: Execute the target sleep strategy on the on-chip storage unit.

[0071] In the embodiments of the present application, the target sleep strategy can be executed on the on-chip storage unit to reduce energy consumption.

[0072] The chip control method according to the embodiments of the present application calculates the energy requirements of the on-chip storage unit under multiple sleep strategies according to the working temperature of the chip, and selects the most energy-efficient target sleep strategy, which can ensure that the chip can achieve the best energy efficiency under various working conditions. This not only reduces unnecessary energy waste, but also significantly extends the battery life or reduces the overall power consumption of the system. In addition, selecting the appropriate sleep strategy according to different temperature conditions can not only better protect the on-chip storage unit, reduce potential damage caused by thermal stress, thereby improving the stability and reliability of the system, but also optimize the wake-up time, enabling the chip to recover from the sleep state to the working state faster and shortening the response delay.

[0073] The embodiments of the present application provide another chip control method. Figure 5 It is a schematic flowchart of the second chip control method provided by the embodiments of the present application.

[0074] It should be noted that this chip control method can be executed alone, or can be executed in combination with any one of the embodiments in the present application or possible implementation manners in the embodiments, or can also be executed in combination with any one of the technical solutions in the related art. The embodiments of the present application do not limit this.

[0075] Such as Figure 5 shown, this chip control method may include the following steps S501 to S505:

[0076] Step S501: Obtain the working temperature of the chip.

[0077] It should be noted that the explanation of step S501 can be referred to the relevant descriptions in any embodiment of the present application, and will not be elaborated here.

[0078] Step S502: Determine the sleep duration of the on-chip storage unit in the data retention policy among multiple sleep modes according to the working state of the electronic device running the chip.

[0079] Among them, the working state of the electronic device running the chip includes but is not limited to: paging state, discontinuous reception state (Connected Mode Discontinuous Reception, abbreviated as CDRX), etc.

[0080] It should be noted that the protocol has stipulated the correspondence between different working states (or called system states) and the sleep duration. Therefore, in the present application, based on the current working state of the electronic device running the chip, the sleep duration corresponding to this working state can be queried from the protocol and used as the sleep duration of the on-chip storage unit in the data retention policy.

[0081] Exemplarily, when the working state of the electronic device is the paging state, the protocol stipulates that the electronic device wakes up every about 1.28 seconds to attempt to receive a page. At this time, the sleep duration of the on-chip storage unit in the data retention policy can be 1.28 seconds.

[0082] Step S503: Determine the target energy required for the on-chip storage unit in the data retention policy according to the working temperature and the sleep duration.

[0083] Among them, the target energy has a positive correlation with the sleep duration, that is, the longer the sleep duration, the higher the target energy. Conversely, the shorter the sleep duration, the lower the target energy.

[0084] Among them, the target energy has a positive correlation with the working temperature of the chip, that is, the higher the working temperature, the greater the target energy. Conversely, the lower the working temperature, the smaller the target energy.

[0085] In the embodiment of the present application, the target energy required for the on-chip storage unit in the data retention policy can be calculated according to the working temperature and the sleep duration of the chip.

[0086] As an example, the power required for the on-chip storage unit to maintain the stored data (denoted as the target power in the present application) can be calculated according to the working temperature of the chip, and the target energy required for the on-chip storage unit in the data retention policy can be calculated according to the target power and the sleep duration.

[0087] Among them, the target power is positively correlated with the operating temperature of the chip, that is, the higher the operating temperature, the greater the target power; conversely, the lower the operating temperature, the smaller the target power.

[0088] Among them, the target energy is positively correlated with the target power, that is, the greater the target power, the higher the target energy; conversely, the smaller the target power, the lower the target energy.

[0089] Step S504: Determine the target sleep strategy from multiple sleep strategies according to the target energy required by the on-chip storage unit in multiple sleep modes.

[0090] Step S505: Execute the target sleep strategy on the on-chip storage unit.

[0091] It should be noted that the explanations of steps S504 to S505 can be referred to the relevant descriptions in any embodiment of this application, and will not be elaborated here.

[0092] In any embodiment of this application, when the target sleep mode is the data retention strategy, in response to this data retention strategy, the on-chip storage unit can be controlled to enter the low-power state, and the stored data can be kept in the on-chip storage unit to continue to be saved, so as to reduce energy consumption.

[0093] In any embodiment of this application, when a wake-up instruction for the chip is received, the chip can be woken up, and the on-chip storage unit can be controlled to exit the low-power state, so that the chip and the on-chip storage unit can quickly resume to the working state and shorten the response delay.

[0094] The chip control method of the embodiment of this application calculates the target energy required by the on-chip storage unit under the data retention strategy by integrating the sleep duration of the on-chip storage unit under the data retention strategy and the operating temperature of the chip, which can improve the rationality and reliability of the calculation results.

[0095] The embodiment of this application provides another chip control method. Figure 6 It is a schematic flowchart of the third chip control method provided by the embodiment of this application.

[0096] It should be noted that this chip control method can be executed alone, or can be executed together with any one embodiment or possible implementation manner in this application, or can also be executed together with any one technical solution in the related art. The embodiment of this application does not limit this.

[0097] As Figure 6 shown, this chip control method may include the following steps S601 to S606:

[0098] Step S601: Obtain the operating temperature of the chip.

[0099] Step S602: Determine the sleep duration of the on-chip storage unit inside the chip under the data retention policy in multiple sleep modes according to the working state of the electronic device where the running chip is located.

[0100] It should be noted that the explanations of steps S601 to S602 can be referred to the relevant descriptions in any embodiment of this application, and will not be elaborated here.

[0101] Step S603: Determine the target power required for the on-chip storage unit to maintain the stored data according to the working temperature.

[0102] In any embodiment of this application, the power required for the on-chip storage unit to maintain the stored data can be directly calculated according to the working temperature of the chip, which is denoted as the target power in this application.

[0103] Among them, the target power has a positive correlation with the working temperature of the chip, that is, the higher the working temperature, the greater the target power, and vice versa, the lower the working temperature, the smaller the target power.

[0104] In any embodiment of this application, the target power required for the on-chip storage unit to maintain the stored data can be indirectly calculated according to the working temperature of the chip. Exemplarily, first, the storage space occupied by the stored data in the on-chip storage unit can be determined, and then, according to the storage space and the working temperature, the mapping relation table associated with the on-chip storage unit can be queried to obtain the target power, that is, the target power refers to the power that has a mapping relation with the above storage space and working temperature in the mapping relation table; among them, the mapping relation table records the mapping relations between different powers and temperatures and storage spaces.

[0105] Among them, the target power has a positive correlation with the storage space occupied by the stored data in the on-chip storage unit, that is, the larger the storage space, the greater the target power, and vice versa, the smaller the storage space, the smaller the target power.

[0106] Among them, the target power also has a positive correlation with the working temperature of the chip, that is, the higher the working temperature, the greater the target power, and vice versa, the lower the working temperature, the smaller the target power.

[0107] In summary, the calculation of the target power not only takes into account the current working temperature of the chip, but also takes into account the storage space occupied by the stored data in the on-chip storage unit, which can improve the reliability and rationality of the calculation results.

[0108] Step S604: Take the product of the target power and the sleep duration as the target energy required for the on-chip storage unit in the data migration policy.

[0109] As an example, the operating temperature of the labeled chip is T, the target power is P retention (T), and the sleep duration is T sleep , and the target power is E retention , then there is:

[0110] E retention = P retention (T) * T sleep ;

[0111] Step S605, determine the target sleep strategy from multiple sleep strategies according to the target energy required to be consumed under multiple sleep strategies.

[0112] Step S606, execute the target sleep strategy on the on-chip storage unit.

[0113] It should be noted that the explanations of steps S605 to S606 can be found in the relevant descriptions in any embodiment of this application, and will not be elaborated here.

[0114] The chip control method of the embodiment of this application calculates the target power required for the on-chip storage unit to maintain the stored data according to the operating temperature of the chip, and takes the product of the target power and the sleep duration as the target energy required for the on-chip storage unit in the data migration strategy, which can improve the effectiveness, rationality, and accuracy of the target energy calculation.

[0115] The embodiment of this application provides another chip control method, Figure 7 which is a schematic flowchart of the fourth chip control method provided by the embodiment of this application.

[0116] It should be noted that this chip control method can be executed alone, or can be executed together with any one embodiment or possible implementation manner in this application, or can also be executed together with any one technical solution in the related art. The embodiment of this application does not limit this.

[0117] As Figure 7 shown, this chip control method may include the following steps S701 to S706:

[0118] Step S701, obtain the operating temperature of the chip.

[0119] It should be noted that the explanation of step S701 can be found in the relevant descriptions in any embodiment of this application, and will not be elaborated here.

[0120] Step S702, determine the first energy required to migrate the stored data from the on-chip storage unit inside the chip to the off-chip storage unit outside the chip according to the storage space occupied by the stored data in the on-chip storage unit inside the chip.

[0121] It should be noted that the explanations of the on-chip storage unit and the off-chip storage unit in the foregoing embodiments also apply to this embodiment, and will not be elaborated here.

[0122] Among them, the first energy is positively correlated with the storage space occupied by the stored data in the on-chip storage unit, that is, the larger the storage space, the higher the first energy; conversely, the smaller the storage space, the lower the first energy.

[0123] In the embodiment of the present application, the first energy required to migrate the stored data from the on-chip storage unit to the off-chip storage unit for storage can be calculated according to the storage space occupied by the stored data in the on-chip storage unit. Exemplarily, the first energy can be as shown in Figure 3 E shown in save .

[0124] Step S703: Determine the second energy required to restore the stored data from the off-chip storage unit to the on-chip storage unit according to the storage space.

[0125] Among them, the second energy is positively correlated with the storage space occupied by the stored data in the on-chip storage unit, that is, the larger the storage space, the higher the second energy; conversely, the smaller the storage space, the lower the second energy.

[0126] In the embodiment of the present application, the second energy required to restore the stored data from the off-chip storage unit to the on-chip storage unit for storage can be calculated according to the storage space occupied by the stored data in the on-chip storage unit. Exemplarily, the second energy can be as shown in Figure 3 E shown in restore .

[0127] Step S704: Determine the target energy required for the data migration strategy of the on-chip storage unit in multiple sleep modes according to the first energy and the second energy.

[0128] It should be noted that the explanations of the sleep mode in the foregoing embodiments also apply to this embodiment, and will not be elaborated here.

[0129] Among them, the target energy is positively correlated with the first energy, that is, the higher the first energy, the higher the target energy; conversely, the lower the first energy, the lower the target energy.

[0130] Among them, the target energy is also positively correlated with the first energy, that is, the higher the second energy, the higher the target energy; conversely, the lower the second energy, the lower the target energy.

[0131] In the embodiment of the present application, the target energy required for the on-chip storage unit under the data migration strategy can be calculated according to the first energy and the second energy.

[0132] As an example, the sum of the first energy and the second energy can be used as the target energy that the on-chip storage unit needs to consume under the data migration strategy.

[0133] As another example, the first energy and the second energy can be weighted and summed to obtain the target energy that the on-chip storage unit needs to consume under the data migration strategy.

[0134] Exemplarily, the target energy = a * the first energy + b * the second energy;

[0135] Where a and b are preset weights. For example, a = 1.1, b = 0.9, or a = 0.8, b = 1.2, etc. The embodiments of the present application do not limit this.

[0136] Step S705: Determine the target sleep strategy from multiple sleep strategies according to the target energy required to be consumed under multiple sleep strategies.

[0137] Step S706: Execute the target sleep strategy on the on-chip storage unit.

[0138] It should be noted that the explanations of steps S705 to S706 can refer to the relevant descriptions in any embodiment of the present application, and will not be elaborated here.

[0139] In any embodiment of the present application, when the target sleep mode is the data migration strategy, in response to this data migration strategy, the stored data in the on-chip storage unit can be migrated to the off-chip storage unit outside the chip, and when the stored data migration is completed, the on-chip storage unit can be controlled to enter the off state to reduce energy consumption.

[0140] In any embodiment of the present application, when a wake-up instruction for the chip is received, the chip can be woken up, and the on-chip storage unit can be controlled to switch from the off state to the on state. When the on-chip storage unit enters the on state, the stored data in the off-chip storage unit can be restored to the on-chip storage unit, so that the chip and the on-chip storage unit can quickly return to the working state and shorten the response delay.

[0141] The chip control method of the embodiments of the present application comprehensively combines the first energy required to migrate the stored data from the on-chip storage unit to the off-chip storage unit and the second energy required to restore the stored data from the off-chip storage unit to the on-chip storage unit to calculate the target energy that the on-chip storage unit needs to consume under the data migration strategy, which can improve the effectiveness, rationality, and accuracy of the target energy calculation.

[0142] In any embodiment of the present application, when determining which sleep strategy the on-chip storage unit adopts, a temperature parameter can be introduced to measure the E of the on-chip storage unit at different temperatures.retention Store according to different levels, and look up the table when needed.

[0143] Exemplarily, the implementation principle of the technical solution provided by this application can be as Figure 8 shown, mainly including the following steps:

[0144] 1. Read the operating temperature T collected by the temperature sensor on the chip.

[0145] 2. Look up the table according to the operating temperature to obtain the target power P required for the on-chip storage unit under the data retention policy retention .

[0146] Exemplarily, the target power P required for the on-chip storage unit under the data retention policy can be obtained by looking up the table according to both the storage space occupied by the stored data in the on-chip storage unit and the operating temperature retention .

[0147] 3. According to the sleep duration T of the on-chip storage unit in the data retention mode sleep and the target power P retention , calculate the target energy E required for the on-chip storage unit under the data retention policy retention . That is, E retention =P retention *T sleep .

[0148] 4. Compare E retention with (the first energy E required for data preservation save +the second energy E required for data recovery restore ). If E retention >(E save +E restore ), then execute the data migration policy for the on-chip storage unit. If E retention <(E save +E restore ), then execute the data retention policy for the on-chip storage unit.

[0149] In summary, even in a high-temperature working environment, the chip can still ensure a very low standby current in the sleep mode, thus effectively reducing energy consumption and improving the overall performance.

[0150] To implement the above embodiments, an embodiment of this application also proposes a chip control device.

[0151] Figure 9 The structural diagram of a chip control device provided by an embodiment of this application.

[0152] As Figure 9As shown, the chip control device 900 may include: an acquisition module 910, a determination module 920, a selection module 930, and an execution module 940.

[0153] Among them, the acquisition module 910 is used to acquire the operating temperature of the chip;

[0154] The determination module 920 is used to determine the target energy required to be consumed by the on-chip storage unit inside the chip under multiple sleep strategies according to the operating temperature;

[0155] The selection module 930 is used to select a target sleep strategy from multiple sleep strategies according to the target energy required to be consumed under multiple sleep strategies;

[0156] The execution module 940 is used to execute the target sleep strategy on the on-chip storage unit.

[0157] Further, in an implementation manner of the embodiment of the present application, among the multiple sleep strategies includes a data retention strategy, and the determination module 920 is used to: determine the sleep duration of the on-chip storage unit under the data retention strategy according to the operating state of the electronic device running the chip; determine the target energy required to be consumed by the on-chip storage unit under the data retention strategy according to the operating temperature and the sleep duration.

[0158] In an implementation manner of the embodiment of the present application, the determination module 920 is used to: determine the target power required to be consumed by the on-chip storage unit to maintain the stored storage data according to the operating temperature; use the product of the target power and the sleep duration as the target energy required to be consumed by the on-chip storage unit under the data migration strategy.

[0159] In an implementation manner of the embodiment of the present application, the determination module 920 is used to: determine the storage space occupied by the stored data in the on-chip storage unit; query the mapping relation table associated with the on-chip storage unit according to the storage space and the operating temperature to obtain the target power; where the mapping relation table records the mapping relations between different powers and temperature and storage space.

[0160] In an implementation manner of the embodiment of the present application, the target sleep strategy is a data retention strategy; the execution module 940 is used to: in response to the data retention strategy, control the on-chip storage unit to enter the low power consumption state and keep the stored data continue to be stored in the on-chip storage unit.

[0161] In an implementation manner of the embodiment of the present application, the chip control device 900 may further include:

[0162] The first control module is used to wake up the chip in response to receiving a wake-up instruction for the chip and control the on-chip storage unit to exit the low power consumption state.

[0163] In an implementation manner of the embodiment of the present application, among multiple sleep strategies, a data migration strategy is further included. The determination module 920 is further configured to: determine the first energy consumed for migrating the stored data from the on-chip storage unit to the off-chip storage unit outside the chip according to the storage space occupied by the stored data in the on-chip storage unit; determine the second energy consumed for restoring the stored data from the off-chip storage unit to the on-chip storage unit according to the storage space; and determine the target energy consumed by the on-chip storage unit under the data migration strategy according to the first energy and the second energy.

[0164] In an implementation manner of the embodiment of the present application, the determination module 920 is configured to: use the sum of the first energy and the second energy as the target energy consumed by the on-chip storage unit under the data migration strategy.

[0165] In an implementation manner of the embodiment of the present application, the target sleep strategy is the data migration strategy. The execution module 940 is configured to: in response to the data migration strategy, migrate the stored data in the on-chip storage unit to the off-chip storage unit outside the chip; and in response to the completion of the migration of the stored data, control the on-chip storage unit to enter the off state.

[0166] In an implementation manner of the embodiment of the present application, the chip control device 900 may further include:

[0167] A second control module, configured to: in response to receiving a wake-up instruction for the chip, wake up the chip; control the on-chip storage unit to switch from the off state to the on state; and in response to the on-chip storage unit entering the on state, restore the stored data in the off-chip storage unit to the on-chip storage unit.

[0168] In an implementation manner of the embodiment of the present application, the selection module 930 is configured to: use the sleep strategy with the lowest target energy as the target sleep strategy.

[0169] It should be noted that the foregoing explanation of the embodiment of the chip control method is also applicable to the chip control device of this embodiment, and will not be elaborated here.

[0170] In the chip control device of the embodiment of the present application, calculating the energy requirements of the on-chip storage unit under multiple sleep strategies according to the operating temperature of the chip and selecting the most energy-efficient target sleep strategy can ensure that the chip can achieve the best energy efficiency under various operating conditions. This not only reduces unnecessary energy waste, but also significantly extends the battery life or reduces the overall power consumption of the system. In addition, selecting a suitable sleep strategy according to different temperature conditions can not only better protect the on-chip storage unit and reduce potential damage caused by thermal stress, thereby improving the stability and reliability of the system, but also optimize the wake-up time, enabling the chip to recover from the sleep state to the working state faster and shortening the response delay.

[0171] To implement the above embodiments, the present application further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the chip control method described in any of the foregoing embodiments is implemented.

[0172] Figure 10 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. For example, the electronic device 1000 may be a vehicle, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0173] Refer to Figure 10 , the electronic device 1000 may include one or more of the following components: a processing component 1002, a memory 1004, a power component 1006, a multimedia component 1008, an audio component 1010, an input / output (I / O) interface 1012, a sensor component 1014, and a communication component 1016.

[0174] The processing component 1002 generally controls the overall operation of the electronic device 1000, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 1002 may include one or more processors 1020 to execute instructions to complete all or part of the steps of the above method. In addition, the processing component 1002 may include one or more modules to facilitate the interaction between the processing component 1002 and other components. For example, the processing component 1002 may include a multimedia module to facilitate the interaction between the multimedia component 1008 and the processing component 1002.

[0175] The memory 1004 is configured to store various types of data to support the operation of the electronic device 1000. Examples of such data include instructions for any application or method operating on the electronic device 1000, contact data, phone book data, messages, pictures, videos, and the like. The memory 1004 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0176] The power component 1006 provides power to various components of the electronic device 1000. The power component 1006 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 1000.

[0177] The multimedia component 1008 includes a screen that provides an output interface between the electronic device 1000 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of the touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 1008 includes a front camera and / or a rear camera. When the electronic device 1000 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0178] The audio component 1010 is configured to output and / or input audio signals. For example, the audio component 1010 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 1000 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 1004 or transmitted via the communication component 1016. In some embodiments, the audio component 1010 further includes a speaker for outputting audio signals.

[0179] The I / O interface 1012 provides an interface between the processing component 1002 and a peripheral interface module, and the peripheral interface module may be a keyboard, a click wheel, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a power button, and a lock button.

[0180] The sensor component 1014 includes one or more sensors for providing status assessments of various aspects of the electronic device 1000. For example, the sensor component 1014 can detect the on / off state of the electronic device 1000, the relative positioning of components, such as the display and keypad of the electronic device 1000. The sensor component 1014 can also detect a change in the position of the electronic device 1000 or a component of the electronic device 1000, the presence or absence of user contact with the electronic device 1000, the orientation or acceleration / deceleration of the electronic device 1000, and the temperature change of the electronic device 1000. The sensor component 1014 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 1014 can also include a light sensor, such as a complementary metal-oxide-semiconductor (CMOS) or a charge-coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor component 1014 can further include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0181] The communication component 1016 is configured to facilitate communication between the electronic device 1000 and other devices in a wired or wireless manner. The electronic device 1000 can access a communication standard-based wireless network, such as WiFi, 4G, or 5G, or a combination thereof. In an exemplary embodiment, the communication component 1016 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1016 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra-Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0182] In an exemplary embodiment, the electronic device 1000 can be implemented by one or more Application-Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field-Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0183] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as the memory 1004 including instructions, and the above instructions can be executed by the processor 1020 of the electronic device 1000 to complete the above method. For example, the non-transitory computer-readable storage medium can be a Read-Only Memory (ROM), Random Access Memory (RAM), Compact Disc Read-Only Memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0184] To implement the above embodiments, the present application also provides a chip. The chip includes an interface circuit and a processing circuit that are coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to execute the chip control method provided in any of the foregoing embodiments.

[0185] Figure 11 It is a schematic structural diagram of a chip proposed in an embodiment of the present application. Reference may be made to Figure 11 the schematic structural diagram of the chip 1100 shown, but not limited thereto.

[0186] The chip 1100 includes a processing circuit 1101, and the processing circuit 1101 is configured to execute any of the above chip control methods.

[0187] In some embodiments, the chip 1100 further includes one or more interface circuits 1102. Optionally, the interface circuit 1102 is connected to the memory 1103. The interface circuit 1102 can be used to receive signals from the memory 1103 or other devices, and the interface circuit 1102 can be used to send signals to the memory 1103 or other devices. For example, the interface circuit 1102 can read the instructions stored in the memory 1103 and send the instructions to the processing circuit 1101.

[0188] In some embodiments, the interface circuit 1102 executes at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1101 executes other steps.

[0189] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. can be replaced with each other.

[0190] In some embodiments, the chip 1100 further includes one or more memories 1103 for storing instructions. Optionally, all or part of the memories 1103 can be outside the chip 1100.

[0191] To implement the above embodiments, the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the chip control method described in any of the foregoing method embodiments.

[0192] To implement the above embodiments, the present application also provides a computer program product, on which a computer program is stored. When the computer program is executed by a processor, it implements the chip control method described in any of the foregoing method embodiments.

[0193] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0194] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0195] Any process or method description shown in a flowchart or described in other ways herein may be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of this application includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in an order opposite to that shown or discussed, according to the functions involved, which should be understood by those skilled in the art to which the embodiments of this application belong.

[0196] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (Random Access Memory, abbreviated as RAM), a read-only memory (Read-Only Memory, abbreviated as ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (Compact Disc Read-Only Memory, abbreviated as CDROM). Additionally, a computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.

[0197] It should be understood that various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well-known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (Programmable Gate Array, abbreviated as PGA), field-programmable gate arrays (Field-Programmable Gate Array, abbreviated as FPGA), etc.

[0198] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the method of implementing the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0199] In addition, each functional unit in various embodiments of the present application may be integrated into one processing module, may exist physically alone for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0200] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A chip control method, characterized in that, Including: Obtaining the operating temperature of the chip; Determining the target energy required for the on-chip storage unit inside the chip under multiple sleep strategies according to the operating temperature; Determining a target sleep strategy from the multiple sleep strategies according to the target energy required under the multiple sleep strategies; Executing the target sleep strategy on the on-chip storage unit.

2. The method according to claim 1, characterized in that, Among the multiple sleep strategies, there is a data retention strategy. The determining the target energy required for the on-chip storage unit inside the chip under multiple sleep strategies according to the operating temperature includes: Determining the sleep duration of the on-chip storage unit under the data retention strategy according to the operating state of the electronic device running the chip; Determining the target energy required for the on-chip storage unit under the data retention strategy according to the operating temperature and the sleep duration.

3. The method according to claim 2, wherein The determining the target energy required for the on-chip storage unit under the data retention strategy according to the operating temperature and the sleep duration includes: Determining the target power required for the on-chip storage unit to retain the stored data according to the operating temperature; Taking the product of the target power and the sleep duration as the target energy required for the on-chip storage unit under the data migration strategy.

4. The method according to claim 3, wherein The determining the target power required for the on-chip storage unit to retain the stored data according to the operating temperature includes: Determining the storage space occupied by the stored data in the on-chip storage unit; Querying a mapping relation table associated with the on-chip storage unit according to the storage space and the operating temperature to obtain the target power; Wherein, the mapping relation table records the mapping relations between different powers and temperature and storage space.

5. The method according to claim 1, wherein The target sleep strategy is a data retention strategy. The executing the target sleep strategy on the on-chip storage unit includes: In response to the data retention strategy, controlling the on-chip storage unit to enter a low-power state and keeping the stored data continue to be stored in the on-chip storage unit.

6. The method according to claim 5, characterized in that, The method further includes: In response to receiving a wake-up instruction for the chip, waking up the chip and controlling the on-chip storage unit to exit the low-power state.

7. The method according to any one of claims 2-6, characterized in that, Among the multiple sleep strategies, there is also a data migration strategy. The determining the target energy required for the on-chip storage unit inside the chip under multiple sleep strategies according to the operating temperature further includes: Determining the first energy required to migrate the stored data from the on-chip storage unit to an off-chip storage unit outside the chip according to the storage space occupied by the stored data in the on-chip storage unit; Determining the second energy required to restore the stored data from the off-chip storage unit to the on-chip storage unit according to the storage space; Determining the target energy required for the on-chip storage unit under the data migration strategy according to the first energy and the second energy.

8. The method according to claim 7, characterized in that, The determining the target energy required for the on-chip storage unit under the data migration strategy according to the first energy and the second energy includes: Take the sum of the first energy and the second energy as the target energy required for the on-chip storage unit under the data migration strategy.

9. The method according to claim 1, characterized in that, The target sleep strategy is a data migration strategy; performing the target sleep strategy on the on-chip storage unit includes: In response to the data migration strategy, migrate the stored data in the on-chip storage unit to an off-chip storage unit outside the chip; In response to the completion of the migration of the stored data, control the on-chip storage unit to enter the off state.

10. The method according to claim 9, wherein The method further includes: In response to receiving a wake-up instruction for the chip, wake up the chip; Control the on-chip storage unit to switch from the off state to the on state; In response to the on-chip storage unit entering the on state, restore the stored data in the off-chip storage unit to the on-chip storage unit.

11. The method according to any one of claims 1-6, characterized in that, Determining the target sleep strategy from the multiple sleep strategies according to the target energy required under the multiple sleep strategies includes: Take the sleep strategy with the lowest target energy as the target sleep strategy.

12. A chip control device, characterized in that, Includes: An acquisition module for acquiring the operating temperature of the chip; A determination module for determining the target energy required for the on-chip storage unit inside the chip under multiple sleep strategies according to the operating temperature; A selection module for selecting a target sleep strategy from the multiple sleep strategies according to the target energy required under the multiple sleep strategies; An execution module for performing the target sleep strategy on the on-chip storage unit.

13. An electronic device, characterized in that, Includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the method according to any one of claims 1 to 11 are implemented.

14. A chip, characterized in that, The chip includes an interface circuit and a processing circuit that are coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is used to implement the method according to any one of claims 1 to 11.

15. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the program instruction is executed by the processor, the steps of the method according to any one of claims 1 to 11 are implemented.

16. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 11.

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