Storage device capable of performing peer-to-peer data transfer and method of operating same

Abstract

A memory device and an operating method of the memory device are provided. A storage device includes a non-volatile memory and a storage controller, in which the storage controller includes: a cache memory that stores some of data stored in the non-volatile memory; an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, providing a second request including the source address to the external storage device, and receive a response including first data corresponding to the source address from an external storage device in response to the second request; an address translation circuit that generates a physical address of a first type based on the destination address; and a cache controller that updates the cache region indicated by the physical address of the first type based on the cache update information.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0011179, filed with the Korean Intellectual Property Office on January 24, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The inventive concept relates to a memory, and more particularly, to a storage device and an operating method of the storage device. Background art

[0004] Semiconductor memories are classified into volatile memory devices that do not retain stored data when power is cut off, such as static random access memories (SRAMs) and dynamic RAMs (DRAMs); and non - volatile memory devices that retain stored data even when power is cut off, such as flash memories, phase - change RAMs (PRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), and ferroelectric RAMs (FRAMs).

[0005] Multiple hosts can access storage devices included in a shared memory pool. When host intervention occurs during data transfer between storage devices, the overhead of data transfer may increase. Therefore, it may be necessary for storage devices to send / receive data in a peer - to - peer (P2P) manner without any host intervention. Summary of the invention

[0006] The inventive concept provides a storage device and an operating method of the storage device, which can maintain cache coherence during peer - to - peer (P2P) data transfer between storage devices by mapping logical addresses to device physical addresses.

[0007] According to an aspect of the inventive concept, there is provided a storage device including a non-volatile memory and a storage controller. The storage controller includes: a cache memory configured to store some of the data stored in the non-volatile memory; an interface circuit configured to receive a first request including a source address related to an external storage device, a destination address related to the storage device, and cache update information indicating a cache update method of the cache memory from a first external host among a plurality of external hosts, provide a second request including the source address to the external storage device, and receive a response including first data corresponding to the source address from the external storage device that responds to the second request; a buffer memory configured to temporarily store the first data received from the external storage device; an address conversion circuit configured to generate a first type of physical address based on the destination address; and a cache controller configured to update a cache area indicated by the first type of physical address based on the cache update information.

[0008] According to another aspect of the inventive concept, there is provided an operation method of a storage device, the operation method including: receiving a first request from an external host, the first request including a source address indicating a storage area of the non-volatile memory, a destination address indicating a storage area of the external storage device, and cache update information indicating a cache update method of the cache memory; generating a first type of physical address indicating a cache area of the cache memory based on the source address; generating a second type of physical address indicating a storage area of the non-volatile memory based on the source address; obtaining data based on the first type of physical address and the second type of physical address; updating a cache area indicated by the first type of physical address based on the cache update information; providing a second request including the destination address and the data to the external storage device; and receiving a response corresponding to the second request from the external storage device.

[0009] According to another aspect of the inventive concept, there is provided an operation method of operating a storage device, the operation method including: receiving a first request from an external host, the first request including a source address indicating one of a storage area of the external storage device and a storage area of the non-volatile memory, a destination address indicating the remaining one of the storage area of the external storage device and the storage area of the non-volatile memory, and cache update information indicating a cache update method of the cache memory; providing a second request including one of the source address and the destination address to the external storage device; generating a first type of physical address indicating a cache area of the cache memory based on the remaining one of the source address and the destination address; updating a cache area indicated by the first type of physical address based on the cache update information; and receiving a response corresponding to the second request from the external storage device. Description of the Drawings

[0010] The embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a storage system according to an embodiment;

[0012] Figure 2 is a diagram showing Figure 1 the software layer of the storage system;

[0013] Figure 3 is a diagram showing a computing system according to an example embodiment;

[0014] Figure 4 is a diagram showing a peer-to-peer (P2P) read operation according to an example embodiment;

[0015] Figure 5 is a diagram showing a P2P read operation according to an example embodiment;

[0016] Figure 6 is a diagram showing a P2P write operation according to an example embodiment;

[0017] Figure 7 is a diagram showing a P2P write operation according to an example embodiment;

[0018] Figure 8 is a diagram showing a computing system according to an example embodiment;

[0019] Figure 9 is a diagram showing a computing system according to an example embodiment;

[0020] Figure 10 is a diagram showing a computing system according to an example embodiment;

[0021] Figure 11 is a block diagram of a computing system according to an embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a block diagram of a storage system 10 according to an embodiment. Referring to Figure 1 , the storage system 10 may include a host 11 and a storage device 100. In an embodiment, the storage system 10 may be an information processing device configured to process various information and store the processed information, such as a personal computer (PC), a laptop computer, a server, a workstation, a smart phone, a tablet PC, a digital camera, and a black box.

[0024] The host 11 can control all operations of the storage system 10. For example, the host 11 can send a request (or command) to the storage device 100 to store data in the storage device 100 or read data stored in the storage device 100. In an embodiment, the host 11 can be a processor core (e.g., a central processing unit (CPU) or an application processor (AP)) configured to control the storage system 10 or a computing node connected through a network.

[0025] In an embodiment, the host 11 can include a host controller 12 and a host memory 13. The host controller 12 can be a device configured to control all operations of the host 11 or control the storage device 100 from the host 11. The host memory 13 can be a buffer memory, a cache memory, or an operating memory used in the host 11.

[0026] The host 11 can send a peer-to-peer (P2P) data transfer trigger request to the storage device 100. In response to the P2P data transfer trigger request, the storage device 100 can provide data to another storage device or receive data from another storage device. The packet format corresponding to the P2P data transfer trigger request can be a CXL.io packet.

[0027] The P2P data transfer trigger request can include a source address indicating a storage area in one of the storage device 100 (e.g., a storage area of the non-volatile memory device 120) and another storage device, a destination address indicating a storage area of the remaining one of the storage device 100 and another storage device, and data size information. In response to the P2P data transfer trigger request, the data included in the storage area indicated by the source address can be sent to the storage area indicated by the destination address.

[0028] The P2P data transfer trigger request can be a block-based request for block-based access. That is, the source address or the destination address can be a logical block address (or a logical address). The block-based request can use the logical block address to indicate the location where data will be written or from which data will be read. When the source address or the destination address is a logical block address, the P2P data transfer trigger request can include data size information in units of blocks. The data size information can indicate the size of the data to be transmitted. For example, in a P2P read request, the data size information can indicate the size of the read data sent from another storage device to the storage device 100, and in a P2P write request, the data size information can indicate the size of the write data sent from the storage device 100 to another storage device. When the source address or the destination address is a logical block address, the unit of the data to be transmitted can be a logical block size (e.g., 512 bytes) or a page size (e.g., 4 kilobytes). However, the scope of the present disclosure is not limited thereto.

[0029] The P2P data transfer trigger request may be a memory-based request for memory-based access. That is, the source address or the destination address may be a host physical address (or a physical address). The memory-based request may use the host physical address to indicate the location where data is to be written or from which data is to be read. When the source address or the destination address is a host physical address, the P2P data transfer trigger request may include data size information in a unit smaller than a block unit (or a page unit), such as a byte unit or a cache line unit. The cache line unit may be 64 bytes. The data size information may indicate the size of the data to be transferred. For example, in a P2P read request, the data size information may indicate the size of the read data sent from another storage device to the storage device 100, and in a P2P write request, the data size information may indicate the size of the write data sent from the storage device 100 to another storage device. When the source address or the destination address is a host physical address, the unit of the data to be transferred may be a byte or a cache line size. However, the scope of the present disclosure is not limited thereto.

[0030] The P2P data transfer trigger request may include cache update information. The cache update information may indicate an update method for the cache memory 116 in the storage device 100 and the cache memory in another storage device. For example, the cache update information may indicate one of a partial update operation, a full update operation, and an invalidation operation. The partial update operation may be an operation of performing an update by storing some (but not all) of the data corresponding to the P2P data transfer trigger request in a cache line in the cache memory 116. The full update operation may be an operation of performing an update by storing all of the data corresponding to the P2P data transfer trigger request in a cache line in the cache memory 116. The invalidation operation may be an operation of invalidating a cache line storing data corresponding to the P2P data transfer trigger request.

[0031] In this specification, the P2P data transfer trigger request may be referred to as a request.

[0032] Although the storage system 10 is shown as including one host in Figure 1 the storage system 10 may include multiple hosts. Each of the multiple hosts may be configured to access the storage device 100.

[0033] For example, each of the multiple hosts may be a computing node configured to operate independently of each other. The multiple hosts may be single-core or multi-core processors included in different computing nodes (or computing systems). Alternatively, at least some of the multiple hosts may be different processors included in the same computing node (or computing system). Alternatively, the multiple hosts may be processes / processors configured to process different applications.

[0034] In an embodiment, the storage system 10 may further include an accelerator (not shown). The accelerator may assist the host in performing various types of arithmetic operations, calculations, etc. on data. The accelerator may be configured to access the storage device 100. For example, the accelerator may send a request to the storage device 100.

[0035] The storage device 100 may operate under the control of the host 11. The storage device 100 may include a storage controller 110 and a non-volatile memory (NVM) device 120. The storage controller 110 may store data in the non-volatile memory device 120 or read data stored in the non-volatile memory device 120 under the control of the host 11. In an embodiment, the storage controller 110 may perform various management operations to efficiently use the non-volatile memory device 120.

[0036] The storage device 100 may manage host physical address to device physical address (H2D) mapping and logical address to device physical address (L2D) mapping. The H2D mapping may include mapping information between the host physical address and the device physical address. The L2D mapping may include mapping information between the logical address and the device physical address. The H2D mapping and the L2D mapping may be stored in the address converter 117, the buffer memory 115, or the non-volatile memory device 120. The storage device 100 may manage logical address to physical page address (L2P) mapping. The L2P mapping may include mapping information between the logical address and the physical page address. The L2P mapping may be stored in the buffer memory 115.

[0037] The host physical address may indicate the actual physical address of the hardware memory device managed by the host 11. The host 11 may identify or manage the storage space of at least one memory device (e.g., a cache memory (not shown), the host memory 13, or the storage device 100) as the host physical address. That is, the host physical address may be used to access the storage space of at least one memory device in units of bytes or in units of cache lines. Although in Figure 1 the storage system 10 is shown as including one storage device, the storage system 10 may include multiple storage devices. The host 11 may be configured to access multiple storage devices. The host 11 may manage a separate host physical address space for each of the multiple storage devices.

[0038] The logical address may indicate the logical block address managed by the host 11. The file system layer (FS) of the host 11 may identify or manage the storage space of the storage device 100 as the logical address. That is, the logical address may be used to access the storage space of the storage device 100 based on blocks or pages.

[0039] The device physical address may indicate the actual physical address of the storage space in the storage device 100 managed by the storage device 100. The device physical address may indicate the actual physical addresses of the non-volatile memory device 120, the buffer memory 115, and the cache memory 116. The device physical address may be used to access the storage space of the storage device 100 in units of bytes or in units of cache lines.

[0040] The physical page address may indicate the actual physical address of the non-volatile memory device 120 managed by the storage controller 110. The storage controller 110 may identify or manage the storage space of the non-volatile memory device 120 as physical page addresses. That is, the physical page address may be used to access the storage space of the non-volatile memory device 120 based on pages.

[0041] In an embodiment, the host 11 may use a logical address or a host physical address to access the storage space of the storage device 100. For example, the storage space of the storage device 100 may be exposed to the host 11 as a memory mapped region. Alternatively, the storage space of the storage device 100 may be exposed to the host 11 as a region that allows block-based access.

[0042] The storage controller 110 may include a central processing unit (CPU) 111, a flash translation layer (FTL) 112, a cache controller 113, a buffer manager 114, a buffer memory 115, a cache memory 116, an address converter 117, a request scheduler 118, a multi-protocol host interface circuit 210, and a memory interface circuit 220.

[0043] The CPU 111 may control all operations of the storage controller 110. The FTL 112 may perform various operations to efficiently use the non-volatile memory device 120. For example, the FTL 112 may be configured to manage the address mapping between the logical address from the host 11 and the physical page address of the storage device 100. That is, the FTL 112 may manage the L2P mapping. For example, the FTL 112 may convert the logical address of the first type request T1RQ into a physical page address with reference to the L2P mapping. The FTL 112 may receive the logical address converted based on the host physical address of the second type request T2RQ with reference to the H2D mapping and the L2D mapping, and may convert the logical address into a physical page address.

[0044] The FTL 112 may perform a wear leveling operation to prevent a certain memory block among the memory blocks (floating blocks) of the non-volatile memory device 120 from deteriorating excessively. The lifetime of the non-volatile memory device 120 may be improved through the wear leveling operation of the FTL 112. The FTL 112 may perform garbage collection on the non-volatile memory device 120 to ensure free memory blocks.

[0045] In an embodiment, the FTL 112 may be implemented in software or hardware. When the FTL 112 is implemented in software, program code or information related to the FTL 112 may be stored in the buffer memory 115 and executed by the CPU 111. When the FTL 112 is implemented in hardware, a hardware accelerator configured to perform the operations of the FTL 112 may be provided separately from the CPU 111.

[0046] The cache controller 113 may control access operations and update operations to the cache memory 116. The cache controller 113 may access the cache memory 116 based on the device physical address. The cache controller 113 may receive cache update information from the host 11 and perform an update operation on the cache memory 116 based on the cache update information. After performing the update operation on the cache memory 116, the cache controller 113 may provide back-invalidate (BI) information to the host 11. In some embodiments, the cache controller 113 may provide BI information to the host 11 before performing the update operation on the cache memory 116. The host 11 may maintain cache coherence with the cache memory 116 based on the BI information.

[0047] The cache controller 113 may check whether data for a given device physical address is cached in the cache memory 116. When data for the device physical address is cached in the cache memory 116 (cache hit), the data stored in the cache line indicated by the device physical address may be immediately available. When data for the device physical address is not cached in the cache memory 116 (cache miss), the corresponding data may be cached from the non-volatile memory device 120 to the cache memory 116 through various cache update methods.

[0048] In an embodiment, the cache controller 113 may support cache coherence. For example, the storage system 10 may use the Compute Express Link (CXL) TM protocol (e.g., CXL.cache) to provide cache coherence. The storage system 10 may provide cache coherence by listening to requests (or BI information) and responses.

[0049] The cache memory 116 may include multiple cache lines (or cache regions). The cache memory 116 may store some (e.g., some but not all) of the data stored in the non-volatile memory device 120 in the multiple cache lines. For example, the cache memory 116 may include multiple cache lines containing tags and data. For example, the tags may store information about the device physical address.

[0050] The buffer manager 114 can manage the buffer memory 115. During the P2P transfer operation between the storage device 100 and the external storage device, the buffer manager 114 can control the buffer memory 115 to temporarily store the data to be provided to the external storage device or the data provided from the external storage device.

[0051] The buffer memory 115 can be a write buffer or a read buffer configured to temporarily store the data input to the storage controller 110 or the data to be output from the storage controller 110. Alternatively, the buffer memory 115 can be configured to store various information required for the operation of the storage controller 110. For example, the buffer memory 115 can store the L2P mapping managed by the FTL 112. Alternatively, the buffer memory 115 can store software, firmware, or information related to the FTL 112. Alternatively, the buffer memory 115 can store the H2D mapping and the L2D mapping managed by the address converter 117.

[0052] In an embodiment, the buffer memory 115 can be a static random access memory (SRAM), but the scope of the present disclosure is not limited thereto, and the buffer memory 115 can be implemented using various types of memory devices (e.g., dynamic random access memory (DRAM), magnetic random access memory (MRAM), and phase change random access memory (PRAM)). For the sake of simplicity of the drawings and convenience of description, in Figure 1 the buffer memory 115 is shown as being included in the storage controller 110, but the scope of the present disclosure is not limited thereto. The buffer memory 115 can be located outside the storage controller 110, and the storage controller 110 can communicate with the buffer memory 115 through the buffer manager 114.

[0053] The address converter 117 can convert the logical address included in the first type of request T1RQ into a device physical address with reference to the L2D mapping. The address converter 117 can convert the host physical address included in the second type of request T2RQ into a device physical address with reference to the H2D mapping. The cache controller 113 can access the cache memory 116 based on the device physical address. The address converter 117 can convert the device physical address into a logical address with reference to the L2D mapping. The FTL 112 can convert the logical address into a physical page address with reference to the L2P mapping.

[0054] The request scheduler 118 can be configured to schedule requests received from multiple hosts including the host 11, requests received from multiple external storage devices, or requests received from an external accelerator.

[0055] In an embodiment, the request scheduler 118 may schedule requests based on cache update information, internal operation information of the non-volatile memory device 120, and cache competition information of the cache memory 116.

[0056] Specifically, when the cache update information included in the P2P data transmission trigger request indicates an invalidation operation, the request scheduler 118 may determine that the importance of the data corresponding to the P2P data transmission trigger request is the lowest, and may sort the requests such that a first number of other requests are processed before subsequent operations corresponding to the P2P data transmission trigger request. When the cache update information included in the P2P data transmission trigger request indicates a partial update operation, the request scheduler 118 may determine that the importance of the data corresponding to the P2P data transmission trigger request is average, and may sort the requests such that a second number of other requests are processed before subsequent operations corresponding to the P2P data transmission trigger request. The second number may be less than the first number. When the cache update information included in the P2P data transmission trigger request indicates a full update operation, the request scheduler 118 may determine that the importance of the data corresponding to the P2P data transmission trigger request is relatively high, and may sort the requests such that a third number of other requests are processed before subsequent operations corresponding to the P2P data transmission trigger request. The third number may be less than the second number. For example, the third number may be 0.

[0057] The request scheduler 118 may schedule requests based on whether internal operations such as garbage collection or wear leveling are performed within the non-volatile memory device 120.

[0058] The request scheduler 118 may schedule requests based on cache competition information indicating the degree to which cache lines in the cache memory 116 are replaced.

[0059] The multi-protocol host interface circuit 210 can be configured to communicate with the host 11 according to a predetermined interface protocol. In an embodiment, the predetermined interface protocol may include at least one of various interface protocols (e.g., Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer System Interface (SCSI) interface, Serial Attached SCSI (SAS) interface, Peripheral Component Interconnect (PCI) interface, PCI Express (PCIe) interface, Non-Volatile Memory Express (NVMe) interface, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash Storage (UFS) interface, Embedded Universal Flash Storage (eUFS) interface, Compact Flash (CF) card interface, and network interface). The multi-protocol host interface circuit 210 can receive signals from the host 11 based on the predetermined interface protocol and operate based on the received signals. Alternatively, the multi-protocol host interface circuit 210 can send signals to the host 11 based on the predetermined interface protocol.

[0060] The memory interface circuit 220 can be configured to communicate with the non-volatile memory device 120 according to a predetermined interface protocol. In an embodiment, the predetermined interface protocol may include at least one of various interface protocols (e.g., toggle interface and Open NAND Flash Interface (ONFI) interface). In an embodiment, the memory interface circuit 220 can communicate with the non-volatile memory device 120 based on the toggle interface. In this case, the memory interface circuit 220 can communicate with the non-volatile memory device 120 through a plurality of channels CH. In an embodiment, each of the plurality of channels CH may include a plurality of signal lines configured to transmit various control signals (e.g., / Chip Enable (CE), Command Latch Enable (CLE), Address Latch Enable (ALE), / Write Enable (WE), / Read Enable (RE), Ready / Busy (R / B), etc.), data signals DQ, and data strobe signals DQS.

[0061] The non-volatile memory device 120 may be configured to store data, output stored data, or erase stored data under the control of the storage controller 110. In an embodiment, the non-volatile memory device 120 may be a two-dimensional or three-dimensional NAND flash memory device, but the scope of the present disclosure is not limited thereto, and the non-volatile memory device 120 may be a memory device based on magnetic RAM (MRAM), spin-transfer torque MRAM, conductive-bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM, or various other types of memories. In an embodiment, the non-volatile memory device 120 may include a plurality of non-volatile memories, and each of the plurality of non-volatile memories may be implemented as a separate chip or a separate package. The storage controller 110 may communicate with each of the plurality of non-volatile memories of the non-volatile memory device 120 through a plurality of channels.

[0062] As described above, the storage device 100 according to an embodiment may transmit data to and receive data from an external storage device in response to a P2P data transfer trigger request provided from the host 11 (e.g., by connecting the storage device 100 to a switch of the external storage device).

[0063] Figure 2 is a diagram showing Figure 1 the software layer of the storage system. Referring to Figure 1 and Figure 2 , the software layer of the storage system 10 may include an application layer APP, a file system layer FS, an address manager AM, a device driver layer DD, an address converter 117, and a flash translation layer 112.

[0064] The application layer APP may include various application programs running on the host 11. The file system layer FS may be configured to organize files or data used by the application layer APP. For example, the file system layer FS may manage the storage space of the storage device 100 as logical block addresses. The file system layer FS may assign logical block addresses to data stored in the storage device 100 and manage the logical block addresses. In an embodiment, the file system layer FS may have different forms according to the operating system (OS) of the host 11. The file system layer FS may include at least one of various file system types (e.g., File Allocation Table (FAT), FAT32, NT File System (NTFS), Hierarchical File System (HFS), Journaling File System 2 (JSF2), XFS, On-disk Structure 5 (ODS-5), UDF, ZFS, Unix File System (UFS), ext2, ext3, ext4, ReiserFS, Reiser4, ISO 9660, Gnome VFS, BFS, and WinFS).

[0065] The address manager AM can manage the storage space of the storage device 100 based on the host physical address. The address manager AM can convert the host physical address to a logical address or convert the logical address to the host physical address.

[0066] The device driver layer DD can perform operations to convert information from the address manager AM, the file system layer FS, or the application layer APP into information recognizable by the storage device 100. In an embodiment, the application layer APP, the file system layer FS, the address manager AM, and the device driver layer DD can be implemented in software and can run on the host 11.

[0067] The address converter 117 can manage the storage space of the storage device 100 based on the device physical address. When receiving the host physical address from the device driver layer DD, the address converter 117 can convert the host physical address to the device physical address by referring to the H2D mapping. The device physical address can be used during the cache update operation. In addition, the address converter 117 can convert the device physical address to a logical address by referring to the L2D mapping. The FTL 112 can convert the converted logical address to a physical page address. The non-volatile memory device 120 can perform internal operations on the area corresponding to the physical page address.

[0068] When receiving the logical address from the device driver layer DD, the address converter 117 can convert the logical address to the device physical address by referring to the L2D mapping. The device physical address can be used during the cache update operation. The FTL 112 can convert the logical address from the device driver layer DD to a physical page address. The non-volatile memory device 120 can perform internal operations on the area corresponding to the physical page address.

[0069] In a typical storage system, the storage device only provides input / output requests in units of blocks or pages, which may be larger than the data size required by the application layer APP. The input / output requests in units of blocks or pages are provided to the storage device through the file system layer FS. Since the size of the data required by the application layer APP is smaller than the block or page unit, the overhead of the software layer increases, and the transmission of unnecessary data increases. Therefore, the performance of the application layer APP may be reduced, and the power / energy efficiency of the entire storage system may be reduced.

[0070] The storage device 100 according to an embodiment can perform P2P transmission operations by using the H2D mapping and the L2D mapping in response to P2P data transmission trigger requests in units smaller than the block or page unit (e.g., byte unit) and P2P data transmission trigger requests in units of blocks or pages.

[0071] By using the H2D mapping and the L2D mapping, the storage device 100 can perform a cache update operation in response to a P2P data transfer trigger request in units smaller than a block or a page (e.g., byte unit) and a P2P data transfer trigger request in units of a block or a page.

[0072] The application layer APP can trigger a P2P transfer operation between the storage device 100 and an external storage device by providing a P2P data transfer trigger request for data smaller than a block or a page in size.

[0073] Since only data smaller than a block or a page in size can be transferred between the storage device 100 and the external storage device, unnecessary data transfer can be reduced. Therefore, the power / energy efficiency can be improved.

[0074] Figure 3 FIG. is a diagram showing a computing system 300 according to an exemplary embodiment.

[0075] Referring to Figure 3 , the computing system 300 may include a first host 311 to a fourth host 314, a first memory device 321 to a sixth memory device 326, a network interface card (NIC) 330, a fabric manager 340, and a CXL switch 350. The CXL switch 350 may be included in a CXL fabric. Although not shown in the figure, the CXL fabric may include a plurality of CXL switches. The fabric manager 340 may control all operations of the CXL fabric. The fabric manager 340 may store assignment information between the fabric manager 340, the first host 311 to the fourth host 314, the NIC 330, and the first memory device 321 to the sixth memory device 326.

[0076] The first host 311 to the fourth host 314, the first memory device 321 to the sixth memory device 326, and the NIC 330 may communicate with each other through the CXL switch 350.

[0077] In an embodiment, each of the first host 311 to the fourth host 314 may be the host 11 described above with reference to Figure 1 and Figure 2 . Although not shown in the figure, each of the first host 311 to the fourth host 314 may be directly connected to a separate memory device. Each of the first memory device 321 to the fifth memory device 325 may be the storage device 100 described above with reference to Figure 1 and Figure 2 .

[0078] The CXL fabric may be connected to an external network or an external fabric through the NIC 330, and may be configured to communicate with an external server through the external network or the external fabric.

[0079] Refer to Figure 3 , the fabric manager 340 can be assigned to the first memory device 321, the first host 311 can be assigned to the NIC 330, the second host 312 can be assigned to the second memory device 322 and the third memory device 323, the third host 313 can be assigned to the fourth memory device 324 and the fifth memory device 325, and the fourth host 314 can be assigned to the sixth memory device 326. The first memory device 321 to the fifth memory device 325 can be referred to as "far local" memory devices, which are connected to the fabric manager 340 and the first host 311 to the third host 313 through the CXL switch 350. The sixth memory device 326 can be referred to as a "near local" memory device, which is directly connected to the fourth host 314.

[0080] The first host 311 to the fourth host 314 can manage the first host physical address HPA1 to the fourth host physical address HPA4 respectively. That is, each of the first host 311 to the fourth host 314 can manage a unique host physical address.

[0081] For example, the second host physical address HPA2 can include a local area, a global fabric-attached memory (G-FAM) area, and a global integrated memory (GIM) area.

[0082] The local area can be an address area that maps to the device physical addresses of the second memory device 322 and the third memory device 323 assigned to the second host 312.

[0083] The G-FAM area can be an address area that maps to the device physical addresses of the G-FAM device (e.g., the first memory device 321).

[0084] The GIM area can be an address area that maps to the device physical addresses of the fourth memory device to the sixth memory device 324, 325, and 326 assigned to other hosts (i.e., the third host 313 and the fourth host 314).

[0085] As described above with reference to Figure 1 and Figure 2 , each of the first host 311 to the fourth host 314 can trigger a P2P transfer operation between the first memory device 321 to the sixth memory device 326 by providing a P2P data transfer trigger request. Each of the first host 311 to the fourth host 314 can maintain cache coherence between the first memory device 321 to the sixth memory device 326 by providing cache update information.

[0086] Figure 4 It is a diagram showing a P2P read operation according to an exemplary embodiment.

[0087] Referring to Figure 4 , the first host 410 can be connected to the first storage device 420 and the second storage device 430 through a CXL switch. The first host 410 can correspond to Figure 1 and Figure 2 the host 11. Each of the first storage device 420 and the second storage device 430 can correspond to Figure 1 and Figure 2 the storage device 100. In some embodiments, the first storage device 420 and the second storage device 430 can be external to each other.

[0088] The first host 410 can manage the host physical address HPA. The host memory 412 can store the host physical address HPA. The host physical address HPA can include a first host physical address HPA_D1 and a second host physical address HPA_D2. The first host physical address HPA_D1 can be an address area mapped to the device physical address DPA_D1 of the first storage device 420. The second host physical address HPA_D2 can be an address area mapped to the device physical address DPA_D2 of the second storage device 430.

[0089] The first host 410 can provide a P2P read trigger request prt_REQ (①) to the first storage device 420 (e.g., to its multi-protocol host interface circuit 210 ( Figure 1 ). The P2P read trigger request prt_REQ can include a source address src (which can identify through a switch such as 350 ( Figure 3) The switch is connected to the external storage device of the first storage device 420 / related to the external storage device), the destination address dest (which can identify the first storage device 420 / related to the first storage device 420), and the cache update information c_info (which can indicate the update method of the cache memory 425). As an example, the P2P read trigger request prt_REQ may include an unordered IO (UIO) packet of CXL.io, and the cache update information c_info may be included in the reserved field of the UIO packet. As an example, the cache update information c_info may be included in a PCIe packet (e.g., an NVMe command). The source address src may be the second host physical address HPA_D2, and the destination address dest may be the logical address LA_D1. The logical address LA_D1 is a logical address managed by the first host 410 and can indicate the storage space of the first storage device 420. The first host 410 may use the logical address LA_D1 or the first host physical address HPA_D1 to access the storage space of the first storage device 420. In some embodiments, the P2P read trigger request prt_REQ may be referred to herein as the "first request", and the multi-protocol host interface circuit 210 may be configured to provide a second request including the source address src to an external storage device connected to the first storage device 420 through a switch. In addition, the multi-protocol host interface circuit 210 may be configured to receive a response including data corresponding to the source address src from the external storage device in response to the second request.

[0090] The first storage device 420 may provide a read command pRd_CMD (e.g., the "second request") including the second host physical address HPA_D2 and the cache update information c_info to the second storage device 430 (②). As an example, the read command pRd_CMD may include a CXL.mem packet, and the cache update information c_info may be included in the reserved field of the CXL.mem packet. As an example, the read command pRD_CMD may include a UIO packet, and the cache update information c_info may be included in the reserved field of the UIO packet. In some embodiments, the read command pRd_CMD may be generated by a direct memory access (DMA) circuit included in the first storage device 420. In addition, the first storage device 420 may activate the buffer memory 424 so that the data received from the second storage device 430 can be stored in the buffer memory 424.

[0091] The address converter 431 included in the second storage device 430 may convert the second host physical address HPA_D2 included in the read command pRd_CMD into the device physical address DPA_D2 of the second storage device 430 (③-①). Specifically, the address converter 431 may refer to the H2D mapping to generate the device physical address DPA_D2 of the second storage device 430 mapped to the second host physical address HPA_D2. The embodiment is not limited thereto, and the address converter 431 may use the H2D mapping algorithm to generate the device physical address DPA_D2.

[0092] The address converter 431 may refer to the L2D mapping and generate the logical address LA_D2 mapped to the device physical address DPA_D2 (③-②). The logical address LA_D2 may be the logical address of the second storage device 430 managed by a host (e.g., the second host) assigned to the second storage device 430. In some embodiments, the L2D mapping may be provided to the storage device 430 when the second storage device 430 is initialized. The logical address LA_D2 may be provided to the FTL 432.

[0093] Among the cache lines included in the cache memory 435, the cache line indicated by the second device physical address DPA_D2 may be transferred to the buffer memory 434 (④-①). Specifically, the cache controller 436 may convert the second device physical address DPA_D2 into an index of the cache line, and when there is a cache line with the converted index (cache hit), the cache controller 436 may provide the data of the cache line to the buffer memory 434. In some embodiments, only some (and thus not all) of the data indicated by the second host physical address HPA_D2 may be stored in the cache memory 435. Therefore, the cache controller 436 may provide the data stored in the cache memory 435 among the data indicated by the second host physical address HPA_D2 to the buffer memory 434.

[0094] The FTL 432 can generate a physical page address based on the logical address LA_D2, and the non-volatile memory 433 can read data from the storage area indicated by the physical page address and provide the read data to the buffer memory 434 (④-②). The non-volatile memory 433 can provide data other than the data cached in the cache memory 435 to the buffer memory 434. That is, when there is no cache line corresponding to the second device physical address DPA_D2 in the cache memory 435 (cache miss), the FTL 432 can read data corresponding to the second device physical address DPA_D2 from the non-volatile memory 433 based on the logical address LA_D2. In some embodiments, only some (and thus not all) of the data indicated by the second host physical address HPA_D2 may be stored in the cache memory 435. Therefore, the FTL 432 can read the data not stored in the cache memory 435 among the data indicated by the second host physical address HPA_D2 from the non-volatile memory 433 and provide the read data to the buffer memory 434. The size of the data indicated by the second device physical address DPA_D2 may be smaller than the size of the data indicated by the logical address LA_D2. For example, the size of the data indicated by the second device physical address DPA_D2 may be 64 bytes, and the size of the data indicated by the logical address LA_D2 may be N kilobytes (N is a natural number).

[0095] The cache controller 436 can perform a cache update operation on the cache memory 435 based on the cache update information c_info (⑤). Specifically, when the cache update information c_info indicates an invalidation operation, the cache controller 436 can invalidate the cache line corresponding to the data stored in the buffer memory 434. When the cache update information c_info indicates a partial update operation, the cache controller 436 can update some (but not all) of the data stored in the buffer memory 434 to the cache line. When the cache update information c_info indicates a full update operation, the cache controller 436 can update all of the data stored in the buffer memory 434 to the cache line.

[0096] The second storage device 430 can provide a read response pRd_RSP including the data RdData stored in the buffer memory 434 to the first storage device 420 (⑥). The data RdData can be stored in the buffer memory 424 in the first storage device 420.

[0097] The address converter 421 of the first storage device 420 may convert the logical address LA_D1 into a first device physical address DPA_D1 (⑦) with reference to the L2D mapping. Thus, the address converter 421 (which may include an address conversion circuit) may be configured to generate a first type of physical address (i.e., the first device physical address DPA_D1) based on the destination address dest (which may be the logical address LA_D1). In some embodiments, the L2D mapping may be provided to the storage device 420 when the first storage device 420 is initialized. Further, according to some embodiments, the address converter 421 may be configured to convert the destination address dest into a first type of physical address (i.e., the first device physical address DPA_D1) when the destination address dest is a logical address indicating data in units of blocks (e.g., the logical address LA_D1).

[0098] The logical address LA_D1 may be provided to the FTL 422, and the FTL 422 may convert the logical address LA_D1 into a physical page address of the non-volatile memory 423 (⑧). Thus, the FTL 422 may be configured to convert the destination address dest (which may be the logical address LA_D1) into a second type of physical address indicating a storage area of the non-volatile memory 423. The non-volatile memory 423 may store the data RdData in the buffer memory 424 in the storage area indicated by the physical page address (⑧). Thus, the non-volatile memory 423 may be configured to store the data stored in the buffer memory 424 in the storage area indicated by the second type of physical address.

[0099] The cache controller 426 may update the data RdData into the cache line (i.e., the cache area) indicated by the first device physical address DPA_D1 among the cache lines of the cache memory 425 (⑨). Specifically, the cache controller 426 may perform an update operation based on the cache update information c_info. When the cache update information c_info indicates an invalidation operation, the cache controller 426 may invalidate the cache line indicated by the first device physical address DPA_D1 in the buffer memory 424. When the cache update information c_info indicates a partial update operation, the cache controller 426 may update some (but not all) of the data RdData stored in the buffer memory 424 into the cache line. When the cache update information c_info indicates a full update operation, the cache controller 426 may update all of the data stored in the buffer memory 424 into the cache line.

[0100] The first storage device 420 may provide a P2P read response prt_RSP to the P2P read trigger request prt_REQ to the first host 410 (⑩).

[0101] Figure 5 FIG. is a diagram showing a P2P read operation according to an exemplary embodiment.

[0102] Referring to Figure 5 , different from Figure 4 , the destination address dest included in the P2P read trigger request prt_REQ may be the first host physical address HPA_D1.

[0103] Therefore, the address converter 421 may convert the first host physical address HPA_D1 to the first device physical address DPA_D1 (⑦-①) with reference to the H2D mapping, and may convert the first device physical address DPA_D1 to the logical address LA_D1 (⑦-②) with reference to the L2D mapping. In some embodiments, when the destination address dest is a host physical address indicating data in a unit smaller than a block unit (e.g., the first host physical address HPA_D1), the address converter 421 may be configured to convert the destination address dest to the first device physical address DPA_D1 (i.e., the first type of physical address), and convert the first device physical address DPA_D1 to a logical address indicating data in block units (e.g., the logical address LA_D1).

[0104] That is, the first storage device 420 may provide a P2P read operation function for the logical address LA_D1 and the first host physical address HPA_D1 by performing address conversion based on the L2D mapping.

[0105] Figure 6 FIG. is a diagram showing a P2P write operation according to an exemplary embodiment.

[0106] Referring to Figure 6 , the first host 410 may provide a P2P write trigger request pwt_REQ (①) to the first storage device 420. The P2P write trigger request pwt_REQ may include a source address src, a destination address dest, and cache update information c_info. As an example, the P2P write trigger request pwt_REQ may include a UIO packet of CXL.io, and the cache update information c_info may be included in a reserved field of the UIO packet. The source address src may be the logical address LA_D1, and the destination address dest may be the second host physical address HPA_D2. The logical address LA_D1 is a logical address managed by the first host 410 and may indicate the storage space of the first storage device 420. The first host 410 may use the logical address LA_D1 or the first host physical address HPA_D1 to access the storage space of the first storage device 420. The second host physical address HPA_D2 may be an address area mapped to the device physical address DPA_D2 of the second storage device 430.

[0107] The address converter 421 of the first storage device 420 can convert the logical address LA_D1 into a first device physical address DPA_D1 (which can be a first type of physical address) with reference to the L2D mapping (②).

[0108] Among the cache lines included in the cache memory 425, the cache line (e.g., cache region) indicated by the first device physical address DPA_D1 can be transferred to the buffer memory 424 (③-①). Specifically, the cache controller 426 can convert the first device physical address DPA_D1 into an index of the cache line, and when there is a cache line with the converted index (cache hit), the cache controller 426 can provide the data of the cache line to the buffer memory 424. In some embodiments, only some (and thus not all) of the data indicated by the logical address LA_D1 can be stored in the cache memory 425. Therefore, the cache controller 426 can provide the data stored in the cache memory 425 among the data indicated by the logical address LA_D1 to the buffer memory 424.

[0109] The FTL 422 can generate a physical page address based on the logical address LA_D1, and the non-volatile memory 423 can read data from the storage area indicated by the physical page address and provide the read data to the buffer memory 424 (③-②). That is, when there is no cache line corresponding to the first device physical address DPA_D1 in the cache memory 425 (cache miss), the FTL 422 can read the data corresponding to the first device physical address DPA_D1 from the non-volatile memory 423 based on the logical address LA_D1. In some embodiments, the non-volatile memory 423 can provide the data other than the data cached in the cache memory 425 to the buffer memory 424. That is, only some (and thus not all) of the data indicated by the logical address LA_D1 can be stored in the cache memory 425. Therefore, the FTL 422 can read the data not stored in the cache memory 425 among the data indicated by the logical address LA_D1 from the non-volatile memory 423 and provide the read data to the buffer memory 424. The size of the data indicated by the first device physical address DPA_D1 can be smaller than the size of the data indicated by the logical address LA_D1. For example, the size of the data indicated by the first device physical address DPA_D1 can be 64 bytes, and the size of the data indicated by the logical address LA_D1 can be N kilobytes (N is a natural number).

[0110] The cache controller 426 may perform a cache update operation (④) on the cache memory 425 based on the cache update information c_info. Specifically, when the cache update information c_info indicates an invalidation operation, the cache controller 426 may invalidate the cache line indicated by the first device physical address DPA_D1. When the cache update information c_info indicates a partial update operation, the cache controller 426 may update some (but not all) of the data stored in the buffer memory 424 to the cache line. When the cache update information c_info indicates a full update operation, the cache controller 426 may update all of the data stored in the buffer memory 424 to the cache line.

[0111] The first storage device 420 may provide a write command pWr_CMD (⑤) including a second host physical address HPA_D2, data WrData stored in the buffer memory 424, and cache update information c_info to the second storage device 430. As an example, the write command pWr_CMD may include a CXL.mem data packet, and the cache update information c_info may be included in a reserved field of the CXL.mem data packet. In some embodiments, the write command pWr_CMD may be generated by a DMA circuit included in the first storage device 420.

[0112] The address converter 431 of the second storage device 430 may convert the second host physical address HPA_D2 to a second device physical address DPA_D2 (which may be a second type of physical address) by referring to the H2D mapping (⑥-①).

[0113] The address converter 431 may convert the second device physical address DPA_D2 to a logical address LA_D2 by referring to the L2D mapping (⑥-②).

[0114] The FTL 432 may convert the logical address LA_D2 to a physical page address by referring to the L2P mapping (⑦-①). The non-volatile memory 433 may store the data WrData stored in the buffer memory 434 in the storage area indicated by the physical page address (⑦-②).

[0115] The cache controller 436 may update the data WrData to the cache line indicated by the second device physical address DPA_D2 among the cache lines of the cache memory 435 (⑧). Specifically, the cache controller 436 may perform an update operation based on the cache update information c_info. When the cache update information c_info indicates an invalidation operation, the cache controller 436 may invalidate the cache line indicated by the second device physical address DPA_D2 in the buffer memory 434. When the cache update information c_info indicates a partial update operation, the cache controller 436 may update some of the data WrData stored in the buffer memory 434 to the cache line. When the cache update information c_info indicates a full update operation, the cache controller 436 may update all of the data WrData stored in the buffer memory 434 to the cache line.

[0116] The second storage device 430 may provide a write response pWr_RSP corresponding to the write command pWr_CMD to the first storage device 420 (⑨).

[0117] The first storage device 420 may provide a P2P write response pwt_RSP to the P2P write trigger request pwt_REQ to the first host 410 (⑩).

[0118] Figure 7 is a diagram showing a P2P write operation according to an exemplary embodiment.

[0119] Refer to Figure 7 , different from Figure 6 , the source address src included in the P2P write trigger request pwt_REQ may be the first host physical address HPA_D1.

[0120] Therefore, the address converter 421 may convert the first host physical address HPA_D1 to the first device physical address DPA_D1 by referring to the H2D mapping (②-①), and may convert the first device physical address DPA_D1 to the logical address LA_D1 by referring to the L2D mapping (②-②).

[0121] That is, the first storage device 420 may provide a P2P write operation function for the logical address LA_D1 and the first host physical address HPA_D1 by performing address conversion based on the L2D mapping.

[0122] Figure 8 is a diagram showing a computing system 800 according to an exemplary embodiment.

[0123] Refer to Figure 8, the first host 811 and the second host 812 can communicate with each other. The first host 811, the second host 812, the first storage device 821, and the second storage device 822 can be interconnected via a CXL switch.

[0124] The first host 811 can provide a write request w_REQ(①) to the first storage device 821. The first storage device 821 can store the write data WrData provided in the write request w_REQ in the storage area indicated by the first host physical address HPA_D1.

[0125] The first host 811 can provide a P2P write trigger request pwt_REQ(②) to the first storage device 821. That is, when the first host 811 determines that the write data WrData is important data, the first host 811 can provide the P2P write trigger request pwt_REQ to the first storage device 821 to be copied to the second storage device 822. The P2P write trigger request pwt_REQ can include the first host physical address HPA_D1 as the source address, the second host physical address HPA_D2 as the destination address, and cache update information c_info.

[0126] The first storage device 821 can provide a P2P write command pWr_CMD(③) to the second storage device 822. The P2P write command pWr_CMD can include the second host physical address HPA_D2 as the destination address, the write data WrData, and cache update information c_info.

[0127] The second storage device 822 can store the write data WrData in the storage area indicated by the second host physical address HPA_D2 and provide a P2P write response pWr_RSP(④) to the first storage device 821.

[0128] The first storage device 821 can provide a P2P write trigger response pwt_RSP(⑤) to the first host 811.

[0129] Figure 9 is a diagram showing a computing system 300 according to an exemplary embodiment.

[0130] Refer to Figure 9 , the second memory device 322 to the fifth memory device 325 can include a buffer area B. The size of the buffer area B can be smaller than the size of the device physical address of each of the second memory device 322 to the fifth memory device 325.

[0131] The second host 312 may allocate the addresses corresponding to the buffer area B of the fourth memory device 324 and the fifth memory device 325 to the GIM area of the second host physical address HPA2. The second host 312 may use the addresses corresponding to the buffer area B in the GIM area of the second host physical address HPA2 as the source address or the destination address.

[0132] The third host 313 may allocate the addresses corresponding to the buffer area B of the second memory device 322 and the third memory device 323 to the GIM area of the third host physical address HPA3. The third host 313 may use the addresses corresponding to the buffer area B in the GIM area of the third host physical address HPA3 as the source address or the destination address.

[0133] Since the address ranges allocated to the second host physical address HPA2 and the third host physical address HPA3 are reduced, the address management overheads of the second host 312 and the third host 313 may be reduced.

[0134] Figure 10 is a diagram showing a computing system 300 according to an exemplary embodiment.

[0135] Referring to Figure 10 , data may be received through the NIC 330, and the received data may be stored in the first memory device 321 (①). Specifically, the first host 311 may be assigned to the NIC 330, and the first host 311 may use the addresses in the G-FAM area to access the first memory device 321.

[0136] The data stored in the first memory device 321 may be sent to the second memory device 322 and the fourth memory device 324 through a P2P data transfer operation (②). Specifically, the first host 311 may provide a data replication signal to the second host 312 and the third host 313.

[0137] The second host 312 may receive the data replication signal and may provide a P2P read trigger request to the second memory device 322 so that the data is transferred from the first memory device 321 to the second memory device 322. The second host 312 may use the addresses in the local area of the second host physical address HPA2 as the destination address of the second memory device 322. The second host 312 may use the addresses in the G-FAM area of the second host physical address HPA2 as the source address.

[0138] The third host 313 can receive a data replication signal and provide a P2P read trigger request to the fourth memory device 324, so that data is transferred from the first memory device 321 to the fourth memory device 324. The third host 313 can use the address of a local area of the third host physical address HPA3 as the destination address of the fourth memory device 324. The third host 313 can use the address of the G-FAM area of the third host physical address HPA3 as the source address.

[0139] Figure 11 is a block diagram of a computing system 1000 according to an embodiment.

[0140] For ease of description, repeated detailed descriptions of the components given above are omitted. Referring to Figure 11 , the computing system 1000 may include a first CPU 1110, a second CPU 1120, a graphics processing unit (GPU) 1130, a neural processing unit (NPU) 1140, a CXL switch SW_CXL, multiple memory devices 1111, 1121, 1131, and 1141, multiple CXL memories 1200_1 to 1200_m, and multiple CXL memories 1300_1 to 1300_n.

[0141] The first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 may be directly connected to the multiple memory devices 1111, 1121, 1131, and 1141, respectively.

[0142] The first CPU 1110, the second CPU 1120, the GPU 1130, the NPU 1140, the multiple CXL memories 1200_1 to 1200_m, and the multiple CXL memories 1300_1 to 1300_n may be commonly connected to the CXL switch SW_CXL and may communicate with each other through the CXL switch SW_CXL.

[0143] In an embodiment, the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 may each be a host (e.g., host 11, 311, 312, 313, 314, 410, 811, or 812) as described with reference to Figures 1 to 10 description.

[0144] In an embodiment, the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 may each manage the multiple CXL memories 1200_1 to 1200_m as one memory cluster and the multiple CXL memories 1300_1 to 1300_n as one memory cluster.

[0145] In an embodiment, each of the plurality of CXL memories 1200_1 to 1200_m may be a storage device or a memory device (e.g., storage device or memory device 100, 321, 322, 323, 324, 325, 420, 430, 821, or 822) as referred to Figures 1 to 10 described.

[0146] According to an exemplary embodiment of the present disclosure, each of the CXL memories 1200_1 to 1200_m may receive a P2P data transfer trigger request from the first CPU 1110, the second CPU 1120, the GPU 1130, or the NPU 1140, and may perform the P2P data transfer operation as referred to above with reference to Figures 1 to 10 described in response to the P2P data transfer trigger request.

[0147] In an embodiment, the CXL switch SW_CXL may be connected to an external network or fabric and may be configured to communicate with an external server through the external network or fabric.

[0148] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A storage device connected to an external storage device through a switch, the storage device comprising: A non-volatile memory; And A storage controller, Wherein, the storage controller comprises: A cache memory configured to store some of the data stored in the non-volatile memory; An interface circuit configured to receive a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory from a first external host among a plurality of external hosts, provide a second request including the source address to the external storage device, and receive a response including first data corresponding to the source address from the external storage device in response to the second request; A buffer memory configured to temporarily store the first data received from the external storage device; An address conversion circuit configured to generate a first type of physical address based on the destination address; and A cache controller configured to update a cache area indicated by the first type of physical address based on the cache update information.

2. The storage device according to claim 1, wherein, The cache controller is further configured to update some of the first data to the cache area, update all of the first data to the cache area, or invalidate the cache area based on the cache update information.

3. The storage device according to claim 1, Among them, The address conversion circuit is further configured to convert the destination address to the first type of physical address when the destination address is a logical address indicating data in units of blocks, Wherein, the storage controller further comprises a flash translation layer configured to convert the destination address to a second type of physical address indicating a storage area of the non-volatile memory, and Wherein, the non-volatile memory is configured to store the first data stored in the buffer memory in the storage area indicated by the second type of physical address.

4. The storage device according to claim 1, Among them, The address conversion circuit is further configured to convert the destination address to the first type of physical address and convert the first type of physical address to a logical address indicating data in units of blocks when the destination address is a host physical address indicating data in units smaller than block units, Wherein, the storage controller further comprises a flash translation layer configured to convert the logical address to a second type of physical address indicating a storage area of the non-volatile memory, and Wherein, the non-volatile memory is configured to store the first data stored in the buffer memory in the storage area indicated by the second type of physical address.

5. The storage device according to claim 1, wherein, The storage controller further comprises a request scheduler configured to schedule requests received from the plurality of external hosts and third requests received from the external storage device.

6. The storage device according to claim 5, wherein, The request scheduler is further configured to: When the cache update information included in the third request indicates that the cache area is invalid, schedule a first quantity of the requests to be processed before the third request; When the cache update information included in the third request indicates that some of the data is updated to the cache area, schedule a second quantity of the requests to be processed before the third request, where the second quantity is less than the first quantity; and When the cache update information included in the third request indicates that all of the data is updated to the cache area, schedule a third quantity of the requests to be processed before the third request, where the third quantity is less than the second quantity.

7. The storage device according to claim 5, wherein, The request scheduler is further configured to perform a scheduling operation based on the cache update information included in the third request, internal operation information of the non-volatile memory, and cache contention information on the cache memory.

8. The storage device according to claim 1, wherein, The interface circuit is further configured to provide a response corresponding to the first request to the first external host when receiving a response to the second request from the external storage device.

9. An operating method of a storage device, the storage device including a non-volatile memory and a storage controller and connected to an external storage device through a switch, the operating method including: Receiving a first request from an external host, the first request including a source address indicating a storage area of the non-volatile memory, a destination address indicating a storage area of the external storage device, and cache update information indicating a cache update method of a cache memory; Generating a first type of physical address indicating a cache area of the cache memory based on the source address; Generating a second type of physical address indicating a storage area of the non-volatile memory based on the source address; Obtaining data based on the first type of physical address and the second type of physical address; Updating the cache area indicated by the first type of physical address based on the cache update information; Providing a second request including the destination address and the data to the external storage device; And Receiving a response corresponding to the second request from the external storage device.

10. The operating method according to claim 9, wherein, Updating the cache area indicated by the first type of physical address includes: performing one of updating some of the data to the cache area indicated by the first type of physical address, updating all of the data to the cache area indicated by the first type of physical address, and invalidating the cache area indicated by the first type of physical address.

11. The operating method according to claim 9, wherein, Obtaining the data based on the first type of physical address and the second type of physical address includes: Reading some of the data from the storage area of the cache memory indicated by the first type of physical address; and Reading the remaining data of the data from the storage area of the non-volatile memory indicated by the second type of physical address.

12. The operating method according to claim 9, wherein, When the source address is a host physical address indicating data in a unit smaller than a block unit, generating the first type of physical address includes converting the host physical address into the first type of physical address, and generating the second type of physical address includes: converting the first type of physical address into a logical address in units of blocks; and converting the logical address into the second type of physical address.

13. The operating method according to claim 9 further includes: Based on the cache update information, schedule requests received from a plurality of external hosts including the external host and a third request received from the external storage device.

14. The operating method according to claim 13, wherein, Scheduling the request and the third request includes: when the cache update information included in the third request indicates invalidating a cache area indicated by the first type of physical address, scheduling a first number of requests among the requests to be processed before the third request; when the cache update information included in the third request indicates updating some of the data to the cache area indicated by the first type of physical address, scheduling a second number of requests among the requests to be processed before the third request, where the second number is less than the first number; and when the cache update information included in the third request indicates updating all of the data to the cache area indicated by the first type of physical address, scheduling a third number of requests among the requests to be processed before the third request, where the third number is less than the second number.

15. An operation method of a storage device, the storage device including a non-volatile memory and a storage controller and connected to an external storage device through a switch, the operation method including: receiving a first request from an external host, the first request including a source address indicating one of a storage area of the external storage device and a storage area of the non-volatile memory, a destination address indicating the remaining one of the storage area of the external storage device and the storage area of the non-volatile memory, and cache update information indicating a method of updating a cache memory; providing a second request including one of the source address and the destination address to the external storage device; generating a first type of physical address indicating a cache area of the cache memory based on the remaining one of the source address and the destination address; updating the cache area indicated by the first type of physical address based on the cache update information; and receiving a response corresponding to the second request from the external storage device.

16. The operating method according to claim 15, wherein, Updating the cache area indicated by the first type of physical address includes: performing one of updating some of the data corresponding to the remaining one of the source address and the destination address to the cache area indicated by the first type of physical address, updating all of the data to the cache area indicated by the first type of physical address, and invalidating the cache area indicated by the first type of physical address.

17. The operating method according to claim 15 further includes: Schedule requests received from a plurality of external hosts including the external host and a third request received from the external storage device based on the cache update information.

18. The operating method according to claim 17, wherein, Scheduling the requests and the third request includes: When the cache update information included in the third request indicates invalidating a cache area indicated by the first type of physical address, scheduling a first quantity of the requests to be processed before the third request; When the cache update information included in the third request indicates updating some of the data corresponding to the remaining one of the source address and the destination address to the cache area indicated by the first type of physical address, scheduling a second quantity of the requests to be processed before the third request, where the second quantity is less than the first quantity; and When the cache update information included in the third request indicates updating all of the data to the cache area indicated by the first type of physical address, scheduling a third quantity of the requests to be processed before the third request, where the third quantity is less than the second quantity.

19. The operating method according to claim 15, Among them, Providing the second request includes providing the second request including the source address to the external storage device, and wherein receiving the response includes receiving the response including data corresponding to the source address, wherein the destination address indicates a storage area of the non-volatile memory, and wherein the operating method further includes storing the data in the storage area of the non-volatile memory indicated by the destination address.

20. The operating method according to claim 15, Among them, The source address indicates a storage area of the non-volatile memory, wherein the operating method further includes reading data from the storage area of the non-volatile memory indicated by the source address, and wherein providing the second request includes providing the second request including the data and the destination address to the external storage device.

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