A data sorting method and hardware accelerator

Abstract

The present application discloses a data sorting method and hardware accelerator, the method comprising: storing multiple target data into corresponding registers based on the arrangement order of registers; performing a first sorting operation on the target data in the registers, comprising: starting from a first register with a first sequence number, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value into the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value into the register that is ranked later or earlier among the two registers involved in the comparison; and performing a sub-operation of an intermediate sorting operation on the target data in the registers, wherein the sub-operation includes a second sorting operation and a third sorting operation. The data sorting method improves the sorting efficiency of the target data and reduces the time complexity of the sorting process.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a data sorting method and a hardware accelerator. Background Art

[0002] Currently, the demand for data sorting operations is increasing in fields such as high-performance computing, big data analysis, and artificial intelligence. To save data calculation and processing time, it is necessary to improve the performance of data sorting operations. Currently, the following data sorting methods are commonly used in the industry. For example, sorting algorithms applied to parallel computing mainly include bubble sort, direct sort, insertion sort, quick sort, and heap sort. Different types of sorting algorithms for parallel computing scenarios generally have the following drawbacks: The calculations of multiple computing units during parallel computing disrupt the regularity of the calculations, reducing the efficiency of parallel computing. Furthermore, the large amount of data accessed from associated memory (such as DRAM) during the calculation process reduces data sorting performance. Summary of the Invention

[0003] The present invention provides a data sorting method, including:

[0004] Based on the arrangement order of the registers, storing the plurality of target data into the corresponding registers respectively;

[0005] performing a first sorting operation on the target data in the registers, comprising: starting from a first register having a first sequence number, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison;

[0006] performing a sub-operation of an intermediate sorting operation on the target data in the register, wherein the sub-operation includes a second sorting operation and a third sorting operation, the second sorting operation including: starting from the second register having the second sequence number, sequentially comparing the target data in two adjacent registers, and comparing the first register with the register having the first-to-last sequence number, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; the third sorting operation including: starting from the second register, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison;

[0007] The first sorting operation and the second sorting operation are repeated alternately multiple times, or the first sorting operation and the third sorting operation are repeated alternately multiple times until all the target data are sorted from large to small or from small to large in numerical value.

[0008] Optionally, when the target data contains multiple data units and is not sorted, the method further includes:

[0009] Based on the arrangement order of the registers, the plurality of data units are stored in the corresponding registers respectively;

[0010] Taking the data units in the register as objects, performing the first sorting operation on them;

[0011] Taking the data unit in the register as an object, performing a sub-operation of the intermediate sorting operation on the data unit;

[0012] The first sorting operation and the second sorting operation are repeated alternately multiple times, or the first sorting operation and the third sorting operation are repeated alternately multiple times until all the data units are sorted from large to small or from small to large in terms of numerical value.

[0013] Optionally, when the target data contains multiple data units and has been sorted, the method further includes:

[0014] Based on the numerical values ​​of the data units, the data units are grouped to form a plurality of data unit groups;

[0015] Grouping the registers based on the arrangement order of the registers to form a plurality of register groups;

[0016] Based on the arrangement order of the register groups, the data unit groups are stored in the corresponding register groups respectively;

[0017] Taking the data unit group in the register group as an object, performing the first sorting operation on the data unit group;

[0018] Taking the data unit group in the register group as an object, performing a sub-operation of the intermediate sorting operation on the data unit group,

[0019] The first sorting operation and the second sorting operation are repeated alternately multiple times, or the first sorting operation and the third sorting operation are repeated alternately multiple times until all the data unit groups are sorted from large to small or from small to large in terms of numerical value.

[0020] Optionally, grouping the data units based on the numerical values ​​of the data units to form a plurality of data unit groups includes: dividing the data units into two data unit groups based on the numerical values ​​of the data unit groups;

[0021] Accordingly, grouping the registers to form a plurality of register groups includes: constructing one register group based on four registers.

[0022] Optionally, the method further includes:

[0023] sorting the target data based on a preset time interval;

[0024] The sorted target data is sent to the memory storage through the memory access controller.

[0025] The embodiment of the present application further provides a hardware accelerator connected to the memory storage, the hardware accelerator comprising:

[0026] Multiple sequentially arranged registers;

[0027] A scheduling unit connected to the registers, configured to store target data into the respective corresponding registers;

[0028] A plurality of basic sorting units are respectively connected to two corresponding adjacent registers, and the basic sorting units are configured to: perform a first sorting operation on the target data in the register under the control of the scheduling unit; perform a sub-operation of the intermediate sorting operation on the target data in the register, the sub-operation including a second sorting operation and a third sorting operation; alternately repeat the first sorting operation and the second sorting operation multiple times, or alternately repeat the first sorting operation and the third sorting operation multiple times until all the target data are sorted from large to small in value, or from small to large in value; wherein,

[0029] The first sorting operation includes: starting from the first register with the first sequence number, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; wherein,

[0030] The second sorting operation includes: starting from the second register with the second sequence number, sequentially comparing the target data in two adjacent registers, and comparing the first register with the register with the last sequence number, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison;

[0031] The third sorting operation includes: starting from the second register, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison.

[0032] Optionally, the hardware accelerator also includes:

[0033] a tightly coupled memory, configured to store the target data;

[0034] A register prefetch unit is connected to the scheduling unit, the register and the tightly coupled memory respectively. After receiving an instruction from the scheduling unit, the register prefetch unit obtains the target data from the tightly coupled memory and loads the target data into the corresponding registers according to the instruction.

[0035] Optionally, a first data multiplexer is provided between the register and the basic sorting unit, the first data multiplexer being connected to the scheduling unit and, under the control of the scheduling unit, selecting one of its input data as output data and sending it to the basic sorting unit;

[0036] A second data multiplexer is provided between the register prefetch unit and the register. The second data multiplexer is connected to the scheduling unit and, under the control of the scheduling unit, selects one of its input data as output data and sends it to the register.

[0037] Optionally, the hardware accelerator also includes:

[0038] A result write-back unit is connected to the basic sorting unit, the scheduling unit and the tightly coupled memory respectively. The result write-back unit stores the sorting result of the sorting operation performed on the target data under the control of the scheduling unit.

[0039] Optionally, the hardware accelerator also includes:

[0040] A memory access controller is respectively connected to the tightly coupled memory and the memory storage, and is used to obtain the target data from the memory storage according to a data call request of the tightly coupled memory, or to send a sorting result of a sorting operation on the target data to the memory storage.

[0041] The data sorting method of the embodiment of the present application achieves the sorting of target data simply and quickly by alternately using the first sorting operation and the intermediate sorting operation on the target data, thereby improving the sorting efficiency of the target data and reducing the time complexity of the sorting process. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a flow chart of a data sorting method according to an embodiment of the present application;

[0043] Figure 2 A flowchart of an embodiment of a data sorting method according to an embodiment of the present application;

[0044] Figure 3 A flowchart of another embodiment of the data sorting method according to an embodiment of the present application;

[0045] Figure 4 Schematic diagram of the first sorting operation and the second sorting operation according to an embodiment of the present application;

[0046] Figure 5 Schematic diagram of the first sorting operation and the third sorting operation according to an embodiment of the present application;

[0047] Figure 6 This is a schematic diagram of performing a first sorting operation and a second sorting operation on data units after grouping according to an embodiment of the present application;

[0048] Figure 7 This is a schematic diagram of performing a first sorting operation and a third sorting operation on data units after grouping according to an embodiment of the present application;

[0049] Figure 8 This is a schematic diagram of the structure of the hardware accelerator according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] Various aspects and features of the present application are described herein with reference to the accompanying drawings.

[0051] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0052] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0053] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0054] It should also be understood that although the present application has been described with reference to certain specific examples, those skilled in the art will readily be able to implement many other equivalent forms of the present application.

[0055] The above and other aspects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0056] Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments described are merely examples of the present application and may be implemented in a variety of ways. Familiar and / or repetitive functions and structures are not described in detail to avoid obscuring the present application with unnecessary or redundant details. Therefore, the specific structural and functional details described herein are not intended to be limiting, but rather serve merely as a basis and representative basis for the claims to teach those skilled in the art to variously utilize the present application with substantially any suitable detailed structure.

[0057] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may all refer to one or more of the same or different embodiments according to the present application.

[0058] A data sorting method according to an embodiment of the present application can be applied in scenarios such as high-performance computing, big data analysis, and artificial intelligence. In the process of processing target data in these scenarios, it is necessary to perform numerical sorting on the target data, so as to facilitate sequential reading and use of the target data. Specifically, the data sorting method can be applied to an electronic device, where multiple target data as processing targets are stored in multiple registers of the electronic device, and then multiple sorting operations are performed on the target data in the registers to gradually achieve the sorting of the target data. The data sorting method can be a sorting method based on the numerical value of the target data from large to small, or a sorting method based on the numerical value of the target data from small to large.

[0059] The data sorting method of the embodiment of the present application is described in detail below with reference to specific embodiments. Figure 1 This is a flow chart of the data sorting method according to an embodiment of the present application. Figure 1 As shown, the method includes the following steps:

[0060] S100 , based on the arrangement order of the registers, storing a plurality of target data into the corresponding registers respectively.

[0061] For example, target data is an object to be processed and needs to be sorted according to numerical values. A register of an electronic device is used to store the target data and has an arrangement order so that corresponding target data can be stored in the arrangement order. During the process of processing the target data, the register arrangement order may not be adjusted; instead, only the storage location of the target data may be adjusted.

[0062] In one embodiment, one register can store one target data. After all target data are stored in the register, the target data form an arrangement order because the register has an arrangement order.

[0063] S200, performing a first sorting operation on the target data in the registers, including: starting from the first register with a first serial number, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value into the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value into the register that is ranked later or earlier among the two registers involved in the comparison.

[0064] For example, combined Figure 4 and Figure 5, registers can be numbered according to their arrangement order. For example, the target data are 0, 1, 2, 3, 4, 5, 6, and 7. The first register x(0) in the first position has the first serial number, the second register x(1) in the second position has the second serial number, the third register x(2) in the third position has the third serial number, and so on. The eighth register x(7) in the last position has the last serial number. Among them, the first register x(0) stores 0, the second register x(1) stores 1, the third register x(2) stores 2, the fourth register x(3) stores 3, the fifth register x(4) stores 4, the sixth register x(5) stores 5, the seventh register x(6) stores 6, and the eighth register x(7) stores 7.

[0065] Starting from the first register x(0) with the first serial number, a first sorting operation is performed on each target data in the register, including comparing the target data 0 in the first register x(0) with the target data 1 in the second register x(1), storing the target data 1 with a larger value in the first register x(0) of the two registers involved in the comparison, and storing the target data 0 with a smaller value in the second register x(1) of the two registers involved in the comparison. Similarly, the target data 2 in the third register x(2) is compared with the target data 3 in the fourth register x(3), storing the target data 3 with a larger value in the third register x(2) of the two registers involved in the comparison, and storing the target data 2 with a smaller value in the fourth register x(3) of the two registers involved in the comparison. All target data are arranged using the above-mentioned similar sorting operations.

[0066] After the first sorting operation, the target data is arranged in the order of 1, 0, 3, 2, 5, 4, 7, and 6. They are stored in the first register x(0), the second register x(1), the third register x(2), the fourth register x(3), the fifth register x(4), the sixth register x(5), the seventh register x(6), and the eighth register x(7), respectively.

[0067] S300, performing a sub-operation of an intermediate sorting operation on the target data in the register, wherein the sub-operation includes a second sorting operation and a third sorting operation, the second sorting operation including: starting from the second register with the second serial number, sequentially comparing the target data in the two adjacent registers, and comparing the first register with the register with the first-to-last serial number, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; the third sorting operation including: starting from the second register, sequentially comparing the target data in the two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison.

[0068] Exemplarily, an intermediate sort operation is another intermediate sort operation performed after the first sort operation is performed on the target data. The intermediate sort operation includes multiple sub-operations, including a second sort operation and a third sort operation. In this embodiment, after the first sort operation is performed on the target data, it is necessary to perform a sub-operation of the intermediate sort operation on the target data. For example, after the first sort operation is performed on the target data, the second sort operation can be performed on the target data, or after the first sort operation is performed on the target data, the third sort operation can be performed on the target data (without performing the second sort operation). Thus, the target data is sorted again.

[0069] In one embodiment, the second sorting operation is described in conjunction with the above embodiment. Figure 4 As shown, after the first sorting operation is performed on the target data, the second sorting operation is performed on the target data. The second sorting operation includes comparing the target data in two adjacent registers in sequence, starting from the second register x(1) with the second sequence number. First, the target data 0 in the second register x(1) is compared with the target data 3 in the third register x(2). The target data 3 with a larger value is stored in the second register x(1) with a higher order, and the target data 0 with a smaller value is stored in the third register x(2) with a lower order. Similarly, similar operations are performed on the fourth to seventh registers.

[0070] In addition, the second sorting operation also includes comparing the target data 1 in the first register x(0) with the target data 6 in the eighth register x(7) having the first-to-last sequence number, storing the target data 6 with a larger value in the first register x(0) with a higher sorting position, and storing the target data 1 with a smaller value in the eighth register x(7) with a lower sorting position.

[0071] In another embodiment, the third sorting operation is described in conjunction with the above embodiment. Figure 5 As shown, after the first sorting operation is performed on the target data, the second sorting operation is not performed on the target data, but a third sorting operation is performed on the target data. The third sorting operation includes comparing the target data in two adjacent registers in sequence, starting from the second register x(1) with the second sequence number. First, the target data 0 in the second register x(1) is compared with the target data 3 in the third register x(2). The target data 3 with a larger value is stored in the second register x(1) with a higher order, and the target data 0 with a smaller value is stored in the third register x(2) with a lower order. Similarly, similar operations are performed on the fourth to seventh registers.

[0072] Furthermore, the target data 1 in the first register x(0) is not adjusted in the third sort operation. Thus, the target data 1 remains stored in the first register x(0). The target data 6 in the eighth register x(7) is not adjusted in the third sort operation. Thus, the target data 6 remains stored in the eighth register x(7).

[0073] In the above embodiment, when comparing target data, target data with larger values ​​are stored in registers with higher sorting, and target data with smaller values ​​are stored in registers with lower sorting. Of course, when comparing target data, depending on the specific sorting target, target data with larger values ​​may be stored in registers with lower sorting, and target data with smaller values ​​may be stored in registers with higher sorting.

[0074] S400, alternately repeating the first sorting operation and the second sorting operation multiple times, or alternately repeating the first sorting operation and the third sorting operation multiple times, until all the target data are sorted from large to small in value, or from small to large in value.

[0075] For example, Figure 4As shown, after performing one of the sub-operations of the intermediate sorting operation on the target data in the register, the first sorting operation and the second sorting operation (a sub-operation of the intermediate sorting operation) need to be repeated alternately multiple times until all the target data are sorted from largest to smallest, or vice versa. For example, a total of seven sorting operations (including multiple first sorting operations and multiple second sorting operations) are required to achieve the desired arrangement of the target data, such as the order after arrangement being 7, 6, 5, 4, 3, 2, 1, 0.

[0076] Or, as Figure 5 As shown, after performing one of the sub-operations of the intermediate sorting operation on the target data in the register, the first sorting operation and the third sorting operation (a sub-operation of the intermediate sorting operation) need to be repeated alternately multiple times until all the target data are sorted from largest to smallest, or vice versa. For example, a total of eight sorting operations (including multiple first sorting operations and multiple third sorting operations) are required to achieve the desired arrangement of the target data, such as the order after arrangement being 7, 6, 5, 4, 3, 2, 1, 0.

[0077] In this embodiment, the sorted target data can be stored in the memory storage of the electronic device to facilitate its retrieval.

[0078] The data sorting method of the embodiment of the present application achieves the sorting of target data simply and quickly by alternately using the first sorting operation and the intermediate sorting operation on the target data, thereby improving the sorting efficiency of the target data and reducing the time complexity of the sorting process.

[0079] In one embodiment of the present application, when the target data contains multiple data units and is not sorted, as shown in FIG. Figure 2 As shown, the method further includes the following steps:

[0080] S10, based on the arrangement order of the registers, storing the plurality of data units into the corresponding registers respectively.

[0081] For example, the target data may be a single data unit or may have multiple data units. The values ​​of the multiple data units may be different, which requires sorting the multiple data units, including sorting from largest to smallest value, or from smallest to largest value. After sorting the data units, the multiple target data are sorted. The specific sorting method can be based on the above content.

[0082] S20: Take the data units in the register as objects and perform the first sorting operation on them.

[0083] Exemplarily, a register can be used not only to store target data for sorting the target data, but also to store data units for sorting the data units. Similar to sorting the target data, a first sorting operation is performed on the data units in the register. The first sorting operation includes: starting from a first register having a first sequence number, sequentially comparing the data units in two adjacent registers, storing the data unit with the larger value in the register with the higher or lower order of the two registers involved in the comparison, and storing the data unit with the smaller value in the register with the lower or higher order of the two registers involved in the comparison.

[0084] S30, taking the data units in the register as objects, and performing the intermediate sorting operation on them.

[0085] Exemplarily, the sub-operation includes a second sorting operation and a third sorting operation, the second sorting operation includes: starting from the second register with the second serial number, comparing the data units in the two adjacent registers in sequence, and comparing the first register with the register with the first-to-last serial number, storing the data unit with the larger value to the register with the earlier or later ranking among the two registers involved in the comparison, and storing the data unit with the smaller value to the register with the later or earlier ranking among the two registers involved in the comparison; the third sorting operation includes: starting from the second register, comparing the data units in the two adjacent registers in sequence, storing the data unit with the larger value to the register with the earlier or later ranking among the two registers involved in the comparison, and storing the data unit with the smaller value to the register with the later or earlier ranking among the two registers involved in the comparison.

[0086] S40, repeating the first sorting operation and the second sorting operation alternately multiple times, or repeating the first sorting operation and the third sorting operation alternately multiple times, until all the data units are sorted from large to small in value, or from small to large in value.

[0087] For example, Figure 4 As shown, after performing a sub-operation of the intermediate sorting operation on the data units in the register, the first sorting operation and the second sorting operation need to be repeated alternately multiple times until all the data units are sorted from large to small or from small to large in value.

[0088] Or, as Figure 5 As shown, after performing a sub-operation of the intermediate sorting operation on the data units in the register, the first sorting operation and the third sorting operation need to be repeated alternately multiple times until all the data units are sorted from large to small or from small to large in terms of value.

[0089] In one embodiment of the present application, when the target data has multiple data units and has been sorted, as shown in FIG. Figure 3 Shown and combined Figure 6 and Figure 7 , the method further comprises:

[0090] S51: Group the data units based on the numerical values ​​of the data units to form a plurality of data unit groups.

[0091] For example, after multiple data units are sorted, all data units can be treated as a target data and sorted, as described in the sorting method above. Alternatively, multiple data units can be grouped to form multiple data unit groups, each of which can be treated as a processing object and sorted.

[0092] For example, multiple data units are sorted as "7, 6, 5, 4, 3, 2, 1, 0". Based on the numerical values ​​of the data units "7, 6, 5, 4, 3, 2, 1, 0", the data units "7, 6, 5, 4, 3, 2, 1, 0" are divided into two groups, forming a first data unit group "7, 6, 5, 4" and a second data unit group "3, 2, 1, 0".

[0093] S52: Group the registers based on the arrangement order of the registers to form a plurality of register groups.

[0094] For example, registers may be grouped based on the number of data unit groups and the number of data units therein, and based on the order in which the registers are arranged. For example, registers may be divided into eight register groups, namely DG0, DG1, DG2, DG3, DG4, DG5, DG6, and DG7, with each register group storing data of one data unit group. Specifically, in combination with the above embodiment, four data units can be stored.

[0095] Preferably, grouping the data units based on the numerical values ​​of the data units to form multiple data unit groups includes: dividing the data units into two data unit groups based on the numerical values ​​of the data unit groups; such as the first data unit group "7, 6, 5, 4" and the second data unit group "3, 2, 1, 0" formed above. Accordingly, grouping the registers to form multiple register groups includes: constructing one register group based on four registers. For example, each register group among DG0, DG1, DG2, DG3, DG4, DG5, DG6, and DG7 includes four registers.

[0096] S53: Based on the arrangement order of the register groups, the data unit groups are stored in the corresponding register groups respectively.

[0097] Illustratively, the register groups have an arrangement order, such as the first register group DG0, the second register group DG1, the third register group DG2, the fourth register group DG3, the fifth register group DG4, the sixth register group DG5, the seventh register group DG6, and the eighth register group DG7. When storing the data unit groups in the register groups, the storage operation can be performed according to the arrangement order of the register groups and the arrangement order of the data unit groups. For example, the first data unit group is stored in the first register group DG0, the second data unit group is stored in the second register group DG1, ..., and the eighth data unit group is stored in the eighth register group DG7.

[0098] S54: Take the data unit group in the register group as an object and perform the first sorting operation on it.

[0099] Illustratively, similar to the process of processing the target data in the register described in the above embodiment, the data unit groups in the register group are taken as objects and a first sorting operation is performed on them, including: starting from the first register group with a first sequence number, the data unit groups in two adjacent register groups are compared in sequence, the data unit group with a larger value is stored in the register group with a higher or lower ranking among the two register groups involved in the comparison, and the data unit group with a smaller value is stored in the register group with a higher or lower ranking among the two register groups involved in the comparison.

[0100] S55 , taking the data unit group in the register group as an object, and performing a sub-operation of the intermediate sorting operation on it.

[0101] Illustratively, similar to the process of processing the target data in the register in the above embodiment, after the first sorting operation is performed on the data unit group in the register group, the data unit group is taken as an object and a sub-operation of the intermediate sorting operation is performed on it, and the sub-operation includes a second sorting operation and a third sorting operation.

[0102] S56, alternately repeating the first sorting operation and the second sorting operation multiple times, or alternately repeating the first sorting operation and the third sorting operation multiple times, until all the data unit groups are sorted from large to small in value, or from small to large in value.

[0103] For example, Figure 6As shown, after performing a sub-operation of the intermediate sorting operation on the data unit groups in the register group, the first sorting operation and the second sorting operation (a sub-operation of the intermediate sorting operation) need to be repeated alternately multiple times until all data unit groups are sorted from largest to smallest value, or vice versa. The value of the data unit group can be a comprehensive value, such as the accumulated value of all data unit groups, or a value obtained through other calculations.

[0104] Or, as Figure 7 As shown, after performing a sub-operation of the intermediate sorting operation on the data unit groups in the register group, it is necessary to alternately repeat the first sorting operation and the third sorting operation (a sub-operation of the intermediate sorting operation) multiple times until all the data unit groups are sorted from large to small in value, or from small to large in value.

[0105] The following combination Figures 4 to 7 , a specific embodiment of the data sorting method of this application is described.

[0106] When performing the first and second sort operations on the target data: the X() sequence is the sorted input array.

[0107] The sorting unit consists of multiple subunits. Each subunit receives two data inputs, X(i) and X(j). After comparison, the maximum value of X(i) and X(j) is assigned to X(i), and the minimum value is assigned to X(j). If the two data are equal, the values ​​of X(i) and X(j) remain unchanged. If the values ​​are swapped, a value swap signal is output.

[0108] Take the sequence length of 8 as an example. The flow of signals is divided into two states:

[0109] In the first sorting operation (state A), adjacent data are sorted in pairs from the first data to the last data.

[0110] In the second sorting operation (state B), adjacent data are sorted in pairs from the second data to the second to last data. At the same time, the first and last data are sorted in pairs.

[0111] Repeating A and B states, the sorting is completed after 7 rounds. If there is no order change between each pair of sorted units in two consecutive rounds, the sorting can be terminated early.

[0112] The time complexity of the algorithm is Ot=Nx(N-1) / 2, which means that a sequence of length N requires at most Ot comparisons to complete the sorting. The space complexity is Os=N, which means that N data must be stored during the sorting process of a sequence of length N.

[0113] In another embodiment, when the first sorting operation and the third sorting operation are performed on the target data:

[0114] In the third sorting operation (state B), the sorting of the first and last data is discarded, but the number of sorting rounds needs to be increased from 7 to 8. At the same time, the early exit condition needs to be changed to state B (the third sorting operation) and no data exchange occurs in state A (the first sorting operation) before state B.

[0115] The space complexity of the variant algorithm is the same as the basic form, but the time complexity is increased to Ot=NxN / 2.

[0116] In yet another embodiment, when the target data contains multiple data units and the data units are not sorted, the data units are grouped and sorted:

[0117] This group sorting meets the needs of sorting very long sequences.

[0118] First, the entire sequence needs to be divided into multiple data unit groups. If the sequence length cannot be divided by the number of groups, the last group can be padded with the minimum or maximum value to make each group equal in length.

[0119] Taking the example of dividing the sequence into 8 equal parts, after the grouping is completed, the sequence is divided into 8 groups corresponding to 8 register groups (DG0~DG7), and each group contains 4 data units.

[0120] After the grouping is completed, the two groups are first merged and sorted. For example, the 8 data units contained in DG0 and DG1 can use the above data sorting method.

[0121] The operations between each data unit group can also be divided into two states A and B.

[0122] The first sorting operation (state A) merges and sorts adjacent groups from the first group to the last group.

[0123] In the second sorting operation (state B), adjacent groups are merged and sorted from the second group to the second to last group. At the same time, the first and last groups are merged and sorted, with larger numbers written back to the first group and smaller numbers written back to the last group.

[0124] Repeating A and B states, the sorting is completed after 7 rounds. If there is no order change between each pair of sorted units in two consecutive rounds, the sorting can be terminated early.

[0125] The third sorting operation can also be used to sort the data unit groups. In the third sorting operation (state B), the first and last data unit groups are not sorted, and an additional sorting operation is required.

[0126] The grouping and sorting method of the data unit group can also be further evolved into a hierarchical grouping structure.

[0127] First, the entire sequence can be divided into multiple equal-length first-level groups. Each group can be further divided into multiple equal-length second-level groups. The second-level groups can be further subdivided into a hierarchy that matches the hardware storage structure. Taking the digital signal processing vector machine (DSP) structure as an example, its typical storage structure is: 16 x 32-bit operation core registers, 128KB core tightly coupled cache, and 1GB external DRAM storage. Based on this structure, for example, when using the DSP to sort 1024x1024 (1M) data, the following can be used:

[0128] The 1024x1024 sequence is first divided into 64 first-level groups of 16x1024 data. Each first-level group requires 16x1024x32 bits = 64KB of storage space (assuming each data item occupies 32 bits of storage space). Therefore, during the calculation process, two 64KB first-level groups can be stored in the core's 128KB tightly coupled cache before the calculation is performed.

[0129] Each primary group can be further divided into 2048 secondary groups of 8 data. Each secondary group requires 8 x 32 bits = 256 bits of storage space. Every two 256-bit secondary groups can be stored in 16 x 32-bit core registers.

[0130] This division allows sorting of the second-level groups to only access core registers, while sorting the first-level groups requires only access to the on-chip tightly coupled cache. This significantly reduces the bandwidth requirements for different types of memory access throughout the computation.

[0131] After the grouping is completed, the lowest level group is first sorted using the basic wave sorting algorithm. Then the above data sorting algorithm is used to sort the groups above the lowest level until the highest level group.

[0132] In one embodiment of the present application, the method further includes: sorting the target data based on a preset time interval; and sending the sorted target data to a memory storage via a memory access controller.

[0133] For example, the target data may change in value during use, resulting in the sorted target data not being sorted from largest to smallest or vice versa. In this embodiment, the target data can be sorted multiple times based on preset time intervals, thereby dynamically adjusting the sorting results of the target data and, to a certain extent, ensuring that the sorting results of the target data meet the usage requirements. Furthermore, after sorting, the target data can be sent to a memory storage device (e.g., DRAM memory) via a memory access controller of the electronic device, which can then store and access the target data.

[0134] The embodiment of the present application also provides a hardware accelerator, which is used to perform sorting operations on target data. Figure 8 As shown, the hardware accelerator is connected to the memory storage.

[0135] The hardware accelerator includes:

[0136] Multiple sequentially arranged registers;

[0137] A scheduling unit connected to the registers, configured to store target data into the respective corresponding registers;

[0138] Multiple basic sorting units are respectively connected to the corresponding two adjacent registers, and the basic sorting units are configured to: perform a first sorting operation on the target data in the register under the control of the scheduling unit; perform a sub-operation of the intermediate sorting operation on the target data in the register, and the sub-operation includes a second sorting operation and a third sorting operation; alternately repeat the first sorting operation and the second sorting operation multiple times, or alternately repeat the first sorting operation and the third sorting operation multiple times until all the target data are sorted from large to small according to the numerical value, or from small to large according to the numerical value.

[0139] For example, target data is an object to be processed and needs to be sorted according to numerical values. A register of an electronic device is used to store the target data and has an arrangement order so that corresponding target data can be stored in the arrangement order. During the process of processing the target data, the register arrangement order may not be adjusted; instead, only the storage location of the target data may be adjusted.

[0140] In one embodiment, one register can store one target data. After all target data are stored in the register, the target data form an arrangement order because the register has an arrangement order.

[0141] The hardware accelerator further includes a scheduling unit connected to a plurality of registers and configured to store target data acquired from a memory storage of the electronic device into the corresponding registers.

[0142] Each basic sorting unit is connected to two corresponding adjacent registers and to the scheduling unit. For example, basic sorting unit 0 is connected to register 0 and register 1, basic sorting unit 1 is connected to register 2 and register 3, basic sorting unit 2 is connected to register 4 and register 5, ..., basic sorting unit N-2 is connected to register 2N-4 and register 2N-3, and basic sorting unit N-1 is connected to register 2N-2 and register 2N-1. At the same time, it is connected to the scheduling unit. Under the control of the scheduling unit, each basic sorting unit performs a first sorting operation on the target data in the corresponding register. For example, basic sorting unit 0 performs a sorting operation on the target data in register 0 and the target data in register 1, basic sorting unit 1 performs a sorting operation on the target data in register 2 and the target data in register 3, and so on.

[0143] The basic sorting unit can use a selector to compare the target data in two adjacent registers. The first sorting operation will be described in conjunction with the above embodiment.

[0144] Starting with register 0, basic sorting unit 0 compares the target data in two adjacent registers, 0 and 1, and stores the target data with the larger value in register 0, and the target data with the smaller value in register 1. Basic sorting unit 1 compares the target data in two adjacent registers, 2 and 3, and stores the target data with the larger value in register 2, and the target data with the smaller value in register 3. ..., basic sorting unit N-1 compares the target data in two adjacent registers, 2N-2 and 2N-1, and stores the target data with the larger value in register 2N-2, and the target data with the smaller value in register 2N-1.

[0145] Under the control of the scheduling unit, each basic sorting unit performs a first sorting operation on the target data in the corresponding register; then performs a sub-operation of the intermediate sorting operation on the target data in the corresponding register. The intermediate sorting operation is a sorting operation of another intermediate step after the first sorting operation is performed on the target data. The intermediate sorting operation includes multiple sub-operations, which include a second sorting operation and a third sorting operation. In this embodiment, each basic sorting unit needs to perform a sub-operation of the intermediate sorting operation on the target data after performing the first sorting operation on the target data. For example, the basic sorting unit can perform a second sorting operation on the target data after performing the first sorting operation on the target data, or can perform a third sorting operation on the target data after performing the first sorting operation on the target data (without performing the second sorting operation). Thus, the target data is sorted again.

[0146] For the second sorting operation, the second sorting operation is explained in combination with the above embodiment. The basic sorting unit performs the second sorting operation including: starting from register 1, the basic sorting unit 1 compares the target data in the two adjacent registers 1 and register 2, stores the target data with a larger value in register 1, and stores the target data with a smaller value in register 2; the basic sorting unit 2 compares the target data in the two adjacent registers 3 and register 4, stores the target data with a larger value in register 3, and stores the target data with a smaller value in register 4, ..., the basic sorting unit N-1 compares the target data in the two adjacent registers 2N-3 and register 2N-2, stores the target data with a larger value in register 2N-3, and stores the target data with a smaller value in register 2N-2.

[0147] The second sorting operation performed by the basic sorting unit further includes: the basic sorting unit 0 compares the target data in the two adjacent registers 0 and 2N-1, stores the target data with a larger value in register 0, and stores the target data with a smaller value in register 2N-1.

[0148] For the third sorting operation, the third sorting operation is explained in combination with the above embodiment. The basic sorting unit performs the third sorting operation including: starting from register 1, the basic sorting unit 1 compares the target data in the two adjacent registers 1 and register 2, stores the target data with a larger value in register 1, and stores the target data with a smaller value in register 2; the basic sorting unit 2 compares the target data in the two adjacent registers 3 and register 4, stores the target data with a larger value in register 3, and stores the target data with a smaller value in register 4, ..., the basic sorting unit N-1 compares the target data in the two adjacent registers 2N-3 and register 2N-2, stores the target data with a larger value in register 2N-3, and stores the target data with a smaller value in register 2N-2.

[0149] In the third sorting operation, basic sorting unit 0 does not adjust the target data in register 0, but maintains the target data in register 0. Basic sorting unit N-1 does not adjust the target data in register 2N-1, but maintains the target data in register 2N-1.

[0150] In one embodiment of the present application, the hardware accelerator further includes:

[0151] a tightly coupled memory, configured to store the target data;

[0152] A register prefetch unit is connected to the scheduling unit, the register and the tightly coupled memory respectively. After receiving an instruction from the scheduling unit, the register prefetch unit obtains the target data from the tightly coupled memory and loads the target data into the corresponding registers according to the instruction.

[0153] Exemplarily, a tightly coupled memory is connected to a scheduling unit and a memory access controller, respectively. The tightly coupled memory obtains target data from the memory storage through the memory access controller and stores the target data. A register prefetch unit is connected to the scheduling unit, the register, and the tightly coupled memory, respectively. When performing a sorting operation on the target data, the scheduling unit sends relevant instructions to the register prefetch unit. After receiving the instructions from the scheduling unit, the register prefetch unit obtains the target data from the tightly coupled memory and loads the target data into its corresponding register according to the instructions. For example, the register prefetch unit obtains target data "0, 1, 2, 3, 4, 5, 6, ..., 2N-2, 2N-1". Target data 0 is loaded into register 0, target data 1 is loaded into register 1, target data 2 is loaded into register 2, ..., target data 2N-2 is loaded into register 2N-2, and target data 2N-1 is loaded into register 2N-1.

[0154] In one embodiment of the present application, a first data multiplexer is provided between the register and the basic sorting unit. The first data multiplexer is connected to the scheduling unit and, under the control of the scheduling unit, selects one of its input data as output data and sends it to the basic sorting unit.

[0155] A second data multiplexer is provided between the register prefetch unit and the register. The second data multiplexer is connected to the scheduling unit and, under the control of the scheduling unit, selects one of its input data as output data and sends it to the register.

[0156] For example, under the control of the scheduling unit, the first data multiplexer can selectively select one of the two input data for output. For example, the first data multiplexer outputs the input data to the corresponding basic sorting unit, and the basic sorting unit may correspond to one or two first data multiplexers, and the basic sorting unit then compares the received target data.

[0157] For example, the first data multiplexer in the first position sends a target data in register 1 and register 2 to the basic sorting unit 1, and the first data multiplexer in the second position sends a target data in register 2 and register 3 to the basic sorting unit 1. The basic sorting unit 1 compares the two target data obtained and outputs the target data with a larger value.

[0158] A second data multiplexer is provided between the register prefetch unit and the register. The second data multiplexer is connected to the scheduling unit and the output end of the basic sorting unit. Under the control of the scheduling unit, the second data multiplexer alternatively determines one of its input data as the output data and sends it to the register for storage.

[0159] In an embodiment of the present application, the hardware accelerator further includes a result write-back unit. The result write-back unit is respectively connected to the basic sorting unit, the scheduling unit, and the tightly coupled memory. Under the control of the scheduling unit, the result write-back unit stores the sorting result of the sorting operation for the target data, and sends the sorting result to the memory through the tightly coupled memory and the memory access controller.

[0160] Next Figures 4 to 8 , a specific embodiment of the hardware accelerator in the embodiment of the present application will be described in detail.

[0161] The register is used to temporarily store the sorted input packet data (data unit or data unit group) and the sorted intermediate result data.

[0162] The second data multiplexer at the front end of the register selects the stored data according to the register load enable signal output by the scheduling unit.

[0163] When the load enable signal is high, the input data of the register prefetch unit is loaded into the register.

[0164] When the load enable signal is low, the result data of the basic sorting unit is loaded into the register for the next sorting use.

[0165] The basic sorting unit is used to compare the input data (such as target data or data unit):

[0166] When in_a >= in_b, output max is selected as in_a, and at the same time output min is selected as in_b, and the "not swapped" output signal is kept as 1.

[0167] When in_a < in_b, output max is selected as in_b, and at the same time output min is selected as in_a, and the "not swapped" output signal is changed to 0.

[0168] The first data multiplexer at the front stage of the basic sorting unit selects the input data according to the first sorting operation (type A) or intermediate sorting operation (type B) selection signal output by the scheduling unit (subsequently, the first sorting operation can be represented by type A, and the intermediate sorting operation can be represented by type B).

[0169] During the first sorting operation (Type A), the corresponding register output is selected as the input to the basic sorting unit. For basic sorting unit N-2, for Type A, registers 2N-4 and 2N-3, numbered 2x(N-2) and 2x(N-2)+1, are selected as inputs.

[0170] When sorting is in the middle of a sort operation (Type B), the outputs of the corresponding adjacent registers are selected as the inputs of the basic sort unit. Taking basic sort unit N-2 as an example, in Type B, registers 2N-5 and 2N-4, numbered 2x(N-2)-1 and 2x(N-2), are selected as inputs. The first basic sort unit is slightly different:

[0171] The in_a and max data paths of the first basic sorting unit remain unchanged; the in_b input is selected as the output of the last register, and the min output is selected as the max output of the next basic sorting unit.

[0172] The third data multiplexer at the subsequent stage of the basic sorting unit selects the output data according to the first sorting operation (type A) or the intermediate sorting operation (type B) selection signal output by the scheduling unit.

[0173] When sorting is of type A, the order of the output results remains unchanged.

[0174] When the sorting is in type B, the max output of the basic sorting unit is replaced by the min output of the basic sorting unit; at the same time, the min output is replaced by the max output of the adjacent basic sorting unit. Taking basic sorting unit N-2 as an example, in type B, the max output of basic sorting unit N-2 is replaced by the min output, and the max output of basic sorting unit N-1 is used to replace the min output of basic sorting unit N-2. The first and last basic sorting units are slightly different:

[0175] The max output of the first basic sorting unit remains unchanged in the B-type sorting operation.

[0176] The min value of the last basic sort unit is replaced with the min value of the first basic sort unit in the B type sort operation.

[0177] The register prefetch unit receives a preload enable signal from the scheduling unit to preload the sorted data.

[0178] After receiving the preload enable signal, the register prefetch unit requests data from the tightly coupled cache according to the preset secondary packet data length (LEN2), the primary packet data length (LEN1) and the base address (BA2) of the data located in the tightly coupled memory.

[0179] The register prefetch unit prefetches data from the tightly coupled cache according to the dispatch unit "LD2_AB type selection" instruction:

[0180] During a Type A secondary sort cycle, starting from base address BA2, each time a load request is received, two secondary groups (i.e., LEN2x2) of data are sequentially requested from the tightly coupled cache, and the corresponding data is placed at the register input port for use by the register. After each request, the request data address is incremented by LEN2x2. When the requested data size reaches LEN1, the request address is restored to the initial BA2.

[0181] During a Type B secondary sort cycle, starting from base address BA2+LEN2, each time a load request is received, two secondary groups (i.e., LEN2x2 data) are sequentially requested from the tightly coupled cache. The corresponding data is then placed at the register input port for use. After each request, the requested data address is incremented by LEN2x2. When the requested data size reaches LEN1-LEN2x2, the request address is restored to the initial BA2. To simplify hardware complexity, the secondary group sorting uses a variant of the group fluctuation sorting algorithm.

[0182] The result write-back unit receives the result write-back enable signal to save the result output by the basic comparison unit and write it back to the tightly coupled cache.

[0183] After receiving the result write-back enable signal, the result write-back unit first saves the calculation result, and then writes the data back to the tightly coupled cache according to the pre-set secondary packet data length (LEN2), primary packet data length (LEN1) and the base address (BA2) of the data located in the tightly coupled memory.

[0184] The result write-back unit writes the result data back to the tightly coupled cache according to the "ST2_AB type selection" instruction of the scheduling unit:

[0185] During a Type A secondary sort cycle, starting from base address BA2, upon receiving a write-back request, the result data is first saved and then two secondary groups, or LEN2x2 data, are sequentially written back to the tightly coupled cache. After each write-back, the write-back data address is incremented by LEN2x2. When the amount of data written back reaches LEN1, the write-back address is restored to the initial BA2.

[0186] During a Type B secondary sort cycle, starting from the base address BA2+LEN2x2, upon receiving a write-back request, the result data is first saved and then two secondary groups, or LEN2x2 data, are sequentially written back to the tightly coupled cache. After each write-back, the write-back data address is incremented by LEN2x2. When the amount of data written back reaches LEN1-LEN1x2, the write-back address is restored to the initial BA2.

[0187] The tightly coupled cache is used to store the first-level packet data.

[0188] After receiving the memory load enable signal, the tightly coupled cache requests data from the DRAM based on the pre-set first-level packet data length (LEN1), the overall data length (LEN), and the base address (BA1) of the data located in the DRAM memory.

[0189] The tightly coupled cache reads data from the DRAM memory through the memory access controller according to the scheduling unit "LD1_AB type selection":

[0190] During a Type A sort cycle, starting from base address BA1, after receiving a load request, two L1x2 packets of data are sequentially requested from the DRAM memory, and the corresponding data is placed in the tightly coupled cache. After each request, the requested data address is incremented by LEN1x2. When the requested data size reaches LEN, the request address is restored to the initial BA1.

[0191] During a Type B sort cycle, starting from base address BA1+LEN1, upon receiving a load request, two first-level groups (i.e., LEN1x2) of data are sequentially requested from the DRAM memory, and the corresponding data is placed in the tightly coupled cache. After each request, the requested data address is incremented by LEN1x2. When the requested data size reaches LEN-LEN1x2, the request address is restored to the initial BA1. To simplify hardware complexity, a variant of the group-wave sorting algorithm is used for first-level group sorting.

[0192] After receiving the memory write-back enable signal, the tightly coupled cache writes data back to the DRAM according to the scheduling unit "ST1_AB type selection" instruction based on the pre-set first-level packet data length (LEN1), the overall data length (LEN), and the base address (BA1) of the data located in the DRAM memory.

[0193] During the A-type sorting cycle, starting from the base address BA1, after receiving a write-back request, two first-level packets (i.e., LEN1x2) of data are sequentially written back to the DRAM memory. After each write-back is completed, the write-back data address is incremented by LEN1x2. When the amount of data written back reaches LEN, the request address is restored to the initial BA1.

[0194] During a Type B sorting cycle, starting from the base address BA1+LEN1, after receiving a write-back request, two first-level packets (i.e., LEN1x2) of data are sequentially written back to the DRAM memory. After each write-back is completed, the write-back data address is incremented by LEN1x2. When the amount of data written back reaches LEN-LEN1x2, the request address is restored to the initial BA1.

[0195] The memory access controller is used to convert the data request from the sequencer into an access request to the DRAM.

[0196] DRAM is a dynamic random access memory (DRAM) with large storage capacity. However, due to the bandwidth limitations of its data transmission interface, its data transmission rate is often much lower than that of a tightly coupled cache.

[0197] The scheduling unit coordinates and sorts the various modules within it to complete the sorting function.

[0198] The scheduling unit schedules the sorting process according to the lengths of the packet data at each level LEN2, LEN1, LEN, the number of secondary packets GC2, and the number of primary packets GC1.

[0199] In this embodiment, in order to simplify the design complexity, a variant sorting mode is used to schedule the first-level and second-level group sorting. The basic sorting adopts the basic sorting algorithm.

[0200] After the operation starts, for the tightly coupled memory, the scheduling unit first clears the first-level sort counter (CNT1), and then:

[0201] A memory load enable request is issued to the tightly coupled memory to load two level 1 packet data.

[0202] The current A or B type cycle is determined based on the current CNT1 value. When CNT1%2=0, the "LD1_AB type selection" signal is identified as an A type cycle (signal is 0); when CNT1%2=1, the "LD1_AB type selection" signal is identified as a B type cycle (signal is 1).

[0203] The current A or B type cycle is determined based on the current CNT1 value. When CNT1%2=0, the "ST1_AB type selection" signal is identified as an A type cycle (signal is 0); when CNT1%2=1, the "ST1_AB type selection" signal is identified as a B type cycle (signal is 1).

[0204] After the two first-level groups in the tightly coupled memory are processed, CNT1 is incremented by one, and then the processing of the next two first-level groups is started. The above operation is repeated until CNT1 equals GC1, and the sorting is completed.

[0205] For the register prefetch unit, the dispatch unit first clears the secondary order load counter (LCNT2), and then:

[0206] A preload enable request is issued to the register prefetch unit to load two secondary grouped data.

[0207] The current A or B type cycle is determined based on the current LCNT2 value. When LCNT1%2=0, the "LD2_AB type selection" signal is identified as an A type cycle (signal is 0); when LCNT2%2=1, the "LD2_AB type selection" signal is identified as a B type cycle (signal is 1).

[0208] After the two second-level groups in the register prefetch unit are processed, LCNT2 is incremented by one, and then the operation of the next two first-level groups is started. The above operation is repeated until LCNT2 is equal to GC2, and the sorting is completed.

[0209] For registers and basic sorting units:

[0210] Before starting sorting after merging each two secondary packets, the scheduling unit first clears the basic sorting counter (BCNT).

[0211] After the register prefetch unit completes loading, it first issues a register load enable instruction to load the data prefetched by the register prefetch unit into the register, and then turns off the register load enable. At the same time, BCNT starts counting, and the basic sort unit increases BCNT by one each time it completes a basic sort.

[0212] The current BCNT value determines whether the current cycle is type A or type B. When BCNT1%2=0, the "AB type selection" signal is identified as a type A cycle (signal 0); when BCNT2%2=1, the "AB type selection" signal is identified as a type B cycle (signal 1).

[0213] The above operation is repeated until BCNT is equal to LEN2x2-1, and the sorting is completed. At the same time, a result write-back enable instruction is sent to the result write-back unit.

[0214] Regarding early termination of sorting:

[0215] For basic sorting: the scheduling unit determines whether the sorting can be ended early by detecting the results of the "AND" operation on the "not occurred" indication of all basic sorting units (only when all basic sorting units have not been exchanged, the "AND" operation result is 1, otherwise it is 0).

[0216] When no data exchange occurs in two consecutive sort operations, the sort is terminated early.

[0217] When no data exchange occurs in the previous two sorts, it indicates that the sorting in the initial state has been completed, and the state of this sorting is marked as the "basic sorting without exchange" state.

[0218] For secondary sorting: the scheduling unit determines whether the sorting can be ended early by detecting "no exchange in basic sorting" detected during the basic sorting process.

[0219] When no data exchange occurs in all basic sorts in three consecutive secondary sort operations, the sorting is terminated early.

[0220] When no data exchange occurs in all basic sorts in the current three secondary sort operations, it indicates that the secondary sort has been completed in the initial state, and the state of this sort is marked as "secondary sort completed".

[0221] For the first-level sorting: the scheduling unit determines whether the sorting can be ended early by detecting the "no exchange in the second-level sorting" detected during the basic sorting process.

[0222] When no data exchange occurs in all secondary sorts in three consecutive primary sort operations, the sorting is terminated early and the sequence sorting is completed.

[0223] Compared with traditional sorting algorithms, the data sorting method of the embodiment of the present application has the following advantages in sorting very long sequences:

[0224] The sorting algorithm is highly regular and can effectively remove data dependencies between the data involved in the operation, making it easier to use highly parallel vector machines and tensor machines to accelerate the operation. At the same time, it can naturally integrate and solidify related operations into vector and tensor processors.

[0225] The hierarchical grouping structure can effectively utilize the storage structure of modern vector and tensor processors to optimize the access bandwidth of the sorting operation to the system DRAM, greatly shortening the sorting time. Take the sorting of 1024x1024 32-bit width data as an example:

[0226] Using traditional algorithms such as bubble sort requires access to 4x(1024x1024)x(1024x1024) / 2x2=4396GB of data from DRAM.

[0227] Use a hierarchical fluctuation sorting approach such as in the example:

[0228] The 1024x1024 sequence is first divided into 64 first-level groups of 16x1024 data. During the operation, the first-level groups are stored in the tightly coupled cache. Subsequent memory accesses generated by the first-level group sorting can be completed in the tightly coupled cache without generating additional data accesses to DRAM.

[0229] According to the characteristics of the sorting algorithm, only 4x(1024x1024)x64x2=0.54GB of data needs to be accessed from DRAM, which greatly reduces the amount of data accessed compared to traditional sorting algorithms.

[0230] An embodiment of the present application further provides a storage medium, which carries one or more computer programs. When the one or more computer programs are executed by a processor, the steps of the method described above are implemented.

[0231] An embodiment of the present application further provides a computer program product, including a computer program / instruction, characterized in that the computer program / instruction implements the steps of the above-mentioned method when executed by a processor.

[0232] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0233] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAMbus RAM (DR RAM).

[0234] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated into the processor.

[0235] It should be noted that the memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0236] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of this application.

[0237] It should be understood that the term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0238] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0239] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0240] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0241] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the hardware accelerator embodiment described above is only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0242] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0243] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0244] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk).

[0245] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data sorting method, characterized in that: include: Based on the arrangement order of the registers, storing the plurality of target data into the corresponding registers respectively; performing a first sorting operation on the target data in the registers, comprising: starting from a first register having a first sequence number, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; performing a sub-operation of an intermediate sorting operation on the target data in the register, wherein the sub-operation includes a second sorting operation and a third sorting operation, the second sorting operation including: starting from the second register having the second sequence number, sequentially comparing the target data in two adjacent registers, and comparing the first register with the register having the first-to-last sequence number, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; the third sorting operation including: starting from the second register, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; The first sorting operation and the second sorting operation are repeated alternately multiple times, or the first sorting operation and the third sorting operation are repeated alternately multiple times until all the target data are sorted from large to small or from small to large in numerical value.

2. The data sorting method according to claim 1, characterized in that: In a case where the target data contains a plurality of data units and the data units are not sorted, the method further includes: Based on the arrangement order of the registers, the plurality of data units are stored in the corresponding registers respectively; Taking the data units in the register as objects, performing the first sorting operation on them; Taking the data unit in the register as an object, performing a sub-operation of the intermediate sorting operation on the data unit; The first sorting operation and the second sorting operation are repeated alternately multiple times, or the first sorting operation and the third sorting operation are repeated alternately multiple times until all the data units are sorted from large to small or from small to large in terms of numerical value.

3. The data sorting method according to claim 1, wherein: In a case where the target data contains a plurality of data units and has been sorted, the method further includes: Based on the numerical values ​​of the data units, the data units are grouped to form a plurality of data unit groups; Grouping the registers based on the arrangement order of the registers to form a plurality of register groups; Based on the arrangement order of the register groups, the data unit groups are stored in the corresponding register groups respectively; Taking the data unit group in the register group as an object, performing the first sorting operation on the data unit group; Taking the data unit group in the register group as an object, performing a sub-operation of the intermediate sorting operation on the data unit group, The first sorting operation and the second sorting operation are repeated alternately multiple times, or the first sorting operation and the third sorting operation are repeated alternately multiple times until all the data unit groups are sorted from large to small or from small to large in terms of numerical value.

4. The data sorting method according to claim 3, wherein: The grouping of the data units based on the numerical values ​​of the data units to form a plurality of data unit groups includes: dividing the data units into two data unit groups based on the numerical values ​​of the data unit groups; Accordingly, grouping the registers to form a plurality of register groups includes: constructing one register group based on four registers.

5. The data sorting method according to claim 1, wherein: The method further comprises: sorting the target data based on a preset time interval; The sorted target data is sent to the memory storage through the memory access controller.

6. A hardware accelerator, characterized in that: Connected to the memory storage, the hardware accelerator includes: Multiple sequentially arranged registers; A scheduling unit connected to the registers, configured to store target data into the respective corresponding registers; A plurality of basic sorting units are respectively connected to two corresponding adjacent registers, and the basic sorting units are configured to: perform a first sorting operation on the target data in the register under the control of the scheduling unit; perform a sub-operation of the intermediate sorting operation on the target data in the register, the sub-operation including a second sorting operation and a third sorting operation; alternately repeat the first sorting operation and the second sorting operation multiple times, or alternately repeat the first sorting operation and the third sorting operation multiple times until all the target data are sorted from large to small in value, or from small to large in value; wherein, The first sorting operation includes: starting from the first register with the first sequence number, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; wherein, The second sorting operation includes: starting from the second register with the second sequence number, sequentially comparing the target data in two adjacent registers, and comparing the first register with the register with the last sequence number, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison; The third sorting operation includes: starting from the second register, sequentially comparing the target data in two adjacent registers, storing the target data with a larger value in the register that is ranked earlier or later among the two registers involved in the comparison, and storing the target data with a smaller value in the register that is ranked later or earlier among the two registers involved in the comparison.

7. The hardware accelerator according to claim 6, characterized in that Also includes: a tightly coupled memory, configured to store the target data; A register prefetch unit is connected to the scheduling unit, the register and the tightly coupled memory respectively. After receiving an instruction from the scheduling unit, the register prefetch unit obtains the target data from the tightly coupled memory and loads the target data into the corresponding registers according to the instruction.

8. The hardware accelerator according to claim 7, characterized in that: A first data multiplexer is provided between the register and the basic sorting unit. The first data multiplexer is connected to the scheduling unit and, under the control of the scheduling unit, selects one of its input data as output data and sends it to the basic sorting unit. A second data multiplexer is provided between the register prefetch unit and the register. The second data multiplexer is connected to the scheduling unit and, under the control of the scheduling unit, selects one of its input data as output data and sends it to the register.

9. The hardware accelerator according to claim 7, characterized in that: Also includes: A result write-back unit is connected to the basic sorting unit, the scheduling unit and the tightly coupled memory respectively. The result write-back unit stores the sorting result of the sorting operation performed on the target data under the control of the scheduling unit.

10. The hardware accelerator according to claim 7, wherein: Also includes: A memory access controller is respectively connected to the tightly coupled memory and the memory storage, and is used to obtain the target data from the memory storage according to a data call request of the tightly coupled memory, or to send a sorting result of a sorting operation on the target data to the memory storage.

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