Hierarchical abstraction method and system for computing resources

Abstract

The application discloses a layered abstraction method and system of computing resources, and relates to the technical field of resource abstraction. The layered abstraction method of computing resources comprises the following steps: constructing a three-level abstraction architecture system; wherein the three-level abstraction architecture system comprises a service interface layer, a device function abstraction layer and a hardware adaptation layer; in the device function abstraction layer, hardware operations are abstracted into multiple independent function modules by adopting horizontal function decoupling, each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library; and a device description structure body is defined in the device function abstraction layer. The application solves the technical problems faced by the existing business system, including but not limited to the following: interface heterogeneity, the driving interface specifications of various hardware platforms are not unified, special adaptation codes need to be developed for each hardware; high resource coupling degree, the business logic and hardware operation codes are deeply coupled, and the hardware switching needs to modify the business layer code.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of resource abstraction, and in particular to a layered abstraction method and system of computing resources. BACKGROUND

[0002] In a heterogeneous computing environment, hardware interfaces provided by different hardware manufacturers (such as NVIDIA GPU, Huawei NPU, Cambrian MLU, etc.) differ significantly, resulting in technical problems faced by business systems including but not limited to the following: interface heterogeneity, non-uniformity of driving interface specifications of each hardware platform, need to develop special adaptation code for each hardware; high resource coupling, deep coupling of business logic and hardware operation code, hardware switching requires modification of business layer code. SUMMARY

[0003] The purpose of the present application is to provide a layered abstraction method and system of computing resources to at least solve one of the problems existing in the prior art.

[0004] Technical solution: A layered abstraction method of computing resources, comprising:

[0005] Constructing a three-level abstraction architecture system; wherein the three-level abstraction architecture system comprises: a service interface layer, a device function abstraction layer, and a hardware adaptation layer;

[0006] In the device function abstraction layer, the hardware operation is abstracted into multiple independent function modules, and each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library through horizontal function decoupling;

[0007] In the device function abstraction layer, a device description structure is defined, and multiple different types of hardware devices are adapted vertically, and each type of hardware device completes hardware adaptation by instantiating the structure and generating a corresponding dynamic link library;

[0008] The device function abstraction layer switches different heterogeneous resources to execute corresponding functions through a run-time dynamic loading method.

[0009] As a preferred, the device function abstraction layer comprises: an inference function library, a codec function library, and an image processing function library.

[0010] As a preferred, the device function abstraction layer adopts horizontal function decoupling, comprising:

[0011] The hardware operation is divided into device management, context management, memory management, and model execution function domains;

[0012] Each function domain corresponds to an independent dynamic link library, and provides services through a standardized C-ABI interface;

[0013] The standardized interface at least includes a device feature query interface, a context lifecycle interface, and an asynchronous execution interface.

[0014] As preferred, the device description structure includes a device identifier, a manufacturer name, a computing architecture type, a memory pool pointer, an error callback function, and a hardware capability matrix.

[0015] As preferred, the hardware adaptation layer includes:

[0016] A set of standardized device operation interfaces, including device initialization, resource release, and configuration update;

[0017] Embedding version compatibility metadata in the hardware adaptation library through a compiler attribute;

[0018] Implementing on-demand loading of dependent libraries using the lazy loading flag of the dynamic link library.

[0019] As preferred, the hardware discovery mechanism of the dynamic loading control system includes:

[0020] Obtaining a list of available hardware adaptation libraries by traversing a predefined hardware library path;

[0021] Parsing the feature matrix exported by each library and matching it with the hardware capability requirements of the service request;

[0022] Building a hardware capability scoring model that includes device computing power, memory bandwidth, and instruction set support.

[0023] As preferred, it also includes: when in the inference service startup phase, the inference class service calls the device management interface provided by the device function abstraction layer, queries the available heterogeneous hardware devices in the system and obtains their identification information;

[0024] According to the device type parameter transmitted by the service, the hardware abstraction library corresponding to the device type is loaded through dynamic linking, and the target device is initialized to create a device context object;

[0025] Loading the inference model and creating a model executor object;

[0026] Calling the unified inference interface provided in the device abstraction library to perform model inference calculation;

[0027] Returning the inference result, and unloading the model, destroying the device context, or exiting the device after the calculation is completed.

[0028] In order to achieve the above purpose, according to another aspect of the present application, a hierarchical abstraction system of computing resources is provided.

[0029] The hierarchical abstraction system of computing resources according to the present application includes:

[0030] A construction module is configured to construct a three-level abstract architecture system, wherein the three-level abstract architecture system comprises a service interface layer, a device function abstraction layer, and a hardware adaptation layer.

[0031] A transverse function decoupling module is configured to decouple functions transversely in the device function abstraction layer, abstract hardware operations into a plurality of independent function modules, and provide a unified abstract interface for the service interface layer in the form of dynamic link libraries.

[0032] A hardware adaptation module is configured to define a device description structure in the device function abstraction layer, and adapt a plurality of different types of hardware devices vertically, and each type of hardware device completes hardware adaptation by instantiating the structure and generating a corresponding dynamic link library.

[0033] A switching reasoning module is configured to switch different heterogeneous resources to execute corresponding functions by a run-time dynamic loading manner in the device function abstraction layer.

[0034] In order to achieve the above-mentioned purpose, according to another aspect of the present application, an electronic device is provided, comprising at least one processor, and a memory connected with the at least one processor in communication; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the layered abstraction method of the computing resource according to any one of the present application.

[0035] In order to achieve the above-mentioned purpose, according to another aspect of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the layered abstraction method of the computing resource according to any one of the present application.

[0036] Beneficial effects: in the embodiment of the present application, the hierarchical abstraction method is adopted, and a three-level abstraction architecture system is constructed; the three-level abstraction architecture system includes a service interface layer, a device function abstraction layer and a hardware adaptation layer; in the device function abstraction layer, the hardware operation is abstracted into a plurality of independent function modules by adopting horizontal function decoupling, each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library; a device description structure body is defined in the device function abstraction layer, and a plurality of different types of hardware devices are vertically adapted, and various types of hardware devices complete hardware adaptation by instantiating the structure body and generating corresponding dynamic link libraries; the device function abstraction layer switches different heterogeneous resources to execute corresponding functions by a running period dynamic loading mode, so as to achieve the purpose of accessing and managing hardware resources by calling services, thereby realizing the technical effect of helping to hide hardware details and simplifying the interaction between the application program and the hardware, and further solving the technical problems faced by the existing business system, including but not limited to the following technical problems: interface heterogeneity, the driving interface specifications of each hardware platform are not unified, and special adaptation code needs to be developed for each hardware; high resource coupling degree, the business logic and the hardware operation code are deeply coupled, and the hardware switching needs to modify the business layer code. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a component diagram of the hierarchical abstraction method of the computing resource according to the embodiment of the present application;

[0038] Figure 2 is a component relationship example diagram of the hierarchical abstraction method of the computing resource according to the embodiment of the present application;

[0039] Figure 3 is a design schematic diagram of the hierarchical abstraction method of the computing resource according to the embodiment of the present application;

[0040] Figure 4 is a detailed design schematic diagram of the hierarchical abstraction method of the computing resource according to the embodiment of the present application;

[0041] Figure 5 is a computing resource scheduling function scheduling timing diagram of the hierarchical abstraction method of the computing resource according to the embodiment of the present application;

[0042] Figure 6 is a flowchart of the hierarchical abstraction system of the computing resource according to the embodiment of the present application;

[0043] Figure 7 is a structure schematic diagram of the hierarchical abstraction system of the computing resource according to the embodiment of the present application; and

[0044] Figure 8 is a structure schematic diagram of the electronic device of the hierarchical abstraction method of the computing resource according to the embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the personnel in the technical field better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0046] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] In addition, the terms "mount", "set", "provided with", "connected", "linked", "sleeved" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally configured; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. Those skilled in the art can understand the specific meaning of the above terms in the present application according to the specific circumstances.

[0048] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0049] As shown in Figures 1-6 According to an embodiment of the present application, a hierarchical abstraction method of computing resources is provided, which comprises the following steps S101 to S104:

[0050] Step S101, a three-level abstraction architecture system is constructed; wherein the three-level abstraction architecture system comprises: a service interface layer, a device function abstraction layer and a hardware adaptation layer;

[0051] Good preliminary system construction effect can be achieved, thereby providing a basis and guarantee for subsequent processing.

[0052] It should be noted that, as Figure 1As shown, the computing resource abstraction is a unified encapsulation of underlying heterogeneous hardware resources, and the device abstraction layer adapts the underlying hardware in the form of a heterogeneous hardware unified adaptation framework (MSAdapter).

[0053] According to the embodiment of the present application, preferably, the device function abstraction layer comprises: an inference function library, a codec function library and an image processing function library.

[0054] The effect of providing a plurality of function libraries can be achieved, thereby achieving the effect of a plurality of functions.

[0055] According to the embodiment of the present application, preferably, the hardware adaptation layer comprises:

[0056] A standard device operation interface set, including device initialization, resource release and configuration update;

[0057] Version compatibility metadata is embedded in the hardware adaptation library through a compiler attribute;

[0058] The on-demand loading of dependent libraries is implemented by using a delay loading flag of a dynamic link library.

[0059] In step S102, the hardware operation is abstracted into a plurality of independent function modules by using horizontal function decoupling in the device function abstraction layer, and each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library;

[0060] According to horizontal function division, each function provides a unified abstract interface for the service in the form of a dynamic link library, and the service only needs to link the library at the time of compilation to conveniently use the function.

[0061] According to the embodiment of the present application, preferably, the horizontal function decoupling in the device function abstraction layer comprises:

[0062] The hardware operation is divided into device management, context management, memory management and model execution function domains;

[0063] Each function domain corresponds to an independent dynamic link library, and provides services through a standardized C-ABI interface;

[0064] The standardized interface at least includes: a device feature query interface, a context life cycle interface and an asynchronous execution interface.

[0065] In step S103, a device description structure body is defined in the device function abstraction layer, and a plurality of different types of hardware devices are vertically adapted, and each type of hardware device completes hardware adaptation by instantiating the structure body and generating a corresponding dynamic link library.

[0066] In the longitudinal dimension, each device abstract library of the function provides hardware abstraction to the lower layer by defining a device structure body, and various hardware adapt to the hardware by instantiating the structure body and compiling into a dynamic link library.

[0067] According to the embodiment of the present application, preferably, the hardware discovery mechanism of the dynamic loading control system comprises:

[0068] The available hardware adaptation library list is obtained by traversing a predefined hardware library path.

[0069] The feature matrix exported by each library is parsed and matched with the hardware capability requirement of the service request.

[0070] A hardware capability scoring model containing device computing power, memory bandwidth and instruction set support is constructed.

[0071] In step S104, the device function abstraction layer switches different heterogeneous resources to execute corresponding functions through a run-time dynamic loading mode.

[0072] The device abstract library flexibly switches different heterogeneous resources to execute corresponding functions through a run-time dynamic loading mode.

[0073] According to the embodiment of the present application, preferably, further comprising: when in the inference service starting stage, the inference type service calls a device management interface provided by the device function abstraction layer, queries available heterogeneous hardware devices in the system and obtains their identification information;

[0074] According to the device type parameter transmitted by the service, a hardware abstract library corresponding to the device type is loaded through a dynamic link mode, the target device is initialized, and a device context object is created;

[0075] The inference model is loaded and a model executor object is created.

[0076] A unified inference interface provided in the device abstract library is called to execute model inference calculation.

[0077] The inference result is returned, and after the calculation is completed, the model is unloaded, the device context is destroyed, or the device is exited.

[0078] The workflow of the present application is shown as follows:

[0079] As shown in Figure 2 , taking a specific target recognition scene as an example, each component service links different MSAdapterAPI function libraries and realizes specific business logic by means of the interfaces thereof, and the function libraries realize calling hardware resources for processing by means of dynamically loading HAL layer manufacturer libraries.

[0080] The specific function design is shown as follows: Figure 3As shown, in the vertical dimension, the device abstraction library for each function provides hardware abstraction to the lower layer by defining device structures. Various types of hardware are adapted by instantiating this structure and compiling it into a dynamic link library. The device abstraction library flexibly switches between different heterogeneous resources to execute the corresponding functions through runtime dynamic loading.

[0081] like Figure 4 As shown, taking inference functionality as an example, inference services implement inference-related business logic using the device management, context management, and model execution interfaces provided by the inference functionality device abstraction library through compile-time static loading. The required hardware device type is specified by passing parameters, without needing to concern itself with the underlying hardware interface calls. Upon receiving a call to its own API from the service, the inference functionality device abstraction library dynamically loads the relevant hardware interface implementations and dependent libraries into memory at runtime and then invokes them, thereby enabling inference using the specified hardware resources.

[0082] like Figure 5 The diagram shows the call flow from the inference service to the device abstraction library for inference functions, and from the device abstraction library to the hardware HAL library for the hardware adaptation layer.

[0083] First, the inference service queries whether the device is available and obtains the device object by calling the device management interface of the device abstraction library. The device abstraction library searches downwards by library name and loads the HAL library of the specified hardware. After loading, it calls the open_device interface to initialize the device and returns the device object.

[0084] After device initialization is complete, a context object is created and initialized using a similar process. Then, model objects are created and loaded using model information.

[0085] Finally, after creating the executor object to complete the inference calculation, the resources are destroyed. This completes a full inference calculation process, and the switching of the underlying hardware of the service layer does not affect the implementation of the service business logic.

[0086] As can be seen from the above description, this application achieves the following technical effects:

[0087] In the embodiment of the present application, a hierarchical abstraction method is adopted, and a three-level abstraction architecture system is constructed. The three-level abstraction architecture system includes a service interface layer, a device function abstraction layer, and a hardware adaptation layer. In the device function abstraction layer, hardware operations are abstracted into a plurality of independent function modules through horizontal function decoupling, and each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library. A device description structure is defined in the device function abstraction layer, and a plurality of different types of hardware devices are adapted vertically. Each type of hardware device completes hardware adaptation by instantiating the structure and generating a corresponding dynamic link library. The device function abstraction layer switches different heterogeneous resources to execute corresponding functions through a run-time dynamic loading method, so as to achieve the purpose of accessing and managing hardware resources by calling services, thereby realizing the technical effect of helping to hide hardware details and simplifying the interaction between an application program and hardware. Thus, the technical problems of the existing business system, including but not limited to the following technical problems, are solved: interface heterogeneity, non-uniformity of the driving interface specifications of each hardware platform, the need to develop special adaptation code for each hardware, high resource coupling degree, deep coupling of business logic and hardware operation code, and the need to modify the business layer code for hardware switching.

[0088] As shown in Figure 7 To achieve the above purpose, according to another aspect of the present application, a hierarchical abstraction system of computing resources is provided. The hierarchical abstraction system of computing resources includes:

[0089] A construction module 701 is configured to construct a three-level abstraction architecture system. The three-level abstraction architecture system includes a service interface layer, a device function abstraction layer, and a hardware adaptation layer.

[0090] Good preliminary system construction effects can be achieved, thereby providing a basis and guarantee for subsequent processing.

[0091] A horizontal function decoupling module 702 is configured to adopt horizontal function decoupling in the device function abstraction layer, to abstract hardware operations into a plurality of independent function modules, and to provide a unified abstract interface for the service interface layer in the form of a dynamic link library.

[0092] According to horizontal function division 703, each function provides a unified abstract interface for services in the form of a dynamic link library, and services only need to link the library during compilation to conveniently use the function.

[0093] A hardware adaptation module 704 is configured to define a device description structure in the device function abstraction layer, and to adapt a plurality of different types of hardware devices vertically. Each type of hardware device completes hardware adaptation by instantiating the structure and generating a corresponding dynamic link library.

[0094] In the longitudinal dimension, each device abstract library of the function provides hardware abstraction to the lower layer by defining a device structure, and various types of hardware adapt to hardware by instantiating the structure and compiling it into a dynamic link library.

[0095] The switching reasoning module is configured to switch different heterogeneous resources to execute corresponding functions by the device function abstraction layer in a run-time dynamic loading manner.

[0096] The device abstract library flexibly switches different heterogeneous resources to execute corresponding functions by a run-time dynamic loading manner.

[0097] From the above description, it can be seen that the application achieves the following technical effects:

[0098] In the embodiment of the application, a hierarchical abstraction manner is adopted, and a three-level abstraction architecture system is constructed; the three-level abstraction architecture system includes a service interface layer, a device function abstraction layer and a hardware adaptation layer; in the device function abstraction layer, hardware operations are abstracted into a plurality of independent function modules by adopting horizontal function decoupling, and each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library; a device description structure is defined in the device function abstraction layer, and a plurality of different types of hardware devices are vertically adapted, and various types of hardware devices complete hardware adaptation by instantiating the structure and generating corresponding dynamic link libraries; the device function abstraction layer switches different heterogeneous resources to execute corresponding functions by a run-time dynamic loading manner, so as to achieve the purpose of accessing and managing hardware resources by calling services, thereby realizing the technical effect of helping to hide hardware details and simplifying the interaction between an application program and hardware, and further solving the technical problems faced by the existing business system, including but not limited to the following technical problems: interface heterogeneity, the driving interface specifications of various hardware platforms are not unified, and special adaptation code needs to be developed for each hardware; high resource coupling degree, the business logic and hardware operation code are deeply coupled, and the hardware switching needs to modify the business layer code.

[0099] As shown in Figure 8 The electronic device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is in communication connection with the at least one processor 11, wherein the memory stores a computer program which can be executed by the at least one processor, and the processor 11 can execute various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0100] A plurality of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, a speaker, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0101] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the hierarchical abstraction method of computing resources.

[0102] In some embodiments, the hierarchical abstraction method of computing resources can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded onto the RAM 13 and executed by the processor 11, one or more steps of the hierarchical abstraction method of computing resources described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the hierarchical abstraction method of computing resources by any other appropriate means, such as by means of firmware.

[0103] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0104] Computer programs for implementing the methods of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer program, when executed, can cause instructions defined in the flow charts and / or block diagrams to be implemented. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package and partially on a remote machine or entirely on a remote machine or server.

[0105] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0106] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0107] The systems and techniques described herein can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described herein, or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0108] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0109] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in different orders, as long as the desired results of the technical solutions of the present disclosure can be achieved, and the present disclosure is not limited herein.

[0110] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of hierarchical abstraction of computing resources, characterized in that, The application comprises the following steps: A three-level abstract architecture system is constructed, wherein the three-level abstract architecture system comprises a service interface layer, a device function abstraction layer, and a hardware adaptation layer; In the device function abstraction layer, horizontal function decoupling is adopted to abstract hardware operations into multiple independent function modules, and each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library; The device function abstraction layer comprises an inference function library, a codec function library, and an image processing function library; The inference function library comprises the following steps: Hardware operations are divided into device management, context management, memory management, and model execution function domains; Each function domain corresponds to an independent dynamic link library, and services are provided through a standardized C-ABI interface; The standardized interface at least comprises a device feature query interface, a context life cycle interface, and an asynchronous execution interface; In the device function abstraction layer, a device description structure is defined, and multiple different types of hardware devices are vertically adapted, and each type of hardware device completes hardware adaptation by instantiating the structure and generating a corresponding dynamic link library; The device function abstraction layer switches different heterogeneous resources to execute corresponding functions through a run-time dynamic loading method; The hardware discovery mechanism of the dynamic loading control system comprises the following steps: An available hardware adaptation library list is obtained by traversing a pre-defined hardware library path; A feature matrix exported by each library is parsed and matched with the hardware capability requirements of a service request; A hardware capability scoring model containing device computing power, memory bandwidth, and instruction set support is constructed; When the inference service starts, the inference class service calls the device management interface provided by the device function abstraction layer, queries the available heterogeneous hardware devices in the system, and obtains their identification information; According to the device type parameter transmitted by the service, a hardware abstraction library corresponding to the device type is loaded through a dynamic link method, the target device is initialized, and a device context object is created; A model execution object is created by loading an inference model; A unified inference interface provided in the device abstraction library is called to execute model inference calculation; The inference result is returned, and the model is unloaded, the device context is destroyed, or the device is exited after the calculation is completed.

2. The hierarchical abstraction method of computing resources according to claim 1, wherein, The device description structure comprises a device identifier, a manufacturer name, a computing architecture type, a memory pool pointer, an error callback function, and a hardware capability matrix.

3. The hierarchical abstraction method of computing resources according to claim 1, wherein, The hardware adaptation layer comprises the following steps: A standard device operation interface set is provided, including device initialization, resource release, and configuration update; Version compatibility metadata is embedded in the hardware adaptation library through a compiler attribute; A delay loading flag of a dynamic link library is used to realize on-demand loading of dependent libraries.

4. A hierarchical abstraction system of computing resources, characterized in that, The application comprises the following steps: A three-level abstract architecture system is constructed, wherein the three-level abstract architecture system comprises a service interface layer, a device function abstraction layer, and a hardware adaptation layer; In the device function abstraction layer, horizontal function decoupling is adopted to abstract hardware operations into multiple independent function modules, and each function module provides a unified abstract interface for the service interface layer in the form of a dynamic link library; The device function abstraction layer comprises an inference function library, a codec function library, and an image processing function library; The inference function library comprises the following steps: The hardware operations are divided into device management, context management, memory management and model execution function domains; Each function domain corresponds to an independent dynamic link library, and services are provided through a standardized C-ABI interface; The standardized interface includes at least a device feature query interface, a context life cycle interface and an asynchronous execution interface; A hardware adaptation module is configured to define a device description structure in the device function abstraction layer, and to vertically adapt a plurality of different types of hardware devices, each type of hardware device completing hardware adaptation by instantiating the structure and generating a corresponding dynamic link library; A switching reasoning module is configured to switch different heterogeneous resources to execute corresponding functions through a run-time dynamic loading manner in the device function abstraction layer; The hardware discovery mechanism of the dynamic loading control system includes: A list of available hardware adaptation libraries is obtained by traversing a predefined hardware library path; A feature matrix exported by each library is parsed and matched with the hardware capability requirements of a service request; A hardware capability scoring model is constructed including device computing power, memory bandwidth and instruction set support; Further comprising: when in the reasoning service startup phase, a reasoning class service calls a device management interface provided by the device function abstraction layer, queries available heterogeneous hardware devices in the system and obtains their identification information; According to the device type parameter transmitted by the service, a hardware abstraction library corresponding to the device type is loaded through a dynamic linking manner, and the target device is initialized, a device context object is created; A reasoning model is loaded and a model executor object is created; A unified reasoning interface provided in the device abstraction library is called to execute model reasoning calculation; The reasoning result is returned, and after the calculation is completed, the model is unloaded, the device context is destroyed or the device is exited.

5. An electronic device, characterized by The electronic device includes: At least one processor; and A memory connected in communication with the at least one processor; wherein The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the hierarchical abstraction method of the computing resource in any one of claims 1-3.

6. A computer readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing the processor to implement the hierarchical abstraction method of the computing resource in any one of claims 1-3 when executed.

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