Multi-channel processing method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a multi-channel processing method and device, electronic equipment, a chip and a storage medium, and relates to the technical field of processors, the method comprises the steps that the instruction fetching sequence of at least one channel to be fetched is determined, and the at least one channel corresponds to the same processor core; enabling each channel to read an instruction according to the instruction fetching sequence; and executing a corresponding operation based on the instruction fetched by each channel. Therefore, the parallel processing capacity can be met through the single-core multi-channel, the performance of the processor is improved, and the method can be suitable for scenes with simple services, high parallel processing requirements and high power consumption requirements.

Description

Technical Field

[0001] The present disclosure relates to the field of processor technologies, and in particular, to a multi-channel processing method, apparatus, electronic device, chip, and storage medium. Background Art

[0002] A variety of sensors are installed in many electronic devices such as wearable electronic watches and bracelets. With the increase in the number of sensors in electronic devices, the processor has higher requirements for parallel processing capabilities while taking into account real-time performance.

[0003] In related technologies, it is usually the Arm (Advanced RISC Machines) or risc-v (Reduced Instruction Set Computer-Fifth Generation) processor that is used to complete sensor data acquisition. The Arm and risc-v processors use multiple cores to meet the parallel processing capabilities, resulting in relatively large power consumption overhead and high costs. Summary of the Invention

[0004] The present disclosure provides a multi-channel processing method, apparatus, electronic device, chip, and storage medium, aiming to solve at least one of the technical problems in related technologies to some extent.

[0005] A first aspect embodiment of the present disclosure provides a multi-channel processing method, including:

[0006] Determining the fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core;

[0007] Fetching instructions for each of the channels according to the fetch order;

[0008] Performing corresponding operations based on the instructions fetched by each of the channels.

[0009] A second aspect embodiment of the present disclosure provides a multi-channel processing apparatus, including:

[0010] A determination module, configured to determine the fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core;

[0011] A fetch module, configured to fetch instructions for each of the channels according to the fetch order;

[0012] An execution module, configured to perform corresponding operations based on the instructions fetched by each of the channels.

[0013] A third aspect embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the multi-channel processing method of the embodiments of the present disclosure.

[0014] A fourth aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the multi-channel processing method disclosed in the embodiments of the present disclosure.

[0015] A fifth aspect embodiment of the present disclosure provides a chip, including a processor and an interface, where the processor is configured to read instructions to execute the multi-channel processing method disclosed in the embodiments of the present disclosure.

[0016] In the embodiments of the present disclosure, first, the instruction fetch order of at least one channel to be fetched is determined, where the at least one channel corresponds to the same processor core, then, according to the instruction fetch order, each channel reads instructions, and finally, based on the instructions fetched by each channel, corresponding operations are executed. Thus, the parallel processing capability can be satisfied through a single-core multi-channel, the processor performance can be improved, it can be applicable to scenarios with simple services, high requirements for parallel processing, and high requirements for power consumption, and the cost is relatively low.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0018] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, wherein:

[0019] Figure 1 is a flowchart of the multi-channel processing method according to the first embodiment of the present disclosure;

[0020] Figure 2 is a comparison diagram of a single-channel processor and a dual-channel processor according to an embodiment of the present disclosure;

[0021] Figure 3 is a flowchart of the multi-channel processing method according to the second embodiment of the present disclosure;

[0022] Figure 4 is a flowchart of the multi-channel processing method according to the third embodiment of the present disclosure;

[0023] Figure 5 is a step diagram of the code execution process within a dual channel;

[0024] Figure 6 is a schematic diagram of a multi-channel processing device according to an embodiment of the present disclosure;

[0025] Figure 7 is a block diagram of a chip for implementing the multi-channel processing method according to an embodiment of the present disclosure;

[0026] Figure 8 is a block diagram of an electronic device for implementing the multi-channel processing method according to an embodiment of the present disclosure. Detailed implementation manners

[0027] Here, some embodiments of the present disclosure will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. Various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will become apparent after understanding the present disclosure. For example, the order of operations described herein is merely an example and is not limited to those set forth herein. Instead, except for operations that must be performed in a specific order, changes can be made as will be apparent after understanding the present disclosure. Additionally, descriptions of features known in the art may be omitted for the sake of clarity and conciseness.

[0028] The implementation manners described in some embodiments of the present disclosure below do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0029] Among them, it should be noted that the execution subject of the multi-channel processing method in this embodiment may be a multi-channel processing device, which can be implemented in software and / or hardware, and this device can be configured in any type of electronic device. Alternatively, the execution subject of the multi-channel processing method in this embodiment may also be a processor, which is not limited herein.

[0030] In the embodiments of the present disclosure, the "processor" will be used as the execution subject to execute the multi-channel processing method for illustration, which is not limited herein.

[0031] Figure 1 is a flowchart of a multi-channel processing method according to the first embodiment of the present disclosure. As Figure 1 shown, the method includes:

[0032] S101: Determine the fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core.

[0033] Among them, at least one channel means that the channel can be one, or it can also be multiple, such as two, three, four, which is not limited here.

[0034] Among them, the fetch order can be the order in which the at least one channel obtains instructions.

[0035] Among them, waiting to fetch instructions means waiting to obtain instructions. It should be noted that when any channel needs to complete a certain task by fetching and executing instructions, it means that the any channel is a channel waiting to fetch instructions.

[0036] For example, after sensors A and B collect data, if channels 1 and 2 are required to fetch instructions, then channels 1 and 2 can be used as the channels waiting to fetch instructions, which is not limited here.

[0037] It can be understood that when there are multiple channels that need to access the same processor core for data processing, in order to ensure the orderliness and fairness of processing, and to avoid fetching conflicts between multiple channels, it is necessary to determine the fetch order of these channels in advance.

[0038] As a possible implementation method, when determining the fetch order of each channel, it can be based on round-robin scheduling, priority scheduling or other scheduling algorithms to ensure workload balance among channels, improve the overall performance of the system, and prevent deadlock states caused by resource contention.

[0039] S102: According to the fetch order, make each channel read instructions.

[0040] It can be understood that in a processor architecture with multiple channels, each channel can independently execute a set of instructions, and each channel can share the same processor core. In order to ensure the orderliness and fairness of instruction execution and avoid fetching conflicts, each channel can be made to read instructions in turn according to the fetch order.

[0041] For example, the processor arranges channels 0, 1, etc. to read instructions according to the fetch order. When channel 0 arrives in sequence, it will read an instruction from the instruction memory, and then channel 1 reads an instruction from the instruction memory.

[0042] In this way, even if there is only one processor core, multi-channel parallel fetching and execution of instructions can be achieved, thereby improving the parallel processing ability of the system. At the same time, a reasonable fetch order can also ensure fairness among channels and prevent a situation where a certain channel is not served for a long time.

[0043] S103: Based on the instructions fetched by each channel, execute the corresponding operations.

[0044] Specifically, the processor can decode the instructions fetched from the channels, identify the operation codes, operands, and control information of the instructions. Then, the decoded instructions can be sent to the corresponding execution units, such as the arithmetic logic unit (ALU), floating-point unit (FPU), memory access unit (MMU), etc., which are not limited here. After that, the execution units can perform corresponding calculations, data reading and writing, or other system operations according to the instruction types.

[0045] It can be understood that the execution units can process data according to the instruction indications, such as performing arithmetic operations, logical operations, loading / storing memory data, etc.

[0046] Optionally, after completing the operations, the execution results can also be written back to the registers or memory for subsequent instructions to use or directly output externally.

[0047] As Figure 2 shown, Figure 2 a dual-channel design is shown, which can allow two tasks to be carried out simultaneously, and can greatly reduce the chip area and power consumption. In Figure 2 the dual-channel sensor data acquisition system shown, there is a processor core and two channels. In this system, the processor core acquires data from the first group of sensors through channel 0 and acquires data from the second group of sensors through channel 1.

[0048] In this design, the same processor core acquires data from two groups of sensors through two groups of channels respectively. Compared with two processor cores acquiring data from two groups of sensors through one channel, an additional channel is added. In this way, the data of the two groups of sensors can be assigned to different channels to achieve task parallel processing, thereby reducing the data transmission delay and improving the system response speed. Since only one processor core is used, the cost is also saved.

[0049] By making full use of the computing power of the processor for sensor data, it should also be noted that Figure 2 the dual-channel design can also be extended to multi-channels. For example, if there are multiple sensors in the system, multiple channels can be used to collect and process data from different sensors. In this way, the parallel processing ability of the system can be further improved, thereby improving the overall performance of the system.

[0050] In the embodiments of the present disclosure, the processor first determines the fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core. Then, according to the fetch order, each channel reads instructions, and finally, based on the instructions fetched by each channel, corresponding operations are executed. Thus, the parallel processing capability can be satisfied through a single-core multi-channel, improving the processor performance, which can be applied to scenarios with simple services, high requirements for parallel processing, high requirements for power consumption, and low costs.

[0051] Figure 3 is a schematic flowchart of a multi-channel processing method according to the second embodiment of the present disclosure. As Figure 3 shown, the method includes:

[0052] S201: In response to receiving a sensor data processing task, determine the processor core to be selected.

[0053] Among them, the purpose of the sensor data processing task can be to collect sensor data or process and analyze sensor data, which is not limited herein.

[0054] It can be understood that the processor in the embodiments of the present disclosure can be a dedicated processor, that is, a processor specifically for processing a certain task.

[0055] As a possible application scenario, the processor in the embodiments of the present disclosure can be a processor specifically for processing sensor data.

[0056] Among them, the sensor data processing task involves obtaining raw data from the sensor and converting it into other information, so as to achieve real-time control, monitoring, analysis, or other purposes.

[0057] It can be understood that after the processor receives a task processing instruction regarding the sensor data processing task, it can determine the processor core to be selected according to the task. Among them, the processor core can be one or more, which is not limited herein.

[0058] Specifically, a processor core with appropriate performance can be selected according to the computing requirements of the task and the complexity of the data to be processed. Some tasks may require higher processor performance to process a large amount of data or perform complex calculations, while other tasks may have lower requirements for processor performance.

[0059] In the embodiments of the present disclosure, the sensor data processing task usually requires parallel processing to accelerate execution. Therefore, selecting a processor core with good parallel processing capabilities can improve the execution efficiency of the task. For example, a processor core that supports parallel computing is more suitable for processing tasks that need to process multiple data streams simultaneously.

[0060] S202: Using a round-robin scheduling method, assign an instruction fetch order to at least one channel corresponding to the processor core.

[0061] Optionally, the number of channels corresponding to each processor core can be determined. The number of channels usually depends on the design of the processor core and the architecture of the system and can be adjusted as needed, which is not limited here.

[0062] Among them, round-robin scheduling is a scheduling algorithm used to allocate resources or determine the execution order among multiple tasks. In the process of assigning an instruction fetch order to the channels corresponding to the processor core, the polling algorithm can be used to ensure that the instruction fetch opportunities are fairly allocated to each channel, thereby achieving balanced utilization of resources.

[0063] For example, the processor arranges for channels such as channel 0 and channel 1 to read instructions according to the instruction fetch order. When channel 0 arrives in sequence, it reads an instruction from the instruction memory, and then channel 1 reads an instruction from the instruction memory.

[0064] In this way, even if there is only one processor core, multi-channel parallel reading and execution of instructions can be achieved, thereby improving the parallel processing ability of the system. At the same time, a reasonable instruction fetch order can also ensure fairness among each channel and prevent a situation where a certain channel is not serviced for a long time.

[0065] S203: According to the instruction fetch order, enable each channel to read instructions from the static random access memory SRAM.

[0066] Among them, static random access memory (SRAM) is a type of computer memory used in applications such as caches and high-speed registers. Compared with dynamic random access memory (DRAM), SRAM does not need to periodically refresh the stored data, so it has a faster access speed and lower power consumption.

[0067] In the embodiments of the present disclosure, when a channel reads instructions, it can read instructions from the SRAM.

[0068] Among them, the SRAM can be directly integrated into the central processing unit CPU chip.

[0069] Optionally, instructions related to the sensor data processing task can be pre-stored in the SRAM, which can reduce the instruction fetch latency. Since the instructions of each channel come from the same SRAM and round-robin scheduling is used for instruction fetching, the number of SRAMs in the system can be greatly simplified, which is convenient for subsequent personnel development and maintenance.

[0070] S204: Based on the instructions fetched by each channel, perform corresponding operations.

[0071] It should be noted that the specific implementation of step S204 can refer to the above embodiments and will not be elaborated here.

[0072] In the embodiments of the present disclosure, first, in response to receiving a sensor data processing task, a processor core to be selected is determined, and then, in a round-robin scheduling manner, an instruction fetch order is assigned to at least one channel corresponding to the processor core. After that, according to the instruction fetch order, each channel reads instructions from the static random access memory (SRAM), and finally, based on the instructions fetched by each channel, corresponding operations are executed. Thus, fetch conflicts can be avoided, and the fetch opportunities can be fairly distributed to each channel, enabling parallel processing operations for each channel. Since each channel obtains instructions from the static random access memory (SRAM), the power-on complexity can be reduced, the power-on startup process is simplified, and the startup time is short.

[0073] Figure 4 It is a flowchart of a multi-channel processing method according to the third embodiment of the present disclosure. As Figure 5 shown, the method includes:

[0074] S301: Determine the instruction fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core.

[0075] S302: According to the instruction fetch order, enable each channel to read instructions.

[0076] It should be noted that the specific implementation of steps S301 - S302 can refer to the above embodiments and will not be elaborated here.

[0077] S303: Decode the instructions fetched by each channel according to a preset instruction format to obtain control signals.

[0078] Among them, different instruction formats map to different control signals, and the corresponding operations are also different. By pre-defining multiple different instruction formats, the requirements for dedicated tasks can be met, and the task processing efficiency can be improved.

[0079] Specifically, the fetched instructions can be decoded according to a custom instruction format and mapped to corresponding operations or actions.

[0080] Optionally, each instruction can occupy three bytes. The decoder will parse the instruction into corresponding control signals (operation codes) for use in the subsequent execution stage.

[0081] S304: Based on the control signals, execute corresponding task operations.

[0082] Among them, the control signal is also the decoding result. For different control signals, the executed operations can also be different. For example: decoding 001 executes action A, decoding 010 executes action B, and decoding 100 executes action H.

[0083] S305: According to the instruction format, determine whether a data write-back operation needs to be executed.

[0084] It should be noted that since there are multiple pre-stored instruction formats, for some instruction formats, the operations mapped need data write-back after being executed, while for some instruction formats, the operations mapped do not need data write-back after being executed.

[0085] That is to say, after executing the corresponding task operation, whether a data write-back operation is still required is determined according to the control signal. Different control signals map different operations. Some operations need data write-back after being executed, and may need to be written back to external memory. Some operations do not need data write-back after being executed.

[0086] S306: If a data write-back operation needs to be executed, then based on the write-back order, make at least one channel execute the data write-back operation.

[0087] Optionally, in the write-back stage, it can be first checked whether there is data to be written back in the at least one channel. If there is data to be written back in only one channel, then this channel can be directly made to perform the write-back operation. If there is data to be written back in multiple channels, then the write-back order of each channel can be first determined.

[0088] Among them, the write-back order can be the order of data write-back for multiple channels. For example, channel 1 and channel 0 perform data write-back in sequence.

[0089] Optionally, before making at least one channel execute the data write-back operation, a round-robin scheduling method can be adopted to allocate the write-back order for the at least one channel.

[0090] Among them, round-robin scheduling is a scheduling algorithm used to make decisions on resource allocation or execution order among multiple tasks. In the allocation of the write-back order for the channels corresponding to the processor cores, the round-robin algorithm can be used to ensure that the fetching opportunity is fairly allocated to each channel, so as to achieve balanced utilization of resources.

[0091] For example, the processor arranges for channel 0 and channel 1 to perform data write-back in sequence according to the write-back order. When channel 0 arrives in order, it writes the data back to external memory, and then channel 1 writes the data back to external memory.

[0092] At the same time, a reasonable write-back order can also ensure fairness among channels and prevent a situation where a certain channel is not served for a long time.

[0093] In the embodiments of the present disclosure, first, the fetch order of at least one channel to be fetched is determined, where the at least one channel corresponds to the same processor core. After that, according to the fetch order, each channel reads an instruction, and then, according to a preset instruction format, the instruction fetched by each channel is decoded to obtain a control signal. After that, based on the control signal, corresponding task operations are performed. Then, it can be judged whether a data write-back operation needs to be performed according to the instruction format. Finally, if a data write-back operation needs to be performed, based on the write-back order, the at least one channel performs the data write-back operation. Thus, by compiling instructions in a preset specified format, it helps to simplify the instruction decoding circuit, save hardware resources, improve the complexity and flexibility of instructions, and is applicable to the design of microcontrollers or embedded systems in specific scenarios. Since the data write-back operation is performed based on the write-back order, this can avoid write-back conflicts and improve the parallel processing ability of the processor.

[0094] Figure 5 It is a step diagram of the code execution process within a dual-channel. As Figure 5 shown, channel 0 needs to execute instruction 11, instruction 21... instruction N1 in sequence, and channel 1 needs to execute instruction 21, instruction 22... instruction N2 in sequence. When channel 0 needs to fetch instruction 11 and channel 1 needs to fetch instruction 21 simultaneously, a fetch conflict will occur. Therefore, a round-robin scheduling method can be adopted for fetching instructions, and then decoding and execution are performed. Considering that both channel 0 and channel 1 may write back to external memory after execution, the same strategy as the fetch conflict can be adopted, that is, a round-robin scheduling method is used for data write-back. The fetching, decoding, execution, and write-back of each channel are processed in a pipeline, which improves the work efficiency. At the same time, the code running between channels is independent of each other, and the requirements of simple services can be completed with very low power consumption.

[0095] To improve work efficiency, Figure 6 is a schematic diagram of a multi-channel processing device according to another embodiment of the present disclosure. As Figure 6 shown, the multi-channel processing device 600 includes:

[0096] A determination module 610, configured to determine the fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core;

[0097] A fetch module 620, configured to cause each of the channels to read an instruction according to the fetch order;

[0098] An execution module 630, configured to perform corresponding operations based on the instructions fetched by each of the channels.

[0099] Optionally, the instruction fetching module is specifically configured to:

[0100] According to the instruction fetching order, each of the channels reads instructions from the static random access memory (SRAM).

[0101] Optionally, the determining module 610 is specifically configured to:

[0102] In response to receiving a sensor data processing task, determine the processor core to be selected;

[0103] Adopt a round-robin scheduling method to allocate an instruction fetching order for at least one channel corresponding to the processor core.

[0104] Optionally, the execution module 630 includes:

[0105] A decoding unit, configured to decode the instructions fetched by each of the channels according to a preset instruction format to obtain control signals;

[0106] An execution unit, configured to perform corresponding task operations based on the control signals.

[0107] Optionally, the execution unit further includes:

[0108] A judgment subunit, configured to judge whether a data write-back operation needs to be performed according to the instruction format;

[0109] A write-back subunit, configured to, if a data write-back operation needs to be performed, cause the at least one channel to perform a data write-back operation according to a write-back order.

[0110] Optionally, the write-back subunit is further configured to:

[0111] Adopt a round-robin scheduling method to allocate the write-back order for the at least one channel.

[0112] In the embodiments of the present disclosure, the processor first determines the instruction fetching order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core. Then, according to the instruction fetching order, each of the channels reads instructions. Finally, based on the instructions fetched by each of the channels, corresponding operations are performed. Thus, the parallel processing capability can be satisfied through a single-core multi-channel architecture, improving the processor performance. It can be applied to scenarios with simple services, high requirements for parallel processing, and high requirements for power consumption, and has a relatively low cost.

[0113] To implement the above embodiments, the present disclosure also proposes a chip, which includes a processor, and the processor is configured to execute the method provided in the foregoing embodiments.

[0114] Figure 7It is a schematic structural diagram of a chip proposed by an embodiment of the present disclosure. Reference may be made to Figure 7 the schematic structural diagram of the chip 1100 shown in Figure 7 , but not limited thereto.

[0115] The chip 1100 includes a processor 1101, and the processor 1101 is configured to execute any of the above methods.

[0116] In some embodiments, the chip 1100 further includes one or more interfaces 1102. Optionally, the interface 1102 is connected to the memory 1103. The interface 1102 can be used to receive signals from the memory 1103 or other devices, and the interface 1102 can be used to send signals to the memory 1103 or other devices. For example, the interface 1102 can read the instructions stored in the memory 1103 and send the instructions to the processor 1101.

[0117] In some embodiments, the interface 1102 executes at least one of the communication steps such as sending and / or receiving in the above method, and the processor 1101 executes other steps.

[0118] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. can be replaced with each other. In some embodiments, the chip 1100 further includes one or more memories 1103 for storing instructions. Optionally, all or part of the memories 1103 can be outside the chip 1100.

[0119] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0120] Figure 8 A block diagram of an exemplary computer device suitable for implementing the embodiments of the present disclosure is shown. Figure 8 The computer device 12 shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0121] As Figure 8 shown, the computer device 12 is presented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0122] Bus 18 represents one or more of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, an Accelerated Graphics Port, a processor bus, or a local bus using any of the various bus architectures. By way of example, such architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnection (PCI) bus.

[0123] Computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by computer device 12, including volatile and nonvolatile media, removable and non-removable media.

[0124] Memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer device 12 may further include other removable / non-removable, volatile / nonvolatile computer system storage media. By way of example only, storage system 34 can be used for reading and writing on non-removable, nonvolatile magnetic media ( Figure 8 not shown, typically referred to as a "hard disk drive").

[0125] Although Figure 8 not shown in the figure, a disk drive for reading and writing on a removable nonvolatile disk (e.g., "floppy disk") and an optical disk drive for reading and writing on a removable nonvolatile optical disk (e.g., Compact Disc Read Only Memory (CD-ROM), Digital Video Disc Read Only Memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0126] A program / utilities 40 having a set (at least one) of program modules 42 can be stored, for example, in a memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods in the embodiments described in this disclosure.

[0127] The computer device 12 can also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, etc.), and can also communicate with one or more devices that enable a user to interact with the computer device 12, and / or communicate with any device that enables the computer device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through an input / output (I / O) interface 22. Moreover, the computer device 12 can also communicate with one or more networks (such as a Local Area Network (LAN), a Wide Area Network (WAN), and / or a public network, such as the Internet) through a network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the computer device 12 through a bus 18. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in conjunction with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0128] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the multi-channel processing method mentioned in the foregoing embodiments.

[0129] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the application disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0130] It should be understood that the present disclosure is not limited to the exact structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

[0131] It should be noted that in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0132] Any process or method description in the flowchart or described in other ways herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. And the scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the technical field to which the embodiments of the present disclosure belong.

[0133] It should be understood that each part of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0134] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods in the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0135] In addition, each functional unit in the various embodiments of the present disclosure can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into a module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, etc.

[0136] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0137] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A multi-channel processing method, characterized in that, including: determining the fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core; fetching instructions for each of the channels according to the fetch order; performing corresponding operations based on the instructions fetched by each of the channels.

2. The method according to claim 1, wherein The fetching instructions for each of the channels according to the fetch order includes: fetching instructions for each of the channels from a static random access memory (SRAM) according to the fetch order.

3. The method according to claim 1, wherein The determining the fetch order of at least one channel to be fetched includes: responding to receiving a sensor data processing task, determining the processor core to be selected; allocating a fetch order for at least one channel corresponding to the processor core by using a round-robin scheduling method.

4. The method according to claim 1, wherein The performing corresponding operations based on the instructions fetched by each of the channels includes: decoding the instructions fetched by each of the channels according to a preset instruction format to obtain control signals; performing corresponding task operations based on the control signals.

5. The method according to claim 4, wherein After the performing corresponding task operations based on the control signals, it further includes: judging whether a data write-back operation needs to be performed according to the instruction format; if a data write-back operation needs to be performed, causing the at least one channel to perform the data write-back operation based on a write-back order.

6. The method according to claim 5, wherein Before the causing the at least one channel to perform the data write-back operation based on the write-back order, it further includes: allocating the write-back order for the at least one channel by using a round-robin scheduling method.

7. A multi-channel processing device, characterized in that, including: a determining module, configured to determine the fetch order of at least one channel to be fetched, where the at least one channel corresponds to the same processor core; a fetching module, configured to fetch instructions for each of the channels according to the fetch order; an executing module, configured to perform corresponding operations based on the instructions fetched by each of the channels.

8. The device according to claim 7, characterized in that, The fetching module is specifically configured to: fetch instructions for each of the channels from a static random access memory (SRAM) according to the fetch order.

9. An electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; where the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1-6.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-6.

11. A chip, characterized in that, including a processor and an interface; the processor is configured to read instructions to execute the method according to any one of claims 1-6.

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