Electronic device, link recovery method, medium and product

Abstract

The present application discloses an electronic device, a link recovery method, a medium and a product. The electronic device includes a controller, a phase-locked loop component, a media access control layer component and an interface component; the controller is connected to the phase-locked loop component and the media access control layer component respectively, and the media access control layer component is connected to the interface component. The controller is used to obtain the stability state of the phase-locked loop component, and according to the stability state, determine the target link recovery mode from the first link recovery mode and the second link recovery mode, and execute the target link recovery mode to recover the link between the electronic device and the opposite device. Among them, the first link recovery mode is to adjust the queue depth of the buffer in the interface component through the media access control layer component; the second link recovery mode is to control the media access control layer component to perform link negotiation with the opposite device. Through the above method, the link stability is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to an electronic device, a link recovery method, a medium, and a product. Background Art

[0002] Electronic devices can connect to a peer device (another electronic device) via a high-speed serial bus standard called Peripheral Component Interconnect Express (PCIe). In electronic devices, phase-locked loop components provide a clock signal, which allows the device to transmit and receive data based on the clock signal.

[0003] However, when the phase-locked loop (PLL) is subject to external interference, the output clock signal may become unstable. In the case of an unstable clock signal, data transmission and reception may be abnormal, resulting in poor stability of the PCIe link between the electronic device and the peer device. Summary of the Invention

[0004] The present application provides an electronic device, a link recovery method, a medium, and a product to at least solve the problem of low link stability in the related art.

[0005] The present application provides an electronic device, comprising a controller, a phase-locked loop component, a media access control layer component, and an interface component; the controller is connected to the phase-locked loop component and the media access control layer component, respectively, and the media access control layer component is connected to the interface component;

[0006] a controller for obtaining a stability state of a phase-locked loop component;

[0007] The controller is further configured to determine a target link recovery mode from a first link recovery mode and a second link recovery mode according to the stability state; the first link recovery mode is to adjust a queue depth of a buffer in the interface component through a media access control layer component; and the second link recovery mode is to control the media access control layer component to perform link negotiation with a peer device.

[0008] The controller is further configured to execute a target link recovery method to recover the link between the electronic device and the opposite device.

[0009] This application also provides a link recovery method, including:

[0010] obtaining a stability state of a phase-locked loop component through a controller;

[0011] Determining, by the controller, a target link recovery mode from a first link recovery mode and a second link recovery mode according to the stability state; the first link recovery mode is to adjust a queue depth of a buffer in an interface component through a media access control layer component; and the second link recovery mode is to control the media access control layer component to perform link negotiation with a peer device;

[0012] The target link recovery mode is executed by the controller to recover the link between the electronic device and the opposite end device.

[0013] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the link recovery method as described above are implemented.

[0014] The present application also provides a computer program product, including a computer program, which implements the steps of the aforementioned link recovery method when executed by a processor.

[0015] Through the present application, a controller in an electronic device can determine a target link recovery mode from a first link recovery mode (adjusting the queue depth of a buffer in an interface component through a media access control layer component) and a second link recovery mode (controlling the media access control layer component to perform link negotiation with a peer device) based on the stability state of a phase-locked loop component, and then execute the target link recovery mode, thereby recovering the link between the electronic device and the peer device and improving link stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 1 ;

[0018] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 2 ;

[0019] Figure 3 A schematic diagram of a link recovery method provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 3 ;

[0021] Figure 5 A flowchart of a link recovery method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0024] Electronic devices can connect to a peer device (another electronic device) via a high-speed serial bus standard called Peripheral Component Interconnect Express (PCIe). In electronic devices, phase-locked loop components provide a clock signal, which allows the device to transmit and receive data based on the clock signal.

[0025] However, when the phase-locked loop (PLL) is subject to external interference, the output clock signal may become unstable. In the case of an unstable clock signal, data transmission and reception may be abnormal, resulting in poor stability of the PCIe link between the electronic device and the peer device.

[0026] Therefore, in response to the above-mentioned technical problems in the related art, it was discovered during research that if a controller in an electronic device can determine a target link recovery mode from a first link recovery mode and a second link recovery mode based on the stability state of a phase-locked loop component, and then execute the target link recovery mode, the link between the electronic device and the peer device can be restored. Therefore, the present application proposes an electronic device, a link recovery method, a medium, and a product. Specifically, the electronic device may include a controller, a phase-locked loop component, a media access control layer component, and an interface component; the controller is connected to the phase-locked loop component and the media access control layer component, respectively, and the media access control layer component is connected to the interface component. The controller is configured to obtain the stability state of the phase-locked loop component and, based on the stability state, determine a target link recovery mode from a first link recovery mode and a second link recovery mode, and then execute the target link recovery mode to restore the link between the electronic device and the peer device. The first link recovery mode is to adjust the queue depth of the buffer in the interface component via the media access control layer component; the second link recovery mode is to control the media access control layer component to perform link negotiation with the peer device.

[0027] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0028] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 1 .

[0029] like Figure 1 As shown, the electronic device 10 includes a controller 101, a phase-locked loop component 102, a media access control layer component 103, and an interface component 104. In addition, the electronic device 10 may further include a physical layer component 105.

[0030] The controller 101 is connected to the phase-locked loop component 102 and the media access control layer component 103 respectively.

[0031] The media access control layer component 103 is connected to the interface component 104 .

[0032] In addition, when the electronic device 10 includes the physical layer component 105 , the physical layer component 105 is connected to the interface component 104 .

[0033] It should be noted that the electronic device 10 may be a solid-state drive or other PCIe device, and this embodiment of the present application is not limited thereto.

[0034] The controller 101 is configured to obtain a stability state of the phase-locked loop component 102 .

[0035] The stability state is a normal state or an abnormal state.

[0036] It should be noted that the abnormal state is any one of the following: an overspeed margin state (also referred to as a PLL_FAST_INFO state), an underspeed margin state (also referred to as a PLL_SLOW_INFO state), an overspeed error state (also referred to as a PLL_FAST_ERR state), and an underspeed error state (also referred to as a PLL_SLOW_ERR state).

[0037] Next, the process of the controller 101 acquiring the stability state of the phase-locked loop component 102 will be described.

[0038] In one implementation:

[0039] The controller 101 is configured to obtain the clock signal frequency of the phase-locked loop component 102. For example, the clock signal frequency may be 100 MHz.

[0040] The controller 101 is configured to determine the stability state of the phase-locked loop component 102 according to the frequency of the clock signal.

[0041] In one implementation, the controller 101 is configured to determine the stability state of the phase-locked loop component 102 according to the clock signal frequency and the frequency range corresponding to each stability state.

[0042] It should be noted that the frequency range corresponding to the normal state is the first frequency range, the frequency range corresponding to the overspeed margin state is the second frequency range, the frequency range corresponding to the underspeed margin state is the third frequency range, the frequency range corresponding to the overspeed error state is the fourth frequency range, and the frequency range corresponding to the underspeed error state is the fifth frequency range.

[0043] It should also be noted that the fifth frequency range is smaller than the third frequency range, the third frequency range is smaller than the first frequency range, the first frequency range is smaller than the second frequency range, and the second frequency range is smaller than the fourth frequency range.

[0044] The controller 101 is further configured to determine a target link recovery mode from the first link recovery mode and the second link recovery mode according to the stability state.

[0045] It should be noted that the first link recovery method is to adjust the queue depth of the buffer in the interface component 104 through the media access control layer component 103 .

[0046] It should also be noted that the buffer includes a receiving buffer (also called a receiving end data buffer) and a sending buffer (also called a sending end data buffer). Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 2 .like Figure 2 As shown, the interface component 104 includes a receiving buffer 1041 and a sending buffer 1042. In addition, the interface component 104 may further include a first register 1043, a decoder 1044, a second register 1045 and an encoder 1046.

[0047] The second link recovery mode is to control the media access control layer component 103 to perform link negotiation with the opposite end device.

[0048] Next, a process in which the controller 101 determines a target link recovery mode from the first link recovery mode and the second link recovery mode according to the stability state is described.

[0049] In one implementation:

[0050] The controller 101 is configured to determine an abnormality level based on the stability state. In one implementation, the controller 101 may determine whether the stability state is abnormal. If the stability state is abnormal, the controller 101 may determine the abnormality level based on the stability state. Furthermore, it should be noted that the controller 101 may continue to monitor the stability state of the phase-locked loop component 102 even if the stability state is not abnormal.

[0051] The abnormality level is a first abnormality level (also referred to as a low abnormality level or a low error abnormality level) or a second abnormality level (also referred to as a high abnormality level or a high error abnormality level).

[0052] It should be noted that when the stability state is an overspeed margin state or an underspeed margin state, the abnormality level is the first abnormality level; when the stability state is an overspeed error state or an underspeed error state, the abnormality level is the second abnormality level.

[0053] The controller 101 may determine that the target link recovery mode is the first link recovery mode based on the abnormality level being the first abnormality level.

[0054] In one implementation, the controller 101 may determine that the link recovery mode is a first sub-link recovery mode in the first link recovery mode based on the abnormality level being the first abnormality level and the stability state being the overspeed margin state, wherein the first sub-link recovery mode is to reduce the queue depth of the buffer.

[0055] In one implementation, the controller 101 may determine that the link recovery mode is the second sub-link recovery mode in the first link recovery mode based on the abnormality level being the first abnormality level and the stability state being the underspeed margin state, wherein the second sub-link recovery mode is to increase the queue depth of the buffer.

[0056] The controller 101 may determine that the target link recovery mode is the second link recovery mode based on the abnormality level being the second abnormality level.

[0057] The controller 101 is further configured to execute a target link recovery mode to recover the link between the electronic device 10 and the opposite device.

[0058] Beneficial effects of this embodiment: In this embodiment, the electronic device may include a controller, a phase-locked loop component, a media access control layer component, and an interface component; the controller is connected to the phase-locked loop component and the media access control layer component, respectively, and the media access control layer component is connected to the interface component. The controller is configured to obtain the stability status of the phase-locked loop component and, based on the stability status, determine a target link recovery method from a first link recovery method (adjusting the queue depth of the buffer in the interface component via the media access control layer component) and a second link recovery method (controlling the media access control layer component to perform link negotiation with the peer device), and execute the target link recovery method to restore the link between the electronic device and the peer device. Through the above-described method, the link can be restored in a timely manner to improve link stability, thereby resolving the problem of poor stability of the PCIe link between the electronic device and the peer device in the related art.

[0059] Next, a description will be given of a process in which the controller 101 executes the target link recovery mode to recover the link between the electronic device 10 and the opposite device when the target link recovery mode is the first link recovery mode.

[0060] In one implementation:

[0061] The controller 101 is configured to send a queue depth adjustment instruction to the interface component 104 through the media access control layer component 103 when the target link recovery mode is the first link recovery mode.

[0062] In one implementation, the first link recovery mode includes a first sub-link recovery mode and a second sub-link recovery mode.

[0063] The first sub-link recovery mode is to reduce the queue depth of the buffer, and the second sub-link recovery mode is to increase the queue depth of the buffer.

[0064] In one implementation, when the target link recovery mode is the first sub-link recovery mode, the controller 101 sends a first queue depth adjustment instruction to the interface component 104 via the media access control layer component 103. The first queue adjustment instruction is an instruction to reduce the queue depth of the buffer.

[0065] In one implementation, when the target link recovery mode is the second sub-link recovery mode, the controller 101 sends a second queue depth adjustment instruction to the interface component 104 via the media access control layer component 103. The second queue adjustment instruction is an instruction to increase the queue depth of the buffer.

[0066] The interface component 104 is configured to adjust the value of the queue depth register corresponding to the buffer based on the queue depth adjustment instruction, so as to adjust the queue depth of the buffer.

[0067] In one implementation, the interface component 104 may adjust the value of the queue depth register corresponding to the buffer based on the first queue depth adjustment instruction. For example, the interface component 104 may adjust the value of the queue depth register from indicating a queue depth of 100 to a queue depth of 50 based on the first queue depth adjustment instruction.

[0068] In one implementation, the interface component 104 may adjust the value of the queue depth register corresponding to the buffer based on the second queue depth adjustment instruction. For example, the interface component 104 may adjust the value of the queue depth register from indicating a queue depth of 100 to a queue depth of 150 based on the second queue depth adjustment instruction.

[0069] Beneficial effects of this embodiment: In this embodiment, when the target link recovery mode is the first link recovery mode, the controller can send a queue depth adjustment instruction to the interface component via the media access control layer component. The interface component, based on the queue depth adjustment instruction, adjusts the value of the queue depth register corresponding to the buffer to adjust the queue depth of the buffer. By increasing the queue depth of the buffer when the stability state is an underspeed margin state, the buffer capacity can be expanded to accommodate clock delay deviation, avoiding link interruptions or invalid retransmissions caused by buffer emptying. In other words, this can prevent buffer emptying (underflow) failures in the interface component due to instability in the phase-locked loop component. By decreasing the queue depth of the buffer when the stability state is an overspeed margin state, this can prevent buffer overflow failures. In other words, by adjusting the queue depth of the buffer, the buffer's ability to withstand underspeed disturbances is improved, the transmit buffer's ability to withstand overspeed congestion is improved, the buffer failure rate is reduced, and link stability is improved.

[0070] Next, a description will be given of a process in which the controller 101 executes the target link recovery mode to recover the link between the electronic device 10 and the opposite device when the target link recovery mode is the second link recovery mode.

[0071] In one implementation:

[0072] Figure 3 A schematic diagram of a link recovery method provided in an embodiment of the present application. Figure 3 As shown, the scenario includes an electronic device 10 and a peer device 20. It should be noted that the peer device 20 may be a central processing unit, a baseboard management controller, or other PCIe devices, and the present embodiment is not limited thereto.

[0073] The electronic device 10 includes a controller 101 , a phase-locked loop component 102 , a media access control layer component 103 , an interface component 104 , and a physical layer component 105 .

[0074] The controller 101 is connected to the phase-locked loop component 102 and the media access control layer component 103. The media access control layer component 103 is connected to the interface component 104. The physical layer component 105 is connected to the interface component 104.

[0075] The peer device 20 includes a peer media access control layer component 201, a peer interface component 202, and a peer physical layer component 203. In addition, the peer device 20 may further include a peer controller 204 and a peer phase-locked loop component 205.

[0076] The opposite-end MAC layer component 201 is connected to the opposite-end interface component 202. The opposite-end physical layer component 203 is connected to the opposite-end interface component 202. In addition, the opposite-end controller 204 can also be connected to the opposite-end PLL component 205 and the opposite-end MAC layer component 201 respectively.

[0077] In addition, it should be noted that the physical layer component 105 can be communicatively connected with the opposite end physical layer component 203 .

[0078] The controller 101 is configured to control the MAC layer component 103 to enter a recovery state (recovery state) from a working state when the target link recovery mode is the second link recovery mode, and to control the MAC layer component 103 to generate a control instruction.

[0079] In one implementation, Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 3 .like Figure 4As shown, the MAC layer component 103 includes a state management component (also known as a Link Training and Status State Machine (LTSSM) management component) 1031, a message enhancement component (also known as an enhanced synchronous transmission component) 1032, and a control instruction generation component (also known as an Electric Idle Exit Ordered Set (EIEOS) component) 1033. State management component 1031 is configured to switch the MAC layer component 103 from a working state to a recovery state in response to control by controller 101; control instruction generation component 1033 is configured to generate control instructions in response to control by controller 101.

[0080] The physical layer component 105 is used to obtain the control instruction sent by the media access control layer component 103 through the interface component 104.

[0081] The physical layer component 105 is further configured to generate a target level signal (EIEOS level signal) according to the recovery state control instruction.

[0082] The physical layer component 105 is further configured to send a target level signal to the peer physical layer component 203 of the peer device 20, so that the peer physical layer component 203 obtains a recovery state control instruction based on the target level signal and sends the recovery state control instruction to the peer media access control layer component 201 via the peer interface component 202. The recovery state control instruction is used to enable the peer media access control layer component 201 to enter a recovery state from a working state.

[0083] The MAC layer component 103 is further configured to, when the MAC layer component 103 is in the recovery state, generate multiple target messages based on the message quantity information, and send the multiple target messages to the peer MAC layer component 201 of the peer device 20 via the interface component 104 and the physical layer component 105. It can be understood that the MAC layer component 103 sends the multiple target messages to the peer MAC layer component 201 via the interface component 104, the physical layer component 105, the peer physical layer component 203, and the peer interface component 202.

[0084] It should be noted that if Figure 4 As shown, the message enhancement component 1032 is used to generate multiple target messages based on the message quantity information.

[0085] The target message is used for the opposite-end MAC layer component 201 in the recovery state to perform link negotiation with the MAC layer component 103 in the recovery state, so as to recover the link between the electronic device 10 and the opposite-end device 20 .

[0086] It should be noted that the message quantity information includes the initial message quantity and the message quantity increase method.

[0087] It should be noted that, in one implementation, the message increasing method is to increase the initial message quantity according to a preset multiple.

[0088] In one implementation, the message increasing method is to increase the initial message quantity according to a preset increase quantity.

[0089] Next, the process of the MAC layer component 103 sending multiple target messages to the peer MAC layer component 201 of the peer device 20 through the interface component 104 and the physical layer component 105 based on the message quantity information will be described.

[0090] In one implementation:

[0091] The target message may include a first target message and a second target message.

[0092] Based on the message quantity information, the MAC layer component 103 sends multiple first target messages to the peer MAC layer component 201 via the interface component 104 and the physical layer component 105, the peer physical layer component 203, and the peer interface component 202. The number of first target messages is determined by the MAC layer component 103 based on the message quantity information. It should be noted that the first target message includes a first supported rate and first indication information. The first supported rate is the maximum rate supported by the electronic device 10, and the second indication information is used to indicate to the electronic device 10 that a rate switch is required.

[0093] In response to receiving the first target message, the peer media access control layer component 201 sends multiple first peer messages to the media access control layer component 103 via the peer interface component 202, the peer physical layer component 203, the physical layer component 105, and the interface component 104. The number of first peer messages is determined by the peer media access control layer component 201 based on the number of initial messages. Furthermore, the first peer messages include a second supported rate and first indication information. The second supported rate is the maximum rate supported by the peer device 20, and the second indication information is used to indicate to the peer device 20 that a rate switch is required.

[0094] In response to receiving the first peer message, the media access control layer component 103 determines a first target negotiated rate based on the second supported rate in the first peer message and the first supported rate (the maximum rate supported by the electronic device 10), and generates a second target message based on the first target negotiated rate. It should be noted that the second target message includes the first target negotiated rate and third indication information. The third indication information is used to instruct the electronic device 10 to stop switching rates.

[0095] Based on the message quantity information, the MAC layer component 103 sends multiple second target messages to the opposite MAC layer component 201 via the interface component 104, the physical layer component 105, the opposite physical layer component 203, and the opposite interface component 202. The number of the second target messages is determined by the MAC layer component 103 based on the message quantity information.

[0096] In response to receiving the second target message, the peer media access control layer component 201 sends a second peer message to the media access control layer component 103 via the peer interface component 202, the peer physical layer component 203, the physical layer component 105, and the interface component 104. The number of second peer messages is determined by the peer media access control layer component 201 based on the number of initial messages. Furthermore, the second peer message includes a second target negotiated rate and fourth indication information. The second target negotiated rate is determined by the peer media access control layer component 201 based on the second supported rate and the first supported rate. The fourth indication information is used to instruct the peer device 20 to stop switching the rate.

[0097] In addition, when the opposite MAC layer component 201 recognizes that the second target negotiated rate is consistent with the first target negotiated rate in the second target message, it controls the opposite MAC layer component 201 to switch from the recovery state to the normal state.

[0098] When the MAC layer component 103 recognizes that the first target negotiated rate is consistent with the second target negotiated rate in the second peer message, the MAC layer component 103 controls the MAC layer component 103 to switch from the recovery state to the normal state.

[0099] Beneficial effects of this embodiment: In this embodiment, when the target link recovery mode is the second link recovery mode, the controller can control the media access control layer component to enter a recovery state from a working state, and control the media access control layer component to generate a control instruction. The physical layer component can obtain the control instruction sent by the media access control layer component through the interface component and generate a target level signal based on the control instruction. The physical layer component can also send the target level signal to the opposite physical layer component of the opposite device, so that the opposite physical layer component obtains a recovery state control instruction based on the target level signal and sends the recovery state control instruction to the opposite media access control layer component through the opposite interface component. The recovery state control instruction is used to cause the opposite media access control layer component to enter a recovery state from a working state. When the media access control layer component is in the recovery state, the media access control layer component can send multiple target messages to the opposite media access control layer component of the opposite device through the interface component and the physical layer component based on message quantity information. The target messages are used for the opposite media access control layer component to perform link negotiation to restore the link between the electronic device and the opposite device. The message quantity information includes an initial message quantity and a message quantity increase method. Through the above method, when determining to use the second link recovery method for link recovery based on the stability state of the phase-locked loop component, on the one hand, by increasing the number of target messages (first target messages and second target messages) based on the message increase method, the probability of the opposite device receiving the target message is increased, thereby improving the effect and success rate of the link negotiation between the electronic device and the opposite device; on the other hand, by re-negotiating the link, the link stability can be improved.

[0100] Figure 5 A flowchart of a link recovery method provided in an embodiment of the present application is provided in Figure 5 , the method specifically comprises the following steps:

[0101] S501: Obtaining a stability state of a phase-locked loop component through a controller.

[0102] In this embodiment, the electronic device includes a controller, a phase-locked loop component, a media access control layer component, an interface component, and a physical layer component. The controller is connected to the phase-locked loop component and the media access control layer component, the media access control layer component is connected to the interface component, and the interface component is connected to the physical layer component.

[0103] The electronic device can obtain the stability status of the phase-locked loop component through the controller.

[0104] In one implementation:

[0105] The electronic device can obtain the clock signal frequency of the phase-locked loop component through the controller.

[0106] The electronic device can determine the stability state of the phase-locked loop component based on the clock signal frequency through the controller.

[0107] S502: Determine, by the controller, a target link recovery mode from the first link recovery mode and the second link recovery mode according to the stability state.

[0108] In this embodiment, the electronic device may determine the target link recovery mode from the first link recovery mode and the second link recovery mode according to the stability state through the controller.

[0109] The first link recovery method is to adjust the queue depth of the buffer in the interface component through the media access control layer component.

[0110] The second link recovery mode is to control the media access control layer component to perform link negotiation with the opposite end device.

[0111] In one implementation:

[0112] The electronic device can determine the abnormality level based on the stability state through the controller.

[0113] Among them, when the stability state is an overspeed margin state or an underspeed margin state, the abnormality level is a first abnormality level; when the stability state is an overspeed error state or an underspeed error state, the abnormality level is a second abnormality level.

[0114] The electronic device may determine, through the controller, that the target link recovery mode is the first link recovery mode based on the abnormality level being the first abnormality level.

[0115] In one implementation, the electronic device, through the controller, may determine that the link recovery mode is the first sub-link recovery mode within the first link recovery mode based on the abnormality level being the first abnormality level and the stability state being the overspeed margin state. Alternatively, the electronic device, through the controller, may determine that the link recovery mode is the second sub-link recovery mode within the first link recovery mode based on the abnormality level being the first abnormality level and the stability state being the underspeed margin state.

[0116] It should be noted that the first sub-link recovery method is to reduce the queue depth of the buffer, and the second sub-link recovery method is to increase the queue depth of the buffer.

[0117] In addition, the electronic device may determine, through the controller, that the target link recovery mode is the second link recovery mode based on the abnormality level being the second abnormality level.

[0118] S503: Execute the target link recovery mode through the controller to recover the link between the electronic device and the opposite device.

[0119] In this embodiment, the electronic device may execute a target link recovery mode through the controller to recover the link between the electronic device and the opposite device.

[0120] In one implementation:

[0121] The electronic device, through the controller, can send a queue depth adjustment instruction to the interface component through the media access control layer component when the target link recovery mode is the first link recovery mode, so that the interface component adjusts the value of the queue depth register corresponding to the buffer based on the queue depth adjustment instruction to adjust the queue depth of the buffer. The buffer includes a receive buffer and a transmit buffer.

[0122] In one implementation:

[0123] The electronic device can control the media access control layer component to enter the recovery state from the working state through the controller when the target link recovery mode is the second link recovery mode, and control the media access control layer component to generate a control instruction.

[0124] In addition, the electronic device can obtain the control instruction sent by the media access control layer component through the physical layer component through the interface component, and generate a target level signal according to the control instruction.

[0125] An electronic device can send a target level signal to a peer physical layer component of a peer device through a physical layer component, so that the peer physical layer component obtains a recovery state control instruction based on the target level signal, and sends the recovery state control instruction to the peer media access control layer component through the peer interface component; the recovery state control instruction is used to enable the peer media access control layer component to enter a recovery state from a working state.

[0126] An electronic device can generate multiple target messages based on message quantity information through a media access control layer component when the media access control layer component is in a recovery state, and send the multiple target messages to the opposite media access control layer component of the opposite device through the interface component and the physical layer component; the target messages are used for the opposite media access control layer component in the recovery state to perform link negotiation with the media access control layer component in the recovery state to restore the link between the electronic device and the opposite device; wherein the message quantity information includes the initial message quantity and the message quantity increase method.

[0127] Beneficial effects of this embodiment: In this embodiment, the electronic device, through a controller, can obtain the stability status of the phase-locked loop component. Based on the stability status, the electronic device determines a target link recovery method from a first link recovery method (adjusting the queue depth of the buffer in the interface component via the media access control layer component) and a second link recovery method (controlling the media access control layer component to perform link negotiation with the peer device). The target link recovery method is then executed to restore the link between the electronic device and the peer device. This method enables timely link recovery, resolving the issue of poor link stability between the electronic device and the peer device in related technologies.

[0128] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above-mentioned link recovery method embodiments when running.

[0129] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0130] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned link recovery method embodiments are implemented.

[0131] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned link recovery method embodiments are implemented.

[0132] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0133] The above is an electronic device, link recovery method, medium and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. An electronic device, characterized in that: It includes a controller, a phase-locked loop component, a media access control layer component and an interface component; the controller is connected to the phase-locked loop component and the media access control layer component respectively, and the media access control layer component is connected to the interface component; The controller is configured to obtain a stability state of the phase-locked loop component; The controller is further configured to determine, based on the stability state being an overspeed margin state or an underspeed margin state, that the abnormality level is a first abnormality level, and, based on the abnormality level being the first abnormality level, determine that a target link recovery mode is a first link recovery mode; wherein, when the abnormality level is the first abnormality level and the stability state is the overspeed margin state, the first link recovery mode is to reduce a queue depth of a buffer in the interface component via the media access control layer component; and when the abnormality level is the first abnormality level and the stability state is the underspeed margin state, the first link recovery mode is to increase a queue depth of the buffer via the media access control layer component; The controller is further configured to determine, based on the stability state being an overspeed error state or an underspeed error state, that the abnormality level is a second abnormality level, and based on the abnormality level being the second abnormality level, determine that the target link recovery mode is a second link recovery mode; the second link recovery mode is to control the media access control layer component to perform link negotiation with the peer device; The controller is further configured to execute the target link recovery mode to recover the link between the electronic device and the opposite device.

2. The electronic device according to claim 1, wherein The controller, when executing the target link recovery mode to recover the link between the electronic device and the peer device, is specifically configured to: When the target link recovery mode is the first link recovery mode, sending a queue depth adjustment instruction to the interface component through the media access control layer component; The interface component is used to adjust the value of the queue depth register corresponding to the buffer zone based on the queue depth adjustment instruction, so as to adjust the queue depth of the buffer zone.

3. The electronic device according to claim 2, wherein: The buffer zone includes a receiving buffer zone and a sending buffer zone.

4. The electronic device according to claim 1, wherein: The electronic device further includes a physical layer component connected to the interface component; the controller, when executing the target link recovery mode to recover the link between the electronic device and the peer device, is specifically configured to: When the target link recovery mode is the second link recovery mode, controlling the media access control layer component to enter a recovery state from a working state, and controlling the media access control layer component to generate a control instruction; The physical layer component is configured to obtain the control instruction sent by the media access control layer component through the interface component, and generate a target level signal according to the control instruction; The physical layer component is further configured to send the target level signal to the opposite physical layer component of the opposite device, so that the opposite physical layer component obtains a recovery state control instruction based on the target level signal, and sends the recovery state control instruction to the opposite media access control layer component via the opposite interface component; the recovery state control instruction is used to enable the opposite media access control layer component to enter a recovery state from a working state; The media access control layer component is further configured to, when the media access control layer component is in the recovery state, generate multiple target messages based on message quantity information, and send the multiple target messages to the opposite media access control layer component of the opposite device through the interface component and the physical layer component; the target messages are used for the opposite media access control layer component in the recovery state to perform link negotiation with the media access control layer component in the recovery state; wherein the message quantity information includes an initial message quantity and a message quantity increase method.

5. The electronic device according to claim 1, wherein The controller, when acquiring the stability state of the phase-locked loop component, is specifically configured to: Obtaining a clock signal frequency of the phase-locked loop component; Based on the clock signal frequency, a stability state of the phase-locked loop component is determined.

6. A link recovery method, characterized in that: include: obtaining a stability state of a phase-locked loop component through a controller; The controller determines, based on whether the stability state is an overspeed margin state or an underspeed margin state, that the abnormality level is a first abnormality level, and determines, based on the abnormality level being the first abnormality level, that the target link recovery mode is a first link recovery mode; wherein, when the abnormality level is the first abnormality level and the stability state is the overspeed margin state, the first link recovery mode is to reduce the queue depth of the buffer in the interface component through the media access control layer component; and when the abnormality level is the first abnormality level and the stability state is the underspeed margin state, the first link recovery mode is to increase the queue depth of the buffer through the media access control layer component; The controller determines, based on the stability state being an overspeed error state or an underspeed error state, that the abnormality level is a second abnormality level, and determines, based on the abnormality level being the second abnormality level, that the target link recovery mode is a second link recovery mode; the second link recovery mode is to control the media access control layer component to perform link negotiation with the peer device; The target link recovery mode is executed by the controller to recover the link between the electronic device and the opposite device.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the link recovery method according to claim 6 when executed by a processor.

8. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the link recovery method according to claim 6 are implemented.

Images