Soft error injection method and FPGA chip

Abstract

The invention discloses a soft error injection method and an FPGA chip, the method is applied to a soft core IP of the FPGA chip, an injection interface of a soft error correction SEC hard core in the FPGA chip is packaged in the soft core IP, and the method comprises the following steps: receiving a setting signal from a user to obtain setting information; generating soft error injection information according to the setting information; and sending the soft error injection information to the SEC hardcore through the injection interface, so that the SEC hardcore injects the soft error according to the soft error injection information. The method does not depend on a JTAG interface during soft error injection, occupied FPGA resources are small, and the injection efficiency is high.

Description

Technical Field

[0001] The present invention belongs to the field of integration technology, and particularly relates to a soft error injection method and an FPGA chip. Background Art

[0002] With the continuous expansion of the scale of Field-Programmable Gate Arrays (FPGAs), the number and density of internal Static Random-Access Memories (SRAMs) increase accordingly. Due to reasons such as electromagnetic radiation and external environmental interference, the probability that the internal memory makes errors and changes the programming logic behavior of the system also increases. However, these errors usually do not permanently damage the FPGA device and are called soft errors. To reduce the impact of soft errors on the FPGA system function, functions of soft error injection, detection (Soft Error Detect, SED), and correction (Soft Error Correct, SEC) are usually integrated in larger-scale FPGAs, which can detect and correct 1-bit data errors and detect consecutive multi-bit data errors.

[0003] During the FPGA development process, soft error injection can be used to simulate hardware failures caused by external radiation. It can not only test and verify the soft error detection and correction functions, but also evaluate and optimize the fault tolerance, reliability, security, and performance of the FPGA system to meet fields with extremely strict industry standards, such as automotive electronics and medical devices. By deliberately injecting different soft errors into the FPGA system to simulate different types and degrees of circuit failures, designers can not only evaluate the performance of the system in the face of various abnormal situations, thereby discovering and solving potential design defects in the system, finding the most suitable fault tolerance scheme for a specific application scenario, and improving the fault tolerance of the system to ensure the stability and robustness of the design; but also evaluate the impact of various soft errors on the FPGA performance, and find the best performance configuration and parameter settings through simulation optimization strategies, thereby improving the overall performance and power consumption efficiency of the FPGA.

[0004] Current popular soft error injection methods have designed independent soft error injection IP cores, EMR (ErrorMessage Register) Unloader IP cores, ASD IP cores, and soft error injection debugger software interfaces to meet the requirements of evaluating and optimizing the fault tolerance, reliability, security, and performance of FPGA systems in high-standard industries. Although users can inject 1-bit or multi-bit soft errors in a specified area according to their needs and compare the single-bit error positions with the sensitivity map to meet the extremely strict requirements of the industry standards. However, when comprehensively implementing functions such as soft error injection, detection, correction, and evaluating the fault tolerance and reliability of FPGA systems, the following drawbacks still exist: (1) In addition to instantiating the above three IP cores in the design, users also need to instantiate the IP cores for soft error detection and correction, which occupies a large amount of internal resources of the FPGA, thus reducing the resource space required for the actual system design. Moreover, the complex interfaces increase the difficulty of use for users; (2) The final soft error injection can only be performed through the software interface using the Joint Test Action Group (JTAG) interface. The JTAG interface can only inject soft errors at one position at a time. If multiple positions need to be injected with soft errors, repeated operations still need to rely on JTAG, resulting in low efficiency.

[0005] Therefore, the current soft error injection method occupies more internal resources of the FPGA and has low efficiency during execution. Summary of the Invention

[0006] Embodiments of the present invention provide a soft error injection method and system, which can solve the problems that the current soft error injection method occupies more internal resources of the FPGA and has low efficiency during execution.

[0007] In a first aspect, embodiments of the present invention provide a soft error injection method, which is applied to a soft core IP of an FPGA chip, and the injection interface of the soft error correction SEC hard core in the FPGA chip is encapsulated in the soft core IP. The method includes: Receiving a setting signal from a user to obtain setting information; Generating soft error injection information according to the setting information; Sending the soft error injection information to the SEC hard core through the injection interface, so that the SEC hard core injects soft errors according to the soft error injection information.

[0008] In a second aspect, embodiments of the present invention provide an FPGA chip, including a soft core IP and a soft error correction SEC hard core, and the injection interface of the SEC hard core is encapsulated in the soft core IP; The soft-core IP is used for: receiving a setting signal from a user to obtain setting information; generating soft error injection information according to the setting information; and sending the soft error injection information to the SEC hard-core through the injection interface. The SEC hard-core is used for: injecting a soft error according to the soft error injection information.

[0009] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: In the soft error injection method provided by the present invention, by encapsulating the injection interface of the SEC hard-core in the FPGA chip on the soft-core IP (similar to the scheduler in the traditional method), the soft-core IP can send an enable signal to the SEC hard-core through the injection interface, and the SEC hard-core injects an error at a soft error injection data address when detecting a rising edge of the enable signal. When performing multi-address error injection, the soft-core IP only needs to send multiple enable signals, which can improve the injection efficiency. Moreover, the generation process of the soft error injection address is executed by the soft-core IP, without occupying the resources of the FPGA. The number of injected soft error addresses can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not require external tools such as a JTAG downloader and a software real-time controller for soft error injection, which can greatly improve the injection efficiency. Description of the Drawings

[0010] Figure 1 It is a schematic diagram of a soft error injection scenario provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of a remote soft error injection scenario provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of a generated interface provided by an embodiment of the present invention; Figure 4 It is a schematic diagram of an interface of the SEC hard-core provided by an embodiment of the present invention; Figure 5 It is a flowchart of an implementation of a soft error injection method provided by an embodiment of the present invention; Figure 6 It is a schematic diagram of an FPGA chip provided by an embodiment of the present invention. Detailed Embodiments

[0011] In the following description, specific details such as specific system architectures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0012] It should be understood that, as used in the specification of the present invention and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their combinations.

[0013] It should also be understood that the term "and / or" as used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0014] As used in the specification of the present invention and the appended claims, the term "if" may be construed, depending on the context, as "when", or "once", or "in response to determining", or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, as meaning "once determined", or "in response to determining", or "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".

[0015] In addition, in the description of the specification of the present invention and the appended claims, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0016] Reference to "an embodiment" or "some embodiments" or the like described in the specification of the present invention means that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the present invention. Thus, statements such as "in an embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0017] Traditional soft error injection methods usually implement soft error injection through the JTAG interface. It is necessary to connect to the JTAG pins of the FPGA, send soft error information to the FPGA through the JTAG interface, and at the same time, modify the value of the specified address through the JTAG interface. For example, change 0x00001234 to 0x00001235 to achieve soft error injection.

[0018] Since the JTAG interface can only send one address at a time, if multiple addresses of the chip registers need to be modified, multiple soft error injection information needs to be transmitted, with a lot of repeated operations and low injection efficiency.

[0019] Moreover, when the traditional soft error injection method performs soft error injection based on the JTAG interface, in addition to relying on the software interface, it also requires a soft error injection IP core, an ASD IP core, an Unloader IP core, and a debugger for assistance, which occupies a relatively large amount of FPGA resources.

[0020] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0021] Figure 1 The figure shows a schematic diagram of a soft error injection scenario provided by an embodiment of the present invention.

[0022] As an example, referring to Figure 1 , if it is necessary to perform soft error injection on the data 0x00001234 stored in the form of the binary code: "00000000 00000000 00010010 00110100", the SEC hard core will read this part of the data. When the address to be injected is read, for example, when the address where the last "0" is stored is read, the soft core IP sends an enable signal through the injection interface encapsulated therein, pulling up a rising edge. The SEC hard core detects the rising edge and performs error injection at this address, modifying the "0" to "1" so as to modify the "4" in 0x00001234 to "5".

[0023] Figure 2 The figure shows a schematic diagram of a remote soft error injection scenario provided by an embodiment of the present invention.

[0024] As an example, referring to Figure 2 , relatively large systems are often composed of multiple small systems, and each has its own core control module to achieve nested control. For example, Figure 2 the subsystem control center and the total control center in . These control centers can all be composed of FPGAs. To ensure the reliability of the entire system, the SEC function is usually called in each control center to ensure the stability of the configuration data. For example, a robot has complex controls in multiple aspects such as hands and feet. The working temperatures of parts such as hands and feet are relatively high, or the working environment is harsh, and higher requirements are placed on the system stability. The method of separately performing soft error injection on the hands and feet of the robot to test the fault tolerance and reliability of the small system is not conducive to testing the chain reaction of the entire robot.

[0025] Since the present invention encapsulates the injection interface of the SEC hard core in the soft core IP, and the soft core IP sends soft error injection information to the SEC hard core based on the injection interface, there is no need to connect the debugger to the JTAG pins of the FPGA in a wired manner. Therefore, referring to Figure 3, based on the method provided by the present invention, a user can select a verification mode, error data, soft error injection address, etc. according to requirements on the generation interface of an external remote control center. The remote control center generates soft error injection information based on this configuration information and sends it to the master control center of the robot in the form of an injected error instruction. The highest-level master control center of the robot can send the soft error injection information to the corresponding SEC hard core of the interface through the injection interface encapsulated in the soft core IP, and the SEC hard core inside the subsystem performs soft error injection according to the soft error injection information.

[0026] For example, the user can click Figure 3 on the generation interface, select the verification mode as continuous verification, check the automatic error correction function of the SEC hard core, check the method of enabling error injection through an enable signal, select the Gaussian distribution, a random algorithm, to generate the soft error injection address, and inject errors at 150 addresses at a time.

[0027] Therefore, for the soft error injection method provided by the present invention, by encapsulating the injection interface of the SEC hard core in the FPGA chip on the soft core IP (similar to the scheduler in the traditional method), the soft core IP can send an enable signal to the SEC hard core through the injection interface. The SEC hard core performs error injection at a soft error injection data address when detecting a rising edge of the enable signal. When performing multi-address error injection, the soft core IP only needs to send multiple enable signals, and the data volume of the enable signals is much smaller than the soft error injection information, which can improve the injection efficiency. Moreover, the generation process of the soft error injection address is executed by the soft core IP, without occupying the resources of the FPGA. The injection quantity of the soft error address can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not require external tools such as a JTAG downloader and a software real-time controller to perform soft error injection, which can greatly improve the injection efficiency.

[0028] Figure 4 The figure shows an interface schematic diagram of an SEC hard core provided by an embodiment of the present invention.

[0029] Exemplarily, the SEC hard core is an existing hardware module in the FPGA, and its functions include verification, soft error injection, and correction functions. Its core interfaces can include Figure 4 SEDENABLE, SEDERR, SEDFRCERR, SEDDONE, ECCERR_INJECT_I, SEDINPROG, ECCERR_INJECT_SHF, AUTODONE in

[0030] Exemplarily, the SEDENABLE interface, SEDFRCERR interface, ECCERR_INJECT_I interface, and ECCERR_INJECT_SHF interface are all input interfaces. The SEDENABLE interface is used to start and stop SED verification. When a rising edge of a signal is detected by this interface, SED verification is started, and when a falling edge of the signal is detected, the verification is stopped. The SEDFRCERR interface is an injection interface encapsulated in the soft core IP and is used to receive an enable signal. The ECCERR_INJECT_I interface is the input end of the soft error injection address, and the ECCERR_INJECT_SHF interface is the error address information shift enable interface. After detecting the enable signal, this interface can cause the SEC hard core to perform error injection for the next address.

[0031] Exemplarily, the SEDERR interface, SEDDONE interface, SEDINPROG interface, and AUTODONE interface are all output interfaces. The SEDERR interface is used to output an error flag signal. When this signal is at a high level, it indicates that the SEC hard core has detected an irreparable SED error. The SEDDONE interface is used to output a first working flag signal, which indicates that a round of SED verification has been completed. The SEDINPROG interface is used to output a second working flag signal. When this signal is at a high level, it indicates that verification is in progress. The AUTODONE interface is used to output a third working flag signal. When this signal is at a high level, it indicates that automatic repair is completed or no error is detected, and when it is at a low level, it indicates that automatic repair of an error is in progress.

[0032] Figure 5 The figure shows a flowchart of the implementation of a soft error injection method provided by an embodiment of the present invention. By way of example and not limitation, this method can be applied to the soft core IP of an FPGA chip, and the injection interface of the SEC hard core in the FPGA chip is encapsulated in this soft core IP. This method may include steps S501 - S503, which are described below.

[0033] S501, receive a setting signal from a user to obtain setting information.

[0034] Exemplarily, referring to Figure 3 , the user can click on the corresponding area in the generation interface to send a setting signal to the soft core IP.

[0035] In a possible implementation manner, referring to Figure 3 , the setting information may include: verification mode, number of soft error injections, specified address, or soft error injection address generation algorithm.

[0036] Exemplarily, the user can select a random algorithm as the soft error injection location generation algorithm to generate a soft error injection address, or directly input the specified address of the soft error injection.

[0037] In one example, the soft error injection location generation algorithm may include various random algorithms such as Gaussian distribution, exponential distribution, Beta distribution, and triangular distribution.

[0038] Exemplarily, the distribution of the generated soft error injection addresses is related to the type of the random algorithm. For example, the distribution of the soft error injection addresses generated based on the Gaussian distribution algorithm satisfies the Gaussian distribution.

[0039] Optionally, the soft error injection addresses in the present invention do not include non-functional regions (i.e., mask regions).

[0040] When the traditional technology injects soft errors into non-functional regions, the injection result feedback is always that no soft error is detected regardless of whether the injection is successful. The present invention avoids such regions during soft error injection, which is beneficial to improving the accuracy of the verification result.

[0041] S502, generate soft error injection information according to the setting information.

[0042] Exemplarily, the soft error injection information may include at least one soft error injection address and a soft error injection logic control file. The soft error injection logic control file can control the SEC core to perform soft error injection at the soft error address.

[0043] S503, send the soft error injection information to the SEC core through the injection interface, so that the SEC core injects soft errors according to the soft error injection information.

[0044] In one example, the soft error injection address can be sent to the SEC core from the injection interface in the form of an enable signal. Exemplarily, refer to Figure 1 , the SEC core can read the data at the soft error injection address under the instruction of the soft error injection logic control file. When the SEC core reads the data at the soft error injection address, the enable signal received by the injection interface will have a rising edge. Detecting this rising edge by the injection interface can instruct the SEC core to perform error injection.

[0045] In the present invention, the injection interface of the SEC hardcore in the FPGA chip is encapsulated on the soft-core IP (similar to the scheduler in the traditional method). The soft-core IP can send an enable signal to the SEC hardcore through the injection interface. When the SEC hardcore detects a rising edge of the enable signal, it injects an error at a soft error injection data address. When performing multi-address error injection, the soft-core IP only needs to send multiple enable signals, which can improve the injection efficiency. Moreover, the generation process of the soft error injection address is executed by the soft-core IP, without occupying the resources of the FPGA. The number of injected soft error addresses can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not require external tools such as a JTAG downloader and a software real-time controller for soft error injection, which can greatly improve the injection efficiency.

[0046] Figure 6 The figure shows a schematic diagram of an FPGA chip provided by an embodiment of the present invention.

[0047] In some embodiments, the chip 600 may include a soft-core IP 610 and an SEC hardcore 620.

[0048] Exemplarily, the soft-core IP 610 may be used to receive a setting signal from a user to obtain setting information; generate soft error injection information according to the setting information; and send the soft error injection information to the SEC hardcore 620 through the injection interface. The SEC hardcore 620 may be used to inject a soft error according to the soft error injection information.

[0049] In the present invention, the injection interface of the SEC hardcore in the FPGA chip is encapsulated on the soft-core IP (similar to the scheduler in the traditional method). The soft-core IP can send an enable signal to the SEC hardcore through the injection interface. When the SEC hardcore detects a rising edge of the enable signal, it injects an error at a soft error injection data address. When performing multi-address error injection, the soft-core IP only needs to send multiple enable signals, which can improve the injection efficiency. Moreover, the generation process of the soft error injection address is executed by the soft-core IP, without occupying the resources of the FPGA. The number of injected soft error addresses can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not require external tools such as a JTAG downloader and a software real-time controller for soft error injection, which can greatly improve the injection efficiency.

[0050] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

Claims

1. A soft error injection method, characterized in that, The method is applied to the soft-core IP of an FPGA chip. The injection interface of the soft error correction (SEC) hard core in the FPGA chip is encapsulated in the soft-core IP. The method includes: Receiving a setting signal from a user to obtain setting information; Generating soft error injection information according to the setting information; Sending the soft error injection information to the SEC hard core through the injection interface to cause the SEC hard core to inject a soft error according to the soft error injection information.

2. The method according to claim 1, characterized in that, Before receiving the setting signal from the user to obtain the setting information, the method further includes: Displaying a generation interface of the soft error injection information to the user to cause the user to send the setting signal based on the generation interface.

3. The method according to claim 1, wherein The soft error injection information includes at least one soft error injection address and a soft error injection logic control file, where the soft error injection logic control file is used to control the SEC hard core to inject a soft error at the soft error injection address.

4. The method according to claim 1, characterized in that, The setting information includes: A check mode, a soft error injection quantity, a specified address, or a soft error injection address generation algorithm.

5. The method according to claim 4, wherein The soft error injection address is the specified address or is generated according to the soft error injection address generation algorithm.

6. The method according to claim 5, characterized in that, The soft error injection address generation algorithm includes Gaussian distribution, exponential distribution, Beta distribution, and triangular distribution random algorithms.

7. The method according to claim 3, wherein The soft error injection address does not include the non-functional area of the FPGA chip.

8. The method according to claim 1, wherein The injection interface is an enable signal interface, which is used to receive an enable signal and indicate the SEC hard core to inject a soft error when the rising edge of the enable signal is detected.

9. An FPGA chip, characterized in that, It includes a soft-core IP and a soft error correction (SEC) hard core, and the injection interface of the SEC hard core is encapsulated in the soft-core IP; The soft-core IP is used to: receive a setting signal from a user to obtain setting information; generate soft error injection information according to the setting information; send the soft error injection information to the SEC hard core through the injection interface; The SEC hard core is used to: inject a soft error according to the soft error injection information.

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