MBIST test system based on multiple algorithms

Abstract

The invention relates to the technical field of chip testing, in particular to a multi-algorithm-based MBIST testing system, which is characterized in that in a scene in which a high-order algorithm is adopted and a basic algorithm is needed for basic rapid testing, the same algorithm instructions in the high-order algorithm and the basic algorithm are multiplexed, and only a target algorithm identifier needs to be configured, so that the high-order algorithm and the basic algorithm can be quickly tested; according to the method, the reference instruction identifier can be initialized, and the algorithm instruction to be skipped after the algorithm instruction is executed is determined, so that an instruction sequence of a whole basic algorithm does not need to be additionally added on the basis of an existing high-order algorithm instruction sequence, and a selection function among multiple algorithms does not need to be realized by adding a large number of selectors; therefore, the area overhead of the test circuit is effectively reduced, and the chip production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to a multi-algorithm-based MBIST testing system. Background Art

[0002] Currently, in the application scenarios of integrated circuits, with the increasing demand for on-chip memories, the proportion of on-chip memories is also getting higher and higher. Especially in artificial intelligence chips, the proportion of on-chip memories far exceeds that of other types of chips. Therefore, in order to ensure the normal use of chips, the testing of on-chip memories is indispensable.

[0003] However, the time-consuming of using the functional testing method to test on-chip memories is long and the coverage rate is low. Therefore, the commonly used method in the prior art is to perform structural testing through Memory Built-In Self-Test (MBIST). The built-in self-test circuit usually implements algorithms that can cover most types of on-chip memory faults. The on-chip memory is tested by starting the test switch, waiting for the test process, and finally collecting the test results.

[0004] The high-order algorithms commonly used for on-chip memory testing will contain more test sequences, and each test sequence will cover fixed faults. In scenarios such as system initialization or rapid on-chip testing, in order to reduce the test time, the prior art usually formulates the basic faults into a basic algorithm separately. The basic algorithm does not execute all the test sequences, but only executes the basic fault detection sequences, and the tester selects and uses them from the basic algorithm and the high-order algorithm according to the test scenario.

[0005] However, in the prior art, the basic algorithm and the high-order algorithm are independently implemented in the circuit, and the function of algorithm selection is supported by adding selectors to each bit of the corresponding high-order algorithm instructions and basic algorithm instructions. Since the number of high-order algorithm instructions is large and the bit width of each algorithm instruction is large, a large number of selectors need to be added, which will greatly increase the area overhead of the test circuit, thus resulting in too high chip production costs.

[0006] Therefore, how to reduce the area overhead of the test circuit on the premise of realizing the function of multi-test algorithm selection has become an urgent problem to be solved. Summary of the Invention

[0007] For the above technical problems, the technical solution adopted by the present invention is as follows: A multi-algorithm-based MBIST testing system, the system includes: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: S101, Initialize the reference instruction identifier according to the configured target algorithm identifier.

[0008] S102, Execute the algorithm instruction corresponding to the reference instruction identifier, and obtain the associated instruction identifier corresponding to the algorithm instruction.

[0009] S103, Update the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier, and return to execute step S102 until the associated instruction identifier meets the first preset condition or the reference instruction identifier meets the second preset condition, and complete the execution of the target algorithm corresponding to the target algorithm identifier.

[0010] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, a multi-algorithm-based MBIST test system provided by the present invention can achieve considerable technical progressiveness and practicality, and has wide industrial utilization value. It has at least the following beneficial effects: In the scenario where the present invention adopts a high-order algorithm and requires a basic algorithm for basic rapid testing, the same algorithm instructions in the high-order algorithm and the basic algorithm are reused. Only by configuring the target algorithm identifier, the reference instruction identifier can be initialized, and the algorithm instruction to be jumped to after the execution of the algorithm instruction can be determined. Therefore, it is not necessary to add an additional instruction sequence of the entire basic algorithm on the basis of the existing high-order algorithm instruction sequence, and it is not necessary to add a large number of selectors to implement the selection function between multiple algorithms, thereby effectively reducing the area overhead of the test circuit and reducing the chip production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 It is a schematic flowchart of the computer program executed by the processor in a multi-algorithm-based MBIST test system provided by an embodiment of the present invention; Figure 2 It is a schematic state diagram of the execution of the algorithm instruction in a multi-algorithm-based MBIST test system provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0014] This embodiment provides a multi-algorithm-based MBIST test system. Refer to Figure 1 , which is a schematic flowchart of a computer program executed by a processor in a multi-algorithm-based MBIST test system provided by an embodiment of the present invention. The system includes: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: S101, initialize a reference instruction identifier according to the configured target algorithm identifier; S102, execute the algorithm instruction corresponding to the reference instruction identifier, and obtain the associated instruction identifier corresponding to the algorithm instruction; S103, update the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier, and return to execute step S102 until the associated instruction identifier meets the first preset condition or the reference instruction identifier meets the second preset condition, and complete the execution of the target algorithm corresponding to the target algorithm identifier.

[0015] Among them, the target algorithm identifier can be configured by the implementer to select the algorithm that needs to be tested from the multiple algorithms supported by the MBIST test.

[0016] The reference instruction identifier corresponds to the algorithm instruction one by one. The associated instruction identifier can be used to identify the instruction identifier corresponding to the algorithm instruction that needs to be jumped to after the execution of the corresponding algorithm instruction.

[0017] The first preset condition can be used to determine whether the algorithm instruction corresponding to the associated instruction identifier is an additional expansion instruction. In this embodiment, the additional expansion instruction only belongs to the basic algorithm instruction sequence. Therefore, the first preset condition can be used to determine whether the basic algorithm instruction sequence has been executed completely, and the second preset condition can be used to determine whether the high-order algorithm instruction sequence has been executed completely.

[0018] Since there is an additional instruction at the end of the algorithm sequence for the basic algorithm compared to the high-order algorithm, after the basic algorithm and the high-order algorithm are reused, an additional expansion instruction needs to be added, and this additional expansion instruction only belongs to the basic algorithm instruction sequence.

[0019] In a specific implementation manner, the target algorithm identifier is a basic algorithm identifier or a high-order algorithm identifier; Initializing the reference instruction identifier according to the configured target algorithm identifier includes: When the target algorithm identifier is the basic algorithm identifier, initializing the reference instruction identifier to a first preset value; When the target algorithm identifier is the high-order algorithm identifier, initializing the reference instruction identifier to a second preset value.

[0020] Among them, the multiple algorithms supported in this embodiment may include a basic algorithm and a high-order algorithm. The basic algorithm may adopt the MarchC+ algorithm. The high-order algorithm instruction sequence usually includes all algorithm instructions in the basic algorithm instruction sequence, and also includes algorithm instructions corresponding to the fault coverage test sequence for byte write enable, algorithm instructions corresponding to the fault coverage test sequences for output enable, chip select enable, and read enable, algorithm instructions corresponding to the test sequence for leakage current fault coverage, etc.

[0021] However, the instruction identifiers corresponding to the same algorithm instructions in the high-order algorithm instruction sequence and the basic algorithm instruction sequence are not the same. Therefore, in the prior art, the basic algorithm is usually implemented separately in a circuit.

[0022] When the reference instruction identifier is the first preset value, the reference instruction identifier corresponds to the first algorithm instruction of the basic algorithm.

[0023] When the reference instruction identifier is the second preset value, the reference instruction identifier corresponds to the first algorithm instruction of the high-order algorithm. In this embodiment, the reference instruction identifier of the algorithm instruction corresponding to the high-order algorithm can be from 1 to N, and N can refer to the number of algorithm instructions in the high-order algorithm, then the second preset value can be 1.

[0024] In a specific implementation manner, updating the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier includes: Determining a first intermediate identifier according to the reference instruction identifier; Determining a second intermediate identifier according to the associated instruction identifier; When the target algorithm identifier is the high-order algorithm identifier or the reference instruction identifier does not meet the third preset condition, updating the reference instruction identifier with the first intermediate identifier; When the target algorithm identifier is the basic algorithm identifier and the reference instruction identifier meets the third preset condition, updating the reference instruction identifier with the second intermediate identifier.

[0025] Among them, both the first intermediate identifier and the second intermediate identifier can be used to determine the algorithm instruction to which the jump needs to be made, and the third preset condition can be used to judge whether an algorithm instruction jump is required.

[0026] Specifically, when the target algorithm identifier is a high-order algorithm identifier, there is no need to consider the associated instruction identifier, and only the algorithm instructions need to be executed in the order of the reference instruction identifier.

[0027] When the target algorithm identifier is a basic algorithm identifier and the reference instruction identifier does not meet the third preset condition, it means that there is no need to perform a jump of algorithm instructions when executing the basic algorithm, and the algorithm instructions are executed in the order of the reference instruction identifier.

[0028] When the target algorithm identifier is a basic algorithm identifier and the reference instruction identifier meets the third preset condition, it means that a jump of algorithm instructions is required when executing the basic algorithm, and the algorithm instructions are executed by jumping according to the associated instruction identifier.

[0029] It should be noted that in the prior art, when the basic algorithm and the high-order algorithm are independently implemented in circuit implementation, selectors need to be added for the j-th bit of the i-th algorithm instruction in the high-order algorithm and the j-th bit of the i-th algorithm instruction in the basic algorithm. The selector is driven by an algorithm selection signal. i can be an integer within the range of [1, N], j can be an integer within the range of [1, J], and J can be the number of bits in a single algorithm instruction in the high-order algorithm. Then, the prior art needs to add an additional N×J selectors to support multi-algorithm testing.

[0030] In this embodiment, only a single selector needs to be added, and the impact on the increase in circuit area can be ignored. This selector is used to determine whether an algorithm instruction needs to jump, and it is driven by whether the target algorithm identifier and the reference instruction identifier meet the third preset condition, and is used to select the reference algorithm identifier corresponding to the next algorithm instruction to jump from the first intermediate identifier and the second intermediate identifier.

[0031] In a specific implementation manner, the determining the first intermediate identifier according to the reference instruction identifier includes: Adding the reference instruction identifier and a third preset value to obtain the added result as the first intermediate identifier.

[0032] Wherein, the third preset value can be 1, that is, the first intermediate identifier always corresponds to the next algorithm instruction in the high-order algorithm of the algorithm instruction corresponding to the current reference instruction identifier.

[0033] In a specific implementation manner, the determining the second intermediate identifier according to the associated instruction identifier includes: Using the associated instruction identifier as the second intermediate identifier.

[0034] Wherein, the second intermediate identifier always corresponds to the next algorithm instruction that needs to jump in the algorithm instruction corresponding to the current reference instruction identifier.

[0035] In a specific embodiment, the third preset condition is that the reference instruction identifier belongs to a preset identifier set, where the preset identifier set includes M preset instruction identifiers, and M is a positive integer.

[0036] Among them, the preset instruction identifier may refer to the instruction identifier corresponding to the algorithm instruction that needs to jump when executing the basic algorithm.

[0037] For example, if the reference instruction identifiers of the algorithm instructions included in the high-order algorithm are 1, 2, 3, 4, 5, and the reference instruction identifiers of the algorithm instructions included in the basic algorithm are 1, 3, 5, then the preset instruction identifiers may be 1, 3. Correspondingly, the associated instruction identifier corresponding to the algorithm instruction when the reference instruction identifier is 1 is 3, and the associated instruction identifier corresponding to the algorithm instruction when the reference instruction identifier is 3 is 5.

[0038] See Figure 2 , which is a schematic diagram of the state when the algorithm instruction is executed in a multi-algorithm-based MBIST test system provided by an embodiment of the present invention. Among them, the reference instruction identifier corresponding to the basic algorithm identifier is initialized to 3. The reference instruction identifiers corresponding to the algorithm instructions included in the basic algorithm are 3, 4, 6, 8, and the reference instruction identifiers corresponding to the algorithm instructions included in the high-order algorithm are 1 to 7. When the target instruction identifier is the first preset value, the basic algorithm is executed, the reference instruction identifier is initialized to 3, the algorithm instruction 3 is executed first, then the algorithm instruction 4 is executed, it is judged that the jump condition is satisfied, the algorithm instruction 6 is executed, it is judged that the jump condition is satisfied, and the algorithm instruction 8 is executed. When the target instruction identifier is the second preset value, the high-order algorithm is executed, the reference instruction identifier is initialized to 1, and the algorithm instructions 1 to 7 are executed in sequence. It should be noted that, for the sake of easy representation, Figure 2 in

[0039] the jump condition is still represented by the target instruction identifier, and the jump condition is only added to the algorithm instructions that need to jump in the basic algorithm. Implementers should be aware that the jump condition needs to be judged after each algorithm instruction is executed.

[0039] In a specific embodiment, the first preset condition is that the associated instruction identifier is the same as the fourth preset value.

[0040] Among them, the fourth preset value may be a value greater than N + 1. Only the associated instruction identifier of the additional expansion instruction in the basic algorithm is the fourth preset value, so that when the associated instruction identifier is the same as the fourth preset value, it can indicate that the basic algorithm has been executed.

[0041] In a specific embodiment, the second preset condition is that the reference instruction identifier is the same as the fifth preset value.

[0042] Among them, the fourth preset value may be N + 1. When the reference instruction identifier is updated to N + 1, it indicates that the high-order algorithm has been executed.

[0043] In this embodiment, in a scenario where a high-order algorithm is adopted and a basic algorithm is required for basic quick testing, the same algorithm instructions in the high-order algorithm and the basic algorithm are reused. Only by configuring the target algorithm identifier can the reference instruction identifier be initialized and the algorithm instruction to jump to after the execution of the algorithm instruction be determined. Therefore, it is not necessary to add an additional instruction sequence of the entire basic algorithm on the basis of the existing high-order algorithm instruction sequence, and it is not necessary to add a large number of selectors to implement the selection function between multiple algorithms, thus effectively reducing the area overhead of the test circuit and lowering the chip production cost.

[0044] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention disclosed is defined by the appended claims.

Claims

1. A MBIST test system based on multiple algorithms, characterized in that, The system includes: a processor and a memory storing a computer program, which when executed by the processor, implements the following steps: S101, initialize a reference instruction identifier according to the configured target algorithm identifier; S102, execute the algorithm instruction corresponding to the reference instruction identifier, and obtain the associated instruction identifier corresponding to the algorithm instruction; S103, update the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier, and return to execute step S102 until the associated instruction identifier meets the first preset condition or the reference instruction identifier meets the second preset condition, and complete the execution of the target algorithm corresponding to the target algorithm identifier.

2. The MBIST test system based on multiple algorithms according to claim 1, characterized in that, The target algorithm identifier is a basic algorithm identifier or a high-order algorithm identifier; The initializing the reference instruction identifier according to the configured target algorithm identifier includes: When the target algorithm identifier is the basic algorithm identifier, initialize the reference instruction identifier to a first preset value; When the target algorithm identifier is the high-order algorithm identifier, initialize the reference instruction identifier to a second preset value.

3. The MBIST test system based on multiple algorithms according to claim 2, characterized in that The updating the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier includes: Determine a first intermediate identifier according to the reference instruction identifier; Determine a second intermediate identifier according to the associated instruction identifier; When the target algorithm identifier is the high-order algorithm identifier or the reference instruction identifier does not meet the third preset condition, update the reference instruction identifier with the first intermediate identifier; When the target algorithm identifier is the basic algorithm identifier and the reference instruction identifier meets the third preset condition, update the reference instruction identifier with the second intermediate identifier.

4. The MBIST test system based on multiple algorithms according to claim 3, wherein The determining the first intermediate identifier according to the reference instruction identifier includes: Add the reference instruction identifier and a third preset value to obtain the added result as the first intermediate identifier.

5. The MBIST test system based on multiple algorithms according to claim 3, wherein The determining the second intermediate identifier according to the associated instruction identifier includes: Use the associated instruction identifier as the second intermediate identifier.

6. The MBIST test system based on multiple algorithms according to claim 3, wherein The third preset condition is: the reference instruction identifier belongs to a preset identifier set, where the preset identifier set includes M preset instruction identifiers, and M is a positive integer.

7. The MBIST test system based on multiple algorithms according to claim 1, characterized in that The first preset condition is: the associated instruction identifier is the same as a fourth preset value.

8. The MBIST test system based on multiple algorithms according to claim 1, characterized in that, The second preset condition is: the reference instruction identifier is the same as a fifth preset value.

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