An MBIST test system based on multiple algorithms

Abstract

The present application relates to the field of chip testing technology, and in particular to an MBIST test system based on multiple algorithms. In a scenario where a high-order algorithm is used and a basic algorithm is required for basic fast testing, the system reuses the same algorithm instructions in the high-order algorithm and the basic algorithm. Only a target algorithm identifier needs to be configured to initialize a reference instruction identifier and determine the algorithm instruction to jump to after the algorithm instruction is executed. Therefore, there is no need to add an additional instruction sequence of the entire basic algorithm on the basis of the existing high-order algorithm instruction sequence, and there is no need to add a large number of selectors to realize the selection function between multiple algorithms, thereby effectively reducing the area overhead of the test circuit and reducing the chip production cost.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, in particular to an MBIST testing system based on multiple algorithms. Background Art

[0002] At present, in the application scenarios of integrated circuits, as the demand for on-chip memory increases, the proportion of on-chip memory is also increasing. Especially in artificial intelligence chips, the proportion of on-chip memory far exceeds that of other types of chips. Therefore, in order to ensure the normal use of the chip, testing of on-chip memory is indispensable.

[0003] However, functional testing of on-chip memory is time-consuming and has low coverage. Therefore, a common approach in the prior art is structural testing using the memory built-in self-test (MBIST). Built-in self-test circuitry typically implements algorithms that can cover most on-chip memory fault types. Testing on-chip memory involves activating a test switch, waiting for the test to complete, and finally collecting test results.

[0004] Conventional high-level algorithms used for on-chip memory testing contain numerous test sequences, each covering fixed faults. To reduce test time in scenarios like system initialization or rapid on-chip testing, existing technologies typically separate basic faults into a single basic algorithm. This basic algorithm does not execute all test sequences, but rather only the basic fault detection sequences. Testers can then choose between the basic and high-level algorithms based on the test scenario.

[0005] However, in the existing technology, basic algorithms and high-order algorithms are implemented separately and independently during circuit implementation, and the algorithm selection function is supported by adding selectors to each bit of each group of corresponding high-order algorithm instructions and basic algorithm instructions. However, due to the large number of high-order algorithm instructions and the large bit width of each algorithm instruction, a large number of selectors need to be added, which will greatly increase the area overhead of the test circuit, thereby resulting in excessively high chip production costs.

[0006] Therefore, how to reduce the area overhead of the test circuit while realizing the multi-test algorithm selection function has become an urgent problem to be solved. Summary of the Invention

[0007] In view of the above technical problems, the technical solution adopted by the present invention is:

[0008] A multi-algorithm-based MBIST test system, comprising a processor and a memory having a computer program stored therein, wherein the computer program, when executed by the processor, performs the following steps:

[0009] S101, initializing a reference instruction identifier according to a configured target algorithm identifier.

[0010] S102: Execute the algorithm instruction corresponding to the reference instruction identifier, and obtain the associated instruction identifier corresponding to the algorithm instruction.

[0011] S103, based on the target algorithm identifier, the reference instruction identifier and the associated instruction identifier, update the reference instruction identifier, and return to execution step S102 until the associated instruction identifier meets the first preset condition or the reference instruction identifier meets the second preset condition, and complete the execution of the target algorithm corresponding to the target algorithm identifier.

[0012] The present invention has obvious beneficial effects compared with the prior art. By means of the above technical solution, the MBIST test system based on multiple algorithms provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0013] In the scenario where a high-order algorithm is adopted and a basic algorithm is required to perform basic fast testing, the present invention reuses the same algorithm instructions in the high-order algorithm and the basic algorithm. It only needs to configure the target algorithm identifier to initialize the reference instruction identifier and determine the algorithm instruction to jump to after the algorithm instruction is executed. Therefore, there is no need to add an additional instruction sequence of the entire basic algorithm on the basis of the existing high-order algorithm instruction sequence, and there is no need to add a large number of selectors to realize the selection function between multiple algorithms, thereby effectively reducing the area overhead of the test circuit and reducing the chip production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic flow chart of a computer program being executed by a processor in an MBIST test system based on multiple algorithms provided by an embodiment of the present invention;

[0016] Figure 2 The present invention provides a schematic diagram of the state of an MBIST test system based on multiple algorithms when executing algorithm instructions. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0018] This embodiment provides a multi-algorithm MBIST test system, see Figure 1 , is a flow chart of a computer program executed by a processor in a multi-algorithm-based MBIST test system provided by an embodiment of the present invention. The system includes: a processor and a memory storing the computer program. When the computer program is executed by the processor, the following steps are implemented:

[0019] S101, initializing a reference instruction identifier according to a configured target algorithm identifier;

[0020] S102, executing the algorithm instruction corresponding to the reference instruction identifier, and obtaining an associated instruction identifier corresponding to the algorithm instruction;

[0021] S103, based on the target algorithm identifier, the reference instruction identifier and the associated instruction identifier, update the reference instruction identifier, and return to execution step S102 until the associated instruction identifier meets the first preset condition or the reference instruction identifier meets the second preset condition, and complete the execution of the target algorithm corresponding to the target algorithm identifier.

[0022] The target algorithm identifier can be configured by the implementer to select the algorithm to be tested from multiple algorithms supported by the MBIST test.

[0023] The reference instruction identifier corresponds to the algorithm instruction one by one, and the associated instruction identifier can be used to identify the instruction identifier corresponding to the algorithm instruction that needs to be jumped to after the corresponding algorithm instruction is executed.

[0024] The first preset condition can be used to determine whether the algorithm instruction corresponding to the associated instruction identifier is an additional extended instruction. In this embodiment, the additional extended instruction only belongs to the basic algorithm instruction sequence. Therefore, the first preset condition can be used to determine whether the basic algorithm instruction sequence has been executed, and the second preset condition can be used to determine whether the high-order algorithm instruction sequence has been executed.

[0025] Since the basic algorithm has an additional instruction at the end of the algorithm sequence compared to the high-order algorithm, additional extended instructions need to be added after the basic algorithm and the high-order algorithm are reused, and the additional extended instructions only belong to the basic algorithm instruction sequence.

[0026] In a specific implementation, the target algorithm identifier is a basic algorithm identifier or a high-order algorithm identifier;

[0027] Initializing the reference instruction identifier according to the configured target algorithm identifier includes:

[0028] When the target algorithm identifier is the basic algorithm identifier, initializing the reference instruction identifier to a first preset value;

[0029] When the target algorithm identifier is the high-order algorithm identifier, the reference instruction identifier is initialized to a second preset value.

[0030] Among them, the multiple algorithms supported by this embodiment may include basic algorithms and high-order algorithms. The basic algorithm may adopt the MarchC+ algorithm. The high-order algorithm instruction sequence generally includes all algorithm instructions in the basic algorithm instruction sequence, and also includes algorithm instructions corresponding to the fault coverage test sequence for byte write enable, algorithm instructions corresponding to the fault coverage test sequence for output enable, chip select enable, and read enable, algorithm instructions corresponding to the leakage current fault coverage test sequence, etc.

[0031] However, the instruction identifiers corresponding to the same algorithm instructions in the high-level algorithm instruction sequence and the basic algorithm instruction sequence are different. Therefore, in the prior art, the basic algorithm is usually implemented in an additional independent circuit.

[0032] When the reference instruction identifier is the first preset value, the reference instruction identifier corresponds to the first algorithm instruction of the basic algorithm.

[0033] When the reference instruction identifier is the second preset value, the reference instruction identifier corresponds to the first algorithm instruction of the high-order algorithm. In this embodiment, the reference instruction identifier of the algorithm instruction corresponding to the high-order algorithm can be from 1 to N, where N can refer to the number of algorithm instructions in the high-order algorithm. The second preset value can be 1.

[0034] In a specific implementation, updating the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier includes:

[0035] determining a first intermediate identifier according to the reference instruction identifier;

[0036] Determine a second intermediate identifier according to the associated instruction identifier;

[0037] When the target algorithm identifier is the high-order algorithm identifier or the reference instruction identifier does not meet a third preset condition, updating the reference instruction identifier with the first intermediate identifier;

[0038] When the target algorithm identifier is the basic algorithm identifier and the reference instruction identifier meets the third preset condition, the reference instruction identifier is updated with the second intermediate identifier.

[0039] The first intermediate identifier and the second intermediate identifier can both be used to determine the algorithm instruction to which the program needs to jump, and the third preset condition can be used to determine whether the algorithm instruction needs to be jumped.

[0040] Specifically, when the target algorithm identifier is a high-order algorithm identifier, there is no need to consider the associated instruction identifier, and the algorithm instructions only need to be executed in the order of the reference instruction identifier.

[0041] When the target algorithm identifier is the basic algorithm identifier and the reference instruction identifier does not meet the third preset condition, it means that there is no need to jump the algorithm instructions when executing the basic algorithm, and the algorithm instructions are executed in the order of the reference instruction identifiers.

[0042] When the target algorithm identifier is the basic algorithm identifier and the reference instruction identifier meets the third preset condition, it means that the algorithm instruction needs to be jumped when executing the basic algorithm, and the algorithm instruction is jumped and executed according to the associated instruction identifier.

[0043] It should be noted that in the prior art, when the basic algorithm and the high-order algorithm are implemented independently during circuit implementation, it is necessary to add selectors for the j-th bit of the i-th algorithm instruction in the high-order algorithm and the j-th bit of the i-th algorithm instruction in the basic algorithm. The selectors are driven by algorithm selection signals, i can refer to an integer in the range of [1, N], j can refer to an integer in the range of [1, J], and J can refer to the number of bits in a single algorithm instruction in the high-order algorithm. The prior art then requires the addition of N×J selectors to support multi-algorithm testing.

[0044] In this embodiment, only a single selector needs to be added, and the impact on the increase in circuit area can be ignored. The selector is used to determine whether the algorithm instruction needs to jump. The selector is driven by whether the target algorithm identifier and the reference instruction identifier meet the third preset condition, and is used to select the reference algorithm identifier corresponding to the next algorithm instruction to jump from the first intermediate identifier and the second intermediate identifier.

[0045] In a specific implementation, determining the first intermediate identifier according to the reference instruction identifier includes:

[0046] The reference instruction identifier and a third preset value are added to obtain an addition result as the first intermediate identifier.

[0047] The third preset value may be 1, that is, the first intermediate identifier always corresponds to the next algorithm instruction in the high-order algorithm of the algorithm instruction corresponding to the current reference instruction identifier.

[0048] In a specific implementation, determining the second intermediate identifier according to the associated instruction identifier includes:

[0049] The associated instruction identifier is used as the second intermediate identifier.

[0050] The second intermediate identifier always corresponds to the next algorithm instruction to be jumped in the algorithm instruction corresponding to the current reference instruction identifier.

[0051] In a specific implementation, the third preset condition is: the reference instruction identifier belongs to a preset identifier set, wherein the preset identifier set includes M preset instruction identifiers, and M is a positive integer.

[0052] Among them, the preset instruction identifier may refer to the instruction identifier corresponding to the algorithm instruction that needs to be jumped when executing the basic algorithm.

[0053] For example, if the reference instruction identifiers of each algorithm instruction contained in the high-order algorithm are 1, 2, 3, 4, and 5, and the reference instruction identifiers of each algorithm instruction contained in the basic algorithm are 1, 3, and 5, then the preset instruction identifiers can be 1, 3. Accordingly, when the reference instruction identifier is 1, the associated instruction identifier corresponding to the corresponding algorithm instruction is 3, and when the reference instruction identifier is 3, the associated instruction identifier corresponding to the corresponding algorithm instruction is 5.

[0054] See also Figure 2 , is a state diagram of algorithm instruction execution in an MBIST test system based on multiple algorithms provided by an embodiment of the present invention, wherein the reference instruction identifier corresponding to the basic algorithm identifier is initialized to 3, the reference instruction identifiers corresponding to the algorithm instructions included in the basic algorithm are 3, 4, 6, and 8, and the reference instruction identifiers corresponding to the algorithm instructions included in the high-order algorithm are 1 to 7. When the target instruction identifier is a first preset value, the basic algorithm is executed, the reference instruction identifier is initialized to 3, and algorithm instruction 3 is executed first, then algorithm instruction 4 is executed. If it is determined that the jump condition is met, algorithm instruction 6 is executed. If it is determined that the jump condition is met, algorithm instruction 8 is executed. When the target instruction identifier is a second preset value, the high-order algorithm is executed, the reference instruction identifier is initialized to 1, and algorithm instructions 1 to algorithm instruction 7 are executed in sequence. It should be noted that, for ease of representation, Figure 2 The jump conditions are still represented by the target instruction identifier, and the jump conditions are only added for the algorithm instructions that the basic algorithm needs to jump to. The implementer should be aware that the jump conditions need to be judged after each algorithm instruction is executed.

[0055] In a specific implementation, the first preset condition is: the associated instruction identifier is the same as a fourth preset value.

[0056] Among them, the fourth preset value can be a value greater than N+1, and only the associated instruction identifier of the additional extended instruction in the basic algorithm is the fourth preset value, so that when the associated instruction identifier is the same as the fourth preset value, it can be indicated that the basic algorithm has been executed.

[0057] In a specific implementation, the second preset condition is: the reference instruction identifier is the same as a fifth preset value.

[0058] Among them, the fourth preset value may be N+1. When the reference instruction identifier is updated to N+1, it indicates that the high-order algorithm has been executed.

[0059] In this embodiment, in a scenario where a high-order algorithm is used and a basic algorithm is required for basic fast testing, the same algorithm instructions in the high-order algorithm and the basic algorithm are reused. It is only necessary to configure the target algorithm identifier to initialize the reference instruction identifier and determine the algorithm instruction to jump to after the algorithm instruction is executed. Therefore, there is no need to add an additional instruction sequence of the entire basic algorithm on the basis of the existing high-order algorithm instruction sequence, and there is no need to add a large number of selectors to realize the selection function between multiple algorithms, thereby effectively reducing the area overhead of the test circuit and reducing the chip production cost.

[0060] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. An MBIST test system based on multiple algorithms, characterized in that, The system includes: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: S101, initializing a reference instruction identifier according to a configured target algorithm identifier, wherein the target algorithm identifier is a basic algorithm identifier or a high-order algorithm identifier; Initializing the reference instruction identifier according to the configured target algorithm identifier includes: When the target algorithm identifier is the basic algorithm identifier, initializing the reference instruction identifier to a first preset value; When the target algorithm identifier is the high-order algorithm identifier, the reference instruction identifier is initialized to a second preset value, when the reference instruction identifier is the first preset value, the reference instruction identifier corresponds to the first algorithm instruction of the basic algorithm, and when the reference instruction identifier is the second preset value, the reference instruction identifier corresponds to the first algorithm instruction of the high-order algorithm; S102, executing the algorithm instruction corresponding to the reference instruction identifier, and obtaining an associated instruction identifier corresponding to the algorithm instruction; S103, updating the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier, and returning to step S102 until the associated instruction identifier satisfies a first preset condition or the reference instruction identifier satisfies a second preset condition, and the execution of the target algorithm corresponding to the target algorithm identifier is completed, wherein updating the reference instruction identifier according to the target algorithm identifier, the reference instruction identifier, and the associated instruction identifier includes: determining a first intermediate identifier according to the reference instruction identifier; Determine a second intermediate identifier according to the associated instruction identifier; When the target algorithm identifier is the high-order algorithm identifier or the reference instruction identifier does not meet a third preset condition, updating the reference instruction identifier with the first intermediate identifier; When the target algorithm identifier is the basic algorithm identifier and the reference instruction identifier meets the third preset condition, the reference instruction identifier is updated with the second intermediate identifier.

2. MBIST test system based on multi-algorithm according to claim 1, is characterized in that, The determining the first intermediate identifier according to the reference instruction identifier includes: The reference instruction identifier and a third preset value are added to obtain an addition result as the first intermediate identifier.

3. MBIST test system based on multi-algorithm according to claim 1, is characterized in that, The determining the second intermediate identifier according to the associated instruction identifier includes: The associated instruction identifier is used as the second intermediate identifier.

4. MBIST test system based on multi-algorithm according to claim 1, is characterized in that, The third preset condition is that the reference instruction identifier belongs to a preset identifier set, wherein the preset identifier set includes M preset instruction identifiers, where M is a positive integer.

5. MBIST test system based on multi-algorithm according to claim 1, is characterized in that, The first preset condition is that the associated instruction identifier is the same as a fourth preset value.

6. MBIST test system based on multi-algorithm according to claim 1, is characterized in that, The second preset condition is that the reference instruction identifier is the same as the fifth preset value.

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