Data accelerator, driving device and chip

Abstract

The invention provides a data accelerator, a driving device and a chip. The method comprises the steps that a configuration module deploys configuration information of data transmission and interrupt processing of external equipment; the main module is used as a medium for data interaction between the processor and external equipment based on the control signal; the control module generates a control signal for scheduling the action of the data interaction based on the configuration information, and maintains the normally online state of the data interaction between the processor and the external device. According to the functional attribute of the external equipment, corresponding configuration information is deployed, a data interaction architecture is set to perform normalization processing on the low-power-consumption external equipment, a path for bridging a high-speed bus by an APB bus is reduced, the path of a data link is shortened, delay is reduced, resource consumption of a chip is reduced, chip function expansion is facilitated, and the cost is reduced. The processor does not need to be awakened for many times, and the normally online state of the low-power-consumption external equipment is achieved.

Description

Technical Field

[0001] This application relates to the technical field of chip design and application, and particularly to a data accelerator, a driving device, and a chip. Background Art

[0002] Many handheld devices and IoT (Internet of Things) devices connect to external sensor devices through a low-speed bus (the full name of the low-speed bus is Advanced Peripheral Bus, abbreviated as APB, which is used to connect low-speed peripherals. APB is used to set up a low-power interface and is used for peripheral devices with low bandwidth and no need for a high-performance bus. APB is a non-pipelined structure, and all signals are only related to the rising edge of the clock. Each transmission takes at least two cycles, without waiting cycles and response signals). Specifically, the external sensor device is bridged to the high-speed bus inside the chip (the high-speed bus includes AHB and AXI) and the on-chip memory of the chip's processor through the APB bus. AHB full name is Advanced High Performance Bus, which is used for the connection between high-performance modules, such as CPU, DMA, DSP, etc. AHB uses a single clock edge operation; a non-three-state implementation method; supports burst transmission; supports segmented transmission; supports multiple master devices; can configure the bus width from 32 bits to 128 bits; supports byte, half-word, and word transmission. AXI full name is Advanced eXtensible Interface, which is an on-chip bus for high performance, high bandwidth, and low latency. Its address / control and data phases are separated, supports unaligned data transmission, and in burst transmission, only the first address is required, and at the same time, the separated read and write data channels support Outstanding transmission access and out-of-order access, and it is easier to perform timing convergence). This connection method has a long data link and a large delay, which will interrupt the processor at random time nodes, resulting in multiple wake-ups of the processor and unable to achieve low-power always-on. On the other hand, the method of bridging the external sensor device to the high-speed bus and the on-chip memory of the chip's processor through the APB bus may cause an increase in the data interaction architecture, resulting in an increase in the resource consumption of the chip and restricting the expansion of the chip's functions.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of this application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of this application. Summary of the Invention

[0004] Embodiments of this application provide a data accelerator, a driving device, and a chip.

[0005] The first aspect of the embodiments of the present application provides a data accelerator, including:

[0006] A configuration module, and the control module is configured to deploy configuration information for data transmission and interrupt processing of external device data according to the functional attributes of the external device and the received processor commands;

[0007] A backbone module, which is connected between the high-speed bus of the processor and the external device, and is used as a medium for data interaction between the processor and the external device based on the control signal;

[0008] A control module, the input end of the control module is connected to the output end of the configuration module, and the output end of the control module is connected to the backbone module, generating the control signal for scheduling the actions of data interaction based on the configuration information, and maintaining the always-on state of data interaction between the processor and the external device.

[0009] The second aspect of the embodiments of the present application provides a driving device, including: the driving device is configured to set executable code, and the executable code controls the operating system to perform data transmission operations with the data accelerator provided in the first aspect of the embodiments of the present application.

[0010] The third aspect of the embodiments of the present application provides a chip, including: a processor, an external device interface, and the data accelerator provided in the first aspect of the embodiments of the present application, wherein: the external device interface is connected to the corresponding external device for data transmission; the data accelerator is connected between the high-speed bus of the processor and the external device interface, and is used to maintain the always-on state of data interaction between the processor and the external device.

[0011] The technical solutions provided by the embodiments of the present application at least bring the following beneficial effects:

[0012] According to the functional attributes of the external device, the corresponding configuration information is deployed, a data interaction architecture is set up to normalize the low-power external device, and the path of the APB bus bridging the high-speed bus is reduced, shortening the path of the data link, reducing latency, reducing the resource consumption of the chip, facilitating the expansion of the chip function, without waking up the processor multiple times, and realizing the always-on state of the low-power external device.

[0013] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0015] Figure 1Schematic diagram of the intelligent sensing hub provided by the first example of this application;

[0016] Figure 2 Schematic diagram of the intelligent sensing hub provided by the second example of this application;

[0017] Figure 3 Schematic diagram of a data accelerator provided by the embodiments of this application;

[0018] Figure 4 Schematic diagram of a chip provided by the embodiments of this application. Detailed implementation manners

[0019] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of this application. On the contrary, they are only examples of devices and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0020] The terms used in the embodiments of this application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of this application. The singular forms "a" and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0021] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the embodiments of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "when" as used herein may be interpreted as "when" or "when" or "in response to determining".

[0022] The embodiments of this application will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain this application and should not be construed as a limitation of this application.

[0023] It should be noted that the data accelerator provided in any embodiment of the present application can be executed alone, or can be executed together with possible implementation methods in other embodiments, or can be executed together with any technical solution in the related art.

[0024] The data accelerator, driving device and chip according to the embodiments of the present application will be described below with reference to the accompanying drawings.

[0025] Figure 1 A structural schematic diagram of an intelligent sensing hub is shown. As Figure 1As shown, the intelligent sensing hub can be a handheld mobile device or an IOT device, which is a software and hardware combined solution based on a low-power MCU (Microcontroller Unit, which reduces the frequency of the central processing unit appropriately and integrates peripheral interfaces such as memory and counter, as well as the display driver circuit on a single chip to form a chip-level computer for different combinations of control in various application scenarios, such as mobile phones, automotive electronics, stepping motors, robotic arms, etc.) and a lightweight RTOS operating system (Real-time operating system, which runs and manages system resources in sequence and provides a consistent foundation for developing application programs. Compared with general operating systems, the biggest feature of a real-time operating system is its real-time nature. If a task needs to be executed, the real-time operating system will execute the task immediately or within a short time without long delays, which ensures the timely execution of each task). Its main function is to connect and process data from various external devices. The external devices perform matching, data reading, and fusion processing through the external device kernel, and then are bridged to the high-speed bus (the high-speed bus includes the AHB bus, AXI bus, etc.), CPU, and on-chip memory (the memory includes static RAM, dynamic RAM, and TCM. The full name of TCM is Tightly Coupled Memories, translated as tightly coupled memory. Different from static RAM and dynamic RAM, TCM is a fixed-size RAM that is tightly coupled to the processor core, providing performance comparable to cache. The advantage compared to cache is that the program code can precisely control the location where functions or code are stored, and TCM will never be kicked out of the main memory, so it has a function preset by the user) through the on-chip APB bus bridge. The CPU deploys a low-speed bus and drivers for external devices. If the data volume is relatively small, the data is directly read by the CPU into the TCM; if the data volume is relatively large, the data can be read into the TCM by DMA (the full name is Direct Memory Access, that is, direct memory access. DMA transfer copies data from one address space to another, providing high-speed data transfer between peripherals and memories or between memories. When the CPU initializes this transfer action, the transfer action itself is implemented and completed by the DMA controller. The DMA transfer method does not require the CPU to directly control the transfer, nor does it have the process of saving and restoring the scene like the interrupt processing method. It opens a direct data transfer channel for RAM and IO devices through hardware, greatly improving the efficiency of the CPU).When a task occurs in an external device, the CPU needs to be awakened so that the CPU is powered on; while when the external device is idle, the CPU enters the sleep or power-off state. Therefore, frequent awakenings will lead to increased power consumption. If the number of external devices increases, it may cause an increase in the data interaction architecture, resulting in increased resource consumption of the chip and restricting the expansion of chip functions. On the one hand,... Figure 1 The architecture shown is a purely hardware-based solution that cannot be functionally configured, and the types and quantities of connected external devices are fixed; any external device may interrupt the CPU at any time node, affecting the data interaction of other external devices.

[0026] Figure 2 Shows a schematic structural diagram of another intelligent sensing hub. As Figure 2 shown, on the basis of the intelligent sensing hub shown in Figure 1 an aggregation module is added, which is used to collect data of external devices, store the collected data in the TCM, and be responsible for the management of relevant interrupt operations. However, this architecture increases the complexity of the chip, resulting in increased resource consumption of the chip.

[0027] Therefore, the present application provides a data accelerator, a driving device, and a chip.

[0028] Figure 3 Is a schematic structural diagram of a data accelerator provided by an embodiment of the present application. As Figure 3 shown, the data accelerator includes:

[0029] As Figure 3 shown, a configuration module, and the control module is used to deploy configuration information for the transmission of external device data and interrupt processing according to the functional attributes of the external device and the received processor commands.

[0030] Optionally, as an example, the configuration module includes: a configuration unit, a command parsing unit, and a first generation unit, where:

[0031] The configuration unit is used to set corresponding descriptors according to the functional attributes of external devices. It should be noted that a descriptor is an object attribute of a "bound behavior". In the descriptor protocol, it can define access to attributes through several methods, including: get(), set(), and delete(). If any of these methods is defined in an object, this object is a descriptor.

[0032] The command parsing unit is used to set corresponding execution policies according to the priorities of processor commands. Further, processor commands enter a queue; the command parsing unit parses the queue to obtain the priorities of the processor commands in the queue; according to the priorities of the processor commands, the command parsing unit sets corresponding execution policies.

[0033] The first generating unit generates configuration information for deploying the transmission and / or interruption processing of external device data based on the descriptor and the execution policy.

[0034] Furthermore, the configuration module can also perform function setting using a hardware description language (based on the hardware description language, setting the interfaces, function logics, connection relationships, timing, frequency, data throughput, etc. of the configuration unit, command parsing unit, and first generating unit, and then combining the configuration unit, command parsing unit, and first generating unit into an actual circuit, converting it to a gate-level circuit netlist through an automatic synthesis tool, and then using an application-specific integrated circuit or field-programmable gate array automatic placement and routing tool to convert the netlist into a specific circuit wiring structure to be implemented), or can also perform function setting using an IP core (the full name of the IP core is Intellectual Property, which is the general term for integrated circuit cores with intellectual property cores, and is an integrated circuit design macro module (logic or functional unit) that has been gradually separated in the chip design process, has been repeatedly verified, has a specific function, can be reused, and contains specific core elements (instruction sets, function descriptions, codes, etc.), and can be understood as a partially reusable "chip design module"). As long as it can deploy the configuration information for the transmission and interruption processing of external device data according to the functional attributes of the external device and the received processor commands, any setting form of the configuration module is applicable, and this embodiment is not limiting.

[0035] As Figure 3 shown, the data accelerator further includes a backbone module, and the backbone module is connected between the high-speed bus of the processor and the external device, and is used as a medium for data interaction between the processor and the external device based on the control signal.

[0036] Optionally, as an example, the backbone module includes a high-speed bus master device and at least one external device core, where:

[0037] The external device core is used for data interaction with the external device. If the number of external device cores exceeds 1, the backbone module further includes a multiplexer. A multiplexer is a multi-input and single-output combinational logic circuit. An n (n>1)-input multiplexer is an n-way digital switch, and can select one output from n inputs to the common output terminal according to different channel selection control signals. It should be noted that the external device core includes at least one of the following: SPI device, I2C device, UART device, I2S device, GPIO device, SDIO device.

[0038] The high-speed bus master is connected between the high-speed bus of the processor and the external device core, and is used as a medium for data interaction between the processor and the external device core. Further, the ways for the processor and the external device to perform data interaction include: when the processor sends data to the external device, the control module adjusts the backbone module to obtain data from the tightly coupled memory of the processor based on the configuration information, and transmits the data to the corresponding external device; when the processor receives data from the external device, the control module writes the data into the tightly coupled memory of the processor based on the configuration information, and the processor performs the next operation.

[0039] Furthermore, the backbone module can also be set up in terms of functions using a hardware description language or an IP core. As long as it can be used as a medium for data interaction between the processor and the external device based on the control signal, any form of setting up the backbone module is applicable and is not limited to this embodiment.

[0040] As Figure 3 shown, the data accelerator further includes a control module. The input end of the control module is connected to the output end of the configuration module, and the output end of the control module is connected to the backbone module, generating the control signal for scheduling the actions of data interaction based on the configuration information and maintaining the always-on state of data interaction between the processor and the external device.

[0041] Optionally, as an example, the control module includes: a detection unit and a second generation unit, where:

[0042] The detection unit detects the empty / full state of the FIFO in the external device based on the configuration information, or executes corresponding responses based on the interrupt request of the external device. Here, FIFO stands for First In, First Out, that is, the data that enters first comes out first, and the data that enters later comes out later. FIFO is a buffer mitigation of the system, used to cache continuous data streams to prevent data loss during ingress and storage operations; centralize data for ingress and storage to avoid frequent bus operations and reduce the burden on the CPU; allow the system to perform DMA operations to improve the data transfer speed.

[0043] The second generation unit generates the control signal for scheduling the actions of data interaction based on the configuration information, and maintains the always-on state of data interaction between the processor and the external device through the control signal.

[0044] Further, when sending data to an external device through the data accelerator, the CPU puts the data into the TCM. The configuration module parses the commands from the command queue according to the priorities and maps the parsing results to the control module. The control module adjusts the backbone module to obtain the data from the TCM and transfers the data to the corresponding external device. It should be noted that if the amount of data is relatively large, the data transfer process is completed through DMA and is not adjusted by the control module.

[0045] When the data accelerator receives data sent by an external device, the control module adjusts according to the empty / full status of the FIFO, the priorities set by the configuration module, and the interrupt requested by the external device, and selects whether to send an interrupt signal to the processor for the next operation according to the adjustment process.

[0046] Since the interrupts of the low-speed bus are concentrated on the data accelerator, the bus settings of the processor can be reduced, saving interrupt resources; when the data accelerator is working, it does not require the intervention of the processor, can expand the functions of the processor, and improve the operating efficiency of the processor; when the processor and the external device interact, the resource consumption is minimized, and the always-online state of the data interaction between the processor and the external device can be maintained.

[0047] Furthermore, the control module can also be set up with a hardware description language or with an IP core. As long as the control signal can schedule the actions of data interaction based on the configuration information and maintain the always-online state of the data interaction between the processor and the external device, any setting form of the backbone module is applicable and is not limited to this embodiment.

[0048] In particular, according to the embodiments of the present application, the process described above with reference to the flowchart can be implemented as a driving device. The driving device is used to set executable code, and the executable code controls the operating system to perform data transfer operations with the data accelerator described in this embodiment. As an example, the format of the file generated by the executable code includes at least one of the following: CAT file format, INF file format, SYS file format, DLL file format. The specific process of the data transfer operation will not be elaborated here.

[0049] According to the functional attributes of the external device, the corresponding configuration information is deployed, a data interaction architecture is set up to normalize the low-power external device, the path of the APB bus bridging the high-speed bus is cut, the path of the data link is shortened, the delay is reduced, the resource consumption of the chip is reduced, which is beneficial to the expansion of the chip functions, and the processor does not need to be woken up multiple times, realizing the always-online state of the low-power external device.

[0050] Figure 4 This is a schematic structural diagram of a chip provided by the embodiments of the present application. As Figure 4As shown, the chip includes: a processor, an external device interface, and the data accelerator of this embodiment, where:

[0051] The external device interface is connected to the corresponding external device and is used for data transmission;

[0052] The data accelerator is connected between the high-speed bus of the processor and the external device interface and is used to maintain the always-on state of the data interaction between the processor and the external device.

[0053] It should be noted that the chip can be set by using an application specific integrated circuit (ASIC for short, which is a proprietary application chip designed and manufactured for specific user requirements and specific electronic systems, and its computing power and computing efficiency can be customized according to algorithm requirements), or can be set by using an IP core. The specific setting process will not be elaborated here one by one.

[0054] The chip can deploy corresponding configuration information according to the functional attributes of the external device, set up a data interaction architecture to normalize low-power external devices, cut off the path of the APB bus bridging the high-speed bus, shorten the path of the data link, reduce latency, reduce the resource consumption of the chip, facilitate the expansion of the chip function, and realize the always-on state of low-power external devices without waking up the processor multiple times.

[0055] After considering the specification and the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present invention. This application is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include the common general knowledge or conventional technical means in the technical field not disclosed in this application. The specification and the embodiments are only regarded as exemplary, and the true scope and spirit of this application are pointed out by the following claims.

[0056] It should be understood that this application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is only limited by the appended claims.

Claims

1. A data accelerator, characterized in that, Comprising: A configuration module, the control module is used to deploy configuration information for data transmission and interruption processing of external device data according to the functional attributes of the external device and the received processor commands; A backbone module, the backbone module is connected between the high-speed bus of the processor and the external device, and is used as a medium for data interaction between the processor and the external device based on the control signal; A control module, the input end of the control module is connected to the output end of the configuration module, and the output end of the control module is connected to the backbone module, generating the control signal for scheduling the actions of data interaction based on the configuration information, and maintaining the always-on state of data interaction between the processor and the external device.

2. The data accelerator according to claim 1, wherein The configuration module includes: a configuration unit, a command parsing unit and a first generation unit, wherein: the configuration unit is used to set corresponding descriptors according to the functional attributes of the external device; the command parsing unit is used to set corresponding execution policies according to the priorities of the processor commands; the first generation unit generates configuration information for deploying data transmission and / or interruption processing of external device data based on the descriptors and execution policies.

3. The data accelerator according to claim 2, wherein, Processor commands enter the queue; the command parsing unit parses the queue to obtain the priorities of the processor commands in the queue; according to the priorities of the processor commands, the command parsing unit sets corresponding execution policies.

4. The data accelerator according to claim 1, wherein The control module includes: a detection unit and a second generation unit, wherein: the detection unit detects the empty / full state of the FIFO in the external device based on the configuration information, or executes corresponding responses based on the interruption requests of the external device; the second generation unit generates the control signal for scheduling the actions of data interaction based on the configuration information, and maintains the always-on state of data interaction between the processor and the external device through the control signal.

5. The data accelerator according to claim 1, wherein The backbone module includes a high-speed bus master device and at least one external device core, wherein: the external device core is used to perform data interaction with the external device; the high-speed bus master device is connected between the high-speed bus of the processor and the external device core, and is used as a medium for data interaction between the processor and the external device core.

6. The data accelerator according to claim 1 or 5, characterized in that, The ways for the processor to perform data interaction with the external device include: when the processor sends data to the external device, the control module adjusts the backbone module to obtain data from the tightly coupled memory of the processor based on the configuration information and transmits the data to the corresponding external device; when the processor receives data from the external device, the control module writes the data into the tightly coupled memory of the processor for the processor to perform the next operation based on the configuration information.

7. The data accelerator according to claim 5, characterized in that The external device core includes at least one of the following: SPI device, I2C device, UART device, I2S device, GPIO device, SDIO device.

8. A driving device, characterized in that, The drive device is used to set executable code, and the executable code controls the data transmission operation between the operating system and the data accelerator as described in any one of claims 1-7.

9. The device according to claim 8, characterized in that, The formats of the files generated by the executable code include any one of the following: CAT file format, INF file format, SYS file format, DLL file format.

10. A chip, characterized in that, The chip includes: a processor, an external device interface, and a data accelerator as described in any one of claims 1-7, wherein: the external device interface is connected to a corresponding external device for data transmission; the data accelerator is connected between the high-speed bus of the processor and the external device interface for maintaining an always-on state of data interaction between the processor and the external device.

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