Data interaction method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computers, in particular to a data interaction method and device, electronic equipment and a storage medium. The method comprises the following steps: monitoring a service data flow adopted when data interaction is carried out between a first processor and a second processor; if the service data flow does not meet the performance requirements of the processors, performing data interaction between the first processor and the second processor by using a hardware management strategy; and if the service data flow meets the performance requirements of the processors, performing data interaction between the first processor and the second processor by using a software management strategy. The data interaction effect can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a data interaction method, apparatus, electronic device, and storage medium. Background Art

[0002] In computing device systems such as servers, mobile, and desktop processors, there are multiple processors. Usually, data interaction can be completed between processors in a Double Data Rate (DDR) synchronous dynamic random access memory. However, due to the large latency of accessing DDR and limited bandwidth, the data interaction effect is poor, affecting the usage experience of the computing device system. Summary of the Invention

[0003] The present disclosure aims to at least solve one of the technical problems in the related art to some extent.

[0004] To this end, the first object of the present disclosure is to propose a data interaction method to improve the data interaction effect.

[0005] The second object of the present disclosure is to propose a data interaction apparatus.

[0006] The third object of the present disclosure is to propose an electronic device.

[0007] The fourth object of the present disclosure is to propose a computer-readable storage medium.

[0008] The fifth object of the present disclosure is to propose a computer program product.

[0009] To achieve the above object, an embodiment of the first aspect of the present disclosure provides a data interaction method, including:

[0010] Monitoring the service data stream used for data interaction between a first processor and a second processor;

[0011] If the service data stream does not meet the processor performance requirements, the first processor and the second processor perform data interaction using a hardware management strategy;

[0012] If the service data stream meets the processor performance requirements, the first processor and the second processor perform data interaction using a software management strategy.

[0013] Optionally, when the first processor and the second processor perform data interaction using a hardware management strategy, it includes:

[0014] If the service data stream does not meet the data cache requirements, the first processor and the second processor perform data interaction through a Double Data Rate synchronous dynamic random access memory;

[0015] If the service data stream meets the data caching requirements, data interaction is performed between the first processor and the second processor through a system-level cache.

[0016] Optionally, the method further includes:

[0017] If the service data stream is shared data and the service data stream is non-cacheable data, the service data stream does not meet the data caching requirements;

[0018] If the service data stream is non-shareable data, the service data stream meets the data caching requirements;

[0019] If the service data stream is the shared data and the service data stream is cacheable data, the service data stream meets the data caching requirements.

[0020] Optionally, data interaction is performed between the first processor and the second processor through a system-level cache, including:

[0021] If the service data stream is non-shareable data, data interaction is performed between the first processor and the second processor through the system-level cache using a first system cache indexing policy;

[0022] If the service data stream is shared data and there is no cache hit for the service data stream in the system-level cache, data interaction is performed between the first processor and the second processor through the system-level cache using a second system cache indexing policy;

[0023] If the service data stream is shared data and there is a cache hit for the service data stream in the system-level cache, data interaction is performed between the first processor and the second processor through the system-level cache using a third system cache indexing policy.

[0024] Optionally, data interaction is performed between the first processor and the second processor through the system-level cache using a third system cache indexing policy, including:

[0025] If the service data stream cannot be core-cleaned and the first processor can access the cache, determine the data identifier corresponding to the service data stream according to the data type of the service data stream;

[0026] Determine the system cache indexing sub-policy corresponding to the data identifier from the third system cache indexing policy;

[0027] Data interaction is performed between the first processor and the second processor through the system-level cache using the system cache indexing sub-policy.

[0028] Optionally, determining the data identifier corresponding to the service data stream according to the data type corresponding to the service data stream includes:

[0029] If the data type corresponding to the service data stream is the write-and-discard type, the cache state at the system level corresponding to the data identifier of the service data stream is the core cleaning state;

[0030] If the data type corresponding to the service data stream is not the write-and-discard type, the cache state at the system level corresponding to the data identifier of the service data stream is the dirty state or the clean state.

[0031] Optionally, data interaction between the first processor and the second processor through the system-level cache using the system cache indexing sub-strategy includes:

[0032] The first processor writes the first service data stream into the system-level cache using the first system cache indexing sub-strategy corresponding to the write data identifier; or,

[0033] The first processor reads the second service data stream stored in the system-level cache using the second system cache indexing sub-strategy corresponding to the read data identifier, where the second service data stream is the service data stream written into the system-level cache by the second processor.

[0034] Optionally, the method further includes:

[0035] If the service data stream cannot be core-cleaned and the first processor cannot access the cache, data interaction between the first processor and the second processor is performed through the system-level cache using the fourth system cache indexing policy.

[0036] Optionally, the first processor or the second processor is any one of the following processors:

[0037] Central processing unit;

[0038] Graphics processing unit.

[0039] To achieve the above object, an embodiment of the second aspect of the present disclosure provides a data interaction device, including:

[0040] A data monitoring unit for monitoring the service data stream used when data interaction occurs between the first processor and the second processor;

[0041] A data interaction unit for, if the service data stream does not meet the processor performance requirements, performing data interaction between the first processor and the second processor using a hardware management strategy;

[0042] The data interaction unit is further configured to, if the service data stream meets the processor performance requirements, perform data interaction between the first processor and the second processor using a software management policy.

[0043] To achieve the above object, an embodiment of the third aspect of the present disclosure provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0044] The memory stores computer-executable instructions;

[0045] The processor executes the computer-executable instructions stored in the memory to implement the method shown in any one of the foregoing first aspects.

[0046] To achieve the above object, an embodiment of the fourth aspect of the present disclosure provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method shown in any one of the foregoing first aspects.

[0047] To achieve the above object, an embodiment of the fifth aspect of the present disclosure provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the method shown in any one of the foregoing first aspects.

[0048] In summary, the method, device, electronic device, and storage medium provided by the present disclosure monitor the service data stream used for data interaction between the first processor and the second processor; if the service data stream does not meet the processor performance requirements, hardware management policy is used for data interaction between the first processor and the second processor; if the service data stream meets the processor performance requirements, software management policy is used for data interaction between the first processor and the second processor. Therefore, by analyzing based on scenarios and adopting different policies for data interaction according to performance, the pertinence is stronger, the power consumption and performance of the processor can be balanced, and the data interaction effect can be improved.

[0049] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, where:

[0051] Figure 1 is a schematic structural diagram of a computing device system provided by an embodiment of the present disclosure;

[0052] Figure 2 is a schematic flowchart of an existing data interaction provided by an embodiment of the present disclosure;

[0053] Figure 3 A flowchart of a data interaction method provided by an embodiment of the present disclosure;

[0054] Figure 4 A flowchart of a data interaction provided by an embodiment of the present disclosure;

[0055] Figure 5 A flowchart of a data interaction provided by an embodiment of the present disclosure;

[0056] Figure 6 A schematic structural diagram of a data interaction device provided by an embodiment of the present disclosure. Detailed implementation manners

[0057] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation of the present disclosure.

[0058] With the development of science and technology, computing device systems such as servers, mobile and desktop processors include multiple processors. Such heterogeneous architectures pose challenges to programmability, and how to effectively synchronize and communicate within and between processors has become the focus of attention.

[0059] In the related art, synchronization and communication within and between processors can be achieved by exposing a global shared memory interface on processors and accelerators. Shared memory can not only increase programmability by providing an intuitive load-store interface for communication, but also help obtain the benefits of locality through programmer-transparent caching.

[0060] Through shared memory, different types of processors can be tightly integrated and actually share the same physical memory, just like in the case of a mobile system-on-chip (SoC), or they may have physically independent memories that provide a logical abstraction of shared memory at runtime.

[0061] Figure 1 A schematic structural diagram of a computing device system provided by an embodiment of the present disclosure. As Figure 1As shown, each Central Processing Unit (CPU), Graphic Processing Unit (GPU), and Accelerator may have multiple cores, and each core has a private Level 1 Cache (L1) and a shared Level 2 Cache (L2). The CPU and the Accelerator can also share the Last Level Cache (LLC) on the memory side, which is non-inclusive unless otherwise specified.

[0062] However, sharing memory also brings a series of problems, such as what consistency model to adopt, how to (effectively) implement the consistency model, especially how the caches within a processor (between L1s) and between processors (L1 and L2) maintain consistency?

[0063] For example, the CPU and GPU need to meet the following characteristics:

[0064] A strict and intuitive memory consistency model that allows synchronization between all threads;

[0065] A cache coherence protocol that can implement the memory consistency model, allowing efficient data sharing and synchronization, and maintaining the simplicity of the conventional GPU architecture, because the main task of the GPU is still the graphics workload.

[0066] In related technologies, a method similar to that of a multi-core CPU can be used to achieve cache coherence, using a protocol independent of the memory model. However, this method is not applicable to the GPU for two main reasons:

[0067] First, a cache coherence protocol similar to that of the CPU will generate a high communication overhead in the GPU environment, because the total capacity of the L1 cache is usually comparable to or even larger than that of the L2, resulting in a large area overhead and a very complex design; second, since the GPU maintains thousands of active hardware threads, a corresponding number of coherence transactions need to be tracked, requiring a large amount of hardware overhead.

[0068] For example, in a game scenario, when the GPU and the CPU complete data interaction in the DDR, due to the large latency of accessing the DDR and the limited bandwidth, the game experience of the GPU is affected.

[0069] Figure 2 A schematic diagram of the process of an existing data interaction provided for the embodiments of the present disclosure. As Figure 2As shown, by introducing a SystemLevelCache (SLC) at the system level as a data interaction intermediary, the gaming experience of the GPU is improved. However, when the SLC is introduced, for the data interaction between the GPU and the CPU, it is necessary to consider how to maintain data consistency, which usually involves software management strategies and hardware management strategies.

[0070] Among them, the consistency of the software management strategy is a traditional solution to the data sharing problem. Here, the software (usually the device driver) must clear or refresh the dirty data in the cache and invalidate the old data in order to share it with other processors or master devices in the system. This requires processor cycles, bus bandwidth, and power.

[0071] The consistency of the hardware management strategy provides an alternative to simplify the software. Using this solution, any cached data marked as "shared" will always be automatically updated. All processors and bus masters in this shared domain see exactly the same value.

[0072] In summary, both the software management strategy and the hardware management strategy have their own advantages and disadvantages. During the interaction between processors, how to integrate the software management strategy and the hardware management strategy to improve the data interaction effect has become the focus of attention.

[0073] The following will describe the present disclosure in detail with specific embodiments.

[0074] In the first embodiment, as Figure 3 shown, Figure 3 is a schematic flowchart of a data interaction method provided by an embodiment of the present disclosure. This method can be implemented depending on a computer program and can run on a device for data interaction. This computer program can be integrated into an application or run as an independent tool class application.

[0075] Among them, the data interaction device can be an electronic device with data interaction capabilities.

[0076] Among them, this data interaction method can be executed by an electronic device, and the electronic device includes but is not limited to a first processor, a second processor, the cloud, etc.

[0077] Specifically, this data interaction method includes the following steps:

[0078] S101, monitor the service data stream used when data is interacted between the first processor and the second processor;

[0079] According to some embodiments, the processor includes, but is not limited to, a CPU, an accelerator, etc. Among them, the accelerator can be regarded as an auxiliary processor, which reduces the burden on the main processor by performing some complex computing tasks. The accelerator includes, but is not limited to, a GPU, a Digital Signal Processor (DSP), an artificial intelligence accelerator (such as a neural engine, a Tensor Processing Unit (TPU), etc.), a cryptographic accelerator, a Field-Programmable Gate Array (FPGA), etc.

[0080] In some embodiments, the service data stream refers to the data used during the flow between a first processor and a second processor in a service process.

[0081] S102, if the service data stream does not meet the processor performance requirements, then the first processor and the second processor use a hardware management strategy for data interaction;

[0082] According to some embodiments, the processor performance requirements refer to the requirements used to determine whether the service data stream has an impact on the performance of the processor.

[0083] For example, when the data volume corresponding to the service data stream is greater than the data volume threshold, the service data stream does not meet the processor performance requirements; when the data volume corresponding to the service data stream is not greater than the data volume threshold, the service data stream meets the processor performance requirements. Or, when the service data stream has an impact on the Power, Performance, Area (PPA) corresponding to the processor, the service data stream does not meet the processor performance requirements; when the service data stream has no impact on the PPA corresponding to the processor, the service data stream meets the processor performance requirements.

[0084] S103, if the service data stream meets the processor performance requirements, then the first processor and the second processor use a software management strategy for data interaction.

[0085] In summary, for the method provided in this embodiment, due to power consumption considerations, instead of adopting a fully coherent manner similar to Atomic Components and Elements (ACE) / Coherent Hub Interface (CHI), through scenario analysis, the data interaction policy is modified under a non-coherent bus architecture, which is more targeted and can balance the power consumption and performance of the processor, thereby improving the data interaction effect. Additionally, by integrating the hardware management policy with the software management policy according to the processor performance requirements, the power consumption and performance of the processor can be balanced, and the data interaction effect can be improved.

[0086] This embodiment also provides another data interaction method. This method can be executed by an electronic device. The electronic device includes but is not limited to a first processor, a second processor, the cloud, etc.

[0087] Specifically, the data interaction method may include the following steps:

[0088] S201, monitor the service data stream used when data is interacted between the first processor and the second processor;

[0089] According to some embodiments, in the case of introducing SLC, the service data stream refers to the SLC service data stream.

[0090] S202, determine whether the service data stream meets the processor performance requirements;

[0091] According to some embodiments, when determining whether the service data stream meets the processor performance requirements by determining whether the service data stream affects PPA, it can be determined whether the service data stream affects PPA by combining the application scenario, for example, mobile phone benchmark scores, system fluency, software experience, etc.; it can also directly set whether the service data stream corresponding to a certain application scenario affects PPA; it can also determine whether the service data stream affects PPA according to the PPA-related threshold parameters.

[0092] S203, if the service data stream meets the processor performance requirements, then use the software management policy for data interaction between the first processor and the second processor;

[0093] According to some embodiments, the software management policy can be, for example, a cache disabling policy. The cache disabling policy is the simplest software management policy, which prohibits the use of SLC and directly enables data interaction between the first processor and the second processor through DDR. However, it may significantly reduce the performance of the first processor and the second processor. To achieve the highest performance, the processor runs at a high frequency through a pipeline and runs from a cache that provides extremely low latency. Caching frequently accessed data can significantly improve performance and reduce Dynamic Random Access Memory (DRAM) access and power consumption. Marking data as "non-cacheable" may affect performance and power consumption.

[0094] Taking a scenario as an example, in the case of data sharing between the CPU and the GPU, during the process of GPU writing and CPU reading, the data interaction is less than the data interaction threshold, the data interaction is small, and the impact of the service data stream on performance is limited, meeting the processor performance requirements. Therefore, data interaction can be carried out by disabling the cache.

[0095] In some embodiments, Figure 4 FIG. is a schematic flow diagram of data interaction provided by an embodiment of the present disclosure. As Figure 4 shown, for GPU writing and CPU reading, a strategy of completely bypassing the SLC is adopted, and data is directly interacted through DDR. After the GPU write operation is completed, the CPU is notified by software, such as an interruption. After receiving the interruption, the CPU reads the new data from the DDR.

[0096] S204, if the service data stream does not meet the processor performance requirements, then determine whether the service data stream meets the data caching requirements;

[0097] According to some embodiments, the data caching requirements refer to the requirements adopted when determining whether the SLC can be used. For example,

[0098] if the service data stream is shared data and the service data stream is non-cacheable data, then the service data stream does not meet the data caching requirements;

[0099] if the service data stream is non-sharable data, then the service data stream meets the data caching requirements;

[0100] if the service data stream is shared data and the service data stream is cacheable data, then the service data stream meets the data caching requirements.

[0101] Among them, shared data refers to data that can be accessed and used simultaneously by multiple users, processes, or devices. Cacheable data refers to data that can be stored in a cache.

[0102] S205. If the service data stream does not meet the data caching requirements, data interaction between the first processor and the second processor is performed through a double data rate synchronous dynamic random access memory.

[0103] According to some embodiments, the interaction method during the data interaction between the first processor and the second processor through DDR can be the same as the software management strategy. Specifically, reference can be made to step S203, which will not be repeated here.

[0104] S206. If the service data stream meets the data caching requirements, data interaction between the first processor and the second processor is performed through a system-level cache.

[0105] According to some embodiments, during the data interaction through the system-level cache, multiple system cache index (SCID) strategies can be adopted for data interaction. The SCID strategy involves replacement algorithms / capacities, etc. Therefore, the effect of data interaction can be improved.

[0106] Among them, the index corresponding to the service data stream can be determined, and then the SCID strategy corresponding to the index can be determined. The index and the SCID strategy are in one-to-one correspondence. The index includes but is not limited to an index indicating that the service data stream is non-shareable data, an index indicating that the service data stream is shareable data and there is no cache hit for the service data stream in the system-level cache, an index indicating that the service data stream is shareable data and there is a cache hit for the service data stream in the system-level cache, etc.

[0107] In some embodiments, if the service data stream is non-shareable data, data interaction between the first processor and the second processor is performed through the system-level cache using the first system cache index strategy.

[0108] If the service data stream is shareable data and there is no cache hit for the service data stream in the system-level cache, data interaction between the first processor and the second processor is performed through the system-level cache using the second system cache index strategy.

[0109] If the service data stream is shareable data and there is a cache hit for the service data stream in the system-level cache, data interaction between the first processor and the second processor is performed through the system-level cache using the third system cache index strategy.

[0110] Among them, cache hit means that when the processor needs to access a certain data or instruction, the corresponding data or instruction can be found in the cache, thus avoiding reading data from a lower-level memory (such as the main memory or the hard disk). Cache hit can significantly improve the performance of the computer because the speed of accessing the cache is usually much faster than accessing the main memory or the hard disk.

[0111] According to some embodiments, in the process of data interaction through system-level caching using the third system cache indexing policy, if the service data stream cannot be core-cleaned and the first processor can access the cache, determine the data identifier corresponding to the service data stream according to the data type of the service data stream; determine the system cache indexing sub-policy corresponding to the data identifier from the third system cache indexing policy; the first processor and the second processor perform data interaction through the system-level cache using the system cache indexing sub-policy.

[0112] In some embodiments, Coreclean means core + clean, which is used to represent the state of the cache line belonging to the processor core. Clean means that the data in the cache is the same as that in the DDR.

[0113] In some embodiments, cache access refers to the process in which a processor attempts to obtain data from the cache (Cache) when it needs to read or write data.

[0114] According to some embodiments, the data identifier is used to identify different system-level cache states. System-level cache states include but are not limited to miss state, Clean state, Dirty state, Coreclean state, etc. Among them, the miss state specifically refers to the invalid state of the SLC cache line, the Clean state means that the SLC cache line is consistent with the DDR data, the Dirty state means that the data in the SLC cache line is new and the data in the DDR is old, and the Coreclean state means that the SLC cache line is the data that is written and evicted by the CPU. Therefore, in the case of the complexity of consistency maintenance caused by multiple levels of caches inside the processor, by introducing multiple system-level cache states, the behavior of data interaction can be analyzed in detail, and the effect of data interaction can be improved.

[0115] For example, if the data type corresponding to the service data stream is the write-evict type, the system-level cache state corresponding to the data identifier of the service data stream is the core-clean state; if the data type corresponding to the service data stream is not the write-evict type, the system-level cache state corresponding to the data identifier of the service data stream is the Dirty state or the Clean state.

[0116] Among them, if the service data stream can be core-cleaned, the processor can handle it according to the miss state and read new data from the DDR.

[0117] In some embodiments, when the first processor writes data to the SLC, the data identifier used is the write data identifier. At this time, the first processor writes the first service data stream to the system-level cache using the first system cache index sub-policy corresponding to the write data identifier.

[0118] In some embodiments, when the first processor reads data from the SLC, the data identifier used is the read data identifier. At this time, the first processor reads the second service data stream stored in the system-level cache using the second system cache index sub-policy corresponding to the read data identifier, where the second service data stream is the service data stream written to the system-level cache by the second processor.

[0119] It is easy to understand that by introducing the data type and the system-level cache state, such as coreclean and writeevict, and describing the role played by the data type and the system-level cache state during data sharing, the accuracy of data interaction can be improved. Without the data type and the system-level cache state, when processors share data, they may access data in non-shared areas. With the cooperation of the data type and the system-level cache state, it can be ensured that there are no problems with data sharing between processors.

[0120] According to some embodiments, the SCID policy may further include a fourth system cache index policy. If the service data stream cannot be core-cleaned and the first processor cannot access the cache, the first processor and the second processor use the fourth system cache index policy to perform data interaction through the system-level cache.

[0121] In some embodiments, the first system cache index policy, the second system cache index policy, the third system cache index policy, and the fourth system cache index policy do not specifically refer to a certain fixed policy and can be adjusted according to the actual application scenario.

[0122] Taking a scenario as an example, in the case of data sharing between the CPU and the GPU, during the process of CPU writing and GPU reading, the data interaction is not less than the data interaction threshold, the data interaction is relatively large, and the service data stream affects the performance and does not meet the processor performance requirements. Therefore, data interaction can be performed through the hardware management policy.

[0123] In some embodiments, Figure 5 is a schematic flowchart of a data interaction provided by an embodiment of the present disclosure. As Figure 5 shown, for GPU writing and CPU reading, when using the hardware management policy, the write operation is not performed in the way of disabling the cache because of low efficiency. Therefore, the write operation is performed in a cacheable way, that is, the data needs to pass through the SLC.

[0124] Among them, for the operation of the CPU writing to the SLC, the appropriate type is the writeevict type. After introducing coreclean, when the SLC receives a write operation of the writeevict type sent by the CPU, the SLC can perform the following operations:

[0125] When the data tag is Miss and allocated (alloc), the SLC state is coreclean. At this time, for incomplete data, the remaining data is read from the DDR, merged and allocated in the cache; for complete data, it is written to the device memory (DMEM); otherwise, it is written to the DDR.

[0126] When the data tag is Hit and coreclean, the SLC state is coreclean. At this time, the cache line is overwritten by strb, where strb is used to determine whether the write operation is complete.

[0127] When the data tag is Hit and clean, the SLC state is clean. At this time, the cache line is overwritten by strb.

[0128] When the data tag is Hit and dirty, the SLC state is dirty. At this time, the cache line is overwritten by strb.

[0129] Among them, after the operation of the CPU writing to the SLC, during the process of the GPU reading the data written by the CPU to the SLC, the SLC can perform the following operations:

[0130] When the data type is read instead of allocated, if the data tag is Miss, the SLC state is Invalid. The SLC reads the data from the DDR and returns the data to the GPU without allocation.

[0131] When the data type is read instead of allocated, if the data tag is Hit and coreclean, the SLC state is clean. The SLC reads the data from the DDR, overwrites the cache line, and returns the data to the GPU.

[0132] When the data type is read instead of allocated, if the data tag is Hit and clean, the SLC state is clean. The SLC restores the data and retains the cache line.

[0133] When the data type is read instead of allocated, if the data tag is Hit and dirty, the SLC state is dirty. The SLC restores the data and retains the cache line.

[0134] When the data type is read allocation, if the data identifier is Miss, the SLC status is clean. The SLC reads data from the DDR, returns the data to the GPU, and performs allocation.

[0135] When the data type is read allocation, if the data identifier is Hit, coreclean, the SLC status is clean. The SLC reads data from the DDR, overwrites the cache line, and returns the data to the GPU.

[0136] When the data type is read allocation, if the data identifier is Hit, clean, the SLC status is clean. The SLC restores the data and retains the cache line.

[0137] When the data type is read allocation, if the data identifier is Hit, dirty, the SLC status is dirty. The SLC restores the data and retains the cache line.

[0138] When the data type is read hit clear, if the data identifier is Miss, the SLC status is Invalid. The SLC reads data from the DDR, returns the data to the GPU, and does not perform allocation.

[0139] When the data type is read hit clear, if the data identifier is Hit, coreclean, the SLC status is clean. The SLC reads data from the DDR, overwrites the cache line, and returns the data to the GPU.

[0140] When the data type is read hit clear, if the data identifier is Hit, clean, the SLC status is clean. The SLC restores the data and retains the cache line.

[0141] When the data type is read hit clear, if the data identifier is Hit, dirty, the SLC status is clean. The SLC returns the data to the GPU and clears the cache line to the DDR.

[0142] When the data type is read hit unlock, if the data identifier is Miss, the SLC status is Invalid. The SLC reads data from the DDR, returns the data to the GPU, and does not perform allocation.

[0143] When the data type is read hit unlock, if the data identifier is Hit, coreclean, the SLC status is Invalid. The SLC reads data from the DDR, invalidates the cache line, and returns the data to the GPU.

[0144] When the data type is read hit unlock, if the data identifier is Hit, clean, the SLC status is Invalid. The SLC returns the data to the GPU and invalidates the cache line.

[0145] When the data type is read hit unlock, if the data identifier is Hit, dirty, the SLC status is Invalid, and the SLC will return the data to the GPU, clear and invalidate the cache line to the DDR.

[0146] In summary, the method provided by the embodiments of the present disclosure can balance the power consumption and performance of the processor and improve the data interaction effect by integrating the hardware management policy of the software management policy according to the processor performance requirements. Secondly, in the hardware management policy, by introducing conditions such as data cache requirements, data types, and system-level cache status, the accuracy of the hardware management policy adopted when determining data interaction can be improved, and the accuracy of data interaction can be improved.

[0147] To implement the above embodiments, the present disclosure also proposes a data interaction device.

[0148] As Figure 6 shown, the data interaction device 600 includes:

[0149] A data monitoring unit 601 for monitoring the service data stream used when data is interacted between the first processor and the second processor;

[0150] A data interaction unit 602 for, if the service data stream does not meet the processor performance requirements, using a hardware management policy for data interaction between the first processor and the second processor;

[0151] The data interaction unit 602 is further configured to, if the service data stream meets the processor performance requirements, use a software management policy for data interaction between the first processor and the second processor.

[0152] Optionally, when the data interaction unit 602 is used for data interaction between the first processor and the second processor using a hardware management policy, it is specifically configured to:

[0153] If the service data stream does not meet the data cache requirements, data interaction between the first processor and the second processor is performed through a double data rate synchronous dynamic random access memory;

[0154] If the service data stream meets the data cache requirements, data interaction between the first processor and the second processor is performed through a system-level cache.

[0155] Optionally, the data interaction unit 602 is further configured to:

[0156] If the service data stream is shared data and the service data stream is non-cacheable data, then the service data stream does not meet the data cache requirements;

[0157] If the service data stream is non-shareable data, then the service data stream meets the data cache requirements;

[0158] If the service data stream is shared data and the service data stream is cacheable data, then the service data stream meets the data caching requirements.

[0159] Optionally, when the data interaction unit 602 is used for data interaction between the first processor and the second processor through the system-level cache, it is specifically used for:

[0160] If the service data stream is non-shareable data, then the first processor and the second processor perform data interaction through the system-level cache using the first system cache indexing policy;

[0161] If the service data stream is shared data and there is no cache hit in the system-level cache for the service data stream, then the first processor and the second processor perform data interaction through the system-level cache using the second system cache indexing policy;

[0162] If the service data stream is shared data and there is a cache hit in the system-level cache for the service data stream, then the first processor and the second processor perform data interaction through the system-level cache using the third system cache indexing policy.

[0163] Optionally, when the data interaction unit 602 is used for data interaction between the first processor and the second processor through the system-level cache using the third system cache indexing policy, it is specifically used for:

[0164] If the service data stream cannot be core-cleared and the first processor can access the cache, then determine the data identifier corresponding to the service data stream according to the data type of the service data stream;

[0165] Determine the system cache indexing sub-policy corresponding to the data identifier from the third system cache indexing policy;

[0166] The first processor and the second processor perform data interaction through the system-level cache using the system cache indexing sub-policy.

[0167] Optionally, when the data interaction unit 602 is used to determine the data identifier corresponding to the service data stream according to the data type of the service data stream, it is specifically used for:

[0168] If the data type corresponding to the service data stream is the write-and-evict type, then the system-level cache status corresponding to the data identifier of the service data stream is the core-cleared status;

[0169] If the data type corresponding to the service data stream is not the write-and-evict type, then the system-level cache status corresponding to the data identifier of the service data stream is the dirty status or the clean status.

[0170] Optionally, when the data interaction unit 602 is used for data interaction between the first processor and the second processor through the system-level cache using the system cache indexing sub-strategy, it is specifically used for:

[0171] The first processor writes the first service data stream into the system-level cache by using the first system cache indexing sub-strategy corresponding to the write data identifier; or,

[0172] The first processor reads the second service data stream stored in the system-level cache by using the second system cache indexing sub-strategy corresponding to the read data identifier, where the second service data stream is the service data stream written into the system-level cache by the second processor.

[0173] Optionally, the data interaction unit 602 is further used for:

[0174] If the service data stream cannot be core-cleared and the first processor cannot access the cache, data interaction is performed between the first processor and the second processor through the system-level cache using the fourth system cache indexing policy.

[0175] Optionally, the first processor or the second processor is any one of the following processors:

[0176] Central processing unit;

[0177] Graphics processing unit.

[0178] It should be noted that the foregoing explanation of the data interaction method embodiment also applies to the data interaction device of this embodiment, and will not be elaborated here.

[0179] In summary, the device provided in the embodiments of the present disclosure, through scenario analysis and considering power consumption, does not adopt a completely consistent manner similar to ACE / CHI, but modifies the data interaction strategy under a non-uniform bus architecture, which is more targeted, and can balance the power consumption and performance of the processor, and can improve the data interaction effect. In addition, by integrating the hardware management strategy of the software management strategy according to the processor performance requirements, the power consumption and performance of the processor can be balanced, and the data interaction effect can be improved.

[0180] To implement the above embodiments, the present disclosure also proposes an electronic device, including: a processor, and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0181] To implement the above embodiments, the present disclosure also proposes a computer-readable storage medium storing computer execution instructions, which are used to implement the method provided in the foregoing embodiments when executed by a processor.

[0182] To implement the above embodiments, the present disclosure also provides a computer program product, including a computer program which, when executed by a processor, implements the method provided in the foregoing embodiments.

[0183] The collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved in the present disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0184] It should be noted that personal information from users should be collected for legal and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after obtaining the informed consent of the user, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization including authorizing relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others with access to the personal information data comply with their privacy policies and procedures.

[0185] The present disclosure anticipates providing embodiments that allow users to selectively block the use or access of personal information data. That is, the present disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, the risk can be minimized by restricting data collection and deleting the data. In addition, when applicable, personal identifiers are removed from such personal information to protect the privacy of the user.

[0186] In the description of the foregoing embodiments, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0187] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0188] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logic function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations where functions may be executed not in the order shown or discussed, including in a substantially simultaneous manner according to the associated functions or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0189] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing a logical function, and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection having one or more wires (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained, for example, electronically by optically scanning the paper or other medium, followed by editing, interpretation, or otherwise appropriate processing if necessary, and then stored in a computer memory.

[0190] It should be understood that various parts of the present disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following techniques known in the art or a combination thereof can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), and the like.

[0191] Those of ordinary skill in the art can understand that all or part of the steps carried out in the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0192] In addition, in each of the various embodiments of the present disclosure, each functional unit may be integrated in a processing module, may exist physically separately for each unit, or two or more units may be integrated in a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0193] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A data interaction method, characterized in that, Including: Monitoring the service data stream used when data is exchanged between the first processor and the second processor; If the service data stream does not meet the processor performance requirements, the first processor and the second processor use a hardware management strategy for data exchange; If the service data stream meets the processor performance requirements, the first processor and the second processor use a software management strategy for data exchange.

2. The method according to claim 1, characterized in that, The first processor and the second processor use a hardware management strategy for data exchange, including: If the service data stream does not meet the data cache requirements, the first processor and the second processor perform data exchange through a double data rate synchronous dynamic random access memory; If the service data stream meets the data cache requirements, the first processor and the second processor perform data exchange through a system-level cache.

3. The method according to claim 2, characterized in that, The method further includes: If the service data stream is shared data and the service data stream is non-cacheable data, then the service data stream does not meet the data cache requirements; If the service data stream is non-shareable data, then the service data stream meets the data cache requirements; If the service data stream is the shared data and the service data stream is cacheable data, then the service data stream meets the data cache requirements.

4. The method according to claim 2, wherein The first processor and the second processor perform data exchange through a system-level cache, including: If the service data stream is non-shareable data, the first processor and the second processor perform data exchange through the system-level cache using a first system cache indexing strategy; If the service data stream is shared data and there is no cache hit for the service data stream in the system-level cache, the first processor and the second processor perform data exchange through the system-level cache using a second system cache indexing strategy; If the service data stream is shared data and there is a cache hit for the service data stream in the system-level cache, the first processor and the second processor perform data exchange through the system-level cache using a third system cache indexing strategy.

5. The method according to claim 4, wherein The first processor and the second processor perform data exchange through the system-level cache using a third system cache indexing strategy, including: If the service data stream cannot be core-cleared and the first processor can access the cache, determine the data identifier corresponding to the service data stream according to the data type corresponding to the service data stream; Determine the system cache indexing sub-strategy corresponding to the data identifier from the third system cache indexing strategy; The first processor and the second processor perform data exchange through the system-level cache using the system cache indexing sub-strategy.

6. The method according to claim 5, characterized in that, The determining the data identifier corresponding to the service data stream according to the data type corresponding to the service data stream includes: If the data type corresponding to the service data stream is the write-through type, the system-level cache state corresponding to the data identifier corresponding to the service data stream is the core-cleared state; If the data type corresponding to the service data stream is not the write-and-discard type, the system-level cache status corresponding to the data identifier of the service data stream is a dirty status or a clean status.

7. The method according to claim 5, characterized in that The data interaction between the first processor and the second processor through the system-level cache adopts the system cache index sub-strategy, including: The first processor writes the first service data stream into the system-level cache by using the first system cache index sub-strategy corresponding to the write data identifier; or, The first processor reads the second service data stream stored in the system-level cache by using the second system cache index sub-strategy corresponding to the read data identifier, where the second service data stream is the service data stream written into the system-level cache by the second processor.

8. The method according to claim 5, wherein The method further includes: If the service data stream cannot be core-cleaned and the first processor cannot access the cache, the data interaction between the first processor and the second processor through the system-level cache adopts the fourth system cache index policy.

9. The method according to claim 1, wherein The first processor or the second processor is any one of the following processors: Central processing unit; Graphics processing unit.

10. A data interaction device, characterized in that, Including: A data monitoring unit, configured to monitor the service data stream used for data interaction between the first processor and the second processor; A data interaction unit, configured to, if the service data stream does not meet the processor performance requirements, use a hardware management policy for data interaction between the first processor and the second processor; The data interaction unit is further configured to, if the service data stream meets the processor performance requirements, use a software management policy for data interaction between the first processor and the second processor.

11. An electronic device, characterized in that, Including: A processor, and a memory communicatively connected to the processor; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory to implement the method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, Computer execution instructions are stored in the computer-readable storage medium, and when the computer execution instructions are executed by a processor, they are used to implement the method according to any one of claims 1 to 9.

13. A computer program product, characterized in that, Including a computer program, which when executed by a processor implements the method according to any one of claims 1 to 9.

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