Board card and interconnection method

Abstract

The application provides a board card and an interconnection method, which can be applied to the technical field of hardware. The board card comprises at least a first mainboard and a second mainboard. The first mainboard comprises a central processing unit, a mainboard interface, a memory and a management controller which are electrically connected to the central processing unit, and the memory is used for deploying an operating system of the central processing unit; and the second mainboard comprises a first switching interface, a switching unit and a controller which are electrically connected, wherein the first mainboard is arranged on the second mainboard and is electrically connected to the second mainboard through the first switching interface and the mainboard interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware, in particular to a board and a method for interconnection. BACKGROUND

[0002] The central processor is one of the core components of the server, and is of high importance to the normal work of the server. On this basis, the related art mainly manufactures the server around the architecture of the central processor. In this way, the manufactured server has high dependence on the central processor, and is difficult to adapt to central processors of various architectures. SUMMARY

[0003] In view of the above problems, the present application provides a board and a method for interconnection.

[0004] According to a first aspect of the present application, a board is provided, comprising at least a first mainboard and a second mainboard; the first mainboard comprises a central processor, a mainboard interface, a memory and a management controller electrically connected to the central processor, and the memory is used to deploy an operating system of the central processor; and the second mainboard comprises a first switching interface, a switching unit and a controller electrically connected, wherein the first mainboard is arranged on the second mainboard and is electrically connected to the second mainboard through the first switching interface and the mainboard interface.

[0005] A second aspect of the present application provides a method for interconnection executed by the above-mentioned board, comprising: the central processor of the first mainboard interconnecting, based on the memory and the management controller of the first mainboard, the switching unit and the controller of the second mainboard via the mainboard interface of the first mainboard and the first switching interface of the second mainboard.

[0006] According to an embodiment of the present application, the central processor, the mainboard interface electrically connected to the central processor, the management controller and the memory on which the operating system of the central processor is deployed are separately integrated on the first mainboard, and the first switching interface, the switching unit and the controller electrically connected are integrated on the second mainboard. In this way, in the case that the first mainboard is arranged on the second mainboard, the first mainboard can be electrically connected to the second mainboard via the first switching interface and the mainboard interface, so as to serve as a server architecture. On this basis, the present application decouples the complete server architecture into the first mainboard and the second mainboard, and can realize replacement of the first mainboard. In this case, the first mainboard of different architectures can be electrically connected to the second mainboard, thereby realizing the compatibility of the second mainboard to the first mainboard of different architectures, i.e. the compatibility of the server architecture to the central processor of different architectures, so that the server adapts to the central processor of different architectures. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A schematic diagram of a board card according to a first embodiment of the present application is shown.

[0009] Figure 2 A schematic diagram of a first main board according to an embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of a first main board and a second main board according to a first embodiment of the present application is shown.

[0011] Figure 4 A schematic diagram of a first main board and a second main board according to a second embodiment of the present application is shown.

[0012] Figure 5 A schematic diagram of a first main board and a second main board according to a third embodiment of the present application is shown.

[0013] Figure 6 A schematic diagram of a first main board and a second main board according to a fourth embodiment of the present application is shown.

[0014] Figure 7A A schematic diagram of a board card and a remote server interconnection according to a first embodiment of the present application is shown.

[0015] Figure 7B A schematic diagram of a board card and a remote server interconnection according to a second embodiment of the present application is shown.

[0016] Figure 8A A connection diagram of a controller according to an embodiment of the present application is shown.

[0017] Figure 8B A connection diagram of a controller according to an embodiment of the present application is shown.

[0018] Figure 9 A schematic diagram of an interconnection method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present application and is not intended to limit the scope of the present application. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that one or more embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "comprising" or "comprises" is used in the sense of "including" or "includes" and not in the sense of "consisting only of" or "consists only of."

[0021] All terms used herein including technical and scientific terms have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the use of certain terms or phrases in various places in the specification is not intended to exclude the use of other terms or phrases that could be substituted therefor.

[0022] In situations where similar terminology is used for similar but not identical conditions (e.g., "at least one of A, B, and C" is used interchangeably with "at least one of A, B, or C"), it will be understood that the meaning is intended to be consistent with the meaning of the terminology as understood by one of ordinary skill in the art unless otherwise indicated.

[0023] It should be noted that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. The terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements. The terms "parallel", "perpendicular", "equal" include the described case and the approximate case similar to the described case, and the approximate case is within an acceptable deviation range, wherein the acceptable deviation range is determined by considering the measurement being discussed and the error related to the measurement of a specific quantity (i.e. the limitation of the measurement system) by a person skilled in the art. For example, "parallel" includes absolute parallel and approximate parallel, wherein the acceptable deviation range of approximate parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximate perpendicular, wherein the acceptable deviation range of approximate perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, less than or equal to 5% of the difference between the two equalities. For a person skilled in the art, the specific meaning of the above terms in the present application can be understood in specific cases.

[0024] In some schemes, the hardware architecture of the server is to take a large central processing unit (CPU) motherboard as the bottom plate, and various devices are designed based on the capability of the central processing unit to realize different functions. In this way, the performance of the device is limited by the parameters of the motherboard. On this basis, after the production of the server, the central processing unit is tightly bound with the hardware system of the server, and it is difficult to make the server compatible with different architectures. In this way, if the motherboard is damaged, more devices need to be replaced, and more resources are consumed. Moreover, the computing performance and data processing capacity of the server are limited by the central processing unit. In this case, once the server is deployed, when the processing capacity is insufficient, it is necessary to increase the server or replace a higher level server, which also faces the problems of complex operation and increased resource consumption. In addition, the server relies too much on a single manufacturer's series of central processing units, and once there are unexpected problems such as supply difficulties or natural disasters, the server products corresponding to the central processing units will face production difficulties.

[0025] To solve the above problems, the application provides a design scheme of a new server architecture, so that the basic circuit of the first motherboard deploying the central processor is designed on a physical card, and the first motherboard can be applied to various scenes as a flexible and expandable expansion card like a computing card. In this way, the central processor of the server system becomes a replaceable component, which is no longer limited to a central processor of a fixed architecture, and is no longer limited to a certain manufacturer and system.

[0026] Figure 1 A schematic diagram of a board card according to the first embodiment of the application is shown.

[0027] As shown in Figure 1 The board card of this embodiment at least includes a first motherboard B1 and a second motherboard B2. It should be understood that the board card of the embodiment of the application can also include other motherboards electrically connected to at least one of the first motherboard B1 and the second motherboard B2, which is not limited in the application.

[0028] The first motherboard B1 can include a central processor 110. The central processor 110 is the core component of the server, responsible for processing computing tasks and running programs. For example, the first motherboard B1 can also include other devices, and the central processor 110 can be electrically connected to and interconnected with other devices on the first motherboard B1 to complete tasks. For example, the central processor 110 of the first motherboard B1 can belong to the X86 architecture, and the embodiment of the application is not limited thereto, and the central processor 110 of the first motherboard B1 can also belong to a non-X86 architecture, such as a microprocessor without interlocked pipeline stages (MIPS) architecture, an Alpha architecture, an advanced RISC machine (ARM) architecture, or a RISC-V architecture, etc. In addition, the central processor 110 can support multiple memory slot sockets to expand the memory.

[0029] The first motherboard B1 can further include a memory 130 electrically connected to the central processor 110, which can be arranged on the above-mentioned memory slot. The memory 130 can serve as the memory of the central processor 110 to store programs and data. The central processor 110 can perform read or write operations on the memory 130 to write data to the memory 130 or read data from the memory 130. The memory 130 can be deployed with an operating system of the central processor 110 to support normal operation of the central processor 110. In this way, the central processor 110 can perform tasks such as computing tasks based on the operating system deployed by the memory 130. The memory 130 can be an M.2 solid state drive (SSD) supporting the M.2 protocol. However, it should be understood that the embodiments of the present application are not limited thereto, and in other embodiments of the present application, a hard disk supporting other protocols can also be used. In addition, the memory 130 can also store other data, such as the results of computing tasks, and the like.

[0030] The first motherboard B1 can further include a management controller 120 electrically connected to the central processor 110. For example, the management controller 120 can be a baseboard management controller (Baseboard Management Controller). The management controller 120 can send task instructions to the central processor 110 to enable the central processor 110 to perform various tasks such as computing tasks based on the task instructions. In addition, the management controller 120 can also collect log information and other information of the central processor 110 to monitor the working state of the central processor 110, and the like, which are not limited by the present application. Similarly to the foregoing description, the management controller 120 can be adapted to the X86 architecture, for example, the central processor 110 can be sent instructions in this architecture to enable the central processor 110 to perform tasks. Moreover, the embodiments of the present application are not limited thereto, and the central processor of the first motherboard B1 can also belong to a non-X86 architecture, such as the MIPS architecture, the Alpha architecture, the ARM or RISC-V architecture, and the like.

[0031] The first motherboard B1 can further include a motherboard interface 140 electrically connected to the central processor 110. The first motherboard B1 can be electrically connected to the second motherboard B2 through the motherboard interface 140, thereby realizing the interconnection of the devices of the first motherboard B1 and the devices of the second motherboard B2. However, it should be understood that the embodiments of the present application are not limited thereto, and in other embodiments of the present application, the first motherboard B1 can also be provided with an interface electrically connected to other external devices, which are not limited by the present application.

[0032] The second mainboard B2 can include a first switching interface 221. For example, the first switching interface 221 can support a Peripheral Component Interconnect Express (PCIE) protocol. In the case that the first mainboard B1 is disposed on the second mainboard B2, the mainboard interface 140 of the first mainboard B1 can be electrically connected with the first switching interface 221 of the second mainboard B2, so as to realize the electrical connection between the first mainboard B1 and the second mainboard B2. For example, the first switching interface 221 of the second mainboard B2 can be provided in the form of a slot. The mainboard interface 140 of the first mainboard B1 can be designed in the form of a golden finger. In this way, the electrical connection can be realized in the form of plugging by inserting the mainboard interface 140 of the first mainboard B1 into the first switching interface 221 of the second mainboard B2, so that the first mainboard B1 can be fixed on the second mainboard B2. It should be understood that the embodiments of the present application are not limited thereto, and the mainboard interface 140 of the first mainboard B1 can also be connected with the first switching interface 221 of the second mainboard B2 in other manners, which will not be described herein.

[0033] The second mainboard B2 can further include a switching unit 210. For example, the switching unit 210 can be a PCIE Switch unit or the like. The switching unit 210 can be electrically connected to the first switching interface 221, and can be interconnected with the central processor 110 via the first switching interface 221 of the second mainboard B2 and the mainboard interface 140 of the first mainboard B1. The switching unit 210 of the second mainboard B2 in the present application can be one or multiple, which is not limited herein.

[0034] The second mainboard B2 can further include a controller 230. For example, the controller 230 can be a programmable controller 230, and specifically can be a Complex Programmable logic device (CPLD) or the like. The controller 230 can also be electrically connected to the first switching interface 221 of the second mainboard B2, so as to be interconnected with the central processor 110 via the first switching interface 221 of the second mainboard B2 and the mainboard interface 140 of the first mainboard B1 in the case that the first mainboard B1 is disposed on the second mainboard B2. Based on this, in the case that the first mainboard B1 is disposed on the second mainboard B2 (for example, is inserted into the first switching interface 221 of the second mainboard B2 in the form of plugging), the first mainboard B1 can be electrically connected to the second mainboard B2, so as to be interconnected with the second mainboard B2. In an embodiment, the controller 230 can also be connected to the switching unit 210, which is not limited herein.

[0035] Based on this, the central processor 110, the mainboard interface 140, the management controller 120 and the memory 130 in which the operating system of the central processor 110 is deployed are separately integrated on the first mainboard B1 to form a minimum system supporting the central processor 110. And the electrically connected first switching interface 221, the switching unit 210 and the controller 230 are integrated on the second mainboard B2. In this way, when the first mainboard B1 is arranged on the second mainboard B2, the first mainboard B1 can be electrically connected to the second mainboard B2 via the first switching interface 221 and the mainboard interface 140, so as to serve as a server architecture. On this basis, the complete server architecture is decoupled into the first mainboard B1 and the second mainboard B2, and the first mainboard B1 can be replaced, in which case the first mainboard B1 of different architectures can be electrically connected to the second mainboard B2, thereby realizing the compatibility of the second mainboard B2 for the first mainboard B1 of different architectures, that is, the compatibility of the server architecture for the central processor 110 of different architectures, so that the server is adapted to the central processor of different architectures.

[0036] Figure 2 A schematic diagram of the first mainboard B1 according to an embodiment of the present application is shown.

[0037] As Figure 2 shown, the first mainboard B1 of this embodiment can include a central processor 110, a management controller 120, a memory 130, a mainboard interface 140, a first expansion interface, a data interface and a power supply. It should be noted that, for the sake of clear illustration Figure 2 of the central processor 110, the management controller 120, the memory 130, the power supply and the interfaces in the first mainboard B1, the connection lines of the central processor 110, the management controller 120, the memory 130, the power supply and the interfaces are not shown. In addition to the aforementioned electrical connection of the central processor 110 to the central processor 110, the management controller 120, the memory 130 and the mainboard interface 140, the central processor 110 can also be electrically connected to the data interface and the first expansion interface arranged on the first mainboard B1. In the present application, the first expansion interface can support protocols such as the multi-channel input / output (MCIO) protocol. Similarly, the second expansion interface and the third expansion interface described later can also support the MCIO protocol for PCIE expansion or CXL (Compute Express Link) expansion, which will not be described hereinafter.

[0038] The data interface can be, but is not limited to, an RJ45 interface, a universal serial bus (USB) interface, or a high definition multimedia interface (HDMI) interface, etc. The data interface can be one or multiple, which is not limited in the application. The data interface can be used to connect external devices. For example, the RJ45 interface can be used to connect remote servers and other devices. The USB interface can be connected to USB external devices, such as a mouse and a keyboard, etc. The HDMI interface can be connected to a display and other devices. In this way, the central processor 110 on the first motherboard B1 can be independently interconnected with external devices via the data interface on the first motherboard B1. The first motherboard B1 as an independent board card can be independently interconnected with other devices, reducing the dependence of the first motherboard B1 and the second motherboard B2, so that the second motherboard B2 can adapt to different architectures of the central processor 110. Based on this, in a typical blade server design, the design architecture of the application is still applicable, and the power module interface design and the interface design of each external expansion device can be designed according to the general connector interface definition, so it can be used with the external devices in the server architecture in the related art. In this way, even if the first motherboard B1 is replaced, it does not affect the expansion function and device compatibility of the server.

[0039] The first expansion interface can be, but is not limited to, a multi-channel input / output interface (Mini Cool Edge I / O, MCIO), etc. The first expansion interface can be one or multiple, which is not limited in the application. For example, the first expansion interface can be electrically connected to the expansion memory 130 to expand the memory of the central processor 110. Specifically, the central processor 110 can write data to the expansion memory 130 via the first expansion interface, or read the data stored in the expansion memory 130. For example, the expansion memory 130 can be a hard disk and other memories 130, specifically, it can be a hard disk arranged on a hard disk backplane. The data format of the hard disk here needs to be updated due to the different software architectures of the central processor 110. Therefore, it is necessary to choose a data format that can be compatible with different systems as much as possible to avoid the hard disk compatibility problem caused by replacing the first motherboard B1, such as the file allocation table 32 (FAT32) data format, the extended file allocation table file system (exFAT) data format. In addition, it is also possible to replace only the first motherboard B1 belonging to the same architecture as the original first motherboard B1. In this way, the compatible replacement of the first motherboard B1 can also be realized, and the hard disk data on the second motherboard B2 will not change due to the replacement of the first motherboard B1, and the system can still continue to run.

[0040] In addition, the first mainboard B1 can further include a power supply, which can supply power for the central processor 110, the management controller 120, the memory 130, the power supply and the interfaces on the first mainboard B1. In this way, the first mainboard B1 can work independently based on the power supply thereof. It should be noted that, Figure 2 The interfaces shown in the middle are only schematic, and other types, other numbers of interfaces, or adaptive adjustment of the positions of the interfaces can be provided, which are not limited in the present application. Figure 2 The interfaces shown in the middle are only schematic, and other types, other numbers of interfaces, or adaptive adjustment of the positions of the interfaces can be provided, which are not limited in the present application.

[0041] With reference to Figure 2 the management controller 120 is adapted to the architecture of the central processor 110. For example, in the case that the architecture of the central processor 110 belongs to the X86 architecture, the management controller 120 should also be adapted to the X86 architecture of the central processor 110; in the case that the architecture of the central processor 110 belongs to the MIPS architecture, the management controller 120 should also be adapted to the MIPS architecture of the central processor 110; in the case that the architecture of the central processor 110 belongs to the Alpha architecture, the management controller 120 should also be adapted to the Alpha architecture of the central processor 110; in the case that the architecture of the central processor 110 belongs to the ARM architecture, the management controller 120 should also be adapted to the ARM architecture of the central processor 110; in the case that the architecture of the central processor 110 belongs to the RISC-V architecture, the management controller 120 should also be adapted to the RISC-V architecture of the central processor 110, and so on. Specifically, the management controller 120 can send instructions to the central processor 110 through the instruction set under the architecture, so as to make the central processor 110 execute tasks and the like. In this way, by setting the management controller 120 on the first board card which can be adapted to the architecture of the central processor 110, the management controller 120 can be replaced at the same time in the case of replacing the first board card, thereby avoiding the problem that the management controller 120 and the central processor 110 of the server bottom plate are not adapted due to only replacing the central processor 110, reducing the dependence of the second mainboard B2 on the central processor 110, so as to make the second mainboard B2 adapt to the central processor 110 of different architectures.

[0042] Figure 3 A schematic diagram of the first mainboard B1 and the second mainboard B2 according to the first embodiment of the present application is shown.

[0043] As Figure 3 shown, the second mainboard B2 of this embodiment can include a switching unit 210, a first switching interface 221, a second switching interface 222, a clock unit and a controller 230. It should be noted that, Figure 3In the embodiment, only one first switching interface 221 and one second switching interface 222 are shown, which does not limit the scheme of the present application. In other embodiments of the present application, the first switching interface 221 and the second switching interface 222 can also be in other numbers. For example, the second switching interface 222 can support the PCIE protocol. For example, the frequency of the clock signal of the clock unit can be 100 MHz, and is not limited to this. The number of pins of the first switching interface 221 and the second switching interface 222 can be 16, and is not limited to this.

[0044] The first port of the switching unit 210 can be electrically connected to the first switching interface 221, and the second port can be electrically connected to the second switching interface 222, so that the data of the first switching interface 221 and the second switching interface 222 can be exchanged. For example, the first port can be used as the uplink port (Root Complex, RC) of the switching unit 210, and is electrically connected to the first switching interface 221. The first switching interface 221 is electrically connected to the first mainboard B1, and receives data from the central processor 110 of the first mainboard B1. Then, the switching unit 210 can send the data received through the first switching interface 221 to the second switching interface 222 through the second port as the downlink port (End Point, EP). For example, the second switching interface 222 can be electrically connected to a device as the downlink device, such as a computing card or a communication card, etc. For example, the computing card can be a graphics processor (Graphics Processing Unit, GPU) or a data processor (Data Processing Unit). The communication card can be a network interface card (Network Interface Card, NIC). On this basis, the mainboard interface 140 of the first mainboard B1 and the first switching interface 221 of the second mainboard B2 are electrically connected, so that the central processor 110 of the first mainboard B1 with different architectures can be interconnected with the computing card or the communication card through the mainboard interface 140, the first switching interface 221, the switching unit 210 and the second switching interface 222, thereby realizing the function of the server and realizing the server compatible with the central processor 110 with different architectures.

[0045] Furthermore, the embodiments of this application are not limited to this. In other embodiments of this application, the second switching interface 222 can also be electrically connected to devices such as disk redundancy cards. For example, the second switching interface 222 can be in the form of a slot, so that the gold finger interface of a card-type device such as a computing card or communication card can be plugged into the second switching interface 222 and electrically connected to the second switching interface 222, thereby electrically connecting to the second motherboard B2. In this way, by using the switching unit 210 to electrically connect the first switching interface 221 and the second switching interface 222, the central processing unit 110 electrically connected to the first switching interface 221 and the device electrically connected to the second switching interface 222 can be interconnected even when the first switching interface 221 is electrically connected to the motherboard interface 140. Thus, even if the first motherboard B1 with a different architecture is replaced, the central processing unit 110 of the different first motherboard B1 after the replacement can still be interconnected with the device at the second switching interface 222 through the switching unit 210, reducing the dependence of the second motherboard B2 on the central processing unit 110, thereby making the second motherboard B2 adaptable to the first motherboard B1 with different architectures. In addition, the central processing unit 110 of the first motherboard B1 can also send a reset signal to the device via the motherboard interface 140, the first switching interface 221, the switching unit 210 and the second switching interface 222 to control the reset of the device as a downlink device.

[0046] Furthermore, the first switching interface 221 and the second switching interface 222 are of the same type, but each has different markings to distinguish them visually. For example, the first switching interface 221 and the second switching interface 222 may not only share the same communication protocol, but also have the same size, depth, etc. However, when the first switching interface 221 and the second switching interface 222 are similar in appearance, different markings can be designed on their surfaces for differentiation. This makes it easy to clearly identify which of the switching interfaces on the second motherboard B2 is the first switching interface 221 used to connect upstream devices such as the first motherboard B1, and which is the second switching interface 222 used to connect downstream devices such as computing cards, communication cards, or disk redundancy cards. This helps to accurately connect the motherboard interface 140 of the replaced first motherboard B1 to the first switching interface 221 of the second motherboard B2, thereby facilitating server support for central processing units 110 with different architectures. For example, the markings can be colored. Specifically, the first switching interface 221 can be blue, and the second switching interface 222 can be black. However, it should be understood that the embodiments of this application are not limited to this. The first switching interface 221 and the second switching interface 222 may also be other colors, or other markings may be designed to distinguish them.

[0047] For example, the first exchange interface 221 and the second exchange interface 222 are both high-speed serial computer expansion bus standard interfaces. For the high-speed serial computer expansion bus standard protocol, the switching unit 210 does not need to distinguish which of the above-mentioned architectures the architecture via the first exchange interface 221 belongs to, and can directly transmit signals of the high-speed serial computer expansion bus standard interface, so as to realize interconnection between the second motherboard B2 and the first motherboard B1 of different architectures. In this way, the second motherboard B2 is compatible with the first motherboard B1 of different architectures.

[0048] In addition, the second motherboard B2 can further include a clock unit. The clock unit can be electrically connected to the first exchange interface 221, the second exchange interface 222, and the switching unit 210, and provide clock signals to the first exchange interface 221, the second exchange interface 222, and the switching unit 210. In this way, in the case that the first motherboard B1 is arranged on the second motherboard B2, the first motherboard B1 can receive clock signals from the clock unit via the first exchange interface 221, and use the received clock signals as its own working clock. Similarly, in the case that the downstream device is arranged on the second motherboard B2, the downstream device can receive clock signals from the clock unit via the second exchange interface 222, and use the received clock signals as its own working clock. Similarly, the switching unit 210 can use the received clock signals as its own working clock. In this way, the first motherboard B1, the switching unit 210, and the downstream device can work based on the same source clock, so as to improve the quality of data interchanged between the first motherboard B1 and the downstream device.

[0049] On this basis, by integrating the central processor 110 into the first motherboard B1 independent of the second motherboard B2, the central processor 110 can receive clock signals same as the downstream device and the switching unit 210 from the clock unit of the second motherboard B2 as its own working clock in the case that the first motherboard B1 is arranged on the second motherboard B2, so as to form a complete server architecture with the entire motherboard. In the case that the first motherboard B1 is separated from the second motherboard B2, the clock unit of the second motherboard B2 can still provide clock signals for the downstream device and the switching unit 210 connected with the second exchange interface 222, and the central processor 110 can independently exchange data with devices electrically connected with the first motherboard B1 based on its own clock signals. In this way, the central processor 110, the switching unit 210, and the downstream device can normally work based on their respective clocks, regardless of whether the first motherboard B1 is arranged on the second motherboard B2 or not, realizing decoupling of the central processor 110 from the second motherboard B2, reducing the dependence of the second motherboard B2 on the central processor 110, so as to enable the second motherboard B2 to adapt to the first motherboard B1 of different architectures.

[0050] The controller 230 can be electrically connected to the first switching interface 221, and determine whether the first switching interface 221 is electrically connected to the mainboard interface 140 of the first mainboard B1 based on a signal received from the first switching interface 221. The controller 230 can also be electrically connected to the clock unit, and the controller 230 can control the clock unit to perform different operations for different connection conditions of the first switching interface 221 and the mainboard interface 140 of the first mainboard B1.

[0051] For example, the controller 230 can control the clock unit to send a clock signal to the first switching interface 221 when detecting that the mainboard interface 140 is electrically connected to the first switching interface 221, or control the clock unit to stop sending the clock signal to the first switching interface 221 when detecting that the mainboard interface 140 is disconnected from the first switching interface 221. The controller 230 can control the clock unit to send a first clock signal to the first switching interface 221 when detecting that the first mainboard B1 is electrically connected to the first switching interface 221. In this case, even if the first mainboard B1 is replaced, the controller 230 can still control the clock unit to provide the clock signal to the replaced first mainboard B1. In this way, the dependence of the second mainboard B2 on the central processing unit 110 is reduced. Moreover, the controller 230 can control the clock unit to stop sending the clock signal to the first switching interface 221 when detecting that the mainboard interface 140 of the first mainboard B1 is disconnected from the first switching interface 221, thereby reducing resource consumption. Furthermore, after the first mainboard B1 is replaced, the clock unit can still be controlled to send the clock signal to the replaced first mainboard B1. That is, even if the first mainboard B1 is replaced, the second mainboard B2 can still work normally. In this way, even if the dependence of the second mainboard B2 on the central processing unit 110 is reduced, the function of the server formed by the first mainboard B1 and the second mainboard B2 is not affected, and the compatibility of the second mainboard B2 to the first mainboard B1 of different architectures is achieved. The replaced first mainboard B1 can belong to a different architecture from the original mainboard.

[0052] In addition, the controller 230 can collect log information of devices managed by the controller 230 and send the log information to the first switching interface 221 when detecting that the mainboard interface 140 is electrically connected to the first switching interface 221. For example, the log information of the devices managed by the controller 230 can be log information of devices electrically connected to the controller 230. For example Figure 2information of the fan and the signal light. Alternatively, the controller 230 can stop sending the log information to the first switching interface 221 in case that the mainboard interface 140 is detected to be electrically disconnected from the first switching interface 221. In this way, the sending of the log information to the first switching interface 221 is stopped in case that the mainboard interface 140 is detected to be electrically disconnected from the first switching interface 221, and the resource consumption is reduced. Furthermore, after the first mainboard B1 is replaced and the mainboard interface 140 of the replaced first mainboard B1 is electrically connected to the first switching interface 221, the first clock signal can still be sent to the replaced first mainboard B1 by the switching unit 210. That is, even if the first mainboard B1 is replaced, the second mainboard B2 can still work normally. In this way, even if the dependence of the second mainboard B2 on the central processor 110 is reduced, the function of the server formed by the first mainboard B1 and the second mainboard B2 is not affected, and the compatibility of the second mainboard B2 to the first mainboard B1 of different architectures is realized.

[0053] In an embodiment of the present application, the central processor 110 can send a control signal to the controller 230 based on the log information in case that the log information is received, so that the controller 230 controls the performance or the working state of the devices under the control of the control signal. For example, the performance of the fan can be controlled, and specifically, the rotating speed of the fan can be controlled. In addition, the working state of the signal light, such as constant light, flashing, etc., can also be controlled. In this way, in case that the mainboard interface 140 of the first mainboard B1 is electrically connected to the first switching interface 221, the controller 230 collects the log information of the devices under its management, and sends the log information to the central processor 110, so that the central processor 110 can send a control signal to the programmable controller 230, and further make the controller 230 control the working state of the devices. In this way, even if the dependence of the second mainboard B2 on the central processor 110 is reduced, the function of the server formed by the first mainboard B1 and the second mainboard B2 is not affected, and the compatibility of the second mainboard B2 to the first mainboard B1 of different architectures is realized.

[0054] In another embodiment of the present application, the central processor 110 sends the log information to the management controller 120 in case that the log information is received. The management controller 120 can send a control signal to the controller 230 based on the log information via the central processor 110 and the mainboard interface 140, so that the controller 230 controls the performance or the working state of the devices under the control of the control signal. Alternatively, the management controller 120 can send a control signal to the controller 230 based on the log information directly via the mainboard interface 140, so that the controller 230 controls the performance or the working state of the devices under the control of the control signal.

[0055] In yet another embodiment of the present application, the second mainboard B2 can further be provided with a performance monitoring device. The performance monitoring device can be used to detect the heat dissipation performance of the fan. For example, the performance monitoring device can be a temperature sensor. The controller 230 can be electrically connected with the performance monitoring device, collect log information of the performance monitoring device, so as to manage the performance monitoring device. For example, the controller 230 can send the log information of the performance monitoring device to the central processor 110. The log information can include the temperature detected by the temperature sensor. Then, the controller 230 can control the fan to increase or decrease the wind speed under the control of the control signal, so as to reasonably dissipate heat of the second mainboard B2 as a whole.

[0056] In yet another embodiment of the present application, in the case that the controller 230 sends the log information to the central processor 110, and the original central processor 110 is replaced, the mainboard interface 140 of the first mainboard B1 can be disconnected from the first switching interface 221. In the case that the mainboard interface 140 of the first mainboard B1 is detected to be disconnected from the switching unit 210, the controller 230 can also stop sending the log information to the first switching interface 221. Then, in the case that the first switching interface 221 is detected to be reconnected with another first mainboard B1, the log information can be sent to another central processor 110 of the another first mainboard B1 via the first switching interface 221 and the mainboard interface 140, and the performance or working state of the controller 230 is controlled under the control of the another central processor 110 of the another first mainboard B1. For example, the log information can include temperature information. The central processor 110 or the management controller 120 can generate a control signal based on the temperature information through a pre-set program, and send the control signal to the controller 230 via the mainboard interface 140 of the first mainboard B1 and the first switching interface 221. In this way, in the case that the processor board card is replaced with another processor board card, the controller 230 can still send the log information to the first switching interface 221. Furthermore, even though the present application reduces the dependence of the second mainboard B2 on the central processor 110, the function of the server formed by the first mainboard B1 and the second mainboard B2 is not affected, and the compatibility of the second mainboard B2 to the first mainboard B1 with different architectures is realized.

[0057] In addition to the fan for global cooling, the second mainboard B2 can be provided with an additional cooling unit. In some schemes, since the central processor 110 is not decoupled from the server, the fan is usually used to cool the server globally to reduce the temperature of the central processor 110. However, in the embodiment of the present application, since the central processor 110 is integrated on the first mainboard B1, a cooling unit dedicated to the central processor 110 can also be provided on the first mainboard B1. Hereinafter, the cooling unit of the first mainboard B1 is referred to as the first cooling unit, and the cooling unit of the second mainboard B2 is referred to as the second cooling unit. On this basis, the first mainboard B1 further includes a first cooling unit for cooling the central processor 110, and the second mainboard B2 further includes a second cooling unit provided at the second switching interface 222. The first cooling unit and the second cooling unit are cooling units of the same type.

[0058] For example, the second cooling unit provided at the second switching interface 222 can be a liquid cooling unit for cooling the compute card, and correspondingly, the first cooling unit can also be a cooling unit for cooling the card-shaped structure. In this way, since the central processor 110 is provided on the first mainboard B1, the same type of cooling unit as the compute card can be used to cool the central processor 110, avoiding the difficulty of cooling the central processor 110 by the fan and other devices for global cooling deployed on the second mainboard B2 after the first mainboard B1 is detached from the second mainboard B2, thereby facilitating the replacement of the second mainboard B2, thereby reducing the dependence between the first mainboard B1 and the second mainboard B2. Further, even if the present application reduces the dependence of the second mainboard B2 on the central processor 110, it does not affect the function of the server formed by the first mainboard B1 and the second mainboard B2 together, and realizes the compatibility of the second mainboard B2 to the first mainboard B1 of different architectures.

[0059] However, it should be understood that the embodiments of this application are not limited to this. In other embodiments of this application, the first cooling unit and the second cooling unit may also be respectively located at the first switching interface 221 and the second switching interface 222 of the second motherboard B2. Since the central processing unit 110 is inserted into a specific location in the form of a card, the same heat dissipation design scheme as that of a high-density computing card can be adopted. Based on this, the heat dissipation design of the central processing unit 110 and the heat dissipation design of the computing card adopt the same scale design. For the case where the two first motherboards B1 are respectively inserted into the two first switching interfaces 221 of the second motherboard B2, the first cooling unit can be designed as a dual-slot passive heat dissipation design, and the overall heat dissipation is controlled by the fan group of the whole machine through the controller 230. Based on this, an active heat dissipation design that supports up to three slots can be designed according to the actual central processing unit 110. In this way, when the motherboard interface 140 of the first motherboard B1 is inserted into the first switching interface 221 and / or the computing card and other devices are inserted into the second switching interface 222, the central processing unit 110 and / or the computing card and other devices of the first motherboard B1 are targeted for cooling.

[0060] Figure 4 A schematic diagram of a first motherboard B1 and a second motherboard B2 according to a second embodiment of this application is shown.

[0061] like Figure 4 As shown, in addition to the central processing unit 110, management controller 120, memory 130, and motherboard interface 140 described above, the first motherboard B1 in this embodiment may also be provided with a first expansion interface. The second motherboard B2 may include a switching unit 210, two first switching interfaces 221, multiple second switching interfaces 222, a controller 230, a control interface, and a power module. It should be understood that the number of the two first switching interfaces 221 described above is only illustrative and is not intended to limit the solution of this application. For example, the second expansion interface may be an MCIOX16 connector interface to distinguish it from the PCIE interfaces of other MCIOX8 interfaces on the second motherboard B2, which can support up to 24 pairs of high-speed serial transceiver pairs. It should be understood that this is only an example. For example, the control interface may support the MCIO protocol.

[0062] In this embodiment, the mainboard interface 140 of the first mainboard B1 can be electrically connected to a first switching interface 221 of the second mainboard B2. The first extension interface of the first mainboard B1 can be electrically connected to a second extension interface of the second mainboard B2, and the second extension interface of the second mainboard B2 can be further electrically connected to another first switching interface 221. The other first switching interface 221 is not connected to the mainboard interface 140 of the first mainboard B1, but is electrically connected to a memory extension card. The memory extension card can be used to extend the memory of the central processor 110. In this way, the central processor 110 can write data to the memory extension card via the first extension interface, the second extension interface and the first switching interface 221, or read data from the memory extension card via the first extension interface, the second extension interface and the first switching interface 221. On this basis, by providing a plurality of first switching interfaces 221 on the second mainboard B2, the memory of the central processor 110 can be extended by providing an extension memory card on the other first switching interface 221 which is not electrically connected to the mainboard interface 140 of the first mainboard B1 when the first mainboard B1 is arranged on the second mainboard B2, thereby avoiding the problem of insufficient memory of the central processor 110 caused by integrating the central processor 110 on the card-type first mainboard B1 which is independent of the second mainboard B2, so as to ensure that the central processor 110 can have sufficient memory even if it is independent of the second mainboard B2. In this way, even if the present application reduces the dependence of the second mainboard B2 on the central processor 110, it does not affect the function of the server formed by the first mainboard B1 and the second mainboard B2 together, and realizes the compatibility of the second mainboard B2 to the first mainboard B1 of different architectures.

[0063] It should be understood that the embodiments of the present application are not limited thereto, and in other embodiments of the present application, the switching unit 210 can also be electrically connected to the first switching interface 221. In this way, the computing card or the communication card connected to the second switching interface 222 can write data to the memory extension card or read data from the memory extension card via the second switching interface 222, the switching unit 210 and the other first switching interface 221, and the like.

[0064] Further, the interval between the second expansion interface and the first switching interface 221 is determined based on a multiple of the size of the first switching interface 221. In this way, by setting the interval between the second expansion interface and the first switching interface 221 as a multiple of the size of the first switching interface 221 (for example, three times the width), it can be ensured that the first switching interface 221 and the second expansion interface have a certain interval position, so that the heat dissipation unit is arranged at the first switching interface 221, facilitating heat dissipation of the central processor 110. Moreover, the embodiments of the present application are not limited thereto, and in other embodiments of the present application, the interval between the plurality of first switching interfaces 221 can also be set as a multiple of the size of the first switching interface 221 (for example, three times the width), so that the heat dissipation unit is arranged at the first switching interface 221, facilitating heat dissipation.

[0065] The control interface of the second mainboard B2 can be electrically connected to a host computer or the like. In this way, the host computer can send a control signal to the switching unit 210 via the control interface to control the operation of the switching unit 210. Alternatively, the host computer can also send a control signal to the controller 230, the first switching interface 221 and the second switching interface 222 via the control interface and the switching unit 210 to control the operation of the controller 230, the first mainboard B1 electrically connected to the first switching interface 221 and the downstream device electrically connected to the second switching interface 222, and the like.

[0066] In addition, the power module of the second mainboard B2 can be used to power the devices on the second mainboard B2, such as the switching unit 210, the two first switching interfaces 221, the plurality of second switching interfaces 222, the controller 230, the control interface, and the like.

[0067] Figure 5 A schematic diagram of the first mainboard B1 and the second mainboard B2 according to the third embodiment of the present application is shown.

[0068] As shown in Figure 5 The first mainboard B1 can include a central processor 110, a management controller 120, a memory 130, a mainboard interface 140 and a first expansion interface. The second mainboard B2 can include a switching unit 210, a first switching interface 221, a plurality of second switching interfaces 222 and a third expansion interface.

[0069] The first expansion interface can be electrically connected to the expansion memory 130, and specifically can be electrically connected to the expansion memory 130 via a hard disk expansion interface. The expansion memory 130 can also be used to expand the memory of the central processor 110. In this way, the first mainboard B1 can write data to the expansion memory 130 via the first expansion interface and the hard disk expansion interface, and can also read the data from the expansion memory 130 via the first expansion interface and the hard disk expansion interface and process the data.

[0070] For example, the extended memory 130 can be a hard disk. The extended memory 130 can be disposed on the hard disk backplane or on the second motherboard B2. In the case where the extended memory 130 is disposed on the hard disk backplane, the hard disk extension interface can be electrically connected to the third extension interface of the second motherboard B2. In this way, the computing card or the communication card electrically connected to the second switching interface 222 can write data to the extended memory 130 via the second switching interface 222, the switching unit 210, the third extension interface, and the hard disk extension interface to store the data, or can read and process the data from the extended memory 130. In this way, by disposing the extended memory 130 on the second motherboard B2, sufficient memory can be ensured for the central processor 110 to work normally. In this way, even if the application reduces the dependence of the second motherboard B2 on the central processor 110, the function of the server formed by the first motherboard B1 and the second motherboard B2 is not affected, and the compatibility of the second motherboard B2 with the first motherboard B1 of different architectures is achieved.

[0071] Figure 6 A schematic diagram of the first motherboard B1 and the second motherboard B2 according to the fourth embodiment of the application is shown.

[0072] As shown in Figure 6 The second motherboard B2 can include a switching unit 210, a plurality of first switching interfaces 221, a plurality of second switching interfaces 222, and a third extension interface. The third extension interface is electrically connected to the hard disk extension interface of the hard disk backplane to be electrically connected to the hard disk of the hard disk backplane.

[0073] The motherboard interfaces 140 of the plurality of first motherboards B1 can be electrically connected to the plurality of first switching interfaces 221, respectively. The plurality of first motherboards B1 can adopt a full-height full-length PCIE card design. Based on this, in an embodiment of the application, the central processors 110 of the plurality of first motherboards B1 all expand their own memory through the extended memory 130. For example, the central processor 110 of any one of the plurality of first motherboards B1 can write storage data to a device via the motherboard interface 140 of the any one of the plurality of first motherboards B1, the corresponding first switching interface 221 (i.e., the first switching interface 221 to which the motherboard interface 140 of the first motherboard B1 is connected), the switching unit 210, and the second switching interface 222. The central processor 110 of another first motherboard B1 of the plurality of first motherboards B1, other than the any one of the plurality of first motherboards B1, reads the storage data of the device via the motherboard interface 140 of the another first motherboard B1, the corresponding first switching interface 221 (i.e., the first switching interface 221 to which the motherboard interface 140 of the first motherboard B1 is connected), the switching unit 210, and the second switching interface 222.

[0074] In another embodiment of the present application, the plurality of first exchange interfaces 221 are electrically connected to each other. For example, the plurality of first exchange interfaces 221 can be electrically connected to each other via a Universal Peripheral Interface (UPI) or an Advanced eXtensible Interface (AXI). In this way, the central processors 110 of the plurality of first motherboards B1 disposed on the second motherboard B2 can call the memory resources of each other to process data, thereby achieving mutual redundancy of the dual motherboards and providing higher core computing capability, and in the case of a central processor 110 failure, the central processor 110 can be quickly replaced. For example, the central processor 110 of any one of the plurality of first motherboards B1 can receive computing data from a computing card or a communication card via the motherboard interface 140 and the corresponding first exchange interface 221, the exchange unit 210, and the second exchange interface 222 of the first motherboard B1, and then the computing data can be written to the memory of the central processor 110 of another one of the plurality of first motherboards B1, or the computing data can also be read from the memory of the central processor 110 of another one of the plurality of first motherboards B1.

[0075] In this way, by disposing the plurality of first motherboards B1 on the second motherboard B2, and the central processor 110 of any one of the plurality of first motherboards B1 can call the memory of the other central processors 110 to store the computing data from the communication card or the computing card. In this way, since the dependence of the server backplane on the central processor 110 is reduced, the plurality of first motherboards B1 can be flexibly deployed on the second motherboard B2, so that the plurality of independent first motherboards B1 are cascaded and process the computing data. On this basis, the architectures of the plurality of first motherboards B1 can be different. In this way, even though the present application reduces the dependence of the second motherboard B2 on the central processor 110, it does not affect the function of the server formed by the plurality of first motherboards B1 and the second motherboard B2 of different architectures, and compatibility of the second motherboard B2 to the first motherboards B1 of different architectures is achieved.

[0076] In another embodiment of the present application, the central processor 110 of any one of the plurality of first motherboards B1 writes the storage data to the expansion memory 130 via the first expansion interface of the first motherboard B1 described above. The central processor 110 of another one of the plurality of first motherboards B1, other than the first motherboard B1, reads the storage data in the expansion memory 130 via the first expansion interface of the other first motherboard B1.

[0077] In addition, in Figure 6The second motherboard B2 shown may also include a second expansion interface and a separate second switching interface 222 electrically connected to the second expansion interface. Similar to the previous description, the second expansion interface of this embodiment can also be used to connect the first expansion interfaces of two first motherboards B1 for PCIe expansion or CXL memory expansion.

[0078] Figure 7A A schematic diagram showing the interconnection between a board according to a first embodiment of this application and a remote server is shown.

[0079] like Figure 7A As shown, in this embodiment, when two first motherboards B1 are installed on the second motherboard B2, the two first motherboards B1 can be electrically connected to the switching unit 210. Thus, the central processing units of the two first motherboards B1 can be interconnected with a computing card or disk array card via the switching unit 210, or the two first motherboards B1 can be interconnected with a remote server via the switching unit 210 and a communication card. Each of the two first motherboards B1 functions as an independent single-processor server. By controlling the configuration of the switching unit 210, two independent computing systems are implemented, independently processing different data from the network and classifying and processing the network data as needed. The dual-processor first motherboard B1 non-interconnected redundancy mode enables rapid system backup and online replacement of the first motherboards B1.

[0080] Furthermore, each of the two first motherboards B1 has a first expansion interface that can be electrically connected to a hard drive located on the second motherboard B2. In this way, each of the two first motherboards B1 can expand its own memory through its connected hard drive.

[0081] Figure 7B A schematic diagram showing the interconnection between a board and a remote server according to a second embodiment of this application is shown.

[0082] like Figure 7B As shown, in this embodiment, when two first motherboards B1 are installed on the second motherboard B2, the two first motherboards B1 can be electrically connected to the switching unit 210. The central processing units (CPUs) of the two first motherboards B1 can be interconnected with a computing card or a disk array card via the switching unit 210, or the two first motherboards B1 can be interconnected with a remote server via the switching unit 210 and a communication card. Unlike the previous description, the two first motherboards B1 can be electrically connected to each other on the second motherboard B2. The CPUs of the two first motherboards B1 can be interconnected via an interconnect serial bus. A unified serial interface is used, and the data format adopts a universal serial protocol, requiring support from the CPUs of the first motherboards B1.

[0083] Thus, the central processors of the two first motherboards B1 can call each other's memory resources to process data interacting with the computing card, the disk array card or the remote server. In this case, the application supports the interconnection of two first motherboards B1 of the same specification, realizes the application system of a dual-channel interconnection server, and provides higher core computing capability. At the same time, one of the two first motherboards B1 is combined with the second motherboard B2 as a master server, and the other first motherboard B1 is synchronized as a redundant backup. Since all peripherals and important storage data can be shared through the exchange unit 210, when any first motherboard B1 fails, it can be quickly replaced to reduce the risk of service interruption. It should be understood that this is not used to limit the embodiments of the application, and the embodiments of the application can support up to 7 first motherboards B1 simultaneously arranged on the second motherboard B2. Considering the sufficient storage and external expansion interface realized in one server, the dual-channel server has greater advantages in the architecture. When only a computing server with external storage server is needed to provide computing power, the design of more first motherboards B1 can be developed according to the application.

[0084] The devices on the first motherboard B1 and the second motherboard B2 have been described in detail above. On this basis, the controller 230 in the application can control the plurality of devices on the second motherboard B2, and the clock unit can provide clock signals to the plurality of devices on the second motherboard B2.

[0085] The following will be described in combination with Figure 8A and Figure 8B Figure 8A The connection diagram of the controller 230 according to the embodiment of the application is shown.

[0086] As Figure 8A ​As shown, the controller 230 can be electrically connected to the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the control module of the power module, the clock unit and the third expansion interface. For example, the controller 230 can provide a control signal to at least one of the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the control module of the power module, the clock unit and the third expansion interface, collect log information from at least one of the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the control module of the power module, the clock unit and the third expansion interface. Wherein, the control module of the power module is used to control the voltage rise or fall of the power supply. It should be understood that the embodiments of the present application are not limited thereto, and the controller 230 can also be electrically connected to other devices on the second mainboard B2, which is not limited herein. For example, the controller 230 can be interconnected with the first switching interface 221 and the second switching interface 222 through a bus such as a system management bus (SMBus) of a PCIE bus. The controller 230 can be interconnected with the switching unit 210 via an I / O (Input / Output, input / output) bus, an I2C bus, a general-purpose input / output (GPIO) bus and the like. The controller 230 can also be interconnected with the second expansion interface, the third expansion interface and the clock unit via an I2C bus and the like. The controller 230 can also be interconnected with the control module of the power module via an I / O bus and the like.

[0087] On this basis, the controller 230 is used for system management of the second mainboard B2, power circuit monitoring, fan control and control of low-speed I / O signals such as signal lights. Wherein, the power circuit design is all used in the power supply design of the general server system. Since almost all variable peripherals depend on the power supply of the mainboard, the main power supply design of the server and the general design are still the same. The power supply design of the first mainboard B1 is also designed by using a general connector power supply in accordance with the PCIe specification, and the second mainboard B2 is designed with sufficient PCIE device external power supply interfaces to meet the power supply requirements of the PCIE device.

[0088] Figure 8B A connection diagram of the controller 230 according to an embodiment of the present application is shown.

[0089] As Figure 8BAs shown, the clock unit can be electrically connected to the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the second expansion interface and the third expansion interface, and provide homologous clock signals to the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the second expansion interface and the third expansion interface. For example, the clock unit can include, but is not limited to, a crystal oscillator, a clock buffer and the like. It should be understood that the embodiments of the present application are not limited thereto, and the clock unit can also be electrically connected to other devices on the second mainboard B2, and provide clock signals to other devices or receive control signals from other devices for controlling the clock unit, which is not limited herein.

[0090] In addition, in the case of multiple first mainboards B1 provided on the second mainboard B2, the clock signal can also be provided to each device of the second mainboard B2 by the central processor of any one of the multiple mainboards. In the case of failure of the central processor of the mainboard, the clock signal can be switched to be provided by the central processor of other first mainboard B1. Alternatively, the controller 230 of the second mainboard B2 can control the clock unit to provide the clock signal.

[0091] The present application is mainly used in the internal structure of desktop, rack-mounted and blade servers, and is designed to enable a same server to support different architectures of central processors and enable the central processors to be replaceable. The present application can also be used in the architecture design of other similar servers or computer hosts, and is not limited to single-server and dual-server, and can even be used in the design of supercomputing servers supporting more channels. Moreover, the design can also be applied to switches, which will not be described herein.

[0092] Figure 9 A schematic diagram of an interconnection method according to an embodiment of the present application is shown.

[0093] As shown, the interconnection method of the embodiment includes operation S910. Figure 9

[0094] In operation S910, the central processor of the first mainboard interconnects the switching unit and the controller of the second mainboard via the mainboard interface of the first mainboard and the first switching interface of the second mainboard based on the memory and the management controller of the first mainboard.

[0095] In the embodiments of the present application, the interconnection method is similar to the operations performed by the board card described above.

[0096] For example, the interconnection with the switching unit of the second mainboard includes that the central processor of the first mainboard interconnects the device via the mainboard interface, the first switching interface, the switching unit and the second switching interface.

[0097] ​For example, the interconnection method further comprises that the central processing units of the plurality of first motherboards are interconnected with each other via the motherboard interfaces and the plurality of first switch interfaces of the plurality of first motherboards.

[0098] For example, the interconnection method further comprises that the central processing unit of the first motherboards sends a reset signal to the device via the motherboard interface, the first switch interface, the switching unit and the second switch interface, so as to control the device to reset.

[0099] For example, the interconnection method further comprises that the central processing unit of any first motherboard of the plurality of first motherboards writes storage data into the device via the motherboard interface, the corresponding first switch interface, the switching unit and the second switch interface of the any first motherboard; and the central processing unit of another first motherboard of the plurality of first motherboards, except the any first motherboard, reads the storage data of the device via the motherboard interface, the corresponding first switch interface, the switching unit and the second switch interface of the another first motherboard.

[0100] For example, the interconnection method further comprises that the central processing unit of any first motherboard of the plurality of first motherboards writes storage data into the extended storage via the first extended interface of the any first motherboard; and the central processing unit of another first motherboard of the plurality of first motherboards, except the any first motherboard, reads the storage data in the extended storage via the first extended interface of the another first motherboard.

[0101] For example, the second motherboard further comprises a clock unit; the clock unit is electrically connected to the controller and the first switch interface; and the interconnection method further comprises that the controller controls the clock unit to provide a clock signal to the first switch interface in a case where it is detected that the first switch interface is electrically connected to the motherboard interface.

[0102] For example, the interconnection method further comprises that the controller controls the clock unit to stop providing the clock signal to the first switch interface in a case where it is detected that the first switch interface is disconnected from the motherboard interface.

[0103] For example, the interconnection method further comprises that the controller sends log information to the central processing unit via the first switch interface and the motherboard interface in a case where it is detected that the first switch interface is electrically connected to the motherboard interface.

[0104] For example, the interconnection method further comprises that the central processing unit sends a control signal to the controller based on the log information in a case where the log information is received, so as to control the working state of the device managed by the controller.

[0105] For example, the interconnection method further comprises that the central processing unit uses the clock signal received via the motherboard interface and the first switch interface as a working clock of itself in a case where the motherboard interface is electrically connected to the first switch interface.

[0106] For example, the interconnection method further includes: in a case where the mainboard interface is disconnected from the first switching interface, the central processing unit uses a clock signal generated by itself as a working clock of itself.

[0107] It should be understood that the method of the embodiments of the present application is not limited thereto, and can be specifically referred to the foregoing description, which will not be repeated here.

[0108] Those skilled in the art can understand that the features described in various embodiments of the present application can be combined and / or combined in various combinations, even if such combinations or combinations are not explicitly described in the present application. In particular, the features described in various embodiments of the present application can be combined and / or combined in various combinations without departing from the spirit and teachings of the present application. All these combinations and / or combinations fall within the scope of the present application.

[0109] The embodiments of the present application are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. Although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Those skilled in the art can make various alternatives and modifications without departing from the scope of the present application, and these alternatives and modifications shall fall within the scope of the present application.

Claims

1. A board card, characterized by, At least comprising an expansion card and a mainboard; The expansion card comprises a central processing unit, a mainboard interface, a memory and a management controller electrically connected to the central processing unit, and the memory is used to deploy an operating system of the central processing unit; the management controller arranged on the expansion card is adapted to the architecture of the central processing unit arranged on the expansion card; the mainboard interface is in the form of a golden finger; and The mainboard comprises a plurality of first switching interfaces, a switching unit, a second switching interface, a clock unit and a controller electrically connected, the first switching interface is in the form of a slot, the second switching interface is used to arrange a computing card, a disk array card or a communication card, the communication card is used to interconnect with a server, and the clock unit is electrically connected to the controller, the first switching interface and the switching unit; Wherein, a plurality of expansion cards with different architectures are arranged on the mainboard and inserted into the plurality of first switching interfaces through the mainboard interface, so as to be electrically connected to the mainboard in the form of plugging and cascaded through the mainboard; the plurality of expansion cards are cascaded through at least one of the following connection modes: the plurality of expansion cards are electrically connected through a serial bus, the plurality of expansion cards are electrically connected through the plurality of first switching interfaces electrically connected to each other, and the plurality of expansion cards are electrically connected through the respective mainboard interfaces, the corresponding first switching interfaces and the switching units; any expansion card in the plurality of expansion cards is used to write data received from the computing card, the disk array card or the communication card into the memory of the central processing unit of other expansion cards in the plurality of expansion cards, and is used to read the data from the memory of the central processing unit of the other expansion cards.

2. The board card of claim 1, wherein The first port of the switching unit is electrically connected to the first switching interface, and the second port is electrically connected to the second switching interface.

3. The board card of claim 2, wherein, The expansion card further comprises a first cooling unit for cooling the central processing unit; the mainboard further comprises a second cooling unit arranged at the second switching interface; the first cooling unit and the second cooling unit are the same type of cooling unit.

4. The board card of claim 2, wherein, The first switching interface and the second switching interface are the same type of interface.

5. The board card of claim 2, wherein, The first switching interface and the second switching interface are both high-speed serial computer expansion bus standard interfaces.

6. The board card of claim 1, wherein, The plurality of first switching interfaces are electrically connected to each other.

7. The board card according to any one of claims 1 to 6, characterized in that, The mainboard further comprises an expansion memory; the expansion card further comprises a first expansion interface, the central processing unit is electrically connected to the first expansion interface, and the first expansion interface is electrically connected to the expansion memory.

8. The board card according to any one of claims 1 to 6, characterized by The first switching interface is a plurality; the mainboard further comprises a second expansion interface; the second expansion interface is electrically connected to the first expansion interface of the expansion card and another first switching interface in the plurality of first switching interfaces which is not connected to the mainboard interface, and the another first switching interface is electrically connected to a memory expansion card.

9. The board card of claim 8, wherein, The interval between the second expansion interface and the first switching interface is determined based on the size multiple of the first switching interface.

10. The board card according to any one of claims 1 to 6, wherein The expansion card further comprises a data interface for connecting an external device.

11. An interconnection method performed by the board card of any one of claims 1-10, comprising: interconnecting, by a central processing unit of the expansion card, with a switching unit and a controller of a motherboard via a motherboard interface of the expansion card and a first switching interface of the motherboard, based on a memory and the controller of the expansion card.

12. The interconnection method of claim 11, wherein, a second switching interface of the switching unit is electrically connected to a device of the motherboard; wherein the interconnecting with the switching unit of the motherboard comprises: interconnecting, by the central processing unit of the expansion card, with the device via the motherboard interface, the first switching interface, the switching unit and the second switching interface.

13. The interconnection method of claim 12, wherein, The interconnection method further comprises: sending, by the central processing unit of the expansion card, a reset signal to the device via the motherboard interface, the first switching interface, the switching unit and the second switching interface, to control the device to reset.

14. The interconnection method of claim 12, wherein, The first switching interface is a plurality; the expansion card is a plurality, and each of the plurality of expansion cards comprises a motherboard interface; the motherboard interface of each of the plurality of expansion cards is respectively electrically connected to the plurality of first switching interfaces; The plurality of first switching interfaces are electrically connected to each other; The interconnection method further comprises: interconnecting, by the central processing unit of each of the plurality of expansion cards, with each other via the motherboard interface of each of the plurality of expansion cards and the plurality of first switching interfaces.

15. The interconnection method of claim 14, wherein, The interconnection method further comprises: writing, by the central processing unit of any one of the plurality of expansion cards, storage data into the device via the motherboard interface of the any one of the plurality of expansion cards, the corresponding first switching interface, the switching unit and the second switching interface; reading, by the central processing unit of another expansion card of the plurality of expansion cards other than the any one of the plurality of expansion cards, storage data of the device via the motherboard interface of the another expansion card, the corresponding first switching interface, the switching unit and the second switching interface.

16. The interconnection method according to any one of claims 11 to 15, wherein The motherboard further comprises an expansion memory; the expansion card further comprises a first expansion interface, the central processing unit is electrically connected to the first expansion interface, and the first expansion interface is electrically connected to the expansion memory; The interconnection method further comprises: writing, by the central processing unit of any one of the plurality of expansion cards, storage data into the expansion memory via the first expansion interface of the any one of the plurality of expansion cards; reading, by the central processing unit of another expansion card of the plurality of expansion cards other than the any one of the plurality of expansion cards, storage data in the expansion memory via the first expansion interface of the another expansion card.

17. The interconnection method according to any one of claims 11 to 15, wherein The motherboard further comprises a clock unit; the clock unit is electrically connected to the controller and the first switching interface; The interconnection method further comprises: controlling, by the controller, the clock unit to provide a clock signal to the first switching interface in a case where it is detected that the first switching interface is electrically connected to the motherboard interface.

18. The interconnection method of claim 17, wherein, The interconnection method further comprises: controlling, by the controller, the clock unit to stop providing the clock signal to the first switching interface in a case where it is detected that the first switching interface is disconnected from the motherboard interface.

19. The interconnection method of claim 18, wherein, The interconnection method further comprises: The controller sends log information to the central processor via the first switching interface and the mainboard interface when detecting that the first switching interface is electrically connected with the mainboard interface.

20. The method of claim 19, wherein, The interconnection method further comprises: The central processor sends a control signal to the controller to control the working state of the device managed by the controller based on the log information when receiving the log information.

21. The interconnection method of claim 17, wherein, The interconnection method further comprises: The central processor uses the clock signal received via the mainboard interface and the first switching interface as its own working clock when the mainboard interface is electrically connected with the first switching interface.

22. The method of claim 21, wherein, The interconnection method further comprises: The central processor uses the clock signal generated by itself as its own working clock when the mainboard interface is disconnected from the first switching interface.

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