Chip design method and device, chip, electronic equipment and storage medium

Abstract

The invention provides a chip design method and device, a chip, electronic equipment and a storage medium. The chip design method comprises the steps that the number of solidification blocks divided by the whole chip is estimated according to service requirements, the port protocol type of a target component integrated by each solidification block is determined, and the compression number of an interface of a compression module / decompression module is determined based on the port protocol type; wherein the compression modules or the decompression modules are integrated on the curing blocks, the compression modules and the decompression modules exist in pairs according to the data interaction relation, and the chips are arranged according to the number of the curing blocks and the compression number of each curing block. According to the scheme, the compression number of the interfaces of the compression module / decompression module needing to be integrated on the curing block is determined according to the port protocol type of the target component integrated on each curing block, chip layout is carried out, the number of the original ports of the target component is compressed, and when the target component is integrated on the curing block, the compression number of the interfaces of the compression module / decompression module needing to be integrated on the curing block is reduced. And the number of external ports of the curing block is greatly reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular, to a chip design method, device, chip, electronic device, and storage medium. Background Art

[0002] With the rapid development of electronic devices, the functions of chips are becoming more and more complex, and the scale is also getting larger. The modules integrated in the chip are also getting larger and more complex, such as processors, storage modules, etc. In order to facilitate the comprehensive implementation of the entire chip, the modules integrated on the chip are usually incorporated into the full-chip netlist in a separate hardened manner. Each hardened area corresponds to a separate area for layout and wiring, which is equivalent to dividing a completed chip into several pieces. If the hardened areas are not hardened in advance, as the chip usage area increases and the wiring becomes more complex, the layout and wiring of the chip will become more difficult.

[0003] The division of the hardened areas generally requires independent semiconductor (Intellectual Property, IP) or independent functions, so that the wiring between the hardenings can be minimized. However, due to the complexity and scale of large system-on-chip (SOC), there are inevitably problems such as complex wiring through the hardenings. Therefore, how to reduce the wiring through the hardenings is an urgent problem to be solved at present. Summary of the Invention

[0004] The present disclosure provides a chip design method, device, chip, electronic device, and storage medium to solve the problems in the related art and reduce the wiring through the hardened blocks.

[0005] A first aspect embodiment of the present disclosure proposes a chip design method, which includes:

[0006] Estimate the number of hardened blocks divided for the entire chip according to service requirements;

[0007] Determine the port protocol type of the target components integrated in each hardened block;

[0008] Determine the compression number of the interfaces of the compression module / decompression module based on the port protocol type; wherein, the compression module or decompression module is integrated on the hardened block, and the compression module and the decompression module exist in pairs according to the data interaction relationship;

[0009] Layout the chip according to the number of hardened blocks and the compression number of each hardened block.

[0010] In some embodiments of the present disclosure, if the port protocol type is a standard port protocol type, the determining the compression number of the interfaces of the compression / decompression module based on the port protocol type includes:

[0011] For each solidification block, determine the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type.

[0012] In some embodiments of the present disclosure, the determining the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type includes:

[0013] Determine the upper compression limit and the lower compression limit of the compression number according to the characteristic information of the standard port protocol type;

[0014] According to the channel size between adjacent solidification blocks, dynamically adjust the compression number of the interfaces of the compression module and the decompression module within the range of the upper compression limit and the lower compression limit.

[0015] In some embodiments of the present disclosure, if the port protocol type is a non-standard port protocol type, the determining the compression number of the interfaces of the compression / decompression module based on the port protocol type includes:

[0016] Analyze the characteristic information of the non-standard port protocol type to obtain the interface characteristic information and the interface sequence information corresponding to the non-standard port protocol type;

[0017] Determine the compression number of the interfaces of the compression module and the decompression module according to the interface characteristic information and the interface sequence information.

[0018] In some embodiments of the present disclosure, the determining the compression number of the interfaces of the compression module and the decompression module according to the interface characteristic information and the interface sequence information includes:

[0019] Determine the upper compression limit and the lower compression limit of the compression number according to the interface characteristic information and the interface sequence information;

[0020] According to the channel size between adjacent solidification blocks, dynamically adjust the compression number of the interfaces of the compression module and the decompression module within the range of the upper compression limit and the lower compression limit.

[0021] In some embodiments of the present disclosure, after the chip is laid out according to the number of solidification blocks and the compression number of each solidification block, the method further includes:

[0022] In a scenario where it is determined that there is data interaction between the first port of a compression module and the second port of a corresponding decompression module at the opposite end, integrate the target components with their respective corresponding compression module or decompression module to obtain the integrated compression module and decompression module;

[0023] Integrate the compression module and the decompression module onto corresponding solidification blocks respectively, where the first port and the second port serve as the external ports of each solidification block.

[0024] In some embodiments of the present disclosure, integrating the compression module and the decompression module onto corresponding solidification blocks respectively includes:

[0025] Configure paired compression algorithms / decompression algorithms for the compression module and the decompression module;

[0026] Integrate the compression module and the decompression module configured with the compression algorithms / decompression algorithms onto corresponding solidification blocks respectively.

[0027] In some embodiments of the present disclosure, after laying out the chip according to the number of solidification blocks and the compression number of each solidification block, the method further includes:

[0028] In a scenario where it is determined that there is data interaction between the first port of a compression module and the third ports of at least two decompression modules at the opposite end, integrate the target components with their respective corresponding compression modules or decompression modules to obtain the integrated compression module and decompression module;

[0029] Integrate the compression module and the at least two decompression modules onto corresponding solidification blocks respectively, where the first port and the third port serve as the external ports of each solidification block.

[0030] In some embodiments of the present disclosure, integrating the compression module and the decompression module onto corresponding solidification blocks respectively includes:

[0031] Configure paired compression algorithms / decompression algorithms for the compression module and the at least two decompression modules;

[0032] Integrate the compression module and the at least two decompression modules configured with the compression algorithms / decompression algorithms onto corresponding solidification blocks respectively.

[0033] An embodiment of the second aspect of the present disclosure provides a chip design device, the device includes:

[0034] A partitioning unit, configured to estimate the number of solidification blocks for partitioning the entire chip according to service requirements;

[0035] A first determination unit, configured to determine the port protocol type of the target components integrated in each solidification block;

[0036] The second determination unit is further configured to determine the compression number of the interfaces of the compression module / decompression module based on the port protocol type; wherein, the compression module or the decompression module is integrated on the solidified block, and the compression module and the decompression module exist in pairs according to the data interaction relationship;

[0037] The layout unit is configured to layout the chip according to the number of the solidified blocks and the compression number of each solidified block.

[0038] In some embodiments of the present disclosure, if the port protocol type is a standard port protocol type, the second determination unit includes:

[0039] The first determination module is configured to, for each solidified block, determine the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type.

[0040] In some embodiments of the present disclosure, the first determination module is further configured to:

[0041] Determine the upper compression limit and the lower compression limit of the compression number according to the characteristic information of the standard port protocol type;

[0042] Dynamically adjust the compression number of the interfaces of the compression module and the decompression module within the range of the upper compression limit and the lower compression limit according to the channel size between adjacent solidified blocks.

[0043] In some embodiments of the present disclosure, if the port protocol type is a non-standard port protocol type, the second determination unit includes:

[0044] The analysis module is configured to analyze the characteristic information of the non-standard port protocol type to obtain the interface characteristic information and the interface sequence information corresponding to the non-standard port protocol type;

[0045] The second determination module is configured to determine the compression number of the interfaces of the compression module and the decompression module according to the interface characteristic information and the interface sequence information.

[0046] In some embodiments of the present disclosure, the second determination module is further configured to:

[0047] Determine the upper compression limit and the lower compression limit of the compression number according to the interface characteristic information and the interface sequence information;

[0048] Dynamically adjust the compression number of the interfaces of the compression module and the decompression module within the range of the upper compression limit and the lower compression limit according to the channel size between adjacent solidified blocks.

[0049] In some embodiments of the present disclosure, the device further includes:

[0050] A first integration unit, configured to, after the layout unit performs layout on the chip according to the number of the solidification blocks and the compression number of each solidification block, in a scenario where it is determined that there is data interaction between a first port of a compression module and a second port of a corresponding decompression module at the opposite end, integrate the target components with their respective corresponding compression modules or decompression modules to obtain the integrated compression modules and decompression modules;

[0051] A second integration unit, configured to respectively integrate the compression modules and the decompression modules on corresponding solidification blocks, where the first port and the second port serve as the external ports of each solidification block.

[0052] In some embodiments of the present disclosure, the second integration unit is further configured to:

[0053] Configure paired compression algorithms / decompression algorithms for the compression modules and the decompression modules;

[0054] Respectively integrate the compression modules and the decompression modules configured with the compression algorithms / decompression algorithms on corresponding solidification blocks.

[0055] In some embodiments of the present disclosure, the apparatus further includes:

[0056] A third integration unit, configured to, after the layout unit performs layout on the chip according to the number of the solidification blocks and the compression number of each solidification block, in a scenario where it is determined that there is data interaction between a first port of a compression module and at least two third ports of corresponding decompression modules at the opposite end, integrate the target components with their respective corresponding compression modules or decompression modules to obtain the integrated compression modules and decompression modules;

[0057] A fourth integration unit, configured to respectively integrate the compression modules and the at least two decompression modules on corresponding solidification blocks, where the first port and the third port serve as the external ports of each solidification block.

[0058] In some embodiments of the present disclosure, the fourth integration unit is further configured to:

[0059] Configure paired compression algorithms / decompression algorithms for the compression modules and the at least two decompression modules;

[0060] Respectively integrate the compression modules and the at least two decompression modules configured with the compression algorithms / decompression algorithms on corresponding solidification blocks.

[0061] A third aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to execute the method described in the first aspect embodiment of the present disclosure.

[0062] A fourth aspect embodiment of the present disclosure provides a chip designed by the method in the first aspect embodiment of the present disclosure.

[0063] A fifth aspect embodiment of the present disclosure provides an electronic device, which includes the chip described in the fourth aspect embodiment of the present disclosure.

[0064] In summary, according to the chip design method proposed by the present disclosure, the method includes estimating the number of fixed blocks divided for the entire chip according to service requirements, determining the port protocol types of the target components integrated in each fixed block, and determining the compression number of the interfaces of the compression module / decompression module based on the port protocol types; wherein, the compression module or decompression module is integrated on the fixed block, and the compression module and the decompression module exist in pairs according to the data interaction relationship, and the chip is laid out according to the number of fixed blocks and the compression number of each fixed block. The solution of the present disclosure determines the compression number of the interfaces of the compression module / decompression module to be integrated on the fixed block according to the port protocol types of the target components integrated in each fixed block, performs the layout of the chip, compresses the number of the original ports of the target components, and greatly reduces the number of external ports of the fixed block when integrating the target components into the fixed block.

[0065] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation to the present disclosure.

[0067] Figure 1 It is a flowchart of a chip design method provided by an embodiment of the present disclosure;

[0068] Figure 2 It is a schematic diagram of a compression module and a decompression module provided by an embodiment of the present disclosure;

[0069] Figure 3 It is a flowchart of a chip design method provided by an embodiment of the present disclosure;

[0070] Figure 4 It is a flowchart of a chip design method provided by an embodiment of the present disclosure;

[0071] Figure 5 Schematic diagram of a chip design device provided by an embodiment of the present disclosure;

[0072] Figure 6 Schematic diagram of a chip design device provided by an embodiment of the present disclosure;

[0073] Figure 7 Schematic diagram of a design device provided by an embodiment of the present disclosure. Detailed implementation manners

[0074] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation to the present disclosure.

[0075] With the rapid development of electronic devices, the functions of chips are becoming more and more complex, and the scale is also getting larger and larger. The modules integrated in the chip are also getting larger and more complex, such as processors, storage modules, etc. In order to facilitate the comprehensive implementation of the entire chip, the modules integrated on the chip are usually incorporated into the full-chip netlist in a separate hardened manner. Each hardened area corresponds to a separate area for layout and wiring, which is equivalent to dividing a completed chip into several pieces. If the hardened areas are not hardened in advance, as the chip usage area increases and the wiring becomes more complex, the layout and wiring of the chip will become more difficult. The division of the hardened areas generally requires independent semiconductors (Intellectual Property, IP) or independent functions, so that the wiring between the hardenings can be minimized. However, due to the complexity and scale of large system-on-chip (SOC), there are inevitably problems such as complex wiring between the hardenings. Therefore, how to reduce the wiring between the hardenings is an urgent problem to be solved at present.

[0076] Therefore, in order to solve the problems existing in the related technologies, the present disclosure proposes a chip design method, which estimates the number of hardened blocks divided for the entire chip according to service requirements, determines the port protocol types of the target components integrated in each hardened block, and determines the compression number of the interfaces of the compression module / decompression module based on the port protocol types; wherein, the compression module or the decompression module is integrated on the hardened block, and the compression module and the decompression module exist in pairs according to the data interaction relationship, and the chip is laid out according to the number of the hardened blocks and the compression number of each hardened block. By means of interface compression, the number of external ports of the hardened block is reduced, and thus the wiring of the hardened block is reduced.

[0077] The embodiments of the present disclosure are not exhaustive. They are only illustrations of some embodiments and do not specifically limit the protection scope of the present disclosure. Without contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be exchanged arbitrarily. In addition, the optional implementation manners in an embodiment can be combined arbitrarily; moreover, the embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and an embodiment can be combined arbitrarily with the optional implementation manners of other embodiments.

[0078] In each embodiment of the present disclosure, unless otherwise specified and there is no logical conflict, the terms and / or descriptions among the embodiments are consistent and can be cited from each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0079] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended as a limitation on the present disclosure.

[0080] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above-mentioned", "said", "afore-mentioned", "this", etc., can mean "one and only one", or can also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression form or a plural expression form.

[0081] In some embodiments, terms such as "in response to...", "in response to determining...", "in the case of...", "when...", "while...", "if...", etc. can be replaced with each other.

[0082] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", etc. can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below", etc. can be replaced with each other.

[0083] In the embodiments of the present disclosure, prefix words such as "first" and "second" are only used to distinguish different described objects, and do not limit the position, order, priority, quantity, or content of the described objects. For the description of the described objects, refer to the description in the claims or the context of the embodiments. Unnecessary limitations should not be formed due to the use of prefix words.

[0084] In the embodiments of the present disclosure, "a plurality of" means two or more.

[0085] In the embodiments of the present disclosure, terms such as "import", "input", and "read in" can be replaced with each other.

[0086] Figure 1 The figure is a flowchart of a chip design method provided for the embodiments of the present disclosure. This method can be applied to the chip design scenario. As Figure 1 shown, the chip design method includes steps 101-104.

[0087] Step 101, estimate the number of hardened blocks divided for the entire chip according to the service requirements.

[0088] In practical applications, the division of hardened blocks (hardenblock) in different SOC systems is not exactly the same, but the overall division principle is to better perform layout and wiring for the floorplan of the chip, and at the same time, the utilization rate of all hardened blocks (hardenblock) can reach the optimum.

[0089] Therefore, in order to improve the utilization rate of each hardened block, it is necessary to make a preliminary estimate of the hardened block (hardenblock) so that the area of each piece of the entire chip can be reasonably utilized.

[0090] When estimating the number of hardened blocks of the chip, it is necessary to estimate according to the actual service requirements. The number of hardened blocks corresponding to different service requirements may be the same or different. Specifically, the embodiments of the present disclosure do not limit this.

[0091] Step 102, determine the port protocol type of the target components integrated in each hardened block.

[0092] Before chip design, the target component IP (Intellectual Property) components included in each hardened block will be determined according to the service requirements. After determining the target IP components, according to the relationship between the target IP components and the fixed port protocol types, it can be determined according to which port protocol type the port of the hardened block (hardenblock) belongs to.

[0093] In the embodiments of the present disclosure, the port protocol types include standard port protocols and non-standard port protocols. Generally, the ports of the quasi-port protocols are universal. Since the ports of the non-standard port protocols are not universal, they cannot be normalized. Therefore, separate processing needs to be performed according to the port protocol types.

[0094] Step 103, determining the compression number of the interface of the compression module / decompression module based on the port protocol type; wherein, the compression module or the decompression module is integrated on the hardening block, and the compression module and the decompression module exist in pairs according to the data interaction relationship.

[0095] In the embodiments of the present disclosure, the port protocol types include standard port protocols and non-standard port protocols. Generally, the ports of the quasi-port protocols are universal. Since the ports of the non-standard port protocols are not universal, they cannot be normalized. Therefore, separate processing needs to be performed according to the port protocol types.

[0096] Plan the development of the compression module and the decompression module based on the division of the hardenblock and the port protocol type. Since it involves the compression of the standard protocol, a deep understanding of the standard protocol is required. For example, which interfaces in the standard protocol can be compressed and which interfaces cannot be uniformly compressed. The same applies to the decompression module at the opposite end of the compression module.

[0097] In addition, attention should also be paid to the paired existence and use of the compression module and the decompression module. The compression algorithm corresponds to the decompression algorithm to ensure the consistency of compression and decompression and prevent misjudgment of the standard protocol due to compression and decompression.

[0098] Specifically, when determining the compression number, the interconnection and interaction between the hardenblocks can be flexibly adjusted according to the current plan and implementation. For example, when the channel between two hardenblocks is tense and sufficient wiring resources cannot be provided, a large compression and decompression ratio can be configured to minimize the wiring resources as much as possible; when the channel between two hardenblocks is sufficient and layout and wiring are not the key bottlenecks, a small compression and decompression ratio can be configured to reduce the change of the standard protocol interface.

[0099] To facilitate the understanding of the compression module and the decompression module, as Figure 2 shown, Figure 2 is a schematic diagram of a compression module and a decompression module provided by the embodiments of the present disclosure. The on-chip interconnection between multiple target IPs is implemented based on the standard port protocol. All target IPs and the bus must meet the standard bus protocol so that data can be completely transmitted between the target IP and the bus. From Figure 2It can be seen that taking the target IPs MST1, MST2, MST3 and SLV1, SLV2, SLV3 as examples, the target IP interface is directly docked with the compression / decompression bus BUS interface, keeping the original interface of the target IP unchanged. The data stream is transferred by two compression / decompression buses. The above target IPs are only exemplary examples, and the embodiments of the present disclosure do not limit the number and layout of the target IP and hardenblock.

[0100] Based on Figure 2 It can be seen from the above figures that during the specific implementation process, the original SOC (system on chip) needs to be modified accordingly. The purpose is to add a separate compression module to the interface where the original hardenblock communicates with the outside according to the standard protocol. At this time, the port exposed on the hardenblock becomes the compression interface of the compression module and the decompression module. Similarly, a corresponding decompression module needs to be integrated on the hardenblock for communication at the other end. The implementation principle of the decompression module is the same as that of the compression module, so it will not be elaborated here.

[0101] Step 104, layout the chip according to the number of the solidification blocks and the compression number of each solidification block.

[0102] The back end of the chip performs synthesis and layout and wiring according to the number of the solidification blocks and the hardenblocks corresponding to the compression number of each solidification block. At this time, there may be a process of multiple iterations. When there are many hardenblocks on the chip and the area is tight, resulting in insufficient resources for layout and wiring during the iteration process, the compression ratio of the standard protocol interface can be increased based on the current evaluation results, and then the wiring resources of the hardenblocks can be further reduced.

[0103] According to the chip design method proposed by the present disclosure, the method includes estimating the number of the solidification blocks divided for the entire chip according to the service requirements, determining the port protocol type of the target components integrated in each solidification block, and determining the compression number of the interfaces of the compression module / decompression module based on the port protocol type; wherein, the compression module or the decompression module is integrated on the solidification block, and the compression module and the decompression module exist in pairs according to the data interaction relationship, and layout the chip according to the number of the solidification blocks and the compression number of each solidification block. The solution of the present disclosure determines the compression number of the interfaces of the compression module / decompression module that needs to be integrated on the solidification block according to the port protocol type of the target components integrated in each solidification block, performs the layout of the chip, compresses the number of the original ports of the target components, and greatly reduces the number of external ports of the solidification block when integrating the target components into the solidification block.

[0104] For a further explanation of step 103, if the port protocol type is a standard port protocol type, the compression number of the interfaces of the compression / decompression module determined based on the port protocol type may include, but is not limited to, being implemented by the following methods, including: for each solidified block, determining the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type. Since the standard port protocol is universal, which interfaces in the standard protocol can be compressed and which cannot be uniformly compressed are the characteristic information of the standard port protocol type and are established. Therefore, when determining the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type, determining the upper compression limit and the lower compression limit of the compression number according to the established characteristic information of the standard port protocol type; according to the channel size between adjacent solidified blocks, dynamically adjusting the compression number of the interfaces of the compression module and the decompression module within the range of the upper compression limit and the lower compression limit.

[0105] In some embodiments, when the channel between adjacent solidified blocks is relatively large, within the range of the upper compression limit and the lower compression limit, dynamically reducing the compression number of the interfaces of the compression module and the decompression module; when the channel between adjacent solidified blocks is relatively small, within the range of the upper compression limit and the lower compression limit, dynamically increasing the compression number of the interfaces of the compression module and the decompression module to reduce the wiring resources of the hardenblock.

[0106] It should be noted that the characteristic information of different standard port protocol types may vary, resulting in differences in the upper compression limit and the lower compression limit. The embodiments of the present disclosure do not limit the upper compression limit and the lower compression limit.

[0107] Figure 3 Further showing a flowchart of a chip design method proposed by the present disclosure. Based on Figure 1 the embodiments shown, for a further explanation of step 103, if the port protocol type is a non-standard port protocol type, Figure 3 the following steps may be included:

[0108] Step 301, analyzing the characteristic information of the non-standard port protocol type to obtain the interface characteristic information and interface sequence information corresponding to the non-standard port protocol type.

[0109] For the interfaces of the non-standard port protocol, it is necessary to sequentially analyze the interface characteristic information and interface sequence information of each interface to determine which interfaces can be compressed and which cannot be compressed.

[0110] Step 302, determining the compression number of the interfaces of the compression module and the decompression module according to the interface characteristic information and interface sequence information.

[0111] Based on the interfaces of non-standard ports that can be compressed, determine the compression numbers of the interfaces of the compression module and the decompression module, and when determining the compression numbers, the interfaces of non-standard ports that cannot be compressed cannot be used as a reference for determination.

[0112] In some embodiments, when determining the compression numbers of the interfaces of the compression module and the decompression module according to the interface characteristic information and interface sequence information, the following implementation methods can be adopted but are not limited to them. For example: determine the upper limit and lower limit of the compression numbers according to the interface characteristic information and interface sequence information, and dynamically adjust the compression numbers of the interfaces of the compression module and the decompression module within the range of the upper limit and lower limit of the compression according to the channel size between adjacent hardened blocks.

[0113] In some embodiments, when the channel between adjacent hardened blocks is relatively large, dynamically reduce the compression numbers of the interfaces of the compression module and the decompression module within the range of the upper limit and lower limit of the compression; when the channel between adjacent hardened blocks is relatively small, dynamically increase the compression numbers of the interfaces of the compression module and the decompression module within the range of the upper limit and lower limit of the compression, so as to reduce the wiring resources of the hardenblock.

[0114] In practical applications, within the same SOC, there may be an interconnection between one target IP and one target IP, or there may be an interconnection between one target IP and multiple target IPs. To meet the communication requirements, as Figure 4 shown, Figure 4 further shows a flowchart of a chip design method proposed by the present disclosure. Figure 4 It may include the following steps:

[0115] Step 401, estimate the number of hardened blocks into which the entire chip is divided according to service requirements;

[0116] Step 402, determine the port protocol types of the target components integrated in each hardened block;

[0117] Step 403, determine the compression numbers of the interfaces of the compression module / decompression module based on the port protocol types; wherein, the compression module or decompression module is integrated on the hardened block, and the compression module and the decompression module exist in pairs according to the data interaction relationship;

[0118] Step 404, layout the chip according to the number of hardened blocks and the compression numbers of each hardened block.

[0119] For the descriptions of steps 401 to 404, reference can be made to the Figure 1 relevant detailed descriptions.

[0120] Step 405, in the scenario where it is determined that there is data interaction between the first port of a compression module and the second port of a decompression module on the opposite end, integrate the target component with the corresponding compression module or decompression module respectively to obtain the integrated compression module and decompression module.

[0121] For the sake of easy understanding, for example, when the upstream is the host IP, the downstream can be docked with the compression bus in the compression module to achieve the docking of the standard protocol interface between the upstream host IP and the downstream compression bus; when the downstream is the slave IP, the upstream can be docked with the decompression bus in the decompression module to achieve the docking of the standard protocol interface between the downstream slave IP and the upstream decompression bus. The compression and decompression buses are implemented according to the agreed compression and decompression algorithms.

[0122] The host IP and the compression bus can be regarded as a whole, that is, the target component is integrated with the compression module, and the internal ordinary signal traces complete the data stream interaction; the slave IP and the decompression bus can be regarded as a whole, that is, the target component is integrated with the decompression module, and the internal ordinary signal traces complete the data stream interaction.

[0123] Step 406, integrate the compression module and the decompression module on the corresponding solidification blocks respectively, where the first port and the second port serve as the external ports of each solidification block.

[0124] Taking the example of Step 405, after executing Step 405, integrate the compression module and the decompression module integrated with the target component on their respective corresponding solidification blocks. Since the compression bus of the compression module integrated with the target component and the decompression bus of the decompression module integrated with the target component can interact as two separate data streams, after the compression module and the decompression module are integrated on the corresponding solidification blocks respectively, because the number of ports of each solidification block decreases due to compression, the number of metal layer traces will be reduced from the original number of signal lines of the standard protocol to the number of compressed signal lines, greatly reducing the number of top-layer metal buses.

[0125] When making corresponding modifications to the original SOC, the purpose is to add separate compression modules and decompression modules to the interfaces of the original hardenblock for communicating with the outside according to the standard protocol. Therefore, the ports exposed on the hardenblock become specific compression interfaces, that is, the first port and the second port serve as the external ports of each solidification block.

[0126] In some embodiments of the present disclosure, to ensure the consistency of compression and decompression and prevent misjudgment of the standard protocol due to compression and decompression, since the compression module and the decompression module exist in pairs, for two hardenblocks with communication interaction, a set of paired compression modules and decompression modules is required.

[0127] Configure paired compression algorithms / decompression algorithms for the compression module and the decompression module, and integrate the compression module and the decompression module configured with the compression algorithms / decompression algorithms onto the corresponding hardened blocks respectively. The embodiments of the present disclosure do not specifically limit the compression algorithms / decompression algorithms, and any implementation manner in the related art can be referred to, which is not limited in the embodiments of the present disclosure.

[0128] As another implementation manner of the embodiments of the present disclosure, in a scenario where it is determined that there is data interaction between the first port of a compression module and the third ports of at least two decompression modules on the opposite side, integrate the target components with their respective corresponding compression modules or decompression modules to obtain the integrated compression module and decompression module, and integrate the compression module and the at least two decompression modules onto the corresponding hardened blocks respectively, where the first port and the third port serve as the external ports of each hardened block.

[0129] When integrating the compression module and the decompression module onto the corresponding hardened blocks respectively, the following implementation manners can be adopted but are not limited to: configure paired compression algorithms / decompression algorithms for the compression module and the at least two decompression modules, and integrate the compression module and the at least two decompression modules configured with the compression algorithms / decompression algorithms onto the corresponding hardened blocks respectively.

[0130] The implementation principle in the scenario where it is determined that there is data interaction between the first port of a compression module and the third ports of at least two decompression modules on the opposite side is the same as that in the scenario where it is determined that there is data interaction between the first port of a compression module and the third port of a decompression module on the opposite side. For details, refer to the detailed description of the above embodiments, and thus will not be elaborated herein.

[0131] It should be noted that to meet the communication requirements, in the scenario where it is determined that there is data interaction between the first port of a compression module and the third ports of at least two decompression modules on the opposite side, that is, when a single hardenblock has communication requirements with multiple other hardenbocks, considering generality and adaptability, it is necessary to ensure that all communication interfaces use a set of compression and decompression algorithms.

[0132] Figure 5 The following is a schematic structural diagram of a chip design device provided by the embodiments of the present disclosure. The device includes:

[0133] A dividing unit 51, configured to estimate the number of solidified blocks for the entire chip division according to service requirements;

[0134] A first determining unit 52, configured to determine the port protocol type of the target components integrated in each solidified block;

[0135] A second determining unit 53, further configured to determine the compression number of the interfaces of the compression module / decompression module based on the port protocol type; wherein, the compression module or the decompression module is integrated on the solidified block, and the compression module and the decompression module exist in pairs according to the data interaction relationship;

[0136] A layout unit 54, configured to perform layout on the chip according to the number of solidified blocks and the compression number of each solidified block.

[0137] In some embodiments of the present disclosure, if the port protocol type is a standard port protocol type, the second determining unit 53 includes:

[0138] A first determining module 531, configured to, for each solidified block, determine the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type.

[0139] In some embodiments of the present disclosure, the first determining module 21 is further configured to:

[0140] Determine the upper compression limit and the lower compression limit of the compression number according to the characteristic information of the standard port protocol type;

[0141] Dynamically adjust the compression number of the interfaces of the compression module and the decompression module within the range of the upper compression limit and the lower compression limit according to the channel size between adjacent solidified blocks.

[0142] In some embodiments of the present disclosure, if the port protocol type is a non-standard port protocol type, the second determining unit 53 includes:

[0143] An analysis module 532, configured to analyze the characteristic information of the non-standard port protocol type to obtain the interface characteristic information and the interface sequence information corresponding to the non-standard port protocol type;

[0144] A second determining module 533, configured to determine the compression number of the interfaces of the compression module and the decompression module according to the interface characteristic information and the interface sequence information.

[0145] In some embodiments of the present disclosure, the second determining module 533 is further configured to:

[0146] Determine the upper compression limit and the lower compression limit of the compression number according to the interface characteristic information and the interface sequence information;

[0147] Dynamically adjust the compression number of the interfaces of the compression module and the decompression module within the compression upper limit and the compression lower limit according to the channel size between adjacent curing blocks.

[0148] In some embodiments of the present disclosure, as Figure 6 shown, the device further includes:

[0149] A first integration unit 55, configured to, after the layout unit performs layout on the chip according to the number of the curing blocks and the compression number of each curing block, in a scenario where it is determined that there is data interaction between a first port of a compression module and a second port of a corresponding decompression module at the opposite end, integrate the target components with the corresponding compression module or decompression module respectively to obtain the integrated compression module and decompression module;

[0150] A second integration unit 56, configured to integrate the compression module and the decompression module onto corresponding curing blocks respectively, where the first port and the second port serve as the external ports of each curing block.

[0151] In some embodiments of the present disclosure, the second integration unit 56 is further configured to:

[0152] Configure paired compression algorithms / decompression algorithms for the compression module and the decompression module;

[0153] Integrate the compression module and the decompression module configured with the compression algorithms / decompression algorithms onto corresponding curing blocks respectively.

[0154] In some embodiments of the present disclosure, as Figure 6 shown, the device further includes:

[0155] A third integration unit 57, configured to, after the layout unit performs layout on the chip according to the number of the curing blocks and the compression number of each curing block, in a scenario where it is determined that there is data interaction between a first port of a compression module and at least two third ports of corresponding decompression modules at the opposite end, integrate the target components with the corresponding compression module or decompression module respectively to obtain the integrated compression module and decompression module;

[0156] A fourth integration unit 58, configured to integrate the compression module and the at least two decompression modules onto corresponding curing blocks respectively, where the first port and the third port serve as the external ports of each curing block.

[0157] In some embodiments of the present disclosure, the fourth integration unit 58 is further configured to:

[0158] Configuring a pair of compression algorithm / decompression algorithm for the compression module and the at least two decompression modules;

[0159] The compression module configured with the compression algorithm / decompression algorithm and the at least two decompression modules are respectively integrated into corresponding solidification blocks.

[0160] Since the device provided in the embodiment of the present disclosure corresponds to the methods provided in the above-mentioned embodiments, the implementation of the method is also applicable to the device provided in the embodiment and will not be described in detail in this embodiment.

[0161] The present disclosure also provides a design device, which can implement the chip design solution provided by the present disclosure by setting the chip design device provided by the present disclosure. In an implementation example, the chip design device provided by the present disclosure can be a functional module device in an electronic design auxiliary tool run by the design device. As an optional implementation, Figure 7 An optional block diagram of a design device provided by an embodiment of the present disclosure is shown exemplarily, referring to Figure 7 , the design device may include: at least one memory 71 and at least one processor 72;

[0162] The memory 71 stores one or more computer executable instructions, and the processor 72 calls the one or more computer executable instructions to execute the chip design method as described in the above embodiment.

[0163] The design device also includes: a communication interface 73 and a communication bus 74. In the embodiment of the present disclosure, the number of the processor 72, the communication interface 73, the memory 71, and the communication bus 74 is at least one, and the processor 72, the communication interface 73, and the memory 71 communicate with each other through the communication bus 74.

[0164] Optionally, the communication interface 73 may be an interface of a communication module for performing network communication.

[0165] Optionally, the processor 72 may be a CPU (central processing unit), a GPU (Graphics Processing Unit), an NPU (embedded neural network processor), an FPGA (Field Programmable Gate Array), a TPU (tensor processing unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present disclosure.

[0166] The memory 71 may include high-speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

[0167] Embodiments of the present disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the methods described in the above embodiments of the present disclosure.

[0168] Embodiments of the present disclosure also provide a chip designed by the chip design method described in any one of the above embodiments. For the specific implementation of the chip design method, reference may be made to the relevant parts of the above embodiments, which will not be elaborated here.

[0169] Embodiments of the present disclosure also provide an electronic device, which includes the chip as described above.

[0170] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present disclosure can be implemented by electronic hardware, computer software, or a combination of both. Whether such a function is implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present disclosure.

[0171] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described here can be implemented in an order different from those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0172] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0173] Any process or method description, whether in a flowchart or otherwise described herein, can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present invention includes additional implementations, where functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0174] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing a logical function, and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (control method) having one or more wirings, a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0175] It should be understood that various parts of the embodiments of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0176] Those of ordinary skill in the art can understand that all or part of the steps carried out in the method of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0177] In addition, in each of the embodiments of the present invention, each functional unit can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in a module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disk, etc.

[0178] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A chip design method, characterized in that, The method includes: Estimating the number of fixed blocks divided in the entire chip according to service requirements; Determining the port protocol types of the target components integrated in each fixed block; Determining the compression number of the interfaces of the compression module / decompression module based on the port protocol types; wherein, the compression module or the decompression module is integrated on the fixed block, and the compression module and the decompression module exist in pairs according to the data interaction relationship; Performing layout on the chip according to the number of fixed blocks and the compression number of each fixed block.

2. The method according to claim 1, wherein If the port protocol type is a standard port protocol type, the determining the compression number of the interfaces of the compression / decompression module based on the port protocol type includes: For each fixed block, determining the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type.

3. The method according to claim 2, wherein The determining the compression number of the interfaces of the compression module and the decompression module according to the characteristic information of the standard port protocol type includes: Determining the upper limit and the lower limit of the compression number according to the characteristic information of the standard port protocol type; Dynamically adjusting the compression number of the interfaces of the compression module and the decompression module within the range between the upper limit and the lower limit according to the channel size between adjacent fixed blocks.

4. The method according to claim 1, wherein If the port protocol type is a non-standard port protocol type, the determining the compression number of the interfaces of the compression / decompression module based on the port protocol type includes: Analyzing the characteristic information of the non-standard port protocol type to obtain the interface characteristic information and the interface sequence information corresponding to the non-standard port protocol type; Determining the compression number of the interfaces of the compression module and the decompression module according to the interface characteristic information and the interface sequence information.

5. The method according to claim 4, wherein The determining the compression number of the interfaces of the compression module and the decompression module according to the interface characteristic information and the interface sequence information includes: Determining the upper limit and the lower limit of the compression number according to the interface characteristic information and the interface sequence information; Dynamically adjusting the compression number of the interfaces of the compression module and the decompression module within the range between the upper limit and the lower limit according to the channel size between adjacent fixed blocks.

6. The method according to any one of claims 1-5, characterized in that, After performing layout on the chip according to the number of fixed blocks and the compression number of each fixed block, the method further includes: In a scenario where it is determined that there is data interaction between the first port of a compression module and the second port of a corresponding decompression module at the opposite end, integrating the target component with the corresponding compression module or decompression module to obtain the integrated compression module and decompression module; Integrating the compression module and the decompression module on the corresponding fixed blocks respectively, wherein the first port and the second port serve as the external ports of each fixed block.

7. The method according to claim 6, wherein The integrating the compression module and the decompression module on the corresponding fixed blocks respectively includes: Configuring paired compression algorithms / decompression algorithms for the compression module and the decompression module; Integrating the compression module and the decompression module configured with the compression algorithms / decompression algorithms on the corresponding fixed blocks respectively.

8. The method according to any one of claims 1-5, characterized in that, After laying out the chip according to the number of the curing blocks and the compression number of each curing block, the method further includes: In a scenario where it is determined that there is data interaction between the first port of a compression module and the third ports of at least two decompression modules at the opposite end, integrating the target components with their respective corresponding compression modules or decompression modules to obtain the integrated compression module and decompression module; Integrating the compression module and the at least two decompression modules onto corresponding curing blocks respectively, wherein the first port and the third port serve as the external ports of each curing block.

9. The method according to claim 8, characterized in that, The integrating the compression module and the decompression module onto corresponding curing blocks respectively includes: Configuring paired compression algorithms / decompression algorithms for the compression module and the at least two decompression modules; Integrating the compression module and the at least two decompression modules configured with the compression algorithms / decompression algorithms onto corresponding curing blocks respectively.

10. A chip design device, characterized in that, The device includes: A partitioning unit, configured to estimate the number of curing blocks for partitioning the entire chip according to service requirements; A first determination unit, configured to determine the port protocol type of the target components integrated in each curing block; A second determination unit, further configured to determine the compression number of the interfaces of the compression module / decompression module based on the port protocol type; wherein the compression module or the decompression module is integrated on the curing block, and the compression module and the decompression module exist in pairs according to the data interaction relationship; A layout unit, configured to lay out the chip according to the number of the curing blocks and the compression number of each curing block.

11. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-9.

12. A chip, characterized in that, The chip is designed by the method according to any one of claims 1-9.

13. An electronic device, characterized in that, The electronic device includes the chip according to claim 12.

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