Self-activation in-memory calculation method based on two-dimensional flash memory, array and storage calculation unit
Through a self-activated in-memory calculation method based on two-dimensional flash memory, the bipolar characteristics and electrostatic doping effect of two-dimensional materials are used to realize the ReUL activation function without external circuits, solving the problem of high power consumption in the prior art and improving the energy efficiency and speed of in-memory calculation.
Patent Information
- Application Number
- CN202510273928.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-07-25
AI Technical Summary
The existing crossbar array in-memory calculation method can only implement linear operations of multiplication and addition, requiring additional nonlinear activation functions, resulting in high power consumption, limiting the energy efficiency development of in-memory computing and neural networks.
The self-activated in-store calculation method based on two-dimensional flash memory is adopted to realize the ReUL activation function through the memory calculation unit, without the need for an external circuit structure, multiplication and self-activate operations are performed using the bipolar characteristics and electrostatic doping effect of the two-dimensional material, and the current output results are accumulated and converted.
Reduces power consumption, improves computing efficiency, achieves fast in-memory computing speed, and reduces the area requirement of additional activation circuits.
Smart Images
Figure CN120373378A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of electronic technology, and particularly relates to a self-activation in-memory computing method, an array, and a memory-computation unit based on a two-dimensional material flash device. Background Art
[0002] With the development of the integrated circuit industry, the traditional von Neumann computing architecture faces severe challenges of the memory wall and the power wall. In-memory computing embeds some computing functions into the memory array, greatly reducing the time and loss of data transmission between the memory array and the computing unit. Currently, due to the high parallelism and simple structure of the crossbar array, mainstream neural networks such as CNN and DNN perform multiplication and addition operations based on the Kirchhoff's current law through the crossbar memory array.
[0003] However, the memory-computation unit based on the crossbar array can only perform linear operations of multiplication and addition, and additional non-linear activation functions are required in actual neural networks to achieve more complex functions. Usually, these non-linear activation functions are implemented through additional circuit structures, such as sense amplifiers SA and analog-to-digital converters ADC, etc. These units have relatively high power consumption, and may even be greater than the total energy consumption of the memory-computation array, restricting the development of high-energy-efficiency in-memory computing and neural networks.
[0004] Therefore, researching and developing a memory-computation multiplication and addition unit that can achieve self-activation to reduce energy consumption without an external activation function has become a key technical problem to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of the present invention is to provide a self-activation in-memory computing method based on two-dimensional flash memory that can reduce the power consumption burden and improve the computing energy efficiency, as well as a self-activation in-memory computing array and a memory-computation unit.
[0006] The present invention provides a self-activation in-memory computing method based on two-dimensional flash memory, which can implement the ReUL activation function, that is, when the input is positive, the original value is output, and when it is negative, 0 is output, to achieve sparse activation without an external additional circuit structure; the in-memory computing unit (abbreviated as the memory-computation unit) involved in the calculation, the array composed of the memory-computation units (abbreviated as the memory-computation unit array), and the row-column controller (including the row controller and the column controller); the specific steps are as follows:
[0007] (1) The memory-computation unit array receives input data through the row-column controller;
[0008] (2) The memory-computation unit performs a multiplication operation based on the stored weights and the input data, and performs a ReUL activation operation;
[0009] (3) The memory-computation unit outputs the operation result after the multiplication operation and the activation operation in the form of current;
[0010] (4) The current outputs of multiple memory - computing units are cumulatively summed on the bit - line, generating the current output of the multiply - add operation, and then generating a voltage output through current - voltage conversion.
[0011] The received input data can be parallel input or serial input.
[0012] The weights and input data are signed 1 - bit, 2 - bit or multi - bit data.
[0013] The ReUL activation operation is characterized in that when the input is positive, the original value is output, and when the input is negative, 0 is output.
[0014] The multiplication operation and the ReUL activation operation refer to the fact that both are implemented simultaneously within the memory - computing unit, rather than first performing the multiplication operation in the memory - computing unit and then completing the ReUL activation through other functional modules.
[0015] In the present invention, a self - activating in - memory computing array is composed of a memory - computing unit array, word - lines, bit - lines, source - lines, a row controller, a column controller, and optionally, a conversion unit. The memory - computing units located in the same column share the bit - line and the source - line, and the memory - computing units located in the same row share the word - line. The row controller is connected to the word - line, the column controller is connected to the source - line, and the conversion unit is connected to the bit - line.
[0016] The memory - computing unit includes a two - dimensional material flash memory device with self - activating properties, which is characterized in that it can realize weight storage and multiplication operation with ReUL self - activating properties. Specifically, after completing the multiplication operation of the input and the weight, when the operation result is negative, 0 is input, and when the operation result is positive, the operation result is output.
[0017] The memory - computing unit of the two - dimensional material flash memory device can store signed weight data. The signed weight data can be 1 - bit, 2 - bit or multi - bit, and the specific value should consider the actual performance of the two - dimensional material flash memory device.
[0018] The storage state of the memory - computing unit of the two - dimensional material flash memory device is controlled by the row controller and the column controller through the word - line and the bit - line. Specifically, for the selected memory - computing unit, the row controller applies a programming pulse through the word - line, and the column controller sets the corresponding bit - line to the programming potential to program the selected unit as required.
[0019] The programming pulse programs the sign and magnitude of the weight stored in the two - dimensional material flash memory device by setting appropriate polarity, amplitude, and pulse width.
[0020] When the memory and computing unit of the two-dimensional material flash device performs a multiplication operation, the row controller inputs data through the word line, performs a multiplication operation with the weights stored in the memory and computing unit, and the operation result of each unit is output to the bit line in the form of current and accumulated through the bit line to achieve the multiply-accumulate operation function.
[0021] Due to the self-activation characteristic of the memory and computing unit, the operation result in the form of current of each memory and computing unit has the following characteristics: when the multiplication operation result is negative, that is, the input data and the stored weight have opposite signs, the current is extremely small, that is, 0 value is output instead of a negative value; when the multiplication operation result is positive, that is, the input data and the stored weight have the same sign, the output current is positive and the magnitude of the current reflects the magnitude of the multiplication operation result, that is, the operation result is output.
[0022] The function of the conversion unit is to convert the current output of the multiply-accumulate operation into a voltage, output it as a calculation result, or apply it as an input to the subsequent in-memory computing array. Specifically, the conversion unit can be a transistor, an inverter, an amplifier or other circuit structures with similar functions.
[0023] The memory and computing unit of the two-dimensional material flash device with the ReUL self-activation function provided by the present invention specifically includes: a two-dimensional material channel, a tunneling dielectric layer, a trap capture layer, a blocking layer, a gate, a source electrode and a drain electrode. The two-dimensional material channel, the tunneling dielectric layer, the trap capture layer and the blocking layer form a stacked structure. The gate is located above the blocking layer, and the source electrode and the drain electrode are in contact with the two-dimensional material channel and are located on both sides.
[0024] The two-dimensional material channel can be monolayer or multilayer graphene, transition metal dichalcogenides (TMDs), and other two-dimensional semiconductor materials. Preferably, a material with bipolar characteristics, such as WSe2, is used.
[0025] The tunneling dielectric layer and the blocking layer can be two-dimensional insulating dielectrics, such as hBN, or oxide insulating dielectrics, such as HfO2, Al2O3, SiO2 or other insulating dielectric layers. The thickness of the tunneling dielectric layer and the blocking layer can be 5nm to 50nm.
[0026] The trap capture layer can be Si3N4, HfO2 or other insulating dielectric materials with a high trap density.
[0027] The gate, the source electrode and the drain electrode are made of metal materials, specifically can be Au, Pt, Cr, Ti, Ag, Bi, Sb, W, TiN and other metal materials, or alloys composed of multiple metals.
[0028] When connecting the memory and computing unit to the self-activation in-memory computing method, the gate is connected to the word line, the source electrode is connected to the source line, and the drain electrode is connected to the bit line.
[0029] The present invention mainly has the following characteristics and effects:
[0030] (1) The in-memory computing method with ReUL self-activation function proposed by the present invention performs self-activation function operations while performing multiplication and addition operations, saving an additional self-activation function module.
[0031] (2) The in-memory computing array with ReUL self-activation function proposed by the present invention adds a self-activation function while performing multiplication operations, eliminating the need for an additional activation circuit, thereby reducing power consumption.
[0032] (3) The two-dimensional material memory and computing unit proposed by the present invention utilizes a bipolar channel material through the electrostatic doping effect, enabling it to exhibit an n-type channel or a p-type channel, thereby realizing the self-activation function.
[0033] (4) By taking advantage of the ultra-thin characteristics of two-dimensional materials, the present invention can perform good gate control and appropriate energy band design, enabling fast data writing and effectively accelerating the memory and computing speed in in-memory computing. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a flowchart of the self-activation in-memory computing method of the present invention.
[0035] Figure 2 is a schematic diagram of the structure of the self-activation in-memory computing array of the present invention.
[0036] Figure 3 is a working state table of the self-activation in-memory computing unit of the present invention.
[0037] Figure 4 is a schematic diagram of the structure of the self-activation in-memory computing unit based on two-dimensional flash memory proposed by the present invention.
[0038] Figure 5 is a schematic diagram of the working principle of the storage state of the self-activation in-memory computing unit proposed by the present invention.
[0039] Figure 6 is a schematic diagram of the working principle of the operation state of the self-activation in-memory computing unit proposed by the present invention.
[0040] In the figure, reference numerals: 1 - in-memory computing unit with ReLU self-activation characteristics, 2 - current-voltage converter, 3 - row controller, 4 - column controller, 5 - two-dimensional channel material, 6 - tunneling dielectric layer, 7 - trap capture layer, 8 - blocking layer, 9 - gate, 10 - source, 11 - drain, 12 - hole, 13 - electron. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0041] The present invention will be further described below through embodiments in conjunction with the accompanying drawings.
[0042] Self-activating in-memory computing, whose computing process is as Figure 1 shown, and the specific steps are as follows:
[0043] S1 The row controller 3 and column controller 4 input data to the in-memory computing unit 1 with ReLU self-activating characteristics via the word line and source line.
[0044] S2 The in-memory computing unit 1 with ReLU self-activating characteristics performs multiplication and ReLU activation operations based on the formula output = max{0, input * weight}
[0045] S3 The in-memory computing unit 1 outputs the operation result in the form of current to the bit line
[0046] S4 The output results of multiple in-memory computing units are accumulated on the bit line to generate the output of the multiply-accumulate operation, and are output in the form of voltage through the current-voltage converter 2.
[0047] The overall in-memory computing array, its structure is shown in Figure 2 shown, where only an m*n memory-computation unit array is shown here.
[0048] Each row of memory-computation units shares a word line WL, and each column of memory-computation units shares a bit line BL and a source line SL. The word line WL is controlled by the row controller 3, the bit line BL is controlled by the column controller 4, and the source line SL generates the current output of the multiply-accumulate operation, is connected to the current-voltage converter 2, and converts the output into a voltage output.
[0049] In one embodiment, the current-voltage converter uses a common-drain connected two-dimensional flash transistor, where the drain is grounded, the source is connected to the bit line, and at the same time generates a voltage output.
[0050] In one embodiment, the voltage output can be output to the external circuit as the operation result; in another embodiment, this voltage output is used as the input of the subsequent in-memory computing array.
[0051] The working method of the in-memory computing array is as follows: During storage, by inputting a large positive pulse or negative pulse on the word line by the row controller, the weight of the memory-computation unit is written as -1 or 1. In one embodiment, the positive pulse is +33V, 30ns; the negative pulse is -30V, 20ns, which is used when a higher programming speed of the storage array is required. In another embodiment, the positive pulse is +19V, 50ms; the negative pulse is -19V, 50ms, and at this time, the reliability can be improved and the requirements for the control circuit can be reduced. During calculation, WL is used as an external input, multiplied by the stored weight, and the output is accumulated on the bit line BL in the form of current to achieve the MAC function. In one embodiment, the input voltage V = 3V is used for 1 input, and the input voltage V = -3V is used for -1 input.
[0052] The self-activation effect of the memory and computing unit is as follows Figure 3 As shown. When the signs of the input and the weight are the same, the output after the operation of the memory and computing unit is 1, that is, a positive current output is generated; when the signs of the input and the weight are opposite, for example, the input is 1 and the weight is -1; or the input is -1 and the weight is 1, the normal multiplication operation should produce a result of -1, that is, a negative current output, while the actually self-activated memory and computing unit will produce an output of 0, that is, a very small current output. The current output generated by the self-activation multiplication operation accumulates on the bit line based on Kirchhoff's current law to form the final self-activation multiply-accumulate output result.
[0053] The self-activation memory and computing unit structure based on two-dimensional flash memory is as follows Figure 4 As shown, in which the two-dimensional channel material 5, the tunneling dielectric layer 6, the trap capture layer 7, and the blocking layer 8 form a storage stack from bottom to top, the gate 9 is located on the side of the blocking layer, and the source 10 and the drain 11 are connected to the two-dimensional channel material and are located at both ends of the channel. In one embodiment, the two-dimensional channel material uses mechanically exfoliated 6nm multi-layer WSe2, the tunneling dielectric layer uses mechanically exfoliated 10nm multi-layer hBN, the trap capture layer uses ALD-grown 6nm HfO2, and the blocking layer uses ALD-grown 20nm Al2O3. The gate, source, and drain use evaporated Cr / Au. When connected to Figure 1 the in-memory computing array shown, the gate 9 is connected to the Figure 1 word line WL shown, the drain 10 is connected to the Figure 1 bit line BL shown, and the source 11 is connected to the Figure 1 source line SL shown.
[0054] The working principle of the self-activated memory and computing unit is as follows Figure 5 、 Figure 6 As shown. In the storage state, when a negative pulse is applied to the gate for writing, holes tunnel into the trap capture layer 3, and the memory and computing unit stores weight = 1. At this time, the channel is induced to be n-type by the holes in the trap capture layer, and the transistor exhibits the performance of an nMOS; when a positive pulse is applied to the gate for writing, electrons tunnel into the trap capture layer 3, and the memory and computing unit stores weight = -1. At this time, the channel is induced to be p-type by the electrons in the trap capture layer, and the transistor exhibits the performance of a pMOS. In one embodiment, the positive pulse is +33V, 30ns; the negative pulse is -30V, 20ns, which can improve the programming speed of the storage.
[0055] In the operation state, when the weight of the self-activating memory-computation unit weight = 1, the transistor behaves as an nMOS. When the input input = 1 and a positive voltage is applied to the gate, the nMOS is turned on at this time, and a large number of electrons are induced in the two-dimensional channel material, forming a large current, and the output is 1; when the input input = -1 and a negative voltage is applied to the gate, the nMOS is turned off at this time, there are few carriers in the two-dimensional channel material, the current is extremely small, and the output is 0. When the weight of the self-activating memory-computation unit weight = -1, the transistor behaves as a pMOS. When the input input = 1 and a positive voltage is applied to the gate, the pMOS is turned off at this time, there are few carriers in the two-dimensional channel material, the current is extremely small, and the output is 0; when the input input = -1 and a negative voltage is applied to the gate, the pMOS is turned on at this time, and a large number of holes are induced in the two-dimensional channel material, forming a large current, and the output is 1.
[0056] It can be seen that this memory-computation unit can implement a multiplication operation with the ReLU activation function. When the stored weight and the input value have the same sign, the multiplication result is positive, and a corresponding large current is output; when the stored weight and the input value have opposite signs, the multiplication result is negative, and the output is 0. Connecting this self-activating memory-computation unit to the in-memory computing array can achieve the self-activating effect of the in-memory computing array, thereby reducing the area and power consumption introduced by the additional self-activation function.
[0057] In summary, compared with the existing in-memory computing methods, the self-activating in-memory computing multiplication and addition method provided by the present invention, on the one hand, by adding the self-activating ReLU function while performing the multiplication operation, it is possible to avoid using an additional external activation circuit, thereby reducing the area and power consumption; on the other hand, using a two-dimensional material memory-computation unit, the bipolar channel material is used through the electrostatic doping effect, that is, by using electrons or holes in the trap capture layer, the channel material can behave as an n-type channel or a p-type channel, controlling the polarity of the transistor, and realizing the self-activation function. In addition, by using the thin layer characteristics and excellent gate control ability of two-dimensional materials, as well as flexible energy band design, it is possible to achieve fast storage and erasure operations of in-memory computing units, improving the speed of in-memory computing.
[0058] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.
Claims
1. A self - activating in - memory computing method based on two - dimensional flash memory, characterized in that, It can implement the ReUL activation function, that is, when the input is positive, the original value is output, and when it is negative, 0 is output to achieve sparse activation without additional external circuit structures; the in-memory computing unit (abbreviated as the computing-in-memory unit) involving self-activation in the calculation and the array composed of the computing-in-memory units (abbreviated as the in-memory computing array), row and column controllers (including row controller and column controller); the specific steps are as follows: (1) The computing-in-memory unit array receives input data through the row and column controllers; (2) The computing-in-memory unit performs a multiplication operation based on the stored weights and the input data, and implements the ReUL activation operation; (3) The computing-in-memory unit outputs the operation result after the multiplication operation and the activation operation in the form of current; (4) The current outputs of multiple computing-in-memory units are cumulatively summed on the bit line to generate the current output of the multiply-accumulate operation, and a voltage output is generated through current-voltage conversion.
2. The self-activation in-memory computing method according to claim 1, wherein: The receiving of the input data is parallel input or serial input; The weights and the input data are signed 1-bit, 2-bit or multi-bit data; The ReUL activation operation is specifically that when the input is positive, the original value is output, and when the input is negative, 0 is output; The multiplication operation and the ReUL activation operation are both implemented in the computing-in-memory unit at the same time.
3. The self-activating in-memory computing method according to claim 2, wherein The self-activation in-memory computing array includes a computing-in-memory unit array, word lines, bit lines, source lines, row controllers, column controllers, and an optional conversion unit; the computing-in-memory units in the same column share the bit line and the source line, and the computing-in-memory units in the same row share the word line; the row controller is connected to the word line, the column controller is connected to the source line, and the conversion unit is connected to the bit line.
4. The self-activating in-memory computing method according to claim 3, wherein The computing-in-memory unit includes a two-dimensional material flash memory device with self-activation properties, which is used to implement weight storage and a multiplication operation with ReUL self-activation properties. Specifically, after completing the multiplication operation of the input and the weight, when the operation result is negative, 0 is input, and when the operation result is positive, the operation result is output; The computing-in-memory unit can store signed weight data, and the signed weight data is 1-bit, 2-bit or multi-bit; The storage state of the computing-in-memory unit is controlled by the row controller and the column controller through the word line and the bit line; specifically, for the selected computing-in-memory unit, the row controller applies a programming pulse through the word line, and the column controller sets the corresponding bit line to the programming potential to program the selected unit as required; The programming pulse programs the symbol and magnitude of the weight stored in the two-dimensional material flash memory device by setting the polarity, amplitude and pulse width; When the computing-in-memory unit performs a multiplication operation, the row controller inputs data through the word line, performs a multiplication operation with the weights stored in the computing-in-memory unit, and the operation result of each unit is output to the bit line in the form of current and accumulated through the bit line to implement the multiply-accumulate operation function.
5. The self-activating in-memory computing method according to claim 4, wherein Due to the self-activation characteristic of the memory and computing unit, the operation result in the form of current for each memory and computing unit is as follows: when the multiplication operation result is negative, that is, the input data has the opposite sign to the stored weight, the current is extremely small, that is, the output is 0 instead of a negative value; when the multiplication operation result is positive, that is, the input data has the same sign as the stored weight, the output current is positive and the magnitude of the current reflects the magnitude of the multiplication operation result, that is, the operation result is output.
6. The self-activation in-memory computing method according to claim 5, wherein The conversion unit is used to convert the current output of the multiply-add operation into a voltage, which is output as the calculation result or applied as an input to the subsequent in-memory computing array; the conversion unit is a transistor, an inverter or an amplifier.
7. The self-activating in-memory computing method according to claim 6, wherein The memory and computing unit is a two-dimensional flash memory device, and its structure includes: a two-dimensional material channel, a tunneling dielectric layer, a trap capture layer, a blocking layer, a gate, a source electrode and a drain electrode; wherein the two-dimensional material channel, the tunneling dielectric layer, the trap capture layer and the blocking layer form a stacked structure; the gate is located above the blocking layer, and the source electrode and the drain electrode are in contact with the two-dimensional material channel and are located on both sides.
8. The self-activation in-memory computing method according to claim 7, wherein: The material of the two-dimensional material channel is single-layer or multi-layer graphene, transition metal dichalcogenides (TMDs), and other two-dimensional semiconductor materials; The materials of the tunneling dielectric layer and the blocking layer are two-dimensional insulating dielectric hBN, or oxide insulating dielectrics HfO2, Al2O3 or SiO2; the thickness of the tunneling dielectric layer and the blocking layer is 5nm to 50nm; The material of the trap capture layer is an insulating dielectric material Si3N4 or HfO2 with a high trap density; The gate, the source electrode and the drain electrode are made of metal materials, specifically selected from Au, Pt, Cr, Ti, Ag, Bi, Sb, W, TiN.
9. A self-activated memory-computation unit, characterized in that, It is a two-dimensional material flash memory device, and its structure includes: a two-dimensional material channel, a tunneling dielectric layer, a trap capture layer, a blocking layer, a gate, a source electrode and a drain electrode; wherein the two-dimensional material channel, the tunneling dielectric layer, the trap capture layer and the blocking layer form a stacked structure; the gate is located above the blocking layer, and the source electrode and the drain electrode are in contact with the two-dimensional material channel and are located on both sides; The material of the two-dimensional material channel is single-layer or multi-layer graphene, transition metal dichalcogenides (TMDs), and other two-dimensional semiconductor materials; The materials of the tunneling dielectric layer and the blocking layer are two-dimensional insulating dielectric hBN, or oxide insulating dielectrics HfO2, Al2O3 or SiO2; the thickness of the tunneling dielectric layer and the blocking layer is 5nm to 50nm; The material of the trap capture layer is an insulating dielectric material Si3N4 or HfO2 with a high trap density; The gate, the source electrode and the drain electrode are made of metal materials, specifically selected from Au, Pt, Cr, Ti, Ag, Bi, Sb, W, TiN.
10. A self-activated in-memory computing array, characterized in that, It includes an array, word lines, bit lines, source lines, a row controller, a column controller, and an optional conversion unit composed of the memory and computing units described in claim 9; the memory and computing units located in the same column share the bit lines and the source lines, and the memory and computing units located in the same row share the word lines; the row controller is connected to the word lines, the column controller is connected to the source lines, and the conversion unit is connected to the bit lines.