Memory device, memory system having same, and method of operating same

Abstract

The invention discloses a memory device, a memory system having the same and an operating method thereof. The method of operating the memory device includes receiving a quadrature clock and performing quadrature error correction of the quadrature clock in a non-sequential scheme, where the quadrature clock includes a first clock, a second clock, a third clock, and a fourth clock having sequential phases.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0011415, filed with the Korean Intellectual Property Office on January 25, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present inventive concept relates to a memory device, a memory system having the same, and an operating method thereof. Background Art

[0003] Generally, a four-phase clock (quadrature clock) may be a clock used in a memory device and other digital systems. The four-phase clock indicates time and may be mainly used to control and synchronize the transfer and storage speeds of data. This may be a periodically variable clock and may have four states (e.g., 0°, 90°, 180°, and 270°) during one period. When a four-phase clock is used, data may be transferred or stored at a faster rate. The clock may help accurately control the timing of data transfer and storage and synchronize with other system components. The period and phase of the four-phase clock should be maintained; otherwise, errors may occur in the transfer and storage of data. To this end, the four-phase clock should be generated and corrected in a clock generator and a distributor. Phase correction of the clock may be mainly performed using a feedback loop. In this loop, the clock may be measured and compared to adjust the signal. A phase correction algorithm may be used to accurately adjust the clock to 0°, 90°, 180°, and 270°. Phase correction of the clock may correct fine errors or delays in the period to maintain accurate timing of data and prevent the occurrence of errors. When data is stably transferred or stored using a four-phase clock, the integrity and reliability of the data may be improved. Data loss or errors may be minimized to improve the performance of the system. Summary of the Invention

[0004] Some aspects of the present inventive concept provide a memory device that performs a new quadrature error correction, a memory system having the same, and an operating method thereof.

[0005] Some aspects of the present inventive concept provide a memory device that performs quadrature error correction at a faster rate while reducing the chip size, a memory system having the same, and an operating method thereof.

[0006] According to some aspects of the inventive concept, a method of operating a memory device includes: receiving a first clock, a second clock, a third clock, and a fourth clock having sequential phase differences; during a first clock cycle, while detecting a first phase difference between the third clock and the fourth clock, updating a first delay code corresponding to a first delay line; during a second clock cycle, while detecting a second phase difference between the second clock and the third clock, updating a fourth delay code corresponding to a fourth delay line according to the first phase difference; during a third clock cycle, while detecting a third phase difference between the first clock and the second clock, updating a third delay code corresponding to a third delay line according to the second phase difference; during a fourth clock cycle, updating a second delay code corresponding to the fourth delay line according to the third phase difference; and during a fifth clock cycle, detecting a fourth phase difference between the fourth clock and the first clock.

[0007] According to some aspects of the inventive concept, a memory device includes: a first clock line, a second clock line, a third clock line, and a fourth clock line that respectively output a first clock, a second clock, a third clock, and a fourth clock having sequential phase differences; a multiplexer that selects a first clock output signal and a second clock output signal from the first clock line to the fourth clock line in response to a selection signal; a first delay line configured to receive the first clock output signal; a second delay line configured to receive the second clock; a third delay line configured to receive the third clock; a fourth delay line configured to receive the fourth clock; a phase detector configured to detect a phase difference between the clock delayed by the first delay line and the clock of the second clock output signal; and digital logic configured to: generate a delay code corresponding to the phase difference and control a delay line corresponding to the delay code among the first delay line to the four delay lines, and the digital logic is configured to: generate a selection signal to select two clocks among the first clock to the fourth clock according to a non-sequential scheme.

[0008] According to some aspects of the inventive concept, a memory system includes: at least one memory device; and a memory controller configured to control the at least one memory device, where the at least one memory device includes: a memory cell array having memory cells connected to word lines and bit lines; an orthogonal error correction circuit configured to receive an orthogonal clock and correct the orthogonal clock; a clock generator configured to generate the corrected orthogonal clock as an internal clock; and control logic configured to control write operations and read operations of the memory cell array, and the orthogonal error correction circuit is configured to correct the orthogonal clock with one phase detector according to a non-sequential scheme.

[0009] According to some aspects of the inventive concept, a method of operating a memory device includes: receiving an orthogonal clock; and performing orthogonal error correction of the orthogonal clock in a non-sequential scheme, the orthogonal clock including a first clock, a second clock, a third clock, and a fourth clock having sequential phases. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a diagram showing a general orthogonal clock.

[0011] Figure 2 is a diagram showing an orthogonal error correction circuit.

[0012] Figure 3 is a diagram showing a sequential correction operation of the orthogonal error correction circuit.

[0013] Figure 4 is a diagram showing a general orthogonal error correction circuit.

[0014] Figure 5 is a diagram showing an operation of the orthogonal error correction circuit for expanded orthogonal error correction.

[0015] Figure 6 is a diagram showing an orthogonal error correction operation in a non-sequential scheme according to some example embodiments.

[0016] Figure 7 is a diagram showing a timing of an orthogonal error correction operation performed in a general sequential scheme.

[0017] Figure 8 is a diagram showing a timing of an orthogonal error correction operation performed in a non-sequential scheme according to some example embodiments.

[0018] Figure 9 is a flowchart showing an operation of an orthogonal error correction circuit according to some example embodiments.

[0019] Figure 10 is a diagram showing a memory system 10 according to some example embodiments.

[0020] Figure 11 is a more detailed diagram showing Figure 10 a memory device according to some example embodiments.

[0021] Figure 12 is a diagram showing a memory device according to some example embodiments.

[0022] Figure 13is a diagram showing the operation of a memory device according to some example embodiments.

[0023] Figure 14 is a diagram showing a memory system according to some example embodiments.

[0024] Figure 15 is a diagram showing a method of generating a strobe signal for a memory device according to some example embodiments.

[0025] Figure 16 is a diagram showing a memory system according to some example embodiments.

[0026] Figure 17 is a diagram showing a multi-layer memory device according to some example embodiments.

[0027] Figure 18 is a diagram showing a semiconductor package according to some example embodiments.

[0028] Figure 19 is a diagram showing an HBM package according to some example embodiments. DETAILED DESCRIPTION

[0029] Hereinafter, the content of the inventive concept will be described clearly and in detail with reference to the accompanying drawings, so that those of ordinary skill in the technical field of the inventive concept can easily implement the inventive concept.

[0030] A memory device and an operation method thereof according to some example embodiments of the present invention can correct a phase error quickly and accurately and are insensitive to mismatches. The memory device of the present invention may include a delay line, a multiplexer, a bang-bang phase detector (BBPD), a loop filter, and control logic. The memory device and operation method of the present invention can correct the phase error non-sequentially and increase the loop speed regardless of the mismatch. In other words, the memory device of the present invention can accurately correct the phase error to 0 with a fast lock time. Compared with sequential phase error correction, the memory device of the present invention can minimize the wait cycle through non-sequential phase error correction. In addition, compared with using multiple loops, the memory device of the present invention can achieve a faster lock time without mismatch problems by using only one loop. Figure 1It is a diagram showing a general orthogonal clock. The data transfer speed required for the memory interface is constantly increasing. Therefore, an orthogonal clock (4-phase clock) can be used to mitigate the increasing internal clock frequency accordingly and improve the timing margin. The first clock I, the second clock Q, the third clock IB, and the fourth clock QB with sequential phases are shown. Two adjacent clocks among the first clock I, the second clock Q, the third clock IB, and the fourth clock QB can have a 90° phase difference from each other. For example, the first clock I and the second clock Q can have a 90° phase difference, the second clock Q and the third clock IB can have a 90° phase difference, the third clock IB and the fourth clock QB can have a 90° phase difference, and the fourth clock QB and the first clock I can have a 90° phase difference.

[0031] Generally, due to PVT (process, voltage, temperature) variations, mismatches, etc. of the clock buffer circuit, phase errors can inevitably occur between orthogonal clocks. Since this causes margin degradation, orthogonal error correction (QEC) for correcting the phase clock may be necessarily used in interfaces using orthogonal clocks. Such QEC can be implemented with an analog circuit or a digital circuit.

[0032] Figure 2 It is a diagram showing an orthogonal error correction circuit. Refer to Figure 2 , the orthogonal error correction circuit 100 may include clock lines 101 to 104, a multiplexer (MUX) 110, delay lines 121 to 124, a phase detector (PD) 130, and digital logic 140.

[0033] The clock lines 101 to 104 can respectively output the clock I corresponding to them and having a sequential phase difference OUT , the clock Q OUT , the clock IB OUT , and the clock QB OUT .

[0034] The multiplexer 110 can be implemented to select two of the first clock line 101 to the fourth clock line 104 in response to a selection signal SEL, and output a first clock output signal Y1 and a second clock output signal Y2 corresponding to two of the first clock line 101 to the fourth clock line 104.

[0035] The first delay line (REF) 121 can be implemented to delay the first clock output signal Y1 according to a first delay code. In this case, the first delay code can be controlled by the digital logic 140. The second delay line 122 can be implemented to delay the second clock Q according to a second delay code IN . The delayed second clock Q INIt can be output to the second clock line 102 via a buffer. In this case, the second delay code can be controlled by the digital logic 140. The third delay line 123 can be implemented to delay the third clock IB according to the third delay code IN . The delayed third clock IB IN can be output to the third clock line 103 via a buffer. In this case, the third delay code can be controlled by the digital logic 140. The fourth delay line 124 can be implemented to delay the fourth clock QB according to the fourth delay code IN . The delayed fourth clock QB IN can be output to the fourth clock line 104 via a buffer. In this case, the fourth delay code can be controlled by the digital logic 140.

[0036] The phase detector 130 can be implemented to detect the phase difference PD between the clock delayed by the first delay line (REF) 121 and the clock of the second clock output signal Y2 OUT . In some example embodiments, the phase detector 130 can be implemented as a switched phase detector.

[0037] The digital logic 140 can be implemented to generate a selection signal SEL to perform an orthogonal error correction operation, or generate the first to fourth delay codes corresponding to the phase difference PD OUT .

[0038] Figure 3 is a diagram showing the sequential correction operation of the orthogonal error correction circuit 100. Referring to Figure 3 , the phase detector 130 can sequentially detect the phase errors of two adjacent clocks (PD OUT -Q OUT , Q OUT -IB OUT , IB OUT -QB OUT , and QB OUT -I OUT in the order of OUT ). The digital logic 140 can generate a delay code (or called a delay line code) according to the output phase difference (PD OUT ), and can adjust the delay lines 121 to 124 of Q, IB, QB, and REF by using the delay code, so that two adjacent clocks can be corrected to have a 90° phase difference. The orthogonal error correction circuit 100 can solve the offset between different phase detectors generated when using multiple phase detectors by using only one phase detector 130.

[0039] As Figure 3 shown, such a sequential algorithm can detect the current phase error to update the delay line code, and then can detect the phase error thereafter. For example, in order to detect QOUT -IB OUT phase error of, can detect I OUT -Q OUT phase error of, and can update the delay line code of Q, and can update the input delay of the phase detector 130 via the buffer and the multiplexer 110. Therefore, after the phase error is detected, it may take at least one clock cycle until the input delay of the phase detector 130 is updated through the delay line and the buffer. One loop operation may require at least 8 clock cycles. Therefore, a relatively long QEC lock time may be spent. When there are n loop operations, the n loop operations may require at least 8×n clock cycles, where n is a positive integer greater than 0.

[0040] Figure 4 is a diagram showing the general quadrature error correction circuit 200. Referring to Figure 4 , the quadrature error correction circuit 200 may include a first multiplexer 211, a second multiplexer 212, delay lines 221-1, 221-2, 222, 223 and 224, a first phase detector 231, a second phase detector 232 and digital logic 240.

[0041] Figure 5 is a diagram showing the operation of the unrolled QEC of the quadrature error correction circuit 200. As Figure 5 shown, the unrolling technique can be used to reduce the lock time. Phase error detection (such as, I-Q or IB-QB) can be performed simultaneously and independently of each other to significantly reduce the lock time. Assuming that the loop operation in Figure 3 requires 8 clock cycles, the unrolling technique in Figure 5 can spend 6 clock cycles in the first loop and 4 clock cycles thereafter. As the loop operation increases according to the initial state, when compared with the lock time in Figure 3 , the lock time can converge to 1 / 2. As Figure 5 shown, two phase detectors 231 and 232 and the loop can be used for the unrolling operation. This can cause an offset problem.

[0042] According to some example embodiments, the quadrature error correction circuit can use one phase detector to detect the phase error in a non-sequential scheme to reduce the offset problem while reducing the lock time.

[0043] Figure 6 is a diagram showing Figure 2 the quadrature error correction operation in the non-sequential scheme in the quadrature error correction circuit 100. As Figure 6 shown, by using the non-sequential algorithm, the lock time of the quadrature error correction circuit 100 in Figure 2 can be significantly improved.

[0044] The phase detector 130 can detect the phase error between two adjacent clocks in the order of IB OUT -QB OUT 、Q OUT -IB OUT 、I OUT -Q OUT and QB OUT -I OUT , generate a delay code according to the detected phase error, and control / adjust / regulate the delay lines 124, 123 and 122 of QB, IB and Q according to the delay code. Such a non-sequential scheme does not require waiting for the update of the previous delay line code at the next detection of the phase error. For example, the phase error of IB OUT -QB OUT can be detected, and the delay line code of QB can be updated. Although the delay can be updated through a buffer, the phase detection of Q OUT -IB OUT independent of QB can be performed simultaneously. Therefore, a separate clock cycle for updating the delay line may not be required.

[0045] One of the four clocks I, Q, IB, and QB can be used as the clock for the digital logic. Since the timing margin of one of the four phase detection operations of IB OUT -QB OUT 、Q OUT -IB OUT 、I OUT -Q OUT and QB OUT -I OUT is insufficient, therefore, according to the type of the clock, in one operation, an additional clock cycle can be used to ensure the margin. For example, when QB is used as the clock for the digital logic 140, since the timing margin is insufficient to update the reference delay line 121 during the period from the phase error detection of QB OUT -I OUT to the phase error detection of I OUT -Q OUT , an additional clock cycle can be used in the loop to update the reference delay line 121 to ensure the margin.

[0046] Figure 7 is a diagram showing the timing of the quadrature error correction operation performed in the general sequential scheme. As shown in Figure 7 , the phase error between adjacent clocks can be corrected sequentially. For example, the phase error of I OUT -Q OUT can be detected, the delay code of the delay line corresponding to Q OUT can be updated, the phase error of Q OUT -IBOUT The phase error of can update the delay code of the delay line corresponding to IB OUT and can detect the phase error of IB OUT -QB OUT The phase error of can update the delay code of the delay line corresponding to QB OUT and can detect the phase error of QB OUT -I OUT The phase error of, and can update the delay code of the reference delay line corresponding to REF

[0047] Figure 8 is a diagram showing the timing of an orthogonal error correction operation performed in a non-sequential scheme according to some example embodiments. Refer to Figure 8 and the orthogonal error correction operation can be performed in the following order

[0048] The phase error of IB - QB (e.g., the first phase difference) can be detected during the first clock cycle, and the first delay code of the reference delay line (e.g., the first delay line (REF) 121, see OUT -QB OUT ) can be updated simultaneously. Then, the phase error of Q - IB (e.g., the second phase difference) can be detected during the second clock cycle, and the fourth delay code of the delay line (e.g., the fourth delay line 124, see Figure 2 ) corresponding to QB can be updated according to the phase error of IB - QB (e.g., the first phase difference) detected simultaneously. Then, the phase error of I - Q (e.g., the third phase difference) can be detected during the third clock cycle, and the third delay code of the delay line (e.g., the third delay line 123, see OUT -IB OUT ) corresponding to IB can be updated according to the phase error of Q - IB (e.g., the second phase difference) detected simultaneously. Then, the phase error detection during the fourth clock cycle can wait for 1 clock cycle, and the second delay code of the delay line (e.g., the second delay line 122, see OUT -QB OUT ) corresponding to Q can be updated according to the phase error of I - Q (e.g., the third phase difference) detected simultaneously. In one embodiment, the second delay code can be updated during I - Q OUT The phase error of can update the delay code of the delay line corresponding to QB Figure 2 ) of the fourth delay code. Then, the phase error of I - Q (e.g., the third phase difference) can be detected during the third clock cycle, and the third delay code of the delay line (e.g., the third delay line 123, see OUT -Q OUT ) corresponding to IB can be updated according to the phase error of Q - IB (e.g., the second phase difference) detected simultaneously. Then, the phase error detection during the fourth clock cycle can wait for 1 clock cycle, and the second delay code of the delay line (e.g., the second delay line 122, see OUT -IB OUT ) corresponding to Q can be updated according to the phase error of I - Q (e.g., the third phase difference) detected simultaneously. In one embodiment, the second delay code can be updated during I - Q OUT (e.g., see Figure 2 ) corresponding to the delay line (e.g., the third delay line 123, see Figure 2 ). Then, the phase error detection during the fourth clock cycle can wait for 1 clock cycle, and the second delay code of the delay line (e.g., the second delay line 122, see OUT ) corresponding to Q can be updated according to the phase error of I - Q (e.g., the third phase difference) detected simultaneously. In one embodiment, the second delay code can be updated during I - Q Figure 2 ) can be updated according to the phase error of I - Q (e.g., the third phase difference) detected simultaneously. In one embodiment, the second delay code can be updated during I - Q OUT -Q OUT (e.g., the third phase difference). In one embodiment, the second delay code can be updated during I - Q OUT -Q OUTThe phase error (e.g., the third phase difference) is updated when it is output. Then, QB can be detected during the fifth clock cycle OUT -I OUT The phase error (e.g., the fourth phase difference). Then, the above process can be repeated. IB can be detected OUT -QB OUT The phase error, and the first delay code of the reference delay line can be updated simultaneously.

[0049] In some example embodiments, the first clock I OUT , the second clock Q OUT , the third clock IB OUT and the fourth clock QB OUT can be quadrature clocks with a sequential phase difference of 90°.

[0050] In some example embodiments, the third clock IB OUT and the fourth clock QB OUT can be selected during the first clock cycle in response to the selection signal SEL = 2'b10, and the first phase difference between the third clock IB OUT and the fourth clock QB OUT can be output. In some example embodiments, the second clock Q OUT and the third clock IB OUT can be selected during the second clock cycle in response to the selection signal SEL = 2'b01, and the second phase difference between the second clock Q OUT and the third clock IB OUT can be output. In some example embodiments, the first clock I OUT and the second clock Q OUT can be selected during the third clock cycle in response to the selection signal SEL = 2'b00, and the third phase difference between the first clock I OUT and the second clock Q OUT can be output. In some example embodiments, the detection of the clock phase difference can wait during the fourth clock cycle in response to the selection signal SEL = 2'b11. In some example embodiments, the fourth clock QB OUT and the first clock I OUT can be selected during the fifth clock cycle while maintaining the selection signal SEL = 2'b11, and the fourth phase difference between the fourth clock QB OUT and the first clock I OUT can be output. In some example embodiments, after the fourth phase difference is detected, the first delay code for controlling the delay of the first delay line can be updated according to the fourth phase difference.

[0051] In some example embodiments, it can be performed by the multiplexer 110 (see Figure 2From the first clock to the fourth clock I OUT , Q OUT , IB OUT and QB OUT to select two clock output signals Y1 and Y2.

[0052] When QEC is implemented using a non-sequential algorithm according to some example embodiments, the lock time can be improved by 5 / 8 without the offset problem of the phase detector 130 when compared with a sequential scheme. When the clock period for update can be increased due to an extended clock buffer, such lock time improvement effect can be increased. The orthogonal error correction circuit according to some example embodiments can (e.g., significantly) improve the lock time without (e.g., significantly) changing the structure of the general dynamic random access memory (DRAM) interface and input / output (I / O). For example, according to some example embodiments, there can be an improvement in the speed, accuracy, device lifetime, and / or power efficiency of the memory device based on the above methods. Thus, the improved devices and methods overcome the deficiencies of conventional devices and methods for operating memory devices while reducing resource consumption, extending device lifetime, increasing data accuracy, and increasing output.

[0053] Figure 9 is a flowchart showing the operation of an orthogonal error correction circuit according to some example embodiments. Referring to Figures 1 to 9 , the orthogonal error correction circuit can perform the orthogonal error correction operation as follows. The orthogonal error correction circuit 100 can receive an orthogonal clock (S110). In this case, the orthogonal clock can include a first clock I, a second clock Q, a third clock IB, and a fourth clock QB having sequential phases. The orthogonal error correction circuit 100 can perform orthogonal error correction in a non-sequential scheme (S120).

[0054] In some example embodiments, the clock can be received from an external device (e.g., a memory controller), and the orthogonal clock can be generated using the clock. In some example embodiments, the orthogonal error correction can be performed during five clock cycles.

[0055] In some example embodiments, the orthogonal error correction operation may include the following operations: during a first clock cycle, an operation of updating a first delay code corresponding to a first delay line while detecting a first phase difference between a third clock IB and a fourth clock QB; during a second clock cycle, an operation of updating a fourth delay code corresponding to a fourth delay line according to the first phase difference while detecting a second phase difference between a second clock Q and the third clock IB; during a third clock cycle, an operation of updating a third delay code corresponding to a third delay line according to the second phase difference while detecting a third phase difference between a first clock I and the second clock Q; during a fourth clock cycle, an operation of updating a second delay code corresponding to a second delay line according to the third phase difference; and an operation of detecting a fourth phase difference between the fourth clock QB and the first clock I during a fifth clock cycle. In some example embodiments, the operation of detecting the phase difference during the fourth clock cycle may be in a waiting state.

[0056] Figure 10 is a diagram showing a memory system 10 according to some example embodiments. Referring to Figure 10 , the memory system 10 may include a memory device 11 and a host device 12.

[0057] The memory device 11 may include a bank region 11-1 and a logic circuit (or control logic) 11-2. The logic circuit 11-2 may include a transmitting circuit that outputs a data signal DQ to the host device 12, and a receiving circuit that receives the data signal DQ, a command signal CMD, an address signal ADDR, etc. from the host device 12. In addition, the logic circuit 11-2 may include a clock circuit that generates a plurality of clocks with different phases using a first clock CLKI and a second clock CLKQ. In some example embodiments, the receiving circuit may be synchronized with the plurality of clocks to parallelize the data signal DQ received from the host device 12, and the transmitting circuit may be synchronized with the plurality of clocks to serialize the data to be output to the host device 12, thereby generating the data signal DQ.

[0058] The host device 12 may be an operation processing unit (such as, an application processor, a central processing unit, a system-on-chip, etc.). The host device 12 may include a memory controller capable of controlling the memory device 11, and may send a data signal DQ to the memory device 11 or receive the data signal DQ from the memory device 11. In addition, the host device 12 may send a command signal CMD, an address signal ADDR, a first clock CLKI, and a second clock CLKQ to the memory device 11. The first clock CLKI and the second clock CLKQ provided by the host device 12 to the memory device 11 may be external clocks and may have different phases. In some example embodiments, the first clock CLKI and the second clock CLKQ have the same frequency and the same duty cycle, and the second clock CLKQ may have a phase that is 90 degrees later than the first clock CLKI.

[0059] Due to a delay difference existing in the signal transmission path between the host device 12 and the memory device 11, a delay occurring in the memory device 11, etc., there may be an error in the phase difference between a plurality of clocks generated by a clock circuit using the first clock CLKI and the second clock CLKQ. In some example embodiments, when the clock circuit generates a first clock to a fourth clock having a 90-degree phase difference using the first clock CLKI and the second clock CLKQ, the phase difference between at least some of the clocks may be shown to have a degree different from 90 degrees.

[0060] The clock circuit may adjust the phase difference of the first clock to the fourth clock within a predetermined (or, optionally, desired, determined, or selected) locking time. In some example embodiments, the clock circuit may adjust the phase difference of the first clock to the fourth clock by selecting two clocks from the first clock to the fourth clock and repeating an operation of adjusting the phase difference between the two clocks. In some example embodiments, the clock circuit may adjust the phase difference of the first clock to the fourth clock by advancing or delaying the time point of the rising edge of another clock based on the rising edge of one of the two selected clocks.

[0061] The locking time may be predetermined (or, optionally, desired, determined, or selected) in the specification of the memory device 11, etc. Therefore, in order to eliminate the error in the phase difference between the first clock to the fourth clock during a predetermined (or, optionally, desired, determined, or selected) locking time, the clock circuit needs to efficiently adjust the phases of the first clock to the fourth clock.

[0062] Figure 11 is a diagram showing more details Figure 10 of the memory device 11. Refer to Figure 11, the memory device 11 may be a semiconductor device-based memory device. The memory device 11 may store data received through the data signal DQ, or may output data as the data signal DQ in response to an address signal ADDR and a command signal CMD received from an external host (e.g., a central processing unit (CPU), an application processor (AP), and a system on chip (SoC)).

[0063] The memory device 11 may include a plurality of bank regions 11-1. The bank region 11-1 may include a memory cell array 61, a row decoder 62, a sense amplifier 63, a column decoder 64, etc. The memory cell array 61 may include a plurality of memory cells, and the plurality of memory cells may be connected to the row decoder 62 and the sense amplifier 63 through a plurality of word lines WL and a plurality of bit lines BL. In some example embodiments, each of the plurality of memory cells may be located at a point where the plurality of word lines WL and the plurality of bit lines BL cross each other. The plurality of memory cells may be arranged in a matrix form in the memory cell array 61, and each of the plurality of memory cells may include at least one memory element for storing data. In this case, the memory element may be a volatile memory element or a non-volatile memory element.

[0064] The control logic 11-2 may receive the address signal ADDR, the command signal CMD, the first clock CLKI, and the second clock CLKQ from the host. The address signal ADDR may include a row address indicating a row in the memory cell array 61 and a column address indicating a column in the memory cell array 61. In some example embodiments, the row decoder 62 may select at least one of the plurality of word lines WL with reference to the row address, and the column decoder 64 may select the sense amplifier 63 connected to at least one of the plurality of bit lines BL with reference to the column address.

[0065] The sense amplifier 63 may include a plurality of bit line sense amplifiers connected to the memory cell array 61 through the plurality of bit lines BL. When a read operation is performed, the bit line sense amplifier connected to the selected bit line among the plurality of bit line sense amplifiers selected by the column decoder 64 may read the data of at least one cell connected to the selected bit line among the memory cells. The input / output circuit 72 of the control logic 11-2 may output the data read by the bit line sense amplifier as the data signal DQ.

[0066] The control logic 11-2 may include various logic circuits for controlling the memory bank area 11-1, and in some example embodiments, may include a clock circuit 71 and an input / output circuit 72. The clock circuit 71 may receive a first clock CLKI and a second clock CLKQ from an external device (e.g., a host), and may generate a plurality of clocks based on the first clock CLKI and supply them to the input / output circuit 72. The input / output circuit 72 may output a data signal DQ in synchronization with the plurality of clocks, or may extract data from the data signal DQ received from the outside. The clock circuit 71 may include a code generator, a delay circuit, and a clock tree. The code generator generates a delay code for adjusting the phase of the clock. The delay circuit adjusts the timing of the rising edge or the falling edge of the clock based on the delay code. The clock tree provides a transmission path for the clock.

[0067] Figure 12 is a diagram showing a memory device 300 according to some example embodiments. Referring to Figure 12 , the clock circuit included in the memory device 300 may include a clock receiver 310, a delay circuit 320, a clock tree 330, a phase splitter 340, a code generator 350, and a multiplexer 360. The plurality of clocks CLK output by the clock circuit may be input to the multiplexer 360. The multiplexer 360 may select one of the plurality of internal data signals DATA0 to DATA3 at the rising edge of each of the plurality of clocks CLK, and may output the selected signal as the data signal DQ. Accordingly, the speed of the data signal DQ may be higher than the speeds of the plurality of internal data signals DATA0 to DATA3.

[0068] The clock receiver 310 may include a receiver that receives the first clock CLKI and the second clock CLKQ. The first clock CLKI and the second clock CLKQ received by the clock receiver 310 may be sent to the delay circuit 320. The delay circuit 320 may adjust the timing of at least one of the rising edge and the falling edge in each of the first clock CLKI and the second clock CLKQ. In some example embodiments, the delay circuit 320 may adjust the falling edge of the first clock CLKI or the rising edge and the falling edge of the second clock CLKQ based on the delay code CD received from the code generator 350. In this case, the rising edge of the first clock CLKI may not be adjusted to a predetermined (or alternatively, desired, determined, or selected) reference time point.

[0069] The first clock CLKI and the second clock CLKQ output by the delay circuit 320 may be transmitted to the phase splitter 340 through the clock tree 330. The clock tree 330 may include at least one repeater for transmitting the first clock CLKI and the second clock CLKQ.

[0070] The phase splitter 340 can use the first clock CLKI and the second clock CLKQ to generate the first clock CLKI, the second clock CLKQ, the third clock CLKIB, and the fourth clock CLKQB. In some example embodiments, the first clock CLKI and the second clock CLKQ can have a 90-degree phase difference. The phase splitter 340 can generate the third clock CLKIB and the fourth clock CLKQB. The third clock CLKIB can be a complementary signal of the first clock CLKI, and the fourth clock CLKQB can be a complementary signal of the second clock CLKQ.

[0071] The code generator 350 can select two or more clocks from among the first to fourth clocks CLKI, CLKQ, CLKIB, and CLKQB, and can output a delay code CD for adjusting the phase difference between the selected clocks. In some example embodiments, the code generator 350 can receive clock output signals from among the first to fourth clocks CLKI, CLKQ, CLKIB, and CLKQB.

[0072] The code generator 350 can compare the clock output signals with each other to generate a delay code. The delay circuit 320 can adjust the timing of the edges of the clocks CLKI / CLKQ based on the delay code generated in a non-sequential scheme.

[0073] Figure 13 is a diagram showing the operation of a memory device according to some example embodiments. Referring to Figure 13 , the operation of the memory device 300 can be performed as follows. The first clock CLKI, the second clock CLKQ, the third clock CLKIB, and the fourth clock CLKQB can have different phases. In some example embodiments, the first clock CLKI and the second clock CLKQ can have a 90-degree phase difference, the first clock CLKI and the third clock CLKIB can have a complementary relationship, and the second clock CLKQ and the fourth clock CLKQB can have a complementary relationship.

[0074] The multiple internal data signals DATA0 to DATA3 generated in the memory device 300 can have the same speed. As referred to Figure 12 above, the multiplexer 360 can receive the multiple internal data signals DATA0 to DATA3 and the first to fourth clocks CLKI, CLKQ, CLKIB, and CLKQB, can select one of the multiple internal data signals DATA0 to DATA3 at the rising edge of each of the first to fourth clocks CLKI, CLKQ, CLKIB, and CLKQB, and can output the selected one as the data signal DQ.

[0075] Referring to Figure 13, the first data D0 transmitted as the first internal data signal DATA0 on the first rising edge of the first clock CLKI can be selected and output as the data signal DQ, and the second data D1 transmitted as the second internal data signal DATA1 on the first rising edge of the second clock CLKQ can be selected as the data signal DQ. Similarly, on the first rising edge of the third clock CLK1B, the third data D2 transmitted as the third internal data signal DATA2 can be output as the data signal DQ, and on the first rising edge of the fourth clock CLKQB, the fourth data D3 transmitted as the fourth internal data signal DATA3 can be selected and output as the data signal DQ.

[0076] In the inventive concept, an orthogonal clock can be generated therein using the received external clock CLK.

[0077] Figure 14 is a diagram showing a memory system 20 according to some example embodiments. Refer to Figure 14 , the memory system 20 may include a memory device 21 and a memory controller 22.

[0078] The memory device 21 can be used as, for example, an operating memory, a working memory, or a buffer memory in a computing system. In some example embodiments, the memory device 21 can be implemented as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small outline DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FBDIMM), a rank buffered DIMM (RBDIMM), a mini DIMM, a micro DIMM, a registered DIMM (RDIMM), or a load reduced DIMM (LRDIMM). In some example embodiments, the memory device 21 can be implemented as a volatile memory. For example, the volatile memory may include at least one of a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a low power double data rate SDRAM (LPDDR SDRAM), a graphics double data rate SDRAM (GDDR SDRAM), a rambus DRAM (RDRAM), and a static RAM (SRAM). In another embodiment, the memory device 21 can be implemented as a non-volatile memory. For example, the non-volatile memory may include any one of a NAND flash memory, a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a NOR flash memory.

[0079] The memory controller 22 can completely control the operation of the memory system 20 and can completely control the exchange of data between the external host and the memory device 21. For example, the memory controller 22 can control the memory device 21 to write or read data according to requests from the host. In addition, the memory controller 22 can apply operation commands for controlling the memory device 21 to control the operation of the memory device 21.

[0080] The memory controller 22 can send a clock CK (or command clock), a command CMD, and an address ADDR to the memory device 21. The memory controller 22 can provide a data clock WCK to the memory device 21 when writing a data signal DQ into the memory device 21 or reading the data signal DQ from the memory device 21. When sending the data signal DQ to the memory controller 22, the memory device 21 can provide a strobe signal DQS to the memory controller 22 together with the data signal DQ.

[0081] The memory device 21 can include a memory cell array 21-1 for storing data signals DQ, a quadrature error correction circuit (QEC) 21-2, a clock generation circuit (CLK Gen) 21-3, and a control logic 21-4. The control logic 21-4 can control the operation of the memory device 21. The QEC 21-2 can simultaneously adjust the skew and duty cycle error of an input clock QEC IN having a 90-degree phase difference generated based on the data clock WCK to generate a corrected clock QEC_OUT having a 90-degree phase difference. In addition, the QEC 21-2 can be implemented to perform phase error correction in a non-sequential scheme as Figures 1 to 13 described. The clock generation circuit 21-3 can generate an output clock and a strobe signal DQS based on the corrected clock QEC_OUT.

[0082] Figure 15FIG. is a diagram illustrating a method of generating a DQS signal of a memory device according to some example embodiments. A data clock buffer may receive a data clock WCK including a pair of differential clocks WCK_c and WCK_t, may generate a first clock CLKI (in-phase clock) and a second clock CLKQ (quadrature-phase clock) having a phase difference of 90° based on the data clock WCK, and may provide the first clock CLKI and the second clock CLKQ to a QEC. The QEC may correct the skew between the first clock CLKI and the second clock CLKQ and the duty cycle error of the first clock CLKI and the second clock CLKQ, may generate corrected clocks CCLKI and CCLKQ having a phase difference of 90°, and may provide them to a clock generation circuit. The clock generation circuit may generate an output clock OCLK and a strobe signal DQS based on the corrected clocks CCLKI and CCLKQ, and may provide the output clock OCLK and the strobe signal DQS to a data input / output buffer. The output clock may be a plurality of clocks having different phases. In one embodiment, the clock generation circuit may generate internal clocks having different phases based on the corrected clocks.

[0083] The control logic 21-4 may control the operation of the memory device 21. For example, the control logic 21-4 may generate control signals such that the memory device 21 performs a write operation or a read operation. The control logic 21-4 may include a command decoder that decodes a command CMD received from the memory controller 22 and a mode register that sets an operation mode of the memory device 21.

[0084] Figure 16 FIG. is a diagram illustrating a memory system 700 according to some example embodiments. Referring to Figure 16 , the memory system 700 may include a plurality of memory modules 701 to 704 and a memory controller 750.

[0085] Each of the plurality of memory modules 701 to 704 may be implemented to control the clock / data delay, slew, or drive strength of a transmission line according to a data pattern when transmitting data. The plurality of memory modules 701 to 704 may include at least one memory device that performs QEC in a non-sequential scheme as described in Figures 1 to 15 .

[0086] In some example embodiments, each of memory modules 701 to 704 may be implemented in the form of a single inline memory module (SIMM) or a dual inline memory module (DIMM). In some example embodiments, memory modules 701 to 704 and a memory controller 750 may be mounted on a system board to transmit and receive data DATA and commands / addresses CMD / ADD through wirings on the system board. Memory devices (e.g., memory devices 710, 720, 730, and 740) included in the memory system 700 may constitute multiple ranks. In some example embodiments, memory devices mounted on different memory modules may be defined as being included in different ranks. Optionally, among memory devices mounted on the same memory module, a memory device mounted on one surface of the module board and a memory device mounted on the other surface of the module board may be defined as being included in different ranks. Memory modules 701 to 704 may be mounted at different positions on the system board, and thus, memory devices of different ranks may send data DATA to and receive data DATA from the memory controller 750 at different physical distances (such as Figure 16 distances a, b, c, and d shown). In one embodiment, the memory controller 750 may include a module information generator for exchanging information (e.g., info_M) with memory modules 701 to 704.

[0087] In some example embodiments, the resistances of data (DATA) transmission paths between memory modules 701 to 704 and the memory controller 750 may be different from each other. In some example embodiments, the physical distance between the first memory module 701 and the memory controller 750 may be relatively short, while the physical distance between the fourth memory module 704 and the memory controller 750 may be relatively long. Accordingly, a training operation according to a data pattern may be performed for each of the memory modules, and optimal timing control may be performed before data transmission according to the result of the execution.

[0088] In some example embodiments, Figures 1 to 15 the memory devices described in

[0089] Figure 17 may be implemented as multi-layer memory devices. Figure 17, the multi-layer memory device 1000 may include a buffer die 1010, a first core die 1020, and a second core die 1030. The first core die 1020 and the second core die 1030 may support the same channel CHa 1001 among multiple channels. In this case, the core dies 1020 and 1030 may be identified by a stack ID SID. For example, the first core die 1020 may correspond to the first stack ID SID0, and the second core die 1030 may correspond to the second stack ID SID1. Although no core die is shown as being disposed between the first core die 1020 and the second core die 1030, different core dies may be located between the first core die 1020 and the second core die 1030.

[0090] The buffer die 1010 and the core dies 1020 and 1030 may communicate through TSVs 1002 and 1003 located in a through-silicon via (TSV, or through-silicon via) region. For example, the buffer die 1010 may send an internal command iCMD to the first core die 1020 or the second core die 1030 through the TSV 1002, and may send data DATA to the first core die 1020 or the second core die 1030 and receive data DATA from the first core die 1020 or the second core die 1030 through the TSV 1003. As Figure 17 shown, although the buffer die 1010 is shown as communicating with the core dies 1020 and 1030 using the same TSVs 1002 and 1003, the buffer die 1010 may communicate using separate TSVs corresponding to each of the core dies 1020 and 1030.

[0091] The second core die 1030 may include a command decoder 1031, a data input / output (I / O) circuit 1032, and a memory cell array 1033. The command decoder 1031, the data input / output circuit 1032, and the memory cell array 1033 may operate in substantially the same manner as the command decoder 1021, the data input / output circuit 1022, and the memory cell array 1023 of the first core die 1020.

[0092] The C / A receiver 1011 may latch the command / address signal C / A based on the clock CK to receive the command CMD and the stack ID SID. The stack ID SID may be an address representing at least one core die to distinguish core dies that support the same channel. The received command CMD and stack ID SID may be provided to the control logic circuit 1012.

[0093] The control logic circuit 1012 may send an internal command iCMD to at least one of the first core die 1020 and the second core die 1030 based on the stack ID SID. For example, when the stack ID SID indicates the first stack ID SID0, the control logic circuit 1012 may send the internal command iCMD to the first core die 1020. In one embodiment, the control logic circuit 1012 may receive a power supply signal PWS from the outside and may send a reset signal RESET to the memory interface 1015.

[0094] In some example embodiments, as Figure 17 shown, when the internal command iCMD and the data DATA are sent to the core dies 1020 and 1030 through the common TSVs 1002 and 1003, the buffer die 1010 may send the stack ID SID to the core dies 1020 and 1030. The core dies 1020 and 1030 may decode the sent stack ID SID and may selectively receive the internal command iCMD and the data DATA. For example, when the stack ID SID indicates the first stack ID SID0, the first core die 1020 may receive the internal command iCMD and the data DATA sent through the TSVs 1020 and 1030. In this case, the second core die 1030 may not receive the internal command iCMD and the data DATA sent through the TSVs 1020 and 1030.

[0095] In some example embodiments, when the internal command iCMD and the data DATA are sent to the core dies 1020 and 1030 through separate TSVs, the buffer die 1010 may send the internal command iCMD and the data DATA to the core die corresponding to the stack ID through separate TSVs. As described above, when the core dies 1020 and 1030 support the same channel CHa, the multi-layer memory device 1000 may perform a write operation and a read operation based on an activation command or a refresh operation based on a refresh command based on at least one of the first core die 1020 and the second core die 1030 according to the stack ID SID. In one embodiment, the buffer die 1010 may include a memory interface (I / F) 1015 that communicates with a host device. The memory interface 1015 may perform a write operation based on a write data strobe signal WDQS and a data signal DQ, and may perform a read operation based on a read data strobe signal RDQS and a data signal DQ.

[0096] In some example embodiments, the inventive concept may be implemented as a semiconductor package.

[0097] Figure 18 is a diagram showing a semiconductor package 2000 according to some example embodiments. Refer to Figure 18, the semiconductor package 2000 may include a multi-layer memory device 2100, a system-on-chip 2200, an interposer 2300, and a package substrate 2400.

[0098] The multi-layer memory device 2100 may include a buffer die 2110 and core dies 2120 to 2150. As Figures 1 to 15 described, in some example embodiments, the multi-layer memory device 2100 may include at least one memory device that performs QEC. Each of the core dies 2120 to 2150 may include a memory cell array. The buffer die 2110 may include a physical layer (PHY) 2111 and a direct access area DAB 2112. The physical layer 2111 may be electrically connected to the physical layer 2210 of the system-on-chip 2200 through the interposer 2300. The multi-layer memory device 2100 may receive signals from the system-on-chip 2200 through the physical layer 2111, or may send signals to the system-on-chip 2200. The physical layer 2111 may include the interface circuit of the buffer die 2110.

[0099] The direct access area 2112 may provide an access path through which the multi-layer memory device 2100 can be tested without going through the system-on-chip 2200. The direct access area 2112 may include conductive devices (e.g., ports or pins) capable of communicating directly with an external test device. The test signals and data received through the direct access area 2112 may be sent to the core dies 2120 to 2150 through the TSVs. The test data read from the core dies 2120 to 2150 for the core dies 2120 to 2150 may be sent to the test device through the TSVs and the direct access area 2112. Thus, a direct access test can be performed on the core dies 2120 to 2150. The buffer die 2110 and the core dies 2120 to 2150 may be electrically connected to each other through the TSVs 2101 and the bumps 2102. The buffer die 2110 may receive signals provided to each channel from the system-on-chip 2200 through the bumps 2102 assigned to each channel. For example, the bumps 2102 may be micro-bumps.

[0100] The system - on - chip 2200 can use the multi - layer memory device 2100 to execute applications supported by the semiconductor package 2000. For example, the system - on - chip 2200 can include a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), or a digital signal processor (DSP) to perform specialized operations. The system - on - chip 2200 can include a physical layer 2210 and a memory controller 2220. The physical layer 2210 can include an input / output circuit for sending signals to the physical layer 2111 of the multi - layer memory device 2100 and receiving signals from the physical layer 2111 of the multi - layer memory device 2100. The system - on - chip 2200 can provide various signals to the physical layer 2111 through the physical layer 2210. The signals provided to the physical layer 2111 can be sent to the core dies 2120 to 2150 through the interface circuit and the TSV 2101 of the physical layer 2111.

[0101] The memory controller 2220 can fully control the operation of the multi - layer memory device 2100. The memory controller 2220 can send signals for controlling the multi - layer memory device 2100 to the multi - layer memory device 2100 through the physical layer 2210. The interposer 2300 can connect the multi - layer memory device 2100 to the system - on - chip 2200. The interposer 2300 can connect the physical layer 2111 of the multi - layer memory device 2100 to the physical layer 2210 of the system - on - chip 2200 and can provide a physical path formed by using a conductive material. Thus, the multi - layer memory device 2100 and the system - on - chip 2200 can be stacked on the interposer 2300 to send signals to each other and receive signals from each other.

[0102] The bumps 2103 can be attached to the upper part of the package substrate 2400, and the solder balls 2104 can be attached to the lower part of the package substrate 2400. For example, the bumps 2103 can be flip - chip bumps. The interposer 2300 can be stacked on the package substrate 2400 through the bumps 2103. The semiconductor package 2000 can send signals to other external packages or semiconductor devices and receive signals from other external packages or semiconductor devices through the solder balls 2104. For example, the package substrate 2400 can be a printed circuit board (PCB).

[0103] In some example embodiments, the inventive concept can be applied to a high - bandwidth memory (HBM) package.

[0104] Figure 19 is a diagram showing an HBM package 3000 according to some example embodiments. Referring to Figure 19 HBM package 3000 can include a plurality of multi - layer memory devices 3100 and a system - on - chip 3200.

[0105] Each of the multiple multi - layer memory devices 3100 may be implemented to perform QEC in a non - sequential scheme as described with reference to Figures 1 to 15 The multi - layer memory device 3100 and the system - on - chip 3200 may be stacked on the interposer 3300, and the interposer 3300 may be stacked on the package substrate 3400. The HBM package 3000 may send signals to and receive signals from other external packages or semiconductor devices through solder balls attached to the lower part of the package substrate 3400. Each of the multi - layer memory devices 3100 may be implemented based on the HBM standard. However, the inventive concept is not limited thereto, and each of the multi - layer memory devices 3100 may be implemented based on GDDR (Graphics Double Data Rate), HMC (Hybrid Memory Cube), or Wide I / O standard.

[0106] The system - on - chip 3200 may include at least one processor (such as a CPU (Central Processing Unit), AP (Application Processor), GPU (Graphics Processor), DPU (Data Processor), NPU (Neural Network Processor), etc.), and multiple memory controllers for controlling the multiple multi - layer memory devices 3100. The system - on - chip 3200 may send signals to and receive signals from the multi - layer memory device corresponding to the system - on - chip 3200 through the memory controller.

[0107] The above - described devices may be implemented using hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in some example embodiments may be implemented using a processor, a controller, an artificial logic unit (ALU), a digital signal processor, a microcomputer, a field - programmable gate array (FPGA), a microprocessor, or one or more general - purpose or special - purpose computers (such as any other device capable of executing and responding to instructions). The processing device may execute an operating system (OS) and one or more software applications executing on the operating system. Additionally, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, one processing device may be described as being used, but those skilled in the art will recognize that the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors or one processor and one controller. Additionally, other processing configurations such as parallel processors are feasible.

[0108] Software may include a computer program, code, instructions, or a combination of one or more of them, and may configure a processing device to operate as needed, or may command the processing device independently or jointly. The software and / or data may be embodied in any type of machine, component, physical device, virtual device, computer storage medium, or device to be interpreted by the processing device or to provide commands or data to the processing device. The software may be distributed on a networked computer system and stored or executed in a distributed manner. The software and data may be stored in or on one or more computer-readable recording media.

[0109] A memory device and an operation method thereof according to some example embodiments may correct a phase error in an orthogonal clock (4-phase clock). A memory device and an operation method thereof according to some example embodiments may correct a phase error faster and more accurately than a sequential scheme. A memory device according to some example embodiments may be implemented by a delay line, a MUX, a switched phase detector (BBPD), a buffer, and control logic circuitry. Since the memory device of the inventive concept uses one loop, the phase error in the orthogonal clock may be accurately corrected to 0 regardless of the mismatch.

[0110] In a general QEC, since two independent phase errors are corrected simultaneously by unfolding, a lock time close to 1 / 2 times faster can be achieved when compared with a sequential scheme. The sequential scheme QEC uses one loop without a mismatch problem, and the correction of the phase error can be performed sequentially in an I-QQ-IBIB-QBQB-I order. In this case, since the QEC loop passes through a delay line, a buffer, a MUX, etc. after the delay code is updated, it may be necessary to wait for at least one cycle until the next phase error correction sequence, so a long lock time may be required. When compared with the sequential scheme, the general QEC may achieve a 1 / 2 level of lock time by unfolding, but as a result, two BBPDs may be used, causing a phase error due to the mismatch solved in the sequential scheme.

[0111] When implementing the inventive concept, there may be no parts to be significantly modified in existing DRAM interfaces and I / Os. The inventive concept may be applied to the design of a high-speed next-generation memory interface, and may be applied even when the number of clock phases used in the interface increases due to an increase in the clock speed, and thus may be configured as an 8-phase or more clock.

[0112] The inventive concept may be a circuit design in a DRAM interface, and may significantly improve the lock time without an offset problem while using QEC.

[0113] The inventive concept discloses a fast quadrature clock error corrector using a non-sequential algorithm. In this case, the phase error detection order can be in a non-sequential scheme to simultaneously perform delay line update and independent phase error detection, minimizing the waiting period due to delay line update and reducing the lock time to 5 / 8 level when compared with the existing QEC. Additionally, since the QEC of the inventive concept uses one loop, it can be robust to mismatches (no offset problem).

[0114] The inventive concept discloses a technique for detecting and correcting phase errors of orthogonal clocks using a non-sequential algorithm. In some example embodiments, the QEC technique of the inventive concept can simultaneously detect delay updates of a delay line and uncorrelated phase errors. The QEC technique of the inventive concept can reduce the waiting time and lock time of the QEC by continuously detecting phase errors of orthogonal clocks while using one phase detector.

[0115] A memory device, a memory system having the same, and an operation method thereof according to the inventive concept can correct orthogonal errors in a non-sequential scheme while using a single phase detector.

[0116] A memory device, a memory system having the same, and an operation method thereof according to the inventive concept can correct orthogonal errors in a non-sequential scheme while using a single phase detector to perform error correction quickly and accurately while reducing the chip size.

[0117] As described herein, any electronic device and / or their components according to any example embodiment may include one or more instances of processing circuitry (such as hardware including logic circuits; a hardware / software combination such as a processor that executes software; or any combination thereof), may be included in one or more instances of processing circuitry (such as hardware including logic circuits; a hardware / software combination such as a processor that executes software; or any combination thereof) and / or may be implemented by one or more instances of processing circuitry (such as hardware including logic circuits; a hardware / software combination such as a processor that executes software; or any combination thereof). For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and programmable logic units, a microprocessor, an application specific integrated circuit (ASIC), a neural network processor (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a DRAM device) that stores a program of instructions, and a processor (e.g., a CPU) that is configured to execute the program of instructions to implement functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or their parts according to any example embodiment and / or any part thereof.

[0118] Although example embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A method of operating a memory device, comprising: Receiving a first clock, a second clock, a third clock, and a fourth clock having sequential phase differences; During a first clock cycle, while detecting a first phase difference between the third clock and the fourth clock, updating a first delay code corresponding to a first delay line; During a second clock cycle, while detecting a second phase difference between the second clock and the third clock, updating a fourth delay code corresponding to a fourth delay line according to the first phase difference; During a third clock cycle, while detecting a third phase difference between the first clock and the second clock, updating a third delay code corresponding to a third delay line according to the second phase difference; During a fourth clock cycle, updating a second delay code corresponding to a second delay line according to the third phase difference; And During a fifth clock cycle, detecting a fourth phase difference between the fourth clock and the first clock.

2. The method according to claim 1, wherein The first clock to the fourth clock are orthogonal clocks with a sequential phase difference of 90°.

3. The method according to claim 1, further comprising: Selecting the third clock and the fourth clock during the first clock cycle; And Outputting the first phase difference between the third clock and the fourth clock during the first clock cycle.

4. The method according to claim 1, further comprising: Selecting the second clock and the third clock during the second clock cycle; And Outputting the second phase difference between the second clock and the third clock during the second clock cycle.

5. The method according to claim 1, further comprising: Selecting the first clock and the second clock during the third clock cycle; And Outputting the third phase difference between the first clock and the second clock during the third clock cycle.

6. The method according to claim 1, wherein, The detection of the clock phase difference during the fourth clock cycle is in a waiting state.

7. The method according to claim 6, wherein, The second delay code is updated when the third phase difference is output.

8. The method according to claim 1, further comprising: Selecting the fourth clock and the first clock during the fifth clock cycle; And Outputting the fourth phase difference between the fourth clock and the first clock during the fifth clock cycle.

9. The method according to claim 1 further comprises: After detecting the fourth phase difference, updating the first delay code corresponding to the first delay line according to the fourth phase difference.

10. The method according to any one of claims 1 to 9 further comprises: At least two of the first clock to the fourth clock are selected by a multiplexer.

11. A memory device, comprising: A first clock line, a second clock line, a third clock line, and a fourth clock line respectively outputting a first clock, a second clock, a third clock, and a fourth clock having sequential phase differences; A multiplexer configured to: select clock lines from the first clock line to the fourth clock line in response to a selection signal to output a first clock output signal and a second clock output signal; A first delay line configured to receive the first clock output signal; A second delay line configured to receive the second clock; A third delay line configured to receive the third clock; A fourth delay line configured to receive the fourth clock; A phase detector configured to detect a phase difference between the clock delayed by the first delay line and the clock of the second clock output signal; And Digital logic configured to: generate a delay code corresponding to the phase difference and control the delay line corresponding to the delay code among the first delay line to the fourth delay line, Among them, the digital logic is further configured to: generate a selection signal to select two clocks from the first clock to the fourth clock according to a non-sequential scheme.

12. The memory device according to claim 11, wherein, The digital logic is configured to: generate a selection signal for selecting the third clock and the fourth clock during the first clock cycle, generate a selection signal for selecting the second clock and the third clock during the second clock cycle, generate a selection signal for selecting the first clock and the second clock during the third clock cycle, wait during the fourth clock cycle, and generate a selection signal for selecting the fourth clock and the first clock during the fifth clock cycle.

13. The memory device according to claim 12, wherein, The digital logic is configured to: during the first clock cycle, update the first delay code corresponding to the first delay line and detect the first phase difference between the third clock and the fourth clock, during the second clock cycle, update the fourth delay code corresponding to the fourth delay line according to the first phase difference and detect the second phase difference between the second clock and the third clock, during the third clock cycle, update the third delay code corresponding to the third delay line according to the second phase difference and detect the third phase difference between the first clock and the second clock, during the fourth clock cycle, update the second delay code corresponding to the second delay line according to the third phase difference, and during the fifth clock cycle, detect the fourth phase difference between the fourth clock and the first clock.

14. The memory device according to claim 13, wherein, The digital logic is configured to: after detecting the fourth phase difference, update the first delay code corresponding to the first delay line according to the fourth phase difference.

15. The memory device according to any one of claims 11 to 14, wherein, The first clock to the fourth clock are used as data strobe signals.

16. A memory system, comprising: at least one memory device; and a memory controller configured to control the at least one memory device, the at least one memory device includes: a memory cell array having memory cells connected to word lines and bit lines; an orthogonal error correction circuit configured to receive an orthogonal clock and correct the orthogonal clock; a clock generator configured to generate an internal clock based on the corrected orthogonal clock; and control logic configured to control write operations and read operations of the memory cell array, The orthogonal error correction circuit is configured to correct the orthogonal clock in a non-sequential scheme using one phase detector.

17. The memory system according to claim 16, wherein, The orthogonal error correction circuit is configured to receive the orthogonal clock from the memory controller.

18. The memory system according to claim 16, wherein, The at least one memory device is configured to generate an orthogonal clock based on the clock received from the memory controller.

19. The memory system according to claim 16, wherein the orthogonal clock includes a first clock, a second clock, a third clock, and a fourth clock having sequential phases, and the orthogonal error correction circuit is configured to: during the first clock cycle, update the first delay code corresponding to the first delay line while detecting the first phase difference between the third clock and the fourth clock; during the second clock cycle, update the fourth delay code corresponding to the fourth delay line according to the first phase difference while detecting the second phase difference between the second clock and the third clock; during the third clock cycle, update the third delay code corresponding to the third delay line according to the second phase difference while detecting the third phase difference between the first clock and the second clock; During a fourth clock cycle, update a second delay code of a second delay line according to a third phase difference; And During a fifth clock cycle, detect a fourth phase difference between a fourth clock and a first clock.

20. The memory system according to any one of claims 16 to 19, wherein the quadrature error correction circuit further includes: a multiplexer configured to select at least two clocks among a first clock to a fourth clock; the one phase detector is configured to: detect a phase difference between the at least two clocks selected by the multiplexer, and the quadrature error correction circuit is configured to control a delay line corresponding to the phase difference according to the phase difference.

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