OTP storage array and operation method thereof
By designing shared programming lines and improved storage modules in OTP storage arrays, the problem of difficulty in reducing the size and complex operation of traditional OTP storage units is solved, and area reduction and programming reliability are improved.
Patent Information
- Application Number
- CN202510423552.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-07-25
AI Technical Summary
The traditional dual-tube/three-tube single-use programmable embedded memory cell (2T/3T OTP cell) is difficult to continue to reduce the size of the memory cell due to the limitation of the anti-fuse tube structure, and the operation method is complicated.
An OTP storage array is designed, multiple OTP storage units are arranged in different directions, sharing a programming line, and multi-threshold storage is realized by improving the design of the storage module, and the operation method is simplified.
It effectively reduces the area of the OTP storage array, simplifies the operation method, and improves the programming reliability and multi-threshold storage capabilities of OTP storage units.
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Figure CN120375892A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor devices, and more specifically, relates to an OTP memory array and an operation method thereof. Background Art
[0002] There is a huge demand for one-time programmable embedded memories in system-on-chip (SOC) designs. Due to the limitations of the anti-fuse structure, it is difficult to further reduce the size of traditional two-transistor / three-transistor one-time programmable embedded memory cells (2T / 3T OTP cells). Summary of the Invention
[0003] In view of the above-mentioned defects or improvement requirements of the prior art, the present invention provides an OTP memory array and an operation method thereof, which reduce the area of the OTP memory array, can be fully implemented based on the CMOS process flow, and make the operation method of the OTP memory array more convenient.
[0004] To achieve the above object, according to one aspect of the present invention, there is provided an OTP memory array including a plurality of OTP memory cells. The plurality of OTP memory cells are arranged in a plurality of rows along a first direction and in a plurality of columns along a second direction; each OTP memory cell includes a selection transistor and a storage module. The gate of the selection transistor is connected to a word line, the first end of the selection transistor is connected to a bit line, the second end of the selection transistor is connected to the first end of the storage module, and the second end of the storage module is a control end connected to a programming line; the gates of a row of selection transistors arranged along the first direction are connected to the same word line WL, the first ends of a column of selection transistors arranged along the second direction are connected to the same bit line BL, and the control ends of a row of storage modules arranged along the first direction and the control ends of another row of storage modules arranged adjacent to the first row along the first direction are connected to the same programming line PL.
[0005] In some embodiments, the storage module includes a storage transistor. The gate of the storage transistor is connected to the control end of the storage module, the first end of the storage transistor is connected to the first end of the storage module, and the second end of the storage transistor is floating.
[0006] In some embodiments, the storage module includes a storage transistor. The gate of the storage transistor is connected to the control end of the storage module, the first end of the storage transistor is connected to the first end of the storage module, and the second end of the storage transistor is connected to the first end of the storage transistor.
[0007] In some embodiments, the storage module includes a storage tube M022 and one or more storage tubes M021; the second end of the selection tube is connected to the first end of an adjacent storage tube M021, the first end of the storage tube M022 is connected to the second end of the adjacent storage tube M021, and the second ends of all the storage tubes M021 are connected to their first ends; the first end of any storage tube M021 is connected to the second end of the selection tube M01 or the second end of the previous storage tube M021, and the second end of any storage tube M021 is connected to the first end of the storage tube M022 or the first end of the next storage tube M021.
[0008] In some embodiments, the storage module includes a plurality of sub-storage modules. The first end of each sub-storage module is connected to the first end of the storage module, and the second end of each sub-storage module is a control end and is connected to the control end of the storage module; multi-threshold storage is achieved through the plurality of sub-storage modules.
[0009] In some embodiments, at least one sub-storage module includes a storage tube. The gate of the storage tube is connected to the control end of the sub-storage module, the first end of the storage tube is connected to the first end of the sub-storage module, and the second end of the storage tube is floating.
[0010] In some embodiments, at least one sub-storage module includes a storage tube. The gate of the storage tube is connected to the control end of the storage module, the first end of the storage tube is connected to the first end of the storage module, and the second end of the storage tube is connected to the first end of the storage tube.
[0011] In some embodiments, at least one sub-storage module includes a storage tube M022 and one or more storage tubes M021; the second end of the selection tube is connected to the first end of an adjacent storage tube M021, the first end of the storage tube M022 is connected to the second end of the adjacent storage tube M021, and the second ends of all the storage tubes M021 are connected to their first ends; the first end of any storage tube M021 is connected to the second end of the selection tube M01 or the second end of the previous storage tube M021, and the second end of any storage tube M021 is connected to the first end of the storage tube M022 or the first end of the next storage tube M021.
[0012] In some embodiments, the word line WL extends in a first direction, and the bit line BL extends in a second direction; the gates of the storage tubes in a row of storage modules arranged in the first direction are oppositely arranged with the gates of the storage tubes in another row of storage modules arranged in the first direction adjacent thereto and staggeredly extend in the second direction. The programming line PL extends in the first direction and forms a conductive connection with the gates of the storage tubes in a row of storage modules arranged in the first direction and the gates of the storage tubes in another row of storage modules arranged in the first direction adjacent thereto.
[0013] According to another aspect of the present invention, there is provided a method for operating the above OTP storage array. When performing a write operation, a first voltage VPW is provided to the word line connected to the OTP storage cell, a second voltage VPP is provided to the programming line connected to the OTP storage cell, and a voltage of 0 is provided to the bit line connected to the OTP storage cell to select the OTP storage cell to perform the write operation, wherein VPW ≤ VPP.
[0014] In some embodiments, when performing a read operation, a third voltage VDD is provided to the word line and the programming line connected to the OTP storage cell, and a voltage of 0 is provided to the bit line connected to the OTP storage cell to select the OTP storage cell to perform the read operation.
[0015] Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects: two groups of OTP storage cells that originally required a separate programming line (PL) each are changed to share one programming line, and the gates of the storage tubes of the two groups of OTP storage cells sharing one programming line are oppositely arranged and staggeredly extended, effectively reducing the area of the OTP storage array and making the operation method of the OTP storage array more convenient. Correspondingly, more space is reserved for the design of the storage module in the OTP storage cell. By improving the design of the storage module in the OTP storage cell, the programming reliability of the OTP storage cell is further improved, and multi-threshold storage is achieved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a schematic diagram of the device structure of a typical OTP storage cell;
[0017] Figure 2A is a schematic diagram of the circuit structure of an OTP storage array;
[0018] Figure 2B is Figure 2A a schematic diagram of the layout structure of the OTP storage array shown;
[0019] Figure 3A is a schematic diagram of the circuit structure of the OTP storage array according to an embodiment of the present invention;
[0020] Figure 3B is Figure 3A a schematic diagram of a layout structure of the OTP storage array shown;
[0021] Figure 4 is a schematic diagram of the circuit structure of an OTP storage cell according to an embodiment of the present invention;
[0022] Figure 5 is a schematic diagram of the circuit structure of an OTP storage cell according to another embodiment of the present invention;
[0023] Figure 6 It is a schematic diagram of the circuit structure of the OTP storage cell according to another embodiment of the present invention. Detailed implementation manners
[0024] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary in nature and not restrictive.
[0025] Figure 1 It is a schematic diagram of the device structure of a typical OTP storage cell. As Figure 1 shown, the OTP storage cell includes a thick-gate-oxide high-voltage selection transistor and a thin-gate-oxide low-voltage storage transistor formed on the same substrate. The thick-gate-oxide high-voltage selection transistor and the thin-gate-oxide low-voltage storage transistor share one active region. Another active region of the thick-gate-oxide high-voltage selection transistor is connected to the bit line (BL), the gate of the thick-gate-oxide high-voltage selection transistor is connected to the word line (WL), and the gate of the thin-gate-oxide low-voltage storage transistor is connected to the program line (PL). Before programming, the anti-fuse dielectric (thin gate oxide layer) of the thin-gate-oxide low-voltage storage transistor is not conductive and is in a high-resistance state, corresponding to the storage state "0"; during programming, the anti-fuse dielectric of the thin-gate-oxide low-voltage storage transistor is broken down and becomes a low-resistance state, corresponding to the storage state "1".
[0026] Figure 2A It is a schematic diagram of the circuit structure of an OTP storage array. As Figure 2A shown, the OTP storage array includes a plurality of OTP storage cells Cell0 to Cell3, and each OTP storage cell includes a selection transistor and a storage transistor. Among them, OTP storage cells Cell0 and Cell1 are arranged along the first direction (for example, the row direction shown in the figure) to form the first row, OTP storage cells Cell2 and Cell3 are arranged along the first direction to form the second row, OTP storage cells Cell0 and Cell2 are arranged along the second direction (for example, the column direction shown in the figure) to form the first column, and OTP storage cells Cell1 and Cell3 are arranged along the second direction to form the second column.
[0027] The gates of the memory tubes in the same row are connected to the same programming line (PL), and the gates of the memory tubes in different rows are connected to different programming lines. For example, the gates of the memory tubes of OTP memory cells Cell0 and Cell1 are connected to the same programming line PL0, and the gates of the memory tubes of OTP memory cells Cell2 and Cell3 are connected to the same programming line PL1. The programming line PL0 and the programming line PL1 are different programming lines.
[0028] Figure 2B Yes Figure 2A The schematic layout structure diagram of the OTP memory array shown, such as Figure 2B shown, the OTP memory cells Cell0 and Cell1 arranged along the first direction are connected to the same programming line PL0, and the OTP memory cells Cell2 and Cell3 arranged along the first direction are connected to the same programming line PL1.
[0029] Figure 3A This is the schematic circuit structure diagram of the OTP memory array according to the embodiment of the present invention. As Figure 3A shown, the OTP memory array includes multiple OTP memory cells Cell0 to Cell3. Each OTP memory cell includes a selection tube and a memory module, and the memory module includes one or more memory tubes. Among them, the OTP memory cells Cell0 and Cell1 are arranged along the first direction (such as the row direction shown in the figure) to form the first row, the OTP memory cells Cell2 and Cell3 are arranged along the first direction to form the second row, the OTP memory cells Cell0 and Cell2 are arranged along the second direction (such as the column direction shown in the figure) to form the first column, and the OTP memory cells Cell1 and Cell3 are arranged along the second direction to form the second column.
[0030] The control ends of the memory modules in the same row are connected to the same programming line (PL). Further, the control ends of the memory modules in adjacent rows share the same programming line. For example, the control ends of the memory modules of OTP memory cells Cell0 and Cell1 are connected to the same programming line PL0, and the control ends of the memory modules of OTP memory cells Cell2 and Cell3 are also connected to the same programming line PL0. That is to say, the memory modules in the first row and the memory modules in the second row share the same programming line.
[0031] The control ends (i.e., gates) of the selection tubes in the same row are connected to the same word line (WL). For example, the control ends of the selection tubes of OTP memory cells Cell0 and Cell1 are connected to the same word line WL0, and the control ends of the selection tubes of OTP memory cells Cell2 and Cell3 are connected to the same word line WL1.
[0032] The first ends of the selection transistors in the same column (corresponding to independent active regions, such as source doping regions) are connected to the same bit line (Bit Line, BL). Here, the independent active region is relative to the active region shared with the storage transistor. For example, the first ends of the selection transistors of memory cells Cell0 and Cell2 are connected to the same bit line BL0, and the first ends of the selection transistors of memory cells Cell1 and Cell3 are connected to the same bit line BL1.
[0033] In each OTP memory cell, the first end of the selection transistor is connected to the corresponding bit line, the second end of the selection transistor is connected to the first end of the storage module, the control end of the selection transistor is connected to the corresponding word line, and the second end (i.e., the control end) of the storage module is connected to the corresponding programming line. For example, in OTP memory cell Cell0, the first end of selection transistor M01 is connected to the corresponding bit line BL0, the second end of selection transistor M01 is connected to the first end of storage module 301, the control end of selection transistor M01 is connected to the corresponding word line WL0, and the control end of storage module 301 is connected to the corresponding programming line PL0. In OTP memory cell Cell1, the first end of selection transistor M11 is connected to the corresponding bit line BL1, the second end of selection transistor M11 is connected to the first end of storage module 303, the control end of selection transistor M11 is connected to the corresponding word line WL0, and the control end of storage module 303 is connected to the corresponding programming line PL0. In OTP memory cell Cell2, the first end of selection transistor M21 is connected to the corresponding bit line BL0, the second end of selection transistor M21 is connected to the first end of storage module 305, the control end of selection transistor M21 is connected to the corresponding word line WL1, and the control end of storage module 305 is connected to the corresponding programming line PL0. In OTP memory cell Cell3, the first end of selection transistor M31 is connected to the corresponding bit line BL1, the second end of selection transistor M31 is connected to the first end of storage module 307, the control end of selection transistor M31 is connected to the corresponding word line WL1, and the control end of storage module 307 is connected to the corresponding programming line PL0.
[0034] Figure 3B is Figure 3A a schematic layout structure diagram of the OTP memory array shown, as Figure 3BAs shown, the first group of OTP memory cells arranged in the first direction (including Cell0 and Cell1) are connected to the same word line WL0, and the second group of OTP memory cells arranged in the first direction (including Cell2 and Cell3) are connected to the same word line WL1; the third group of OTP memory cells arranged in the second direction (including Cell0 and Cell2) are connected to the same bit line BL0 (not shown in the figure), and the fourth group of OTP memory cells arranged in the second direction (including Cell1 and Cell3) are connected to the same bit line BL1 (not shown in the figure); the first group of OTP memory cells arranged in the first direction (including Cell0 and Cell1) and the second group of OTP memory cells arranged in the first direction (including Cell2 and Cell3) are connected to the same programming line PL0. The word lines WL0 and WL1 and the programming line PL0 extend in the first direction, and the bit lines BL0 and BL1 extend in the second direction. In some embodiments, the second direction and the first direction are substantially perpendicular, that is, the rows and columns are substantially perpendicular, and each OTP memory cell forms a two-dimensional array structure.
[0035] The OTP memory cells Cell0 and Cell2 are arranged in the second direction, the gates of the memory tubes in Cell0 and the gates of the memory tubes in Cell2 are arranged opposite to each other and extend staggeredly in the second direction. The OTP memory cells Cell1 and Cell3 are arranged in the second direction, the gates of the memory tubes in Cell1 and the gates of the memory tubes in Cell3 are arranged opposite to each other and extend staggeredly in the second direction. The programming line PL0 extends in the first direction and forms a conductive connection with the gates of Cell0 and Cell1 in the first group of OTP memory cells and the gates of Cell2 and Cell3 in the second group of OTP memory cells.
[0036] It should be understood that the first group of OTP memory cells may have Cell0 and Cell1 and more OTP memory cells, the second group of OTP memory cells may have Cell2 and Cell3 and more OTP memory cells, and the programming line PL0 always forms a conductive connection with the gates of the memory tubes in the first group of OTP memory cells and the second group of OTP memory cells in the first direction.
[0037] Compared with Figure 2A the structure shown, Figure 3A the structure shown changes the two rows of OTP memory cells that originally required separate use of a programming line PL0 and PL1 to share a programming line PL0. Correspondingly, Figure 3B in the structure shown, the gates of the memory tubes of the two groups of OTP memory cells sharing the programming line are arranged opposite to each other and extend staggeredly in the second direction. Only a single programming line PL0 extending in the first direction is required to connect the gates of the memory tubes of the two groups of OTP memory cells, effectively reducing the area of the OTP memory array.
[0038] In addition, simplifying two programming lines into one also makes the operation method of the OTP storage array more convenient.
[0039] Specifically, for the structure shown in Figure 2A , the voltage application conditions for the programming operation (write operation) and read operation of the OTP storage array are shown in Table 1; for the structure shown in Figure 3A , the voltage application conditions for the programming operation (write operation) and read operation of the OTP storage array are shown in Table 2. Among them, the voltage unit is V.
[0040] Table 1
[0041] Operation type BL0 WL0 PL0 BL1 WL1 PL1 Write operation 0 VPP VPP VPP 0 0 Read operation 0 VDD VDD VDD 0 0
[0042] Table 2
[0043] Operation type BL0 WL0 PL0 BL1 WL1 Write operation 0 VPW VPP VPW 0 Read operation 0 VDD VDD VDD 0
[0044] By adopting the voltage application conditions in Table 1 and selecting appropriate voltages for VPP and VDD, the write operation and read operation of Cell0 can be achieved. By adopting the voltage application conditions in Table 2 and selecting appropriate voltages for VPW, VPP, and VDD, and VPW ≤ VPP, the write operation and read operation of Cell0 can be achieved. It can be seen that, compared with Figure 2A , adopting the OTP storage array structure shown in Figure 3A saves one data line and simplifies the processing of data signals.
[0045] During the write operation, with the voltage application conditions shown in Table 2, the voltage application situations of Cell0 to Cell3 are shown in Table 3. During the read operation, with the voltage application conditions shown in Table 2, the voltage application situations of Cell0 to Cell3 are shown in Table 4.
[0046] It can be seen that during the write operation, a first voltage VPW is provided for the word line connected to the OTP storage cell, a second voltage VPP is provided for the programming line linked to the OTP storage cell, and a 0 voltage is provided for the bit line connected to the OTP storage cell to select the OTP storage cell to perform the write operation. During the read operation, a third voltage VDD is provided for the word line and programming line connected to the OTP storage cell, and a 0 voltage is provided for the bit line connected to the OTP storage cell to select the OTP storage cell to perform the read operation.
[0047] Table 3
[0048] Memory cell WL PL BL Cell0 (selected) VPW VPP 0 Cell1 (not selected) VPW VPP VPW Cell2 (not selected) 0 VPP 0 Cell3 (not selected) 0 VPP VPW
[0049] Table 4
[0050] Memory cell WL PL BL Cell0 (selected) VDD VDD 0 Cell1 (not selected) VDD VDD VDD Cell2 (not selected) 0 VDD 0 Cell3 (not selected) 0 VDD VDD
[0051] Furthermore, adopting the solution that two rows of OTP storage units in the embodiments of the present invention share one programming line can be compatible with different storage modules. That is to say, the storage modules in the OTP storage units can adopt different structures according to actual needs.
[0052] In some embodiments, each storage module includes a storage tube. The gate of the storage tube is connected to the control end of the storage module. The first end of the storage tube is connected to the first end of the storage module, and the second end of the storage tube is floating. There is an equivalent capacitance between the gate of the storage tube and the active region corresponding to the first end of the storage tube. That is, the storage tube substantially provides an equivalent capacitance connected in series with the active region corresponding to the second end of the selection tube. Specifically, as Figure 3A shown, the storage module 301 includes a storage tube M02. The gate of the storage tube M02 is connected to the control end of the storage module 301. The first end of the storage tube M02 is connected to the first end of the storage module 301, and the second end of the storage tube M02 is floating. There is an equivalent capacitance between the gate of the storage tube M02 and the active region corresponding to its first end. That is, the storage tube M02 substantially provides an equivalent capacitance C1 connected in series with the active region corresponding to the second end of the selection tube M01.
[0053] In some embodiments, each storage module includes a storage tube. The gate of the storage tube is connected to the control end of the storage module. The first end of the storage tube is connected to the first end of the storage module, and the second end of the storage tube is connected to the first end of the storage tube. There is an equivalent capacitance between the gate of the storage tube and the active region corresponding to the first end of the storage tube and between the gate of the storage tube and the active region corresponding to the second end of the storage tube respectively. That is, the storage tube substantially provides two equivalent capacitances connected in series with the active region corresponding to the second end of the selection tube.
[0054] Specifically, as Figure 4 shown, the OTP storage unit includes a selection tube M01 and a storage module 401. The storage module 401 includes a storage tube M02. The gate of the storage tube M02 is connected to the control end of the storage module 401. The first end of the storage tube M02 is connected to the first end of the storage module 401, and the second end of the storage tube M02 is connected to the first end of the storage tube M02. There is an equivalent capacitance C1 between the gate of the storage tube M02 and the active region corresponding to the first end of the storage tube M02, and there is an equivalent capacitance C2 between the gate of the storage tube M02 and the active region corresponding to the second end of the storage tube M02. That is, the storage tube M02 substantially provides two equivalent capacitances C1 and C2 connected in series with the active region corresponding to the second end of the selection tube M01, and the equivalent capacitance C1 and the equivalent capacitance C2 are in parallel.
[0055] In some embodiments, each storage module includes a first storage transistor and a second storage transistor. The gates of the first storage transistor and the second storage transistor are connected to the control terminal of the storage module. The first end of the first storage transistor is connected to the first end of the storage module. The second end of the first storage transistor is connected to the first end of the second storage transistor. The second end of the second storage transistor is floating. There is an equivalent capacitance between the gate of the first storage transistor and the active region corresponding to the first end of the first storage transistor, and there is also an equivalent capacitance between the gate of the first storage transistor and the active region corresponding to the second end of the first storage transistor. That is, the storage transistor essentially provides two equivalent capacitances connected in series with the active region corresponding to the second end of the select transistor. There is an equivalent capacitance between the gate of the second storage transistor and the active region corresponding to the first end of the second storage transistor. That is, the second storage transistor essentially provides an equivalent capacitance connected in series with the active region corresponding to the second end of the select transistor.
[0056] Specifically, as Figure 5 shown, the OTP storage cell includes a select transistor M01 and a storage module 501. The storage module 501 includes a first storage transistor M021 and a second storage transistor M022. The gates of the first storage transistor M021 and the second storage transistor M022 are connected to the control terminal of the storage module 501. The first end of the first storage transistor M021 is connected to the first end of the storage module 501. The second end of the first storage transistor M021 is connected to the first end of the second storage transistor M022. The second end of the second storage transistor M022 is floating. There is an equivalent capacitance C1 between the gate of the first storage transistor M021 and the active region corresponding to its first end, and there is an equivalent capacitance C2 between the gate of the first storage transistor M021 and the active region corresponding to its second end. That is, the first storage transistor M021 essentially provides two equivalent capacitances C1 and C2 connected in series with the active region corresponding to the second end of the select transistor M01. There is an equivalent capacitance C3 between the gate of the second storage transistor M022 and the active region corresponding to its first end. That is, the second storage transistor M022 essentially provides an equivalent capacitance C3 connected in series with the active region corresponding to the second end of the select transistor M01. The equivalent capacitance C1, the equivalent capacitance C2, and the equivalent capacitance C3 are connected in parallel.
[0057] Furthermore, according to actual needs, one or more first storage transistors M021 (not shown in the figure) can be provided between the select transistor M01 and the second storage transistor M022. The second end of the select transistor M01 is connected to the first end of the adjacent first storage transistor M021. The first end of the second storage transistor M022 is connected to the second end of the adjacent first storage transistor M021. The second end of each first storage transistor M021 is connected to the first end of this first storage transistor M021. In addition, the first end of any first storage transistor M021 is connected to the second end of the select transistor M01 or the second end of the previous first storage transistor M021, and the second end of any first storage transistor M021 is connected to the first end of the second storage transistor M022 or the first end of the next first storage transistor M021.
[0058] In some embodiments, when multiple memory tubes MX are included in the memory module, the memory tubes MX are the same. In some embodiments, when multiple memory tubes MX are included in the memory module, at least two memory tubes MX are different.
[0059] From memory module 301 to memory module 501, the number of equivalent capacitors connected in series to the active region corresponding to the second end of the selection tube M01 continuously increases, which is equivalent to increasing the number of anti-fuse capacitors included in the OTP memory cell. When programming the OTP memory cell, the probability of multiple equivalent capacitors breaking down simultaneously is obviously lower than that of a single equivalent capacitor breaking down. Therefore, as the number of equivalent capacitors increases, the probability of programming failure of the OTP memory cell decreases, which means the programming reliability of the OTP memory cell is improved.
[0060] Figure 6 Another memory module structure is given. As Figure 6 shown, the OTP memory cell includes a selection tube M01 and a memory module 601. The memory module 601 includes multiple memory tubes M021 (the number of memory tubes M021 can be set according to actual requirements, and the three shown in the figure are only examples). The gate of each memory tube M021 is connected to the control end of the memory module 601, the first end of each memory tube M021 is connected to the second end of the selection tube M01, and the second end of each memory tube M021 is floating. By adjusting the magnitude of the gate voltage Vwl of the selection tube M01, the programming current Ipgm is controlled, and thus the number of memory tubes M021 broken down in the memory module 601 is controlled. Therefore, various resistances after different memory tubes M021 are broken down can be obtained.
[0061] More generally, in some embodiments, the memory module in the OTP memory cell further includes multiple sub-memory modules. The first end of each sub-memory module is connected to the first end of the memory module, and the second end (i.e., the control end) of each sub-memory module is connected to the control end of the memory module. Multi-threshold storage is achieved through multiple sub-memory modules. In some embodiments, the sub-memory module is implemented as the memory module 301. In some embodiments, the sub-memory module is implemented as the memory module 401. In some embodiments, the sub-memory module is implemented as the memory module 501 and its variants. In some embodiments, the structures of the sub-memory modules are the same. In some embodiments, at least two sub-memory modules have different structures.
[0062] The memory tubes in the above embodiments can be implemented as NMOS tubes or PMOS tubes.
[0063] In the present invention, two groups of OTP memory cells that originally required a separate programming line (PL) are changed to share one programming line. Moreover, the gates of the memory tubes of the two groups of OTP memory cells sharing one programming line are oppositely arranged and staggeredly extended, effectively reducing the area of the OTP memory array and making the operation method of the OTP memory array more convenient. Correspondingly, more space is reserved for the design of the storage module in the OTP memory cell. By improving the design of the storage module in the OTP memory cell, the programming reliability of the OTP memory cell is further improved, and multi-threshold storage is achieved.
[0064] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0065] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.
[0066] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more (two or more) executable instructions for implementing a specific logical function or process. And the scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in the reverse order according to the involved functions, rather than in the order shown or discussed.
[0067] The logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatus, or devices.
[0068] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the method in the above embodiments can be completed by instructing relevant hardware through a program, and this program can be stored in a computer-readable storage medium. When this program is executed, it includes one or a combination of the steps of the method embodiment.
[0069] In addition, in each embodiment of the present application, each functional unit can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. If the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a magnetic disk, an optical disk, etc.
[0070] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various changes or substitutions, and these should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. An OTP storage array, characterized in that, It includes multiple OTP storage units which are arranged in multiple rows along a first direction and in multiple columns along a second direction; each OTP storage unit includes a selection transistor and a storage module. The gate of the selection transistor is connected to a word line, the first end of the selection transistor is connected to a bit line, the second end of the selection transistor is connected to the first end of the storage module, and the second end of the storage module is a control end connected to a programming line; the gates of the selection transistors in a row arranged along the first direction are connected to the same word line WL, the first ends of the selection transistors in a column arranged along the second direction are connected to the same bit line BL, and the control ends of the storage modules in a row arranged along the first direction and the control ends of the storage modules in another row arranged along the first direction adjacent thereto are connected to the same programming line PL.
2. The OTP storage array according to claim 1, wherein The storage module includes a storage transistor, the gate of the storage transistor is connected to the control end of the storage module, the first end of the storage transistor is connected to the first end of the storage module, and the second end of the storage transistor is floating.
3. The OTP storage array according to claim 1, wherein The storage module includes a storage transistor, the gate of the storage transistor is connected to the control end of the storage module, the first end of the storage transistor is connected to the first end of the storage module, and the second end of the storage transistor is connected to the first end of the storage transistor.
4. The OTP storage array according to claim 1, wherein The storage module includes a storage transistor M022 and one or more storage transistors M021; the second end of the selection transistor is connected to the first end of an adjacent storage transistor M021, the first end of the storage transistor M022 is connected to the second end of the adjacent storage transistor M021, and the second ends of all the storage transistors M021 are connected to their first ends; the first end of any storage transistor M021 is connected to the second end of the selection transistor M01 or the second end of the previous storage transistor M021, and the second end of any storage transistor M021 is connected to the first end of the storage transistor M022 or the second end of the next storage transistor M021.
5. The OTP storage array according to claim 1, wherein The storage module includes multiple sub-storage modules, the first end of each sub-storage module is connected to the first end of the storage module, the second end of each sub-storage module is a control end connected to the control end of the storage module; multi-threshold storage is realized through the multiple sub-storage modules.
6. The OTP storage array according to claim 5, wherein At least one sub-storage module includes a storage transistor, the gate of the storage transistor is connected to the control end of the sub-storage module, the first end of the storage transistor is connected to the first end of the sub-storage module, and the second end of the storage transistor is floating.
7. The OTP storage array according to claim 5, wherein At least one sub-storage module includes a storage transistor, the gate of the storage transistor is connected to the control end of the storage module, the first end of the storage transistor is connected to the first end of the storage module, and the second end of the storage transistor is connected to the first end of the storage transistor.
8. The OTP storage array according to claim 5, wherein At least one sub-storage module includes a storage transistor M022 and one or more storage transistors M021; the second end of the selection transistor is connected to the first end of an adjacent storage transistor M021, the first end of the storage transistor M022 is connected to the second end of the adjacent storage transistor M021, and the second ends of all the storage transistors M021 are connected to their first ends; the first end of any storage transistor M021 is connected to the second end of the selection transistor M01 or the second end of the previous storage transistor M021, and the second end of any storage transistor M021 is connected to the first end of the storage transistor M022 or the second end of the next storage transistor M021.
9. The OTP storage array according to any one of claims 1 to 8, characterized in that, The word line WL extends along a first direction, and the bit line BL extends along a second direction; the gates of the memory transistors in a row of memory modules arranged along the first direction are oppositely disposed with respect to the gates of the memory transistors in another row of memory modules arranged along the first direction and staggeredly extend in the second direction. The programming line PL extends along the first direction and forms conductive connections with the gates of the memory transistors in a row of memory modules arranged along the first direction and the gates of the memory transistors in another row of memory modules arranged along the first direction.
10. The method for operating an OTP storage array according to any one of claims 1 to 9, characterized in that, When performing a write operation, a first voltage VPW is provided to the word line connected to the OTP memory cell, a second voltage VPP is provided to the programming line connected to the OTP memory cell, and a voltage of 0 is provided to the bit line connected to the OTP memory cell to select the OTP memory cell to perform the write operation, where VPW ≤ VPP; when performing a read operation, a third voltage VDD is provided to the word line and the programming line connected to the OTP memory cell, and a voltage of 0 is provided to the bit line connected to the OTP memory cell to select the OTP memory cell to perform the read operation.