Packaging substrate and manufacturing method thereof

Abstract

The invention provides a packaging substrate and a manufacturing method thereof, the packaging substrate comprises a substrate main body and a middle layer, the middle layer is arranged in the substrate main body, the middle layer comprises a substrate, a first device, a second device and a second dielectric layer, the first device comprises a first electrode layer, a second electrode layer, a first dielectric layer, a first extraction electrode and a second extraction electrode, the first electrode layer covers the inner wall and the bottom surface of the deep hole of the first device region and the upper surface of the substrate, the first dielectric layer covers the exposed surface of the first electrode layer, the second electrode layer comprises a seed layer and a conductive layer, and the second device comprises a resistance layer, a third extraction electrode and a fourth extraction electrode, the second dielectric layer covers the exposed surfaces of the second electrode layer and the resistance layer; and the first, second, third and fourth extraction electrodes all penetrate through the second dielectric layer. According to the invention, the passive device is integrated in the silicon-based intermediate layer, and then the silicon-based intermediate layer is used as an intermediate layer to be embedded in the substrate main body, so that the size of the packaging substrate is reduced, and the integration level of the packaging structure is improved at the same time.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a packaging substrate and a manufacturing method thereof. Background Art

[0002] Chip passive devices (such as capacitors and resistors) are usually mounted on the surface of the packaging substrate to meet the requirements of chip power integrity and signal integrity. Generally speaking, the chip passive device array will occupy about 30% of the surface area of the packaging substrate, making the packaging substrate require a larger size to facilitate wiring and pin layout. In today's situation where the size of electronic products is getting smaller and the integration degree is getting higher, this way of surface-mounted passive discrete device arrays can no longer meet the product requirements.

[0003] Currently, embedding passive discrete devices into the packaging substrate is a feasible solution to reduce the size of electronic products and improve the packaging integration degree. However, due to the large number of passive discrete devices, their relatively thick thickness (greater than 200 μm), and large size, embedding all of them into the packaging substrate will occupy a large amount of wiring space in the substrate. In this case, it is necessary to ensure that the size and thickness of the packaging substrate are much larger than the size or thickness of the passive discrete devices, which is not conducive to reducing the size of the packaging structure and improving the integration degree of the packaging structure.

[0004] Therefore, there is an urgent need to find a manufacturing method for a packaging substrate that can effectively reduce the size of the packaging structure and improve the integration degree of the packaging structure. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a packaging substrate and a manufacturing method thereof, which are used to solve the problem that the passive devices embedded in the packaging substrate in the prior art are relatively large, which is not conducive to reducing the size of the packaging structure and improving the integration degree of the packaging structure.

[0006] To achieve the above purpose and other related purposes, the present invention provides a manufacturing method for a packaging substrate, including the following steps:

[0007] Provide a substrate, at least one first device area and at least one second device area are defined on the substrate, a plurality of deep holes arranged at intervals are formed on the upper surface layer of the first device area, and the bottom surface of the deep hole is spaced from the bottom surface of the substrate by a preset distance;

[0008] Form a first electrode layer covering the upper surface of the substrate, the bottom surface and the inner wall of the deep hole, and form a first dielectric layer covering the exposed surface of the first electrode layer;

[0009] Form a seed layer covering the exposed surface of the first dielectric layer, and form a conductive layer covering the upper surface of the seed layer and filling the deep holes based on the seed layer. The conductive layer and the seed layer constitute a second electrode layer;

[0010] Form at least one trench penetrating the second electrode layer above the substrate in the second device region. The bottom surface of the trench exposes the first dielectric layer, and form a resistance layer filling the trench;

[0011] Form a second dielectric layer covering the exposed surfaces of the second electrode layer and the resistance layer, and form a first lead electrode, a second lead electrode, a third lead electrode, and a fourth lead electrode penetrating the second dielectric layer. The first lead electrode and the second lead electrode are electrically connected to the first electrode layer and the second electrode layer respectively to jointly constitute a first device with the first dielectric layer. The third lead electrode and the fourth lead electrode are electrically connected to the resistance layer respectively and are spaced apart by a preset distance to constitute a second device;

[0012] Use the substrate on which at least the first device and the second device are integrated as an intermediate layer and bury it in a preset position of the substrate body to obtain a packaged substrate.

[0013] Optionally, a dielectric layer is further provided on the upper surface layer of the substrate, and the first dielectric layer covers the upper surface of the dielectric layer.

[0014] Optionally, the aperture range of the deep holes is 0.5 μm to 10 μm, and the depth range of the deep holes is 0.5 μm to 20 μm.

[0015] Optionally, the thickness range of the first electrode layer is 0.1 μm to 0.5 μm, the thickness range of the seed layer is 0.1 μm to 0.5 μm, and the thickness range of the second electrode layer above the substrate is 0.3 μm to 2 μm.

[0016] Optionally, the thickness range of the first dielectric layer is 0.1 μm to 1.0 μm.

[0017] Optionally, the thickness range of the resistance layer is 0.3 μm to 2 μm.

[0018] Optionally, before forming the second dielectric layer and after forming the resistance layer, it further includes the step of forming electrode lead holes penetrating the second electrode layer and the first dielectric layer. The bottom surface of the electrode lead holes exposes the first electrode layer, and the second dielectric layer fills the electrode lead holes.

[0019] Optionally, before forming the first lead electrode and after forming the second dielectric layer, it further includes a step of forming a first contact hole that penetrates the second dielectric layer filling the electrode lead hole and exposes the bottom surface of the first electrode layer, and the first lead electrode fills the first contact hole.

[0020] Optionally, before forming the second lead electrode, the third lead electrode, and the fourth lead electrode and after forming the second dielectric layer, it further includes steps of forming a second contact hole, a third contact hole, and a fourth contact hole that penetrate the second dielectric layer. The bottom surface of the second contact hole exposes the second electrode layer, the second lead electrode fills the second contact hole, the bottom surfaces of the third contact hole and the fourth contact hole both expose the resistance layer, and the third lead electrode and the fourth lead electrode respectively fill the third contact hole and the fourth contact hole.

[0021] The present invention also provides a packaging substrate, including:

[0022] A substrate body;

[0023] An intermediate layer buried at a preset position of the substrate body. The intermediate layer includes a substrate, at least one first device, at least one second device, and a second dielectric layer. The first device includes a first electrode layer, a first dielectric layer, a second electrode layer, a first lead electrode electrically connected to the first electrode layer, and a second lead electrode electrically connected to the second electrode layer. The first electrode layer covers the inner wall and bottom surface of the deep hole in the first device region of the substrate and the upper surface of the substrate. The first dielectric layer covers the exposed surface of the first electrode layer. The second electrode layer includes a seed layer covering the exposed surface of the first dielectric layer and a conductive layer covering the exposed surface of the seed layer and filling the deep hole. The second device includes a resistance layer located in the second device region of the substrate and filling the trench penetrating the second electrode layer, a third lead electrode electrically connected to the resistance layer, and a fourth lead electrode electrically connected to the resistance layer. The bottom surface of the trench exposes the first dielectric layer. The second dielectric layer covers the exposed surfaces of the second electrode layer and the resistance layer. The first lead electrode, the second lead electrode, the third lead electrode, and the fourth lead electrode all penetrate the second dielectric layer.

[0024] As described above, the packaging substrate and its manufacturing method of the present invention improve the manufacturing process of the packaging substrate, integrate passive devices required for the circuit in the packaging substrate into the silicon substrate to form a silicon-based intermediate layer, and bury the silicon-based intermediate layer as the intermediate layer at a preset position of the substrate body, reducing the size of the passive device array and correspondingly reducing the size of the packaging substrate. Since all passive devices required for the circuit in the packaging substrate are integrated into the silicon-based intermediate layer, the process of mounting passive devices during the manufacturing process of the packaging substrate is avoided, reducing the process cost of manufacturing the substrate and simultaneously reducing the probability of scrapping the packaging substrate due to misplacement of passive devices, improving the yield of manufacturing the packaging substrate. In addition, since the passive devices required for the circuit of the packaging substrate are integrated into the silicon-based intermediate layer and the silicon-based intermediate layer is buried in the substrate body, the passive devices are closer to the pins of the packaged devices or chips, ensuring the power integrity and signal integrity of the devices or chips, while increasing the wiring and pin density of the packaging substrate, further reducing the size of the packaging substrate, and then reducing the size of the packaging structure and improving the integration degree of the packaging structure, which has high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It shows a process flow chart of the manufacturing method of the packaging substrate of the present invention.

[0026] Figure 2 It shows a schematic cross-sectional structure diagram of the substrate of the manufacturing method of the packaging substrate of the present invention.

[0027] Figure 3 It shows a schematic cross-sectional structure diagram after forming deep holes in the manufacturing method of the packaging substrate of the present invention.

[0028] Figure 4 It shows a schematic cross-sectional structure diagram after forming the first electrode layer in the manufacturing method of the packaging substrate of the present invention.

[0029] Figure 5 It shows a schematic cross-sectional structure diagram after forming the first dielectric layer in the manufacturing method of the packaging substrate of the present invention.

[0030] Figure 6 It shows a schematic cross-sectional structure diagram after forming the seed layer in the manufacturing method of the packaging substrate of the present invention.

[0031] Figure 7 It shows a schematic cross-sectional structure diagram after forming the conductive layer in the manufacturing method of the packaging substrate of the present invention.

[0032] Figure 8 It shows a schematic cross-sectional structure diagram after thinning the conductive layer in the manufacturing method of the packaging substrate of the present invention.

[0033] Figure 9Schematic cross-sectional structure diagram after forming a trench in the manufacturing method of the encapsulation substrate of the present invention.

[0034] Figure 10 Schematic cross-sectional structure diagram after forming a resistive material layer in the manufacturing method of the encapsulation substrate of the present invention.

[0035] Figure 11 Schematic cross-sectional structure diagram after forming a resistive layer in the manufacturing method of the encapsulation substrate of the present invention.

[0036] Figure 12 Schematic cross-sectional structure diagram after forming an electrode lead-out hole in the manufacturing method of the encapsulation substrate of the present invention.

[0037] Figure 13 Schematic cross-sectional structure diagram after forming a second dielectric layer in the manufacturing method of the encapsulation substrate of the present invention.

[0038] Figure 14 Schematic cross-sectional structure diagram after forming a first contact hole in the manufacturing method of the encapsulation substrate of the present invention.

[0039] Figure 15 Schematic cross-sectional structure diagram after forming a second contact hole, a third contact hole, and a fourth contact hole in the manufacturing method of the encapsulation substrate of the present invention.

[0040] Figure 16 Schematic cross-sectional structure diagram after forming an electrode material layer in the manufacturing method of the encapsulation substrate of the present invention.

[0041] Figure 17 Schematic cross-sectional structure diagram after forming a first lead-out electrode, a second lead-out electrode, a third lead-out electrode, and a fourth lead-out electrode in the manufacturing method of the encapsulation substrate of the present invention.

[0042] Figure 18 Schematic cross-sectional structure diagram after forming an isolation material layer in the manufacturing method of the encapsulation substrate of the present invention.

[0043] Figure 19 Schematic cross-sectional structure diagram after forming an isolation layer in the manufacturing method of the encapsulation substrate of the present invention.

[0044] Explanation of the reference numerals in the drawings

[0045] 1 Substrate

[0046] 11 First device area

[0047] 12 Second device area

[0048] 13 Deep hole

[0049] 14 Dielectric layer

[0050] 2 First electrode layer

[0051] 21 First dielectric layer

[0052] 3 Second electrode layer

[0053] 31 Seed layer

[0054] 32 Conductive layer

[0055] 33 Groove

[0056] 34 Electrode lead-out hole

[0057] 4 Resistance layer

[0058] 40 Resistance material layer

[0059] 5 Second dielectric layer

[0060] 51 First contact hole

[0061] 52 Second contact hole

[0062] 53 Third contact hole

[0063] 54 Fourth contact hole

[0064] 6 First lead-out electrode

[0065] 60 Electrode material layer

[0066] 61 Isolation layer

[0067] 62 Isolation material layer

[0068] 7 Second lead-out electrode

[0069] 8 Third lead-out electrode

[0070] 9 Fourth lead-out electrode Detailed implementation manners

[0071] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] Please refer to Figures 1 to 19It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0073] Embodiment 1

[0074] This embodiment provides a method for manufacturing a packaging substrate. As Figure 1 shown, it is a process flow chart of the method for manufacturing the packaging substrate, including the following steps:

[0075] S1: Provide a substrate, at least one first device area and at least one second device area are defined on the substrate. A plurality of deep holes are formed at intervals on the upper surface layer of the first device area, and the bottom surface of the deep hole is spaced from the bottom surface of the substrate by a preset distance;

[0076] S2: Form a first electrode layer covering the upper surface of the substrate, the bottom surface, and the inner wall of the deep hole, and form a first dielectric layer covering the exposed surface of the first electrode layer;

[0077] S3: Form a seed layer covering the exposed surface of the first dielectric layer, and form a conductive layer covering the upper surface of the seed layer and filling the deep hole. The conductive layer and the seed layer constitute a second electrode layer;

[0078] S4: Form at least one trench penetrating the second electrode layer above the substrate in the second device area. The bottom surface of the trench exposes the first dielectric layer, and form a resistance layer filling the trench;

[0079] S5: Form a second dielectric layer covering the exposed surfaces of the second electrode layer and the resistance layer, and form a first lead electrode, a second lead electrode, a third lead electrode, and a fourth lead electrode penetrating the second dielectric layer. The first lead electrode and the second lead electrode are respectively electrically connected to the first electrode layer and the second electrode layer to jointly form a first device with the first dielectric layer. The third lead electrode and the fourth lead electrode are respectively electrically connected to the resistance layer and spaced by a preset distance to form a second device;

[0080] S6: Use the substrate on which at least the first device and the second device are integrated as an intermediate layer and bury it at a preset position in the substrate body to obtain a packaging substrate.

[0081] Please refer to Figures 2 to 8, perform the steps S1, S2, and S3: Provide a substrate 1, at least one first device region 11 and at least one second device region 12 are defined on the substrate 1, a plurality of deep holes 13 arranged at intervals are formed on the upper surface layer of the first device region 11, and the bottom surface of the deep hole 13 is spaced from the bottom surface of the substrate 1 by a preset distance; form a first electrode layer 2 covering the upper surface of the substrate 1, the bottom surface and the inner wall of the deep hole 13, and form a first dielectric layer 21 covering the exposed surface of the first electrode layer 2; form a seed layer 31 covering the exposed surface of the first dielectric layer 21, and form a conductive layer 32 covering the upper surface of the seed layer 31 and filling the deep hole 13 based on the seed layer 31, and the conductive layer 32 and the seed layer 31 constitute a second electrode layer 3.

[0082] Specifically, on the premise of ensuring that the substrate 1 can integrate passive devices with the number required for the circuits in the package substrate, the size and thickness of the substrate 1 can be selected according to actual situations, which will not be limited here. In this embodiment, the thickness range of the substrate 1 is 500 μm to 1000 μm, so as to facilitate burying the substrate 1 into the package substrate, and at the same time, it can ensure that the substrate 1 after burying the integrated passive devices has no influence on the thickness of the package substrate.

[0083] As an example, as Figure 2 shown, it is a schematic cross-sectional structure diagram of the substrate 1, and a dielectric layer 14 is further provided on the upper surface layer of the substrate 1, and the first electrode layer 2 covers the upper surface of the dielectric layer 14.

[0084] Specifically, the method for forming the dielectric layer 14 on the upper surface layer of the substrate 1 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0085] Specifically, the dielectric layer 14 is used as a buffer layer for the mask layer for fabricating the deep hole 13. On the premise of ensuring the film-forming quality of the mask layer for fabricating the deep hole 13 subsequently, the thickness of the dielectric layer 14 can be selected according to actual situations, which will not be limited here.

[0086] Specifically, as Figure 3 shown, it is a schematic cross-sectional structure diagram after forming the deep hole 13. Forming the deep hole 13 includes the following steps: forming a patterned first photoresist layer (not shown) on the upper surface of the dielectric layer 14; forming the deep hole 13 based on the patterned first photoresist layer.

[0087] Specifically, the method for forming the patterned first photoresist layer is the common photoresist coating, drying, exposure, and development processes, which will not be elaborated here.

[0088] Specifically, the method for forming the deep hole 13 includes dry etching, wet etching, or other suitable methods. In this embodiment, the substrate 1 is etched by inductively coupled plasma deep silicon etching process (dry etching) to obtain the deep hole 13.

[0089] As an example, the aperture range of the deep hole 13 is 0.5 μm to 10 μm, and the depth range of the deep hole 13 is 0.5 μm to 20 μm.

[0090] Specifically, when ensuring that the performance of the first device fabricated in the first device region 11 meets the requirements of the circuit in the packaging substrate, the number of the deep holes 13 can be selected according to the actual situation, which is not limited here; the aperture and depth of the deep holes 13 can also be selected as other suitable values.

[0091] Specifically, before forming the first electrode layer 2 and after forming the deep hole 13, it further includes the step of removing the first photoresist layer.

[0092] Specifically, the method for removing the first photoresist layer is a common photoresist removal and stripping method, which will not be elaborated here.

[0093] Specifically, as Figure 4 shown, it is a schematic cross-sectional structure diagram after forming the first electrode layer 2. The method for forming the first electrode layer 2 includes magnetron sputtering, atomic layer deposition, chemical vapor deposition, or other suitable methods.

[0094] Specifically, the material of the first electrode layer 2 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, graphene, or other suitable electrode materials.

[0095] As an example, the thickness range of the first electrode layer 2 is 0.1 μm to 0.5 μm.

[0096] Specifically, as Figure 5 shown, it is a schematic cross-sectional structure diagram after forming the first dielectric layer 21. The method for forming the first dielectric layer 21 includes atomic layer deposition, chemical vapor deposition, or other suitable methods.

[0097] As an example, the thickness range of the first dielectric layer 21 is 0.1 μm to 1.0 μm.

[0098] Specifically, the first dielectric layer 21 is the intermediate dielectric layer in the formed first device. Based on the needs of the performance of the first device, the first dielectric layer 21 can also be of other suitable thicknesses.

[0099] As an example, as Figure 6As shown, it is a schematic cross-sectional structure diagram after forming the seed layer 31, and the thickness range of the seed layer 31 is 0.1 μm to 0.5 μm.

[0100] Specifically, the seed layer 31 is used to form a buffer layer for the conductive layer 32, and the method for forming the seed layer 31 includes magnetron sputtering, atomic layer deposition, chemical vapor deposition, or other suitable methods.

[0101] Specifically, as Figure 7 As shown, it is a schematic cross-sectional structure diagram after forming the conductive layer 32. The method for forming the conductive layer 32 includes chemical vapor deposition, electroplating, or other suitable methods. In this embodiment, based on the seed layer 31, the conductive layer 32 with a thickness of 25 μm is formed by electroplating to ensure that the conductive layer 32 completely fills the remaining gap in the deep hole 13, and at the same time, the upper surface of the conductive layer 32 is higher than the upper surface of the substrate 1 by a preset distance.

[0102] Specifically, as Figure 8 As shown, it is a schematic cross-sectional structure diagram after thinning the conductive layer 32. After forming the conductive layer 32 and before forming the trench, there is also a step of thinning the conductive layer 32 to make the thickness of the second electrode layer 3 formed by the thinned conductive layer 32 and the seed layer 31 reach a preset thickness value.

[0103] Specifically, the method for thinning the conductive layer 32 includes chemical mechanical polishing or other suitable methods.

[0104] As an example, the thickness range of the second electrode layer located above the substrate is 0.3 μm to 2 μm, that is, the sum of the thicknesses of the seed layer 31 and the conductive layer 32 located directly above the substrate ranges from 0.3 μm to 2 μm.

[0105] Please refer to again Figures 9 to 19, perform the steps S4, S5, and S6: form at least one trench 33 penetrating the second electrode layer 3 above the substrate 1 in the second device region 12, the bottom surface of the trench 33 exposing the first dielectric layer 21, and form a resistance layer 4 filling the trench 33; form a second dielectric layer 5 covering the exposed surfaces of the second electrode layer 3 and the resistance layer 4, and form a first lead electrode 6, a second lead electrode 7, a third lead electrode 8, and a fourth lead electrode 9 penetrating the second dielectric layer 5. The first lead electrode 6 and the second lead electrode 7 are respectively electrically connected to the first electrode layer 2 and the second electrode layer 3 to jointly form a first device with the first dielectric layer 21. The third lead electrode 8 and the fourth lead electrode 9 are respectively electrically connected to the resistance layer 4 and are spaced a preset distance to form a second device; bury the substrate 1 integrated with at least the first device and the second device as an intermediate layer into a preset position of a substrate body (not shown) to obtain a packaged substrate.

[0106] Specifically, as Figure 9 shown, it is a schematic cross-sectional structure diagram after forming the trench 33. Forming the trench 33 includes the following steps: form a patterned second photoresist layer (not shown) on the upper surface of the second electrode layer 3; form the trench based on the patterned second photoresist layer.

[0107] Specifically, the method of forming the patterned second photoresist layer is the commonly used photoresist coating, drying, exposure, and development processes, which will not be elaborated here.

[0108] Specifically, the method of forming the trench 33 includes dry etching, wet etching, or other suitable methods. In this embodiment, an ion beam etching (dry etching) process is used to etch the exposed second electrode layer 3 to obtain the trench 33, and the bottom surface of the etched trench 33 exposes the first dielectric layer 21.

[0109] Specifically, after forming the trench 33 and before forming the resistance layer 4, it further includes the step of removing the second photoresist layer covering the upper surface of the second electrode layer 3.

[0110] Specifically, the method of removing the second photoresist layer is the commonly used photoresist layer stripping method, which will not be elaborated here.

[0111] Specifically, after forming the trench 33 and before obtaining the resistance layer 4 filling the trench 33, it further includes the step of forming a resistance material layer 40 covering the upper surface of the second electrode layer 3 and filling the trench 33.

[0112] Specifically, as Figure 10As shown, it is a schematic cross-sectional structure diagram after forming the resistor material layer 40. The method for forming the resistor material layer 40 includes magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods.

[0113] Specifically, the material of the resistor material layer 40 includes titanium nitride, chromium, silicon carbide, or other suitable resistor materials.

[0114] Specifically, after forming the conductive layer 32 and before forming the trench 33, the conductive layer 32 may not be thinned. After forming the resistor material layer 40, while removing the resistor material layer 40 covering the upper surface of the conductive layer 32, the conductive layer 32 and the resistor material layer 40 located in the trench 33 are thinned.

[0115] Specifically, when the conductive layer 32 is thinned and then the resistor material layer 40 is formed, the upper surface of the resistor material layer 40 located in the trench 33 is not lower than the upper surface of the second electrode layer 3.

[0116] Specifically, as Figure 11 shown, it is a schematic cross-sectional structure diagram after forming the resistor layer 4. When the conductive layer 32 is thinned before forming the trench 33, after forming the resistor material layer 40 and before forming the resistor layer 4, it further includes the step of removing the resistor material layer 40 covering the upper surface of the second electrode layer 3.

[0117] Specifically, when the conductive layer 32 is thinned before forming the trench 33, the method for removing the resistor material layer 40 covering the upper surface of the second electrode layer 3 includes chemical mechanical polishing or other suitable methods; when the conductive layer 32 is not thinned before forming the trench 33, the method for removing the resistor material layer 40 covering the upper surface of the second electrode layer 3 and thinning the conductive layer 32 includes chemical mechanical polishing or other suitable methods.

[0118] As an example, as Figure 12 shown, it is a schematic cross-sectional structure diagram after forming the electrode lead hole 34. Before forming the second dielectric layer 5 and after forming the resistor layer 4, it further includes the step of forming the electrode lead hole 34 penetrating through the second electrode layer 3 and the first dielectric layer 21, and the bottom surface of the electrode lead hole 34 exposes the first electrode layer 2.

[0119] Specifically, forming the electrode lead hole 34 includes the following steps: forming a patterned third photoresist layer (not shown) covering the exposed upper surfaces of the second electrode layer 3 and the resistor layer 4; forming the electrode lead hole 34 based on the patterned third photoresist layer.

[0120] Specifically, the method for forming the patterned third photoresist layer is the common process of photoresist coating, drying, exposure, and development, which will not be elaborated here.

[0121] Specifically, the method for forming the electrode lead-out hole 34 includes dry etching, wet etching, or other suitable methods. In this embodiment, an ion beam etching process is used to etch the exposed second electrode layer 3 and the first dielectric layer 21 located below the second electrode layer 3 to obtain the electrode lead-out hole 34.

[0122] Specifically, when ensuring the performance of the first device, the opening size and shape of the electrode lead-out hole 34 can be selected according to the actual situation, and will not be restricted here.

[0123] Specifically, before forming the second dielectric layer 5 and after forming the electrode lead-out hole 34, it further includes the step of removing the third photoresist layer covering the exposed upper surface of the second electrode layer 3 and the resistor layer 4.

[0124] Specifically, the method for removing the third photoresist layer is the common photoresist removal and stripping method, which will not be elaborated here.

[0125] Specifically, as Figure 13 shown, it is a schematic cross-sectional structure diagram after forming the second dielectric layer 5. The method for forming the second dielectric layer 5 includes chemical vapor deposition, physical vapor deposition, sputtering, or other suitable methods. In this embodiment, the second dielectric layer 5 is formed by a sputtering process.

[0126] Specifically, when ensuring the performance of the passive devices formed in the substrate 1, the thickness of the second dielectric layer 5 can be selected according to the actual situation, and will not be restricted here.

[0127] As an example, as Figure 14 shown, it is a schematic cross-sectional structure diagram after forming the first contact hole 51. Before forming the first lead-out electrode 6 and after forming the second dielectric layer 5, it further includes the step of forming a first contact hole 51 that penetrates and fills the second dielectric layer 5 of the electrode lead-out hole 34 and exposes the first electrode layer 2 at the bottom surface, and the first lead-out electrode 6 fills the first contact hole 51.

[0128] Specifically, forming the first contact hole 51 includes the following steps: forming a patterned fourth photoresist layer (not shown) on the upper surface of the second dielectric layer 5; forming the first contact hole 51 based on the patterned fourth photoresist layer.

[0129] Specifically, the method for forming the patterned fourth photoresist layer is the common process of photoresist coating, drying, exposure, and development, which will not be elaborated here.

[0130] Specifically, the first contact hole 51 is used to lead out the electrode of the first device. The method for forming the first contact hole 51 includes dry etching, wet etching or other suitable methods. In this embodiment, an ion beam etching process is used to etch the second dielectric layer 5 filling the electrode lead-out hole 34 to obtain the first contact hole 51.

[0131] Specifically, after forming the first contact hole 51 and before forming the first lead-out electrode 6, it further includes the step of removing the fourth photoresist layer covering the upper surface of the second dielectric layer 5.

[0132] Specifically, the method for removing the fourth photoresist layer is a commonly used photoresist removal and stripping method, which will not be elaborated here.

[0133] Specifically, as Figure 15 shown, it is a schematic cross-sectional structure diagram after forming the second contact hole 52, the third contact hole 53 and the fourth contact hole 54. After forming the second dielectric layer 5 and before forming the second lead-out electrode 7, the third lead-out electrode 8 and the fourth lead-out electrode 9, it further includes the step of forming the second contact hole 52, the third contact hole 53 and the fourth contact hole 54 penetrating through the second dielectric layer 5. The bottom surface of the second contact hole 52 exposes the second electrode layer 3. The second lead-out electrode 6 fills the second contact hole 52. The bottom surfaces of the third contact hole 53 and the fourth contact hole 54 both expose the resistor layer 4. The third lead-out electrode 8 and the fourth lead-out electrode 9 respectively fill the third contact hole 53 and the fourth contact hole 54.

[0134] Specifically, forming the second contact hole 52, the third contact hole 53 and the fourth contact hole 54 includes the following steps: forming a patterned fifth photoresist layer (not shown) on the upper surface of the second dielectric layer 5; synchronously forming the second contact hole 52, the third contact hole 53 and the fourth contact hole 54 based on the patterned fifth photoresist layer.

[0135] Specifically, the method for forming the patterned fifth photoresist layer is a commonly used photoresist coating, baking, exposure and development process, which will not be elaborated here.

[0136] Specifically, the method for synchronously forming the second contact hole 52, the third contact hole 53 and the fourth contact hole 54 includes dry etching, wet etching or other suitable methods. In this embodiment, an ion beam etching process is used to etch the exposed second dielectric layer 5 to obtain the second contact hole 52, the third contact hole 53 and the fourth contact hole 54.

[0137] Specifically, under the condition of ensuring the performance of the passive devices formed in the substrate 1, the second contact hole 52, the third contact hole 53, and the fourth contact hole 54 can also be formed step by step.

[0138] Specifically, after forming the second contact hole 52, the third contact hole 53, and the fourth contact hole 54, and before forming the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9, it further includes the step of removing the fifth photoresist layer.

[0139] Specifically, the method of removing the fifth photoresist layer is a commonly used photoresist removal and stripping method, which will not be elaborated here.

[0140] Specifically, as Figure 16 shown, it is a schematic cross-sectional structure diagram after forming the electrode material layer 60. Forming the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 includes the following steps: forming a buffer layer (not shown) covering the exposed surfaces of the first contact hole 51, the second contact hole 52, the third contact hole 53, and the fourth contact hole 54 and the upper surface of the second dielectric layer 5; thickening the buffer layer to a preset thickness based on the buffer layer to obtain the electrode material layer 60; forming a patterned sixth photoresist layer on the upper surface of the electrode material layer 60, and synchronously forming the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 based on the patterned sixth photoresist layer.

[0141] Specifically, the method of forming the buffer layer includes chemical vapor deposition, physical vapor deposition, evaporation, atomic layer deposition, magnetron sputtering, or other suitable methods. In this embodiment, the buffer layer is formed by using a magnetron sputtering process.

[0142] Specifically, the method of thickening the buffer layer includes chemical vapor deposition, physical vapor deposition, evaporation, atomic layer deposition, magnetron sputtering, electroplating, or other suitable methods. In this embodiment, the buffer layer is thickened by using an electroplating process so that the thickness of the electrode material layer 60 formed by thickening the buffer layer reaches 8 μm to 10 μm.

[0143] Specifically, the method of forming the patterned sixth photoresist layer is a commonly used photoresist coating, drying, exposure, and development process, which will not be elaborated here.

[0144] Specifically, as Figure 17As shown, it is a schematic cross-sectional structure diagram after forming the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9. The method for simultaneously forming the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 includes dry etching, wet etching, or other suitable methods. In this embodiment, an ion beam etching process is used to etch the exposed electrode material layer 60 to obtain the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9.

[0145] Specifically, on the premise of ensuring the performance of the passive devices in the substrate 1, the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 can also be formed step by step.

[0146] Specifically, after forming the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9, before burying the substrate 1 as an intermediate layer into the substrate body, it further includes the step of removing the sixth photoresist layer.

[0147] Specifically, the method for removing the sixth photoresist layer is a commonly used photoresist removal and stripping process, which will not be elaborated here.

[0148] Specifically, after forming the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9, before burying the substrate 1 as an intermediate layer into the substrate body, it further includes the step of forming a spacer layer 61 to fill the gaps between the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9.

[0149] Specifically, forming the spacer layer 61 includes the following steps: forming a spacer material layer 62 that covers the exposed surfaces of the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 and the exposed upper surface of the second dielectric layer 5, and the upper surface of the spacer material layer 62 is higher than the upper surfaces of the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 by a preset distance; thinning the spacer material layer 62 by a preset thickness to obtain the spacer layer 61.

[0150] Specifically, as Figure 18 shown, it is a schematic cross-sectional structure diagram after forming the spacer material layer 62. The method for forming the spacer material layer 62 includes sputtering, chemical vapor deposition, physical vapor deposition, or other suitable methods. In this embodiment, the spacer material layer 62 is formed by a sputtering process.

[0151] Specifically, the material of the isolation material layer 62 includes silicon dioxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0152] Specifically, the upper surface of the isolation material layer 62 is 1 μm to 2 μm higher than the upper surfaces of the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9.

[0153] Specifically, as Figure 19 shown, it is a schematic cross-sectional structure diagram after forming the isolation layer 61. While thinning the isolation material layer 62, the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 are also thinned, so that the first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 are synchronously thinned by 3 μm to 4 μm, and at the same time, the isolation layer 61 is obtained.

[0154] Specifically, the method of burying the intermediate layer into the substrate body is a common packaging substrate manufacturing process, which will not be elaborated here.

[0155] Specifically, by fabricating passive discrete devices required in the circuit on the substrate 1, the size of the passive device array is reduced, and the problem that the size of the packaging substrate is large after the passive devices are buried in the packaging substrate is solved.

[0156] Specifically, integrating the passive devices onto the substrate and burying the substrate as the intermediate layer into the substrate body avoids the process of mounting passive devices during the manufacturing process of the packaging substrate, reduces the process cost of mounting passive devices multiple times, and at the same time can reduce the problem of scrapping the packaging substrate due to misplacement of passive devices, improving the yield of manufacturing the packaging substrate and increasing the economic benefits.

[0157] The manufacturing method of the packaging substrate in this embodiment improves the manufacturing process of the packaging substrate. First, integrate the passive devices required in the circuit onto the substrate 1, and then bury the substrate 1 integrated with the passive devices as the intermediate layer into the packaging substrate body, reducing the size of the passive device array, and then the size of the packaging substrate can be correspondingly reduced. At the same time, since all the passive devices required for the circuit are integrated onto the substrate 1, the process of mounting passive devices during the manufacturing process of the packaging substrate is avoided, reducing the process cost of mounting passive devices multiple times, reducing the problem of scrapping the packaging substrate due to misplacement of passive devices, improving the yield of manufacturing the packaging substrate, and increasing the economic benefits.

[0158] Embodiment 2

[0159] This embodiment provides a packaging substrate, which includes a substrate body and an intermediate layer. The intermediate layer is buried at a preset position of the substrate body. The intermediate layer includes a substrate 1, at least one first device, at least one second device, and a second dielectric layer 5. The first device includes a first electrode layer 2, a first dielectric layer 21, a second electrode layer 3, a first lead electrode 6 electrically connected to the first electrode layer 2, and a second lead electrode 7 electrically connected to the second electrode layer 3. The first electrode layer 2 covers the inner wall and bottom surface of the deep hole 13 in the first device area 11 of the substrate 1 and the upper surface of the substrate 1. The first dielectric layer 21 covers the exposed surface of the first electrode layer 2. The second electrode layer 3 includes a seed layer 31 covering the exposed surface of the first dielectric layer 21 and a conductive layer 32 covering the exposed surface of the seed layer 31 and filling the deep hole 13. The second device includes a resistance layer 4 located in the second device area 12 of the substrate 1 and filling the trench 33 penetrating the second electrode layer 3, a third lead electrode 8 electrically connected to the resistance layer 4, and a fourth lead electrode 9 electrically connected to the resistance layer 4. The bottom surface of the trench 33 exposes the first dielectric layer 21. The second dielectric layer 5 covers the exposed surfaces of the second electrode layer 3 and the resistance layer 4. The first lead electrode 6, the second lead electrode 7, the third lead electrode 8, and the fourth lead electrode 9 all penetrate the second dielectric layer 5.

[0160] Specifically, the size of the substrate body is related to the size and structure of the device or chip to be packaged, which is not limited here.

[0161] Specifically, the size and thickness of the intermediate layer are determined by the size of the substrate 1 and the size of the passive devices integrated in the substrate 1, which is not limited here.

[0162] Specifically, on the premise of ensuring the quality of the production of passive devices, the material of the substrate 1 can be selected according to the actual situation, which is not limited here. For example, the material of the substrate 1 can be silicon, silicon germanium, or silicon carbide. In this embodiment, an undoped silicon wafer is used as the substrate 1, that is, the substrate 1 is a silicon-based substrate, and the intermediate layer obtained by integrating passive devices on the substrate 1 is a silicon-based intermediate layer.

[0163] Specifically, a dielectric layer 14 is further provided on the upper surface layer of the substrate 1, and the material of the dielectric layer 14 includes silicon dioxide, silicon oxynitride, or other suitable buffer dielectric materials.

[0164] Specifically, the aperture range of the deep hole 13 is 0.5 μm to 10 μm, and the depth range of the deep hole 13 is 0.5 μm to 20 μm.

[0165] Specifically, the material of the first electrode layer 2 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, graphene, or other suitable electrode materials.

[0166] Specifically, the material of the first dielectric layer 21 includes one or more of ONO (Oxide-Nitride-Oxide, silicon dioxide - silicon nitride - silicon dioxide), silicon nitride (Si3N4), silicon dioxide (SiO2), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or can also be other suitable dielectric materials.

[0167] Specifically, the material of the seed layer 31 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, graphene, or other suitable conductive materials; the material of the conductive layer 32 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, graphene, or other suitable conductive materials. In this embodiment, a copper layer is used as the conductive layer 32.

[0168] Specifically, when ensuring the performance of the second device, the opening size and opening shape of the trench 33 can be selected according to actual circumstances and are not limited here.

[0169] Specifically, the upper surface of the resistance layer 4 is flush with the upper surface of the second electrode layer 3.

[0170] Specifically, an electrode lead-out hole 34 that penetrates the second electrode layer 3 and the first dielectric layer 21 and whose bottom surface exposes the first electrode layer 2 is further provided in the silicon-based intermediate layer, and the second dielectric layer 5 fills the electrode lead-out hole 34.

[0171] Specifically, the material of the second dielectric layer 5 includes one or more of ONO, silicon nitride, silicon dioxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or can also be other suitable dielectric materials.

[0172] Specifically, the first contact hole 51 penetrates and fills the second dielectric layer 5 that fills the electrode lead-out hole 34, and there is a second dielectric layer 5 with a preset thickness between the inner wall of the first contact hole 51 and the inner wall of the electrode lead-out hole 34.

[0173] Specifically,

[0174] Specifically, when ensuring the performance of the first device, the opening size and opening shape of the first contact hole 51 can be selected according to actual circumstances and are not limited here; the opening size and opening shape of the second contact hole 52 can be selected according to actual circumstances and are not limited here.

[0175] Specifically, on the premise of ensuring the performance of the second device, the opening size and shape of the third contact hole 53 can be selected according to the actual situation, which will not be limited here; the opening size and shape of the fourth contact hole 54 can be selected according to the actual situation, which will not be limited here.

[0176] Specifically, the first lead electrode 6 fills the first contact hole 51, the second lead electrode 7 fills the second contact hole 52, the third lead electrode 8 fills the third contact hole 53, and the fourth lead electrode 9 fills the fourth contact hole 54.

[0177] Specifically, the material of the first lead electrode 6 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum or other suitable conductive materials; the material of the second lead electrode 7 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum or other suitable conductive materials; the material of the third lead electrode 8 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum or other suitable conductive materials; the material of the fourth lead electrode 9 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum or other suitable conductive materials.

[0178] Specifically, an isolation layer 61 for filling the gaps between the first lead electrode 6, the second lead electrode 7, the third lead electrode 8 and the fourth lead electrode 9 is further provided in the silicon-based intermediate layer to ensure the insulation performance between the lead electrodes and protect each lead electrode at the same time.

[0179] Specifically, by integrating the passive device into the silicon-based intermediate layer, the passive device is closer to the pins of the packaged device or chip, ensuring the power integrity and signal integrity of the device or chip.

[0180] Specifically, integrating the passive device into the silicon-based intermediate layer and burying the silicon-based intermediate layer into the substrate body can greatly improve the wiring and pin density of the packaging substrate, effectively reduce the size of the packaging structure, make the electronic product smaller in size and higher in integration.

[0181] The packaging substrate of this embodiment improves the structure of the packaging substrate, integrates the passive devices required in the circuit of the packaging substrate into the silicon-based intermediate layer, and buries the silicon-based intermediate layer as the intermediate layer into the substrate body, making the passive device closer to the pins of the packaged device or chip, ensuring the power integrity and signal integrity of the device or chip, and at the same time can greatly improve the wiring and pin density of the packaging substrate, effectively reduce the size of the packaging structure, make the electronic product smaller in size and higher in integration.

[0182] In summary, the packaging substrate and its manufacturing method of the present invention improve the manufacturing process of the packaging substrate, integrate the passive devices required for the circuit in the packaging substrate into the silicon-based intermediate layer, and use the silicon-based intermediate layer as the intermediate layer at a preset position buried in the substrate body, reducing the size of the passive device array, and then correspondingly reducing the size of the packaging substrate. At the same time, since the passive devices required for the circuit in the packaging substrate are all integrated in the silicon-based intermediate layer, the process of mounting passive devices during the manufacturing process of the packaging substrate is avoided, the process cost of mounting passive devices multiple times is reduced, and the problem of scrapping the packaging substrate due to incorrect mounting of passive devices is reduced, improving the yield of manufacturing the packaging substrate. In addition, since the passive devices required for the circuit of the packaging substrate are integrated in the silicon-based intermediate layer, and the silicon-based intermediate layer is buried at a preset position of the substrate body, the passive devices are closer to the pins of the packaged devices or chips, ensuring the power integrity and signal integrity of the devices or chips, and at the same time can greatly improve the wiring and pin density of the packaging substrate, enhancing the integration degree of the packaging structure. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0183] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a packaging substrate, characterized in that Including the following steps: Providing a substrate, at least one first device region and at least one second device region are defined on the substrate, a plurality of deep holes arranged at intervals are formed on the upper surface layer of the first device region, and the bottom surface of the deep hole is spaced from the bottom surface of the substrate by a preset distance; Forming a first electrode layer covering the upper surface of the substrate, the bottom surface and the inner wall of the deep hole, and forming a first dielectric layer covering the exposed surface of the first electrode layer; Forming a seed layer covering the exposed surface of the first dielectric layer, and forming a conductive layer covering the upper surface of the seed layer and filling the deep hole based on the seed layer, the conductive layer and the seed layer constitute a second electrode layer; Forming at least one trench penetrating the second electrode layer above the substrate in the second device region, the bottom surface of the trench exposes the first dielectric layer, and forming a resistance layer filling the trench; Forming a second dielectric layer covering the exposed surfaces of the second electrode layer and the resistance layer, and forming a first lead electrode, a second lead electrode, a third lead electrode and a fourth lead electrode penetrating the second dielectric layer, the first lead electrode and the second lead electrode are respectively electrically connected to the first electrode layer and the second electrode layer to jointly constitute a first device with the first dielectric layer, the third lead electrode and the fourth lead electrode are respectively electrically connected to the resistance layer and spaced by a preset distance to constitute a second device; Using the substrate on which at least the first device and the second device are integrated as an intermediate layer and burying it in a preset position of the substrate body to obtain a packaged substrate.

2. The manufacturing method of the encapsulation substrate according to claim 1, wherein: A dielectric layer is further provided on the upper surface layer of the substrate, and the first dielectric layer covers the upper surface of the dielectric layer.

3. The manufacturing method of the encapsulation substrate according to claim 1, wherein: The aperture range of the deep hole is 0.5μm to 10μm, and the depth range of the deep hole is 0.5μm to 20μm.

4. The manufacturing method of the encapsulation substrate according to claim 1, wherein: The thickness range of the first electrode layer is 0.1μm to 0.5μm, the thickness range of the seed layer is 0.1μm to 0.5μm, and the thickness range of the second electrode layer located above the substrate is 0.3μm to 2μm.

5. The manufacturing method of the encapsulation substrate according to claim 1, characterized in that: The thickness range of the first dielectric layer is 0.1μm to 1.0μm.

6. The manufacturing method of the encapsulation substrate according to claim 1, wherein: The thickness range of the resistance layer is 0.3μm to 2μm.

7. The manufacturing method of the packaging substrate according to claim 1, wherein: Before forming the second dielectric layer and after forming the resistance layer, it further includes the step of forming an electrode lead-out hole penetrating the second electrode layer and the first dielectric layer, the bottom surface of the electrode lead-out hole exposes the first electrode layer, and the second dielectric layer fills the electrode lead-out hole.

8. The manufacturing method of the encapsulation substrate according to claim 7, wherein: Before forming the first lead electrode and after forming the second dielectric layer, it further includes the step of forming a first contact hole penetrating the second dielectric layer filling the electrode lead-out hole and the bottom surface of which exposes the first electrode layer, and the first lead electrode fills the first contact hole.

9. The manufacturing method of the encapsulation substrate according to claim 1, wherein: Before forming the second lead electrode, the third lead electrode, and the fourth lead electrode, after forming the second dielectric layer, it further includes the steps of forming second contact holes, third contact holes, and fourth contact holes penetrating through the second dielectric layer. The bottom surface of the second contact hole exposes the second electrode layer, the second lead electrode fills the second contact hole, the bottom surfaces of the third contact hole and the fourth contact hole both expose the resistor layer, and the third lead electrode and the fourth lead electrode respectively fill the third contact hole and the fourth contact hole.

10. An encapsulation substrate, characterized in that, Comprising: A substrate body; An intermediate layer embedded at a preset position of the substrate body. The intermediate layer includes a substrate, at least one first device, at least one second device, and a second dielectric layer. The first device includes a first electrode layer, a first dielectric layer, a second electrode layer, a first lead electrode electrically connected to the first electrode layer, and a second lead electrode electrically connected to the second electrode layer. The first electrode layer covers the inner wall and bottom surface of the deep hole in the first device region of the substrate and the upper surface of the substrate. The first dielectric layer covers the exposed surface of the first electrode layer. The second electrode layer includes a seed layer covering the exposed surface of the first dielectric layer and a conductive layer covering the exposed surface of the seed layer and filling the deep hole. The second device includes a resistor layer located in the second device region of the substrate and filling the trench penetrating through the second electrode layer, a third lead electrode electrically connected to the resistor layer, and a fourth lead electrode electrically connected to the resistor layer. The bottom surface of the trench exposes the first dielectric layer. The second dielectric layer covers the exposed surfaces of the second electrode layer and the resistor layer. The first lead electrode, the second lead electrode, the third lead electrode, and the fourth lead electrode all penetrate through the second dielectric layer.

Images