QFN lead frame and preparation method thereof and QFN packaging structure

Abstract

The present invention discloses a QFN lead frame, a preparation method thereof, and a QFN packaging structure. The QFN lead frame is manufactured by a process combining etching and stamping. The inner pins and base islands are stamped by stamping to make them lower than the outer pins and in a step-like shape, thereby providing a support frame for the new QFN packaging structure. This not only improves production efficiency but also reduces production costs, providing the possibility for large-scale production. The QFN packaging structure adopts a lead frame with an upper and lower double-layer pin structure, breaking the limitation of traditional packaging welding points that are only on the same plane, effectively increasing the internal wiring space and solder point distribution space of the chip, and improving the integration of the packaging structure. The structural design of the lead frame in the present invention increases the heat dissipation area of ​​the chip, especially by setting the upper and lower two-layer pin structure to form a multi-level heat dissipation network, which greatly improves the heat dissipation efficiency and effectively meets the heat dissipation requirements of large-size chip packaging structures.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a QFN lead frame, a preparation method thereof, and a QFN packaging structure. Background Art

[0002] As the chip carrier of the integrated circuit, the lead frame is a key structural component that uses bonding materials to achieve electrical connection between the internal circuit lead ends of the chip and the external leads to form an electrical circuit. It acts as a bridge connecting to external wires and is also the main way to dissipate heat inside the chip. Lead frames are required in most semiconductor integrated blocks.

[0003] The traditional QFN package structure uses a conventional leadframe as the main structure, with pins distributed around the edges of the product. This structural design limits product flexibility in applications and, due to the limited pin space and number of pins, results in low integration. Furthermore, the leadframe in the traditional QFN package structure is a flat frame, which is prone to delamination and poor wire bonding during the encapsulation and wire bonding processes. Furthermore, the package structure completely encapsulates the leadframe within the package, resulting in a limited heat dissipation path, relying primarily on the backside of the base island located at the center of the package bottom. This slow heat dissipation makes it difficult to meet growing heat dissipation requirements and also reduces product lifespan. To overcome these shortcomings, the industry has been seeking new QFN package design solutions.

[0004] Several improvements have been proposed in the prior art, such as improving the heat dissipation performance and integration of the package by modifying the lead frame structure and optimizing the pin distribution. However, these solutions still have limitations, such as suboptimal heat dissipation and insufficient pin stability, and have not yet fully resolved the technical challenges of the traditional QFN package structure.

[0005] Therefore, there is an urgent need to provide a new lead frame structure. Summary of the Invention

[0006] To address these issues, the present invention provides a QFN leadframe and its fabrication method. This leadframe, with multiple turns of pins located in different planes, is produced through a combination of etching and stamping. The resulting QFN package structure increases internal chip wiring space and solder joint distribution, improving the package's integration and heat dissipation area. In particular, by arranging pins in different planes, a multi-layered heat dissipation network is formed, significantly improving heat dissipation efficiency and effectively meeting the heat dissipation requirements of large-scale chip packaging structures.

[0007] In a first aspect, the present invention discloses a method for preparing a QFN lead frame, the method comprising the following steps:

[0008] S1. Provide a high-strength metal substrate and use a chemical etching process to form a base island and multiple rings of pins on the front of the metal substrate. The multiple rings of pins are arranged around the base island. The multiple rings of pins include an inner ring of pins and at least one outer ring of pins. The inner pins are closest to the base island.

[0009] S2. stamping the metal substrate to form an independent QFN lead frame; in the stamping process, the base island and the inner lead area are stamped downward from the front side to the back side of the QFN lead frame, so that the QFN lead frame has a stepped structure;

[0010] The base island and the inner pin surface are in the same plane, the base island, the inner pin surface and the outer pin surface are not in the same plane, and the outer pin surface is higher than the base island and the inner pin surface.

[0011] Preferably, the punching distance is 1-5 mm.

[0012] Preferably, the outer pins are arranged in a circle.

[0013] Preferably, the metal substrate is made of copper or copper alloy.

[0014] In a second aspect, the present invention discloses a QFN lead frame prepared according to the above method, which includes a metal substrate and a base island and multiple inner and outer rings of pins arranged on the front side of the metal substrate. The multiple rings of pins are arranged around the base island. The multiple rings of pins include one circle of inner pins and at least one circle of outer pins. The inner pins are closest to the base island. The QFN lead frame has a stepped structure, the base island and the inner pin surfaces are in the same plane, the base island, the inner pin surfaces and the outer pin surfaces are not in the same plane, and the outer pin surfaces are higher than the base island and the inner pin surfaces.

[0015] In a third aspect, the present invention further discloses a QFN packaging structure, including the aforementioned QFN lead frame. Specifically, a semiconductor chip is mounted on the base island of the QFN lead frame, and after the semiconductor chip is electrically connected to the inner pins and outer pins through leads, the semiconductor chip and the leads are plastic-sealed to form a plastic-sealed part, thereby forming a QFN packaging structure with a stepped structure.

[0016] Preferably, the exposed pins in the QFN package structure are electroplated with tin or tin alloy.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention uses a combined etching and stamping process to manufacture the QFN lead frame. The inner pins and base island are stamped to be lower than the outer pins, forming a step-like shape, thereby providing a support frame for the novel QFN package structure. By changing the lead frame manufacturing process and adopting a combined etching and stamping method, not only is production efficiency improved, but production costs are also reduced, making it possible to manufacture on a large scale.

[0019] 2. The QFN package structure of the present invention adopts a lead frame with an upper and lower double-layer pin structure, breaking the limitation of traditional package solder joints that are only on the same plane, effectively increasing the internal wiring space and solder joint distribution space of the chip, improving the integration of the package structure, and providing the possibility of realizing more complex wiring design.

[0020] 3. The structural design of the lead frame in the present invention increases the heat dissipation area of ​​the chip, especially by setting up two layers of pin structures, forming a multi-level heat dissipation network, greatly improving the heat dissipation efficiency, and effectively meeting the heat dissipation requirements of large-size chip packaging structures.

[0021] 4. The QFN package structure of the present invention makes the pin distribution more uniform and is no longer limited to the edges of the package structure, which significantly improves the flexibility of the package structure in application and provides more options for the design of electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the structure of the QFN lead frame in Example 1 of the present invention;

[0023] Figure 2 Schematic diagram of the side structure of the QFN lead frame in Example 1 of the present invention;

[0024] Figure 3 Schematic diagram of the QFN package structure in Example 2 of the present invention;

[0025] Figure 4 is another schematic diagram of the QFN package structure;

[0026] Figure 5 This is the process flow chart of QFN packaging structure.

[0027] Explanation of reference numerals: QFN lead frame 1, metal substrate 101, base island 102, inner pin 103, inner pin surface 1031, outer pin 104, outer pin surface 1041, semiconductor chip 2, lead 3, plastic packaging part 4. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0029] Example 1

[0030] This embodiment discloses a method for preparing a QFN lead frame, specifically, a method for preparing the QFN lead frame 1 by using a process combining etching and stamping.

[0031] The chemical etching process mentioned in this embodiment forms the base island 102 and multiple turns of leads on the front surface of the metal substrate 101. This process is prior art and is briefly described here. The lead frame forming process mainly develops a production process (taking the mechanical template electroplating process as an example): frame design, etching mold creation, raw material pre-cleaning, dry film pressing, exposure, development, etching, film stripping, dry film pressing, exposure, development, silver plating, film stripping, stamping, and packaging. A stamping process is added to the etched lead frame production process. The matching stamping tool is created according to the design. The lead frame is silver-plated and then stamped to complete the production.

[0032] The manufacturing method of the QFN lead frame 1 disclosed in this embodiment includes the following steps:

[0033] S1. Provide a high-strength metal substrate 101, and use a chemical etching process to form a base island 102 and multiple circles of pins on the front of the metal substrate 101. The multiple circles of pins are arranged around the base island 102. The multiple circles of pins include a circle of inner pins 103 and at least one circle of outer pins 104. The inner pins 103 are closest to the base island 102.

[0034] S2. Stamping the metal substrate 101 to form an independent QFN lead frame 1; in the stamping process, the base island 102 and the inner pin 103 area are stamped downward from the front to the back of the QFN lead frame 1, so that the QFN lead frame 1 has a stepped structure.

[0035] The base island 102 and the inner pin surface 1031 are in the same plane, the base island 102 , the inner pin surface 1031 and the outer pin surface 1041 are not in the same plane, and the outer pin surface 1041 is higher than the base island 102 and the inner pin surface 1031 .

[0036] The QFN lead frame 1 prepared according to the above method has a schematic diagram of its specific structure as shown in FIG. Figure 1 The schematic diagram of the side structure is shown in Figure 2 In this embodiment, the outer pins 104 are arranged in a circle as an example.

[0037] The QFN lead frame 1 includes a metal substrate 101, a base island 102 and multiple inner and outer rings of pins arranged on the front of the metal substrate 101. The multiple rings of pins are arranged around the base island 102. The multiple rings of pins include a circle of inner pins 103 and at least one circle of outer pins 104. The inner pins 103 are closest to the base island 102. The QFN lead frame 1 has a stepped structure. The base island 102 and the inner pin surface 1031 are in the same plane. The base island 102, the inner pin surface 1031 and the outer pin surface 1041 are not in the same plane, and the outer pin surface 1041 is higher than the base island 102 and the inner pin surface 1031.

[0038] The high-strength metal substrate 101 is made of copper or copper alloy, such as C7025 alloy. The metal substrate 101 in the present invention is a copper strip with a thickness of 0.1-0.2 mm.

[0039] In this embodiment, the metal substrate 101 (using a copper strip as an example) is first chemically cleaned (acid or alkaline), ultrasonically cleaned, and rinsed with deionized water to remove grease, oxides, and impurities from the copper strip's surface, ensuring a clean surface. A photoresist dry film is then laminated onto the copper strip's surface to serve as a mask for subsequent pattern transfer. Ultraviolet light is then transmitted through a mask (photoresist plate) to expose the dry film, transferring the circuit pattern onto the film (the unexposed portions are soluble). An alkaline solution dissolves the unexposed dry film, exposing the copper areas to be etched and forming the circuit pattern. An acidic etchant dissolves the exposed copper, retaining the circuit pattern protected by the dry film. The remaining dry film is removed with an alkaline solution, resulting in a preliminarily formed copper lead frame structure. The dry film is laminated again to prepare for subsequent selective silver plating. The exposure and development steps are repeated to expose only the pads and lead areas to be silver-plated. Silver (Ag) is electroplated, typically to a thickness of 1-5 μm, to improve the solderability and conductivity of the island 102 pads and lead pads. Non-exposed areas are protected with a dry film. The dry film is removed, completing the selectively silver-plated leadframe, which includes the island 102 and multiple rings of leads. In this embodiment, a single ring of outer leads 104 is used as an example. An inner ring of leads 103 and an outer ring of leads 104 surround the island 102, with the inner leads 103 closest to the island 102. A high-precision die is used to stamp the copper strip to form the individual QFN leadframes 1, with positioning holes and the outline punched out.

[0040] This embodiment differs from conventional leadframe stamping in that, during the stamping process, the base island 102 and inner lead 103 regions are stamped downward from the front to the back of the QFN leadframe 1, forming a stepped structure between the inner leads 103 and outer leads 104 of the QFN leadframe 1. Specifically, the stamping process stamps the base island 102 and inner lead 103 regions of the leadframe downward by a certain distance, typically 1-5 mm.

[0041] The structure and distribution of the inner pins 103 and the outer pins 104 of the QFN lead frame 1 in this embodiment make the pin distribution more uniform. When the lead frame is used to prepare a QFN package structure, the pins are no longer limited to the edges of the package structure, which can improve the flexibility of the package structure in application and provide more options for the design of electronic devices.

[0042] This embodiment uses a process combining etching and stamping to manufacture the QFN lead frame 1. The inner pins 103 and the base island 102 are stamped by stamping, so that the inner pins 103 and the base island 102 area are lower than the outer pins 104 area, forming a step shape, thereby providing a support frame for the new QFN packaging structure. By changing the manufacturing process of the lead frame and adopting a combination of etching and stamping, not only the production efficiency is improved, but also the production cost is reduced, which makes it possible to make large-scale production.

[0043] Example 2

[0044] This embodiment discloses a QFN packaging structure, the structural diagram of which is shown in FIG. Figure 3 and Figure 4 As shown. It includes the QFN lead frame 1 prepared in Example 1. Specifically, a semiconductor chip 2 is mounted on the base island 102 of the QFN lead frame 1. After the semiconductor chip 2 is electrically connected to the inner pins 103 and the outer pins 104 via the leads 3, the semiconductor chip 2 and the leads 3 are plastic-encapsulated to form a plastic-encapsulated portion 4, thereby forming a QFN package structure with a stepped structure.

[0045] The semiconductor chip 2 may be adhered to the base island 102 of the lead frame by means of a conductive adhesive, or may be electrically connected to the pads of the base island 102 by means of the leads 3 .

[0046] The plastic packaging material may be epoxy molding compound (EMC), which can effectively protect the circuit structure inside the packaging structure.

[0047] The exposed pins in the QFN package structure are electroplated with tin or tin alloy to enhance the oxidation resistance and welding performance of the package structure.

[0048] The main production process for the QFN package structure includes die placement, wire bonding, mold lamination, encapsulation, film removal, tinning, cutting, and packaging. The packaging process is largely similar to the industry standard. In this embodiment, the customized encapsulation mold is first laminated, and the semi-finished package with wire bonding is then placed on the laminated mold for encapsulation. This overcomes the limitation of traditional frames requiring lamination parallel to the frame surface to prevent overflow. After injection molding, the film paper is separated from the lead frame.

[0049] The QFN package structure in this embodiment adopts a lead frame with an upper and lower double-layer pin structure, breaking the limitation of traditional package solder joints that are only on the same plane, making the pin distribution more uniform and no longer limited to the edges of the package structure. It effectively increases the internal wiring space and solder joint distribution space of the chip, improves the integration of the package structure, and significantly improves the flexibility of the package structure in application, providing the possibility of realizing more complex wiring design and providing more options for the design of electronic equipment.

[0050] The entire process flow chart of Example 1 and Example 2 of the present invention is as follows Figure 5 As shown in the figure, the process flow of QFN packaging structure includes: raw materials - pre-cleaning - pressing dry film - exposure - development - etching - film stripping - pressing dry film - exposure - development - silver plating - film stripping - stamping - mounting - wire bonding - encapsulation - tinning; finally cutting and packaging.

[0051] The QFN packaging structure in this embodiment has a stepped structure in appearance. This structure increases the heat dissipation area of ​​the chip. Through the upper and lower layers of pin structures, a multi-level heat dissipation network is formed, which greatly improves the heat dissipation efficiency and effectively meets the heat dissipation requirements of large-size chip packaging structures.

[0052] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other variations and improvements can be made without departing from the creative concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A method for preparing a QFN lead frame, characterized in that: The method comprises the following steps: S1. Provide a high-strength metal substrate and use a chemical etching process to form a base island and multiple rings of pins on the front of the metal substrate. The multiple rings of pins are arranged around the base island. The multiple rings of pins include an inner ring of pins and at least one outer ring of pins. The inner pins are closest to the base island. S2. stamping the metal substrate to form an independent QFN lead frame; in the stamping process, the base island and the inner lead area are stamped downward from the front side to the back side of the QFN lead frame, so that the QFN lead frame has a stepped structure; The base island and the inner pin surface are in the same plane, the base island, the inner pin surface and the outer pin surface are not in the same plane, and the outer pin surface is higher than the base island and the inner pin surface; The base island is used to mount a semiconductor chip. After the semiconductor chip is electrically connected to the inner pins and the outer pins through leads, the semiconductor chip and the leads are plastic-sealed to form a plastic-sealed portion, thereby forming a QFN package structure with a stepped structure. The inner pins and outer pins form an upper and lower pin structure, which increases the internal wiring space and solder joint distribution space of the semiconductor chip and also forms a multi-level heat dissipation network.

2. The method according to claim 1, characterized in that The punching distance is 1-5 mm.

3. The method according to claim 2, characterized in that The outer pins are arranged in a circle.

4. The method according to claim 3, characterized in that The metal substrate is made of copper or copper alloy.

5. A QFN lead frame, prepared according to the method according to any one of claims 1 to 4, characterized in that: It includes a metal substrate and a base island and multiple inner and outer rings of pins arranged on the front side of the metal substrate. The multiple rings of pins are arranged around the base island. The multiple rings of pins include one inner ring of pins and at least one outer ring of pins. The inner pins are closest to the base island. The QFN lead frame has a stepped structure. The base island and the inner pin surfaces are in the same plane. The base island, the inner pin surfaces and the outer pin surfaces are not in the same plane, and the outer pin surfaces are higher than the base island and the inner pin surfaces.

6. A QFN package structure, comprising the QFN lead frame according to claim 5, characterized in that: A semiconductor chip is mounted on the base island of the QFN lead frame, and after the semiconductor chip is electrically connected to the inner pins and outer pins through leads, the semiconductor chip and leads are plastic-encapsulated to form a plastic-encapsulated portion, thereby forming a QFN package structure with a stepped structure.

7. The QFN package structure according to claim 6, wherein: Electroplating of tin or tin alloy is performed on the exposed leads of the QFN package structure.

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