Semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, and the method comprises the steps: employing a ceramic packaging core plate as a basic support, forming a first groove in a ceramic substrate, forming a first through hole below the first groove, enabling the front surface of a first chip to be downward, and enabling the first chip to be embedded into the first groove, a first through hole is formed in the first chip, bonding connection with the first chip is achieved through a first metal layer in the first through hole, the wiring density and the integration degree are improved, a multi-layer added layer structure is formed, a second groove is formed in an outer added layer, a second chip is embedded in the second groove, metal columns are formed on an upper wiring structure, and a third chip is connected with the metal columns in a bonding mode. According to the preparation method, 3D integration of multiple chips and a ceramic core plate system is realized, the problem of buckling deformation of a high-lamination-number packaging substrate is effectively solved, the heat-conducting property of the packaging structure is remarkably improved, meanwhile, the chips are embedded into the ceramic core plate, the wiring density is improved, and the reliability of the packaging structure is improved. The integration level and the performance of the ceramic core plate structure are greatly improved through multi-chip packaging.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology towards high power, high integration, and miniaturization, packaging substrates are simultaneously facing the dual challenges of heat dissipation and structural stability. On the one hand, the working power consumption of high-power devices such as AI chips and high-performance computing processors continues to climb, resulting in a sharp increase in the heat flux density per unit area. On the other hand, to meet the requirements of higher integration, advanced packaging technologies generally adopt a multi-layer stacked structure of 14-20 layers and miniaturize metal lines to the level of 2μm - 8μm. This high-density interconnect structure not only significantly increases the thermal resistance, making it more difficult to timely export heat, but also generates greater thermo-mechanical stress due to the difference in the coefficient of thermal expansion (CTE) between different materials during temperature changes. This requires that the new generation of packaging substrates must achieve a breakthrough balance between high thermal conductivity and excellent dimensional stability. It is necessary to use high-thermal-conductivity medium materials to improve the heat dissipation efficiency, and at the same time, optimize the core board structure and material formula to enhance mechanical rigidity and reduce thermal deformation. Summary of the Invention

[0003] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor packaging structure and a preparation method thereof, which are used to solve the problems of warping deformation and insufficient thermal conductivity of high-stack-layer packaging substrates in the prior art.

[0004] To achieve the above object and other related objects, the present invention provides a preparation method of a semiconductor packaging structure, and the preparation method includes:

[0005] S1, providing a ceramic packaging core board, the ceramic packaging core board includes a ceramic substrate, the ceramic substrate has opposite front and back surfaces, and the ceramic packaging core board further includes at least one first groove formed at a preset position on the front surface of the ceramic substrate and a plurality of first through holes penetrating the ceramic substrate from a preset position at the bottom of the first groove;

[0006] S2, forming a first metal layer filling the first through holes;

[0007] S3, forming a plurality of second through holes penetrating the ceramic substrate;

[0008] S4, embedding the first chip to be packaged face down into the first groove, and the first chip is bonded to the first metal layer through first bumps on the front surface;

[0009] S5, forming a first dielectric layer filling the second through holes and covering the front and back surfaces of the obtained structure;

[0010] S6, form a third through-hole penetrating the first dielectric layer, and form a micro-blind hole penetrating the first dielectric layer on the back surface of the obtained structure and exposing the surface of the first metal layer;

[0011] S7, form a second metal layer that fills the third through-hole and the micro-blind hole and covers the front and back surfaces of the obtained structure;

[0012] S8, use a photolithography process to etch the second metal layer, retaining the second metal layer in the third through-hole and at preset regions at both ends thereof, and the second metal layer in the micro-blind hole and at preset regions below it;

[0013] S9, form at least one additional layer on each of the front and back surfaces of the obtained structure, the additional layer being electrically connected to the second metal layer, and the outer additional layer in the additional layer includes a second dielectric layer and a third metal layer;

[0014] S10, form at least one second groove at a preset position in the second dielectric layer on the front surface of the obtained structure;

[0015] S11, embed the second chip to be encapsulated with its front side facing up into the second groove, and the front surface of the second chip has second bumps;

[0016] S12, form an upper wiring structure on the front surface of the obtained structure, the upper wiring structure includes a third dielectric layer and a fourth metal layer, and the fourth metal layer is electrically connected to the second bumps and the additional layer; form a lower wiring structure on the back surface of the obtained structure, the lower wiring structure includes a fourth dielectric layer and a fifth metal layer, and the fifth metal layer is electrically connected to the additional layer;

[0017] S13, form a plurality of metal pillars on the fourth metal layer;

[0018] S14, bond the third chip to be encapsulated to the metal pillars.

[0019] Optionally, in step S13, the method of forming a plurality of metal pillars on the fourth metal layer includes:

[0020] S131, form a first solder mask layer covering the front surface of the obtained structure;

[0021] S132, form a plurality of metal pillars that penetrate the first solder mask layer and are in contact connection with the fourth metal layer;

[0022] In step S13, it further includes the steps of forming a second solder mask layer on the back surface of the obtained structure and performing an opening process on the second solder mask layer to expose the surface of the fifth metal layer to form a solder pad;

[0023] After step S13, it further includes the step of implanting solder balls on the solder pad.

[0024] Optionally, the ceramic encapsulation core board is formed by a multi-layer co-fired ceramic process, and the ceramic encapsulation core board further includes at least one metal layer embedded in the ceramic substrate.

[0025] Optionally, the ceramic encapsulation core board is formed by a 3D printing process or a laser drilling process.

[0026] Optionally, the material of the ceramic substrate is Al2O3, AlN or Si3N4.

[0027] Optionally, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are all ABF.

[0028] Optionally, in step S2, the method for forming the first metal layer filling the first through hole includes:

[0029] S21, forming a first seed layer on the side wall of the first through hole, the bottom wall and the side wall of the first groove, and the surface of the ceramic substrate;

[0030] S22, forming a first metal layer filling the first through hole;

[0031] S23, removing the first seed layer and the first metal layer outside the first through hole.

[0032] Optionally, in step S5, a first dielectric layer filling the second through hole and covering the front and back surfaces of the obtained structure is formed by a vacuum hot pressing process.

[0033] Optionally, in step S7, the method for forming a second metal layer filling the third through hole and the micro blind hole and covering the front and back surfaces of the obtained structure includes:

[0034] S71, depositing a second seed layer on the side wall of the third through hole, the side wall and the bottom wall of the micro blind hole, and the surface of the first dielectric layer;

[0035] S72, forming a second metal layer filling the third through hole and the micro blind hole and covering the front and back surfaces of the obtained structure by an electroplating process.

[0036] The present invention also provides a semiconductor package structure, which is prepared by using the preparation method of the semiconductor package structure described in any one of the above, and the semiconductor package structure includes:

[0037] A ceramic encapsulation core board having opposite front and back surfaces;

[0038] A first chip embedded face-down in the front surface of the ceramic encapsulation core board;

[0039] At least one build-up layer formed on the front and back of the ceramic package core board, the build-up layer including an outer build-up layer located on the outside, and the build-up layer being electrically connected to the first chip;

[0040] A second chip embedded in the outer build-up layer on the front;

[0041] An upper wiring structure formed above the second chip and the outer build-up layer on the front, the upper wiring structure being electrically connected to the second chip and the build-up layer;

[0042] A lower wiring structure formed below the outer build-up layer on the back, the lower wiring structure being electrically connected to the build-up layer;

[0043] A plurality of metal posts in contact connection with the upper wiring structure;

[0044] A third chip bonded to the metal posts.

[0045] As described above, the semiconductor package structure and its manufacturing method of the present invention have the following beneficial effects: By using a ceramic package core board as a basic support, forming a first groove on the ceramic substrate and a first through hole below it, embedding the first chip face down into the first groove, and realizing the bonding connection with the first chip through the first metal layer in the first through hole, the wiring density and integration are improved. By forming a multi-layer build-up structure, the number of wiring layers is increased, meeting the requirements of high-performance processors for high-stack packaging. A second groove is set in the build-up layer and the second chip is embedded to further improve the wiring structure. Finally, metal posts are formed on the upper wiring structure and the third chip is bonded to the metal posts. This manufacturing method realizes the 3D integration of multiple chips and the ceramic core board system, effectively solves the warping deformation problem of the high-stack number packaging substrate, significantly improves the thermal conductivity of the package structure, and at the same time embeds chips on the ceramic core board to increase the wiring density. Through multi-chip packaging, the integration and performance of the ceramic core board structure are greatly improved, meeting the requirements of modern semiconductor devices for high power, high frequency and high integration, and greatly improving the overall performance and stability of the semiconductor package. Description of the Drawings

[0046] Figure 1 It shows a schematic flow chart of the manufacturing method of the semiconductor package structure of the present invention.

[0047] Figures 2 to 20 It shows a schematic structural diagram presented by each step of the manufacturing method of the semiconductor package structure of the present invention.

[0048] Description of Component Labels

[0049] 10 Ceramic package core board

[0050] 11 Ceramic substrate

[0051] 111 Front side

[0052] 112 Back side

[0053] 12 First through-hole

[0054] 13 First groove

[0055] 14 Metal layer

[0056] 15 First seed layer

[0057] 16 First metal layer

[0058] 17 Second through-hole

[0059] 18 First chip

[0060] 19 First bump

[0061] 191 Filling layer

[0062] 20 First dielectric layer

[0063] 21 Third through-hole

[0064] 22 Micro blind via

[0065] 23 Second seed layer

[0066] 24 Second metal layer

[0067] 25 Three-layer build-up

[0068] 26 Outer build-up

[0069] 261 Second dielectric layer

[0070] 262 Third metal layer

[0071] 27 Second groove

[0072] 28 Second chip

[0073] 29 Second bump

[0074] 30 Chip bonding film

[0075] 31 Upper wiring structure

[0076] 311 Third dielectric layer

[0077] 312 Fourth metal layer

[0078] 32 Lower wiring structure

[0079] 321 Fourth dielectric layer

[0080] 322 Fifth metal layer

[0081] 33 First solder mask layer

[0082] 34 Metal posts

[0083] 35 Second solder mask layer

[0084] 36 Pad

[0085] 37 Third chip

[0086] 38 Second bump

[0087] 39 Surface treatment layer

[0088] 40 Solder ball

[0089] Steps S1 to S14 Specific implementation manners

[0090] The following uses specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0091] Please refer to Figures 1 to 20 . It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0092] This embodiment provides a method for manufacturing a semiconductor packaging structure, as Figure 1 shown. The manufacturing method includes:

[0093] S1. Provide a ceramic packaging core board, where the ceramic packaging core board includes a ceramic substrate, the ceramic substrate has opposite front and back surfaces, and the ceramic packaging core board further includes at least one first groove formed at a preset position on the front surface of the ceramic substrate and a plurality of first through holes penetrating the ceramic substrate from a preset position at the bottom of the first groove;

[0094] S2. Form a first metal layer filling the first through holes;

[0095] S3. Form a plurality of second through holes penetrating the ceramic substrate;

[0096] S4, embed the first chip to be encapsulated face - down into the first groove, and bond - connect the first chip to the first metal layer through the first bumps on the front face;

[0097] S5, form a first dielectric layer that fills the second through - hole and covers the front and back of the obtained structure;

[0098] S6, form a third through - hole penetrating the first dielectric layer, and form a micro - blind hole penetrating the first dielectric layer on the back of the obtained structure and exposing the surface of the first metal layer;

[0099] S7, form a second metal layer that fills the third through - hole and the micro - blind hole and covers the front and back of the obtained structure;

[0100] S8, use a photolithography process to etch the second metal layer, retaining the second metal layer in the third through - hole and its two preset regions at both ends, and the second metal layer in the micro - blind hole and its preset region below;

[0101] S9, form at least one build - up layer on the front and back of the obtained structure, the build - up layer is electrically connected to the second metal layer, and the outer build - up layer in the build - up layer includes a second dielectric layer and a third metal layer;

[0102] S10, form at least one second groove at a preset position in the second dielectric layer on the front of the obtained structure;

[0103] S11, embed the second chip to be encapsulated face - up into the second groove, and the front face of the second chip has second bumps;

[0104] S12, form an upper - layer wiring structure on the front of the obtained structure, the upper - layer wiring structure includes a third dielectric layer and a fourth metal layer, and the fourth metal layer is electrically connected to the second bumps and the build - up layer; form a lower - layer wiring structure on the back of the obtained structure, the lower - layer wiring structure includes a fourth dielectric layer and a fifth metal layer, and the fifth metal layer is electrically connected to the build - up layer;

[0105] S13, form a number of metal pillars on the fourth metal layer;

[0106] S14, bond - connect the third chip to be encapsulated to the metal pillars.

[0107] The manufacturing method of the semiconductor packaging structure of this embodiment uses a ceramic packaging core board as the basic support, forms a first groove on the ceramic substrate and a first through hole below it, embeds the first chip face down into the first groove, and realizes the bonding connection with the first chip through the first metal layer in the first through hole, improving the wiring density and integration. By forming a multi-layer build-up structure, the number of wiring layers is increased, meeting the requirements of high-performance processors for high-stack packaging. A second groove is set in the build-up to embed the second chip, further improving the wiring structure. Finally, metal pillars are formed on the upper wiring structure and the third chip is bonded to the metal pillars. This manufacturing method realizes the 3D integration of multiple chips and the ceramic core board system, effectively solves the warping deformation problem of the high-stack number packaging substrate, significantly improves the thermal conductivity of the packaging structure, and at the same time embeds chips on the ceramic core board to increase the wiring density. Through multi-chip packaging, the integration and performance of the ceramic core board structure are greatly improved, meeting the requirements of modern semiconductor devices for high power, high frequency, and high integration, and greatly improving the overall performance and stability of semiconductor packaging.

[0108] The following will describe in detail the manufacturing method of the semiconductor packaging structure of this embodiment with reference to specific drawings.

[0109] As Figure 2 and Figure 3 shown, first, step S1 is carried out to provide a ceramic packaging core board 10. The ceramic packaging core board 10 includes a ceramic substrate 11, the ceramic substrate 11 has opposite front face 111 and back face 112, and the ceramic packaging core board 10 further includes at least one first groove 13 formed at a preset position on the front face 111 of the ceramic substrate 11 and a plurality of first through holes 12 penetrating the ceramic substrate 11 from a preset position at the bottom of the first groove 13.

[0110] The ceramic substrate 11 is a kind of inorganic packaging substrate. Its higher hardness compared with the organic packaging substrate makes it have less warping under the high-stack structure. In the integrated circuit lithography process, less warping means a higher tolerance for the depth of focus of the lithography system, thus avoiding problems such as insufficient lithography energy or out-of-tolerance dimensions of ultra-fine lines caused by defocusing due to the surface undulation of the substrate in a high-resolution lithography system. At the same time, the ceramic substrate 11 has good thermal expansion coefficient matching with the copper foil, which can effectively avoid thermal stress caused by temperature difference and ensure the stability of the packaging structure. In addition, the thermal conductivity of the ceramic substrate 11 is at least 40 times that of the organic packaging substrate. In high-performance computing processors, excellent thermal conductivity can avoid problems such as frequency reduction caused by excessive temperature during long-term high-frequency operation of the processor, resulting in a decline in processor performance and interruption of application services.

[0111] As an example, the ceramic encapsulation core board 10 can be formed by a 3D printing process or a laser drilling process, and the formed structure is as Figure 2 shown; alternatively, the ceramic encapsulation core board 10 can be formed by a multi-layer co-fired ceramic process. The ceramic encapsulation core board 10 further includes at least one metal layer 14 embedded in the ceramic substrate 11, and the formed structure is as Figure 3 shown. In this embodiment, the structure of the ceramic encapsulation core board 10 as shown in Figure 2 is taken as an example to illustrate the preparation method of the subsequent semiconductor encapsulation structure.

[0112] Further, as an example, the multi-layer co-fired ceramic process includes, but is not limited to, a high-temperature calcined ceramic process (HTCC), a low-temperature calcined ceramic process (LTCC), and an active metal brazed ceramic substrate process (AMB). The material of the metal layer 14 includes, but is not limited to, tungsten, tungsten-molybdenum alloy, and molybdenum-manganese alloy, and preferably tungsten. Tungsten can be used as a thermal barrier layer to reduce the direct thermal shock of high temperature to the ceramic substrate 11, and the thermal expansion coefficients of ceramic and tungsten are relatively close. By designing the tungsten layer, the interfacial stress can be reduced, and delamination or cracking can be avoided.

[0113] As an example, the material of the ceramic substrate 11 can be alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4). The thickness of the ceramic substrate 11 can be 200 μm to 5 mm, and its material and thickness can be selected according to specific functions and application scenarios, and no excessive limitation is made here.

[0114] It should be noted here that the front and back of the structures obtained in the subsequent steps of the preparation method of the semiconductor encapsulation structure in this embodiment are both defined based on the opposite front 111 and back 112 of the ceramic substrate 11.

[0115] As Figure 6 shown, then step S2 is carried out to form a first metal layer 16 filling the first through hole 12.

[0116] As a specific example, the method for forming the first metal layer 16 filling the first through hole 12 includes:

[0117] S21, as Figure 4 shown, a first seed layer 15 is formed on the side wall of the first through hole 12, the bottom wall and side wall of the first groove 13, and the surface of the ceramic substrate 11 by, for example, electroless copper plating, physical vapor deposition, or plasma-enhanced atomic layer deposition process. The first seed layer 15 can be one or more than two metal layers, preferably a single copper layer, or more than two metal layers with the upper metal layer being a copper layer. The thickness of the copper layer is preferably 0.5 μm to 1.0 μm.

[0118] S22, asFigure 5 As shown, a first metal layer 16 filling the first through hole 12 is formed by, for example, an electroplating process or a process of filling a metal conductive adhesive.

[0119] S23, as Figure 6 As shown, the first seed layer 15 and the first metal layer 16 outside the first through hole 12 are removed by, for example, an excimer laser etching process or a plasma etching process.

[0120] As Figure 7 As shown, then step S3 is carried out to form a plurality of second through holes 17 penetrating the ceramic substrate 11.

[0121] As an example, the second through holes 17 can be formed by a process including but not limited to laser (picosecond or femtosecond) drilling.

[0122] As Figure 8 As shown, then step S4 is carried out to embed the first chip 18 to be encapsulated face down into the first groove 13, and the first chip 18 is bonded to the first metal layer 16 through the first bumps 19 on the front side.

[0123] As an example, a thermocompression bonding process is used to realize the bonding connection between the first bumps 19 and the first metal layer 16 to form an interconnection with high precision, high strength and high reliability.

[0124] As an example, the size of the first groove 13 formed in step S1 is slightly larger than the size of the first chip 18 to facilitate embedding the first chip 18 into the first groove 13.

[0125] As an example, as Figure 8 As shown, a filling layer 191 is formed between the front side of the first chip 18 and the first groove 13. The material of the filling layer 191 is, for example, an insulating material such as a non-conductive thin film or a non-conductive paste, which provides additional mechanical support for the first chip 18, prevents the first chip 18 from being damaged by physical impact during use, and can avoid short-circuit faults of the first chip 18.

[0126] As Figure 9 As shown, then step S5 is carried out to form a first dielectric layer 20 filling the second through holes 17 and covering the front and back sides of the obtained structure.

[0127] As a preferred example, a vacuum hot pressing process is used to form the first dielectric layer 20 that fills the second through-hole 17 and covers the front and back surfaces of the obtained structure, improving the filling quality while enhancing the interface bonding strength. Preferably, in this embodiment, the first dielectric layer 20 is an ABF (Ajinomoto Build-up Film) to achieve fine wiring, improve the input / output pin (I / O) density and wiring flexibility of the packaging structure. The thickness of the first dielectric layer 20 can be exemplarily 20 μm to 1 mm, which can be set according to actual needs and is not overly restricted here.

[0128] As Figure 10 shown, then step S6 is carried out to form a third through-hole 21 penetrating the first dielectric layer 20 and a micro blind hole 22 penetrating the back surface of the obtained structure and exposing the surface of the first metal layer 16.

[0129] As an example, a CO2 laser drilling process or a UV laser drilling process can be used to form the third through-hole 21 and the micro blind hole 22 to achieve precise aperture control, meet the requirements of different aperture ranges of the third through-hole 21 and the micro blind hole 22, ensure dimensional accuracy and consistency, and meet the requirements of semiconductor packaging for fine structures and reliable performance. The cross-sectional diameter of the formed third through-hole 21 is exemplarily 100 μm to 1 mm, and the cross-sectional diameter of the micro blind hole 20 is exemplarily 10 μm to 500 μm.

[0130] As Figure 12 shown, then step S7 is carried out to form a second metal layer 24 that fills the third through-hole 21 and the micro blind hole 22 and covers the front and back surfaces of the obtained structure.

[0131] As a specific example, as Figure 11 and Figure 12 shown, the method for forming a second metal layer 24 that fills the third through-hole 21 and the micro blind hole 22 and covers the front and back surfaces of the obtained structure includes:

[0132] S71, as Figure 11 shown, exemplarily, a second seed layer 23 is deposited on the sidewalls of the third through-hole 21, the sidewalls and bottom wall of the micro blind hole 22, and the surface of the first dielectric layer 20 by a chemical copper plating process, a physical vapor deposition process, or a plasma-enhanced atomic layer deposition process. The second seed layer 23 can be one or more metal layers. Preferably, a single copper layer is used, or two or more metal layers with the upper metal layer being a copper layer. The thickness of the copper layer is preferably 0.5 μm to 1.0 μm.

[0133] S72, as Figure 12As shown, a second metal layer 24 that fills the third through-hole 21 and the micro blind via 22 and covers the front and back surfaces of the obtained structure is formed by an electroplating process. The second metal layer 24 is preferably an electroplated copper layer, and the thickness of the second metal layer 24 covering the front and back surfaces of the obtained structure is exemplarily 10 μm to 1 mm.

[0134] As Figure 13 shown, then step S8 is performed. The second metal layer 24 is etched by a photolithography process, and the second metal layer 24 in the third through-hole 21 and the preset areas at both ends thereof, and the second metal layer 24 in the micro blind via 22 and the preset areas below thereof are retained. It should be noted here that the retained second metal layer 24 in this step is not limited to the above areas, and also exists in other circuit areas of the semiconductor package structure ( Figure 13 not shown).

[0135] As an example, when etching the second metal layer 24 by a photolithography process, it further includes steps of thinning and planarizing the surface of the second metal layer 24 to reduce the difficulty of the photolithography process and improve the film formation quality.

[0136] As Figure 14 shown, then step S9 is performed. At least one build-up layer is formed on the front and back surfaces of the obtained structure. The build-up layer is electrically connected to the second metal layer 24. The outer build-up layer 26 in the build-up layer includes a second dielectric layer 261 and a third metal layer 262.

[0137] As an example, the build-up layer includes a build-up dielectric layer and a build-up metal layer. Preferably, a build-up seed layer is formed below the build-up metal layer.

[0138] As an example, the production of the build-up layer can be completed through processes such as laminating the build-up dielectric layer, laser drilling, desmearing, plating through hole (PTH), pasting dry film, exposure, development, electroplating, stripping, and flash etching, and the above process flow is repeated according to the target stack structure number. As Figure 14 shown, in this embodiment, three build-up layers 25 are formed on the front and back surfaces of the structure as an example for display. It should be noted that the build-up layer located on the outermost layer of the structure as Figure 14 shown is the outer build-up layer 26. Preferably, in this embodiment, the build-up dielectric layer (including the second dielectric layer 261) is ABF to achieve fine wiring, improve I / O density and wiring flexibility.

[0139] As Figure 15 shown, then step S10 is performed. At least one second groove 27 is formed at a preset position in the second dielectric layer 261 on the front surface of the obtained structure by using, for example, a laser grooving process.

[0140] AsFigure 16 As shown, the next step is to perform step S11 , embedding the second chip 28 to be packaged into the second groove 27 with the front side facing upward, and the front side of the second chip 28 has a second bump 29 .

[0141] As an example, the size of the second groove 27 formed in step S10 is slightly larger than the size of the second chip 28 , so as to facilitate embedding the second chip 28 into the second groove 27 .

[0142] like Figure 17 As shown, step S12 is then performed to form an upper wiring structure 31 on the front side of the obtained structure, wherein the upper wiring structure 31 includes a third dielectric layer 311 and a fourth metal layer 312, and the fourth metal layer 312 is electrically connected to the second bump 29 and the build-up layer; and a lower wiring structure 32 is formed on the back side of the obtained structure, wherein the lower wiring structure 32 includes a fourth dielectric layer 321 and a fifth metal layer 322, and the fifth metal layer 322 is electrically connected to the build-up layer.

[0143] As an example, the third dielectric layer 311 and the fourth dielectric layer 321 are both ABF to achieve refined wiring and improve input / output pin (I / O) density and wiring flexibility.

[0144] As an example, the upper wiring structure 31 and the lower wiring structure 32 can be manufactured by laminating dielectric layers, laser drilling, Desmear, PTH, dry film lamination, exposure, development, electroplating, film stripping and flash etching.

[0145] like Figure 18 As shown, step S13 is then performed to form a plurality of metal pillars 34 on the fourth metal layer 312 .

[0146] As a preferred example, a method of forming a plurality of metal pillars 34 on the fourth metal layer 312 includes:

[0147] S131, forming a first solder resist layer 33 covering the front side of the obtained structure.

[0148] S132 , forming a plurality of metal pillars 34 penetrating the first solder resist layer 33 and contacting and connecting with the fourth metal layer 312 . The metal pillars 34 can be formed by electroplating copper, nickel or tin, for example.

[0149] Step S13 exemplarily also includes forming a second solder resist layer 35 on the back side of the obtained structure, and performing window processing on the second solder resist layer 35 to expose the surface of the fifth metal layer 322 to form a pad 36 .

[0150] As a further example, in step S131, the first solder mask layer 33 and the through holes with preset sizes can be formed through processes such as solder mask coating, solder mask exposure, solder mask development, and solder mask opening. Among them, the method of solder mask opening can be, for example, ultraviolet (UV) opening to improve the opening accuracy. In step S132, copper is electroplated in the through holes to form the metal posts 34; the second solder mask layer 35 and the pads 36 can be formed through processes such as solder mask coating, solder mask exposure, and solder mask development.

[0151] As a further example, as Figure 19 shown, after forming the second solder mask layer 35 on the back surface of the obtained structure and performing a windowing process on the second solder mask layer 35 to expose the surface of the fifth metal layer 322, it further includes a step of surface treating the fifth metal layer 322 to form a surface treatment layer 39.

[0152] As a further example, the fifth metal layer 322 can be surface treated by using an ENEPIG (electroless nickel electroless palladium immersion gold) process, an OSP (organic solderability preservative) process, or an ENIG (electroless nickel immersion gold) process to improve the welding performance of the pads 36 and prevent oxidation and corrosion.

[0153] As Figure 20 shown, then step S14 is carried out, and the third chip 37 to be encapsulated is bonded and connected to the metal posts 34.

[0154] Specifically, the third chip 37 is thermocompression bonded to the metal posts 34 through the third bumps 38 on the front surface to form a high-precision, high-strength, and high-reliability interconnection.

[0155] As an example, as Figure 20 shown, after step S13, it further includes a step of implanting solder balls 40 on the pads 36.

[0156] As a further example, the solder balls 40 can be formed by using a solder paste printing process or a ball implantation process, and the formed solder balls 40 are tin balls, which are used to realize the contact connection between the packaging structure and the PCB (Printed Circuit Board).

[0157] So far, the preparation of the semiconductor packaging structure of this embodiment is completed, and the formed semiconductor packaging structure is as Figure 16 shown.

[0158] This embodiment also provides a semiconductor packaging structure, as Figure 20 shown. This semiconductor packaging structure can be prepared by using the above-mentioned preparation method of the semiconductor packaging structure, but it is not limited thereto, and other suitable preparation methods can also be used. The semiconductor packaging structure includes:

[0159] A ceramic package core board 10, the ceramic package core board 10 having opposite front and back sides;

[0160] A first chip 18 embedded face - down in the front side of the ceramic package core board 10;

[0161] At least one build - up layer formed on the front and back sides of the ceramic package core board 10, the build - up layer including an outer build - up layer 26 on the outside, the build - up layer being electrically connected to the first chip 18;

[0162] A second chip 28 embedded in the outer build - up layer 26 on the front side;

[0163] An upper wiring structure 31 formed above the second chip 28 and the outer build - up layer 26 on the front side, the upper wiring structure 31 being electrically connected to the second chip 28 and the build - up layer;

[0164] A lower wiring structure 32 formed below the outer build - up layer 26 on the back side, the lower wiring structure 32 being electrically connected to the build - up layer;

[0165] A plurality of metal pillars 34 in contact connection with the upper wiring structure 31;

[0166] A third chip 37 bonded to the metal pillars 34.

[0167] For the semiconductor package structure of this embodiment, by using a ceramic package core board as the basic support, embedding a first chip inside it, and forming a multi - layer build - up structure including an outer build - up layer, an upper wiring structure and a lower wiring structure, the wiring density and integration degree are significantly improved. By embedding a second chip into the outer build - up layer and forming an upper wiring structure electrically connected to the build - up layer, the packaging efficiency is further optimized. Then, by bonding the metal pillars to the third chip, the high - density integration and high - reliability interconnection of multiple chips are completed. This structure effectively solves the warping deformation and heat dissipation problems of high - stack - layer packaging substrates, significantly improves the thermal conductivity and integration degree of the packaging structure, and meets the requirements of modern semiconductor devices for high power, high frequency and high integration.

[0168] As an example, as Figure 20 shown, the semiconductor package structure further includes:

[0169] A first solder mask layer 33 covering the upper wiring structure 31, the metal pillars 34 passing through the first solder mask layer 33 and being in contact connection with the upper wiring structure 31;

[0170] A second solder mask layer 35 covering the lower wiring structure 32, and pads 36 formed by opening windows in the second solder mask layer 35;

[0171] Solder balls 40 planted on the pads 36.

[0172] As an example, such as Figure 20 shown, in this embodiment, three layers of build-up layers 25 are formed on the front and back of the structure as an example for display. The actual number of build-up layers can be designed in a stacked manner according to requirements, and no excessive restrictions are imposed here.

[0173] As an example, for the beneficial effects that can be achieved by the semiconductor packaging structure of this embodiment, reference can be made to the specific description in the manufacturing method, and details will not be elaborated here.

[0174] In summary, for the semiconductor packaging structure and its manufacturing method of the present invention, by using a ceramic packaging core board as the basic support, forming a first groove on the ceramic substrate and a first through hole below it, embedding the first chip face down into the first groove, and realizing the bonding connection with the first chip through the first metal layer in the first through hole, the wiring density and integration degree are improved. By forming a multi-layer build-up structure, the number of wiring layers is increased, meeting the requirements of high-performance processors for high-stack packaging. A second groove is set in the build-up layer and the second chip is embedded to further improve the wiring structure. Finally, metal pillars are formed on the upper-layer wiring structure and the third chip is bonded to the metal pillars. This manufacturing method realizes the 3D integration of multiple chips and the ceramic core board system, effectively solves the warping deformation problem of the high-stack number packaging substrate, significantly improves the thermal conductivity of the packaging structure, and at the same time embeds chips on the ceramic core board to increase the wiring density. Through multi-chip packaging, the integration degree and performance of the ceramic core board structure are greatly improved, meeting the requirements of modern semiconductor devices for high power, high frequency, and high integration degree, and greatly improving the overall performance and stability of semiconductor packaging. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0175] The above embodiments are only used to illustrate the principles and effects of the present invention, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor packaging structure, characterized in that, The preparation method includes: S1. Provide a ceramic packaging core board, which includes a ceramic substrate having opposite front and back surfaces. The ceramic packaging core board further includes at least one first groove formed at a preset position on the front surface of the ceramic substrate and a plurality of first through holes penetrating the ceramic substrate from a preset position at the bottom of the first groove; S2. Form a first metal layer filling the first through holes; S3. Form a plurality of second through holes penetrating the ceramic substrate; S4. Embed the first chip to be packaged with its front side facing down into the first groove. The first chip is bonded to the first metal layer through first bumps on the front side; S5. Form a first dielectric layer filling the second through holes and covering the front and back surfaces of the obtained structure; S6. Form a third through hole penetrating the first dielectric layer, and form a micro blind hole penetrating the first dielectric layer on the back surface of the obtained structure and exposing the surface of the first metal layer; S7. Form a second metal layer filling the third through hole and the micro blind hole and covering the front and back surfaces of the obtained structure; S8. Use a photolithography process to etch the second metal layer, and retain the second metal layer in the third through hole and its preset regions at both ends, and the second metal layer in the micro blind hole and its preset regions below; S9. Form at least one layer of build-up layer on each of the front and back surfaces of the obtained structure. The build-up layer is electrically connected to the second metal layer. The outer build-up layer in the build-up layer includes a second dielectric layer and a third metal layer; S10. Form at least one second groove at a preset position in the second dielectric layer on the front surface of the obtained structure; S11. Embed the second chip to be packaged with its front side facing up into the second groove. The front surface of the second chip has second bumps; S12. Form an upper wiring structure on the front surface of the obtained structure. The upper wiring structure includes a third dielectric layer and a fourth metal layer. The fourth metal layer is electrically connected to the second bumps and the build-up layer; form a lower wiring structure on the back surface of the obtained structure. The lower wiring structure includes a fourth dielectric layer and a fifth metal layer. The fifth metal layer is electrically connected to the build-up layer; S13. Form a plurality of metal pillars on the fourth metal layer; S14. Bond the third chip to be packaged to the metal pillars.

2. The manufacturing method of the semiconductor package structure according to claim 1, wherein: In step S13, the method of forming a plurality of metal pillars on the fourth metal layer includes: S131. Form a first solder mask layer covering the front surface of the obtained structure; S132. Form a plurality of metal pillars penetrating the first solder mask layer and in contact connection with the fourth metal layer; In step S13, it further includes the steps of forming a second solder mask layer on the back surface of the obtained structure and performing an opening process on the second solder mask layer to expose the surface of the fifth metal layer to form a solder pad; After step S13, it further includes the step of implanting solder balls on the solder pad.

3. The manufacturing method of the semiconductor package structure according to claim 1, characterized in that: The ceramic packaging core board is formed by a multi-layer co-fired ceramic process. The ceramic packaging core board further includes at least one layer of metal layer embedded in the ceramic substrate.

4. The manufacturing method of the semiconductor package structure according to claim 1, characterized in that: The ceramic packaging core board is formed by a 3D printing process or a laser drilling process.

5. The method for manufacturing a semiconductor package structure according to claim 1, wherein: The material of the ceramic substrate is Al2O3, AlN or Si3N4.

6. The manufacturing method of the semiconductor package structure according to claim 1, wherein: The first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are all ABF.

7. The method for manufacturing a semiconductor package structure according to claim 1, wherein: In step S2, the method for forming the first metal layer filling the first through hole includes: S21, forming a first seed layer on the sidewall of the first through hole, the bottom wall and the sidewall of the first groove, and the surface of the ceramic substrate; S22, forming a first metal layer filling the first through hole; S23, removing the first seed layer and the first metal layer outside the first through hole.

8. The method for manufacturing the semiconductor package structure according to claim 1, wherein: In step S5, a first dielectric layer filling the second through hole and covering the front and back surfaces of the obtained structure is formed by a vacuum hot pressing process.

9. The method for manufacturing a semiconductor package structure according to claim 1, wherein In step S7, the method for forming a second metal layer filling the third through hole and the micro blind hole and covering the front and back surfaces of the obtained structure includes: S71, depositing a second seed layer on the sidewall of the third through hole, the sidewall and the bottom wall of the micro blind hole, and the surface of the first dielectric layer; S72, forming a second metal layer filling the third through hole and the micro blind hole and covering the front and back surfaces of the obtained structure by an electroplating process.

10. A semiconductor package structure, characterized in that, Prepared by using the preparation method of the semiconductor packaging structure according to any one of claims 1 to 9, the semiconductor packaging structure includes: A ceramic packaging core board having opposite front and back surfaces; A first chip embedded face-down in the front surface of the ceramic packaging core board; At least one build-up layer formed on the front and back surfaces of the ceramic packaging core board, the build-up layer includes an outer build-up layer located on the outside, and the build-up layer is electrically connected to the first chip; A second chip embedded in the outer build-up layer on the front surface; An upper wiring structure formed above the second chip and the outer build-up layer on the front surface, and the upper wiring structure is electrically connected to the second chip and the build-up layer; A lower wiring structure formed below the outer build-up layer on the back surface, and the lower wiring structure is electrically connected to the build-up layer; A plurality of metal pillars in contact connection with the upper wiring structure; A third chip bonded to the metal pillars.

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