High-density chip packaging structure and preparation method thereof

Abstract

The invention provides a high-density chip packaging structure and a preparation method thereof, and relates to the technical field of semiconductors, the high-density chip packaging structure comprises a first substrate, a first chip, a second chip, a third chip, a chip stacking module and a plastic package body, a first heat dissipation column is arranged on the first substrate, the back face of the third chip is arranged on the first heat dissipation column, and a second heat dissipation column is arranged on the second substrate; and the front surface of the second chip is also provided with a second heat dissipation column. The chip stacking module is stacked on the second chip and the third chip, and the bottom side of the chip stacking module is provided with a first conductive column and a second conductive column. Compared with the prior art, the first conductive columns and the second conductive columns are designed on the chip stacking module in advance, modular packaging is adopted, and the stacking density and the packaging integration degree can be greatly improved. Moreover, through the arrangement of the first heat dissipation column and the second heat dissipation column, the heat dissipation effect of the whole structure can be greatly improved, the binding force between the plastic package body and the chip is improved, and the structural stability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a high-density chip packaging structure and a method for manufacturing the same. Background Art

[0002] With the rapid development of the semiconductor industry, the existing multi-chip packaging stacking technology integrates chips by forming metal posts on a substrate and then stacking the chips again. Due to process limitations, the integration degree and chip stacking density of the existing multi-chip packaging stacking technology are relatively low, resulting in an overly large overall occupied space and being unfavorable for the miniaturization of the packaging structure.

[0003] In addition, for the existing stacked packaging structure, as the number of stacked chips increases, the generated heat increases, and the existing heat dissipation structure is difficult to meet the heat dissipation requirements, resulting in a relatively poor overall heat dissipation effect. Summary of the Invention

[0004] The object of the present invention is to provide a high-density chip packaging structure and a method for manufacturing the same, which can adopt a modular stacking structure, greatly improve the stacking density and packaging integration degree, and at the same time, greatly improve the stacking heat dissipation effect.

[0005] In one aspect, an embodiment of the present invention provides a high-density chip packaging structure, including: A first substrate, on which a first heat dissipation post is provided; A first chip, the front surface of which is attached to one side of the first substrate where the first heat dissipation post is provided, and is spaced apart from the first heat dissipation post; A second chip, the back surface of which is attached to the back surface of the first chip, and a second heat dissipation post is further provided on the front surface of the second chip; A third chip, the back surface of which is disposed on the first heat dissipation post and the second heat dissipation post, and one side edge region of the third chip corresponds to the back surface of the second chip, and a first photosensitive region is further provided on the other side edge region of the front surface of the third chip; A chip stacking module, which is stacked on the second chip and the third chip, and a first conductive post and a second conductive post are provided on the bottom side of the chip stacking module, the first conductive post is connected to the front surface of the second chip, and the second conductive post is connected to the front surface of the third chip; A plastic package, which is disposed on the first substrate and covers the first chip, the second chip, the third chip and the chip stacking module; Among them, the plastic package is also provided with a first photosensitive channel corresponding to the first photosensitive area, and the chip stacking module is also provided with a first photosensitive port corresponding to the first photosensitive area. The first photosensitive port corresponds to the first photosensitive channel and exposes the first photosensitive area.

[0006] In some preferred embodiments, the chip stacking module comprises: a second substrate; a fourth chip, wherein a front surface of the fourth chip is attached to one side of the second substrate; a fifth chip, wherein the back side of the fifth chip is attached to the back side of the fourth chip, and the front side of the fifth chip is provided with the second conductive column and the third heat dissipation column, and the fifth chip is electrically connected to the third chip through the second conductive column; a sixth chip, wherein the back side of the sixth chip is attached to an end of the third heat dissipation column away from the fifth chip, and the first conductive column is further disposed on the front side of the sixth chip, and the sixth chip is electrically connected to the second chip through the first conductive column; The fourth chip, the fifth chip and the sixth chip are all staggered with respect to the first photosensitive area, and the first photosensitive port is arranged at an edge of the first substrate.

[0007] In some preferred embodiments, the chip stacking module also includes a first cylinder, which is arranged on one side of the second substrate and surrounds the first photosensitive port, one end of the first cylinder away from the second substrate is connected to the front of the third chip and surrounds the first photosensitive area, and the plastic package is wrapped around the outer periphery of the first cylinder to form the first photosensitive channel in the first cylinder.

[0008] In some preferred embodiments, a first transparent adhesive layer is further provided at one end of the first cylinder close to the second substrate, the first transparent adhesive layer covers the first photosensitive port, and the first cylinder is fixed to the second substrate through the first transparent adhesive layer.

[0009] In some preferred embodiments, a third conductive column is further disposed on the back side of the sixth chip, and the third conductive column is connected to the front side of the third chip, so that the sixth chip is electrically connected to the third chip.

[0010] In some preferred embodiments, a fiber optic module is further provided in the first photosensitive channel, the plastic package body is wrapped around the fiber optic module, one end of the fiber optic module is connected to the first photosensitive area, and the other end is exposed from the plastic package body.

[0011] In some preferred embodiments, a first encapsulation layer is provided between the first chip and the first substrate, the first encapsulation layer is spaced from the first heat dissipation posts, and a second encapsulation layer is provided between the fourth chip and the second substrate.

[0012] In some preferred embodiments, the projections of the first chip, the second chip, the fourth chip, and the fifth chip on the first substrate overlap, and the projections of the third chip and the seventh chip on the first substrate partially overlap.

[0013] In some preferred embodiments, a first adhesive film layer is provided on the back surface of the first chip, and the back surface of the first chip and the back surface of the second chip are bonded together through the first adhesive film layer; a second adhesive film layer is provided on the back surface of the fourth chip, and the back surface of the fourth chip and the back surface of the fifth chip are bonded together through the second adhesive film layer.

[0014] In some preferred embodiments, the high-density chip packaging structure further includes a stacked wiring layer, the stacked wiring layer is disposed on a surface of the plastic package away from the first substrate and is connected to the second substrate, and the first photosensitive opening is exposed outside the stacked wiring layer.

[0015] In some preferred embodiments, a seventh chip is further attached to the back surface of the sixth chip, the plastic package covers the seventh chip, the front surface of the seventh chip faces away from the sixth chip and is provided with fourth conductive posts, the stacked wiring layer partially covers the side wall of the second substrate, and the fourth conductive posts are connected to the stacked wiring layer so that the seventh chip is electrically connected to the stacked wiring layer through the fourth conductive posts.

[0016] In some preferred embodiments, the high-density chip packaging structure further includes an eighth chip and a ninth chip, the eighth chip and the ninth chip are spaced and attached to a side of the stacked wiring layer away from the plastic package, and a third encapsulation layer is further provided on a side of the stacked wiring layer away from the plastic package, and the third encapsulation layer covers the periphery of the eighth chip and the ninth chip.

[0017] In some preferred embodiments, a second photosensitive area is further provided on the front surface of the sixth chip, a second photosensitive channel is further provided in the plastic package, a second photosensitive opening is further provided in the stacked wiring layer, one end of the second photosensitive channel is joined to the second photosensitive area, and the other end is joined to the second photosensitive opening.

[0018] In some preferred embodiments, a second cylinder is provided on the front surface of the sixth chip. One end of the second cylinder is joined around the second photosensitive area, and a second transparent adhesive layer is provided at the other end of the second cylinder. The second transparent adhesive layer covers the second photosensitive opening. The encapsulant is wrapped around the second cylinder, and a second photosensitive channel is formed inside the second cylinder.

[0019] In some preferred embodiments, the second cylinder is joined to the surface of the first substrate, and a reflection module is provided inside the second cylinder. The reflection module is provided at the bent portion of the second cylinder.

[0020] In a second aspect, an embodiment of the present invention provides a method for manufacturing a high-density chip packaging structure for manufacturing the aforementioned high-density chip packaging structure. The manufacturing method includes: Providing a first substrate; Forming a first heat dissipation pillar on the first substrate; Attaching the front surface of the first chip to the first substrate, and attaching the back surface of the second chip to the back surface of the first chip; Forming a second heat dissipation pillar on the front surface of the second chip, where the second heat dissipation pillar is flush with the first heat dissipation pillar; Attaching the back surface of the third chip to the first heat dissipation pillar and the second heat dissipation pillar, where one side edge area of the third chip corresponds to the back surface of the second chip, and a first photosensitive area is further provided on the other side edge area of the front surface of the third chip; Stacking the chip stacking module on the second chip and the third chip. Wherein, a first conductive pillar and a second conductive pillar are provided on the bottom side of the chip stacking module. The first conductive pillar is connected to the front surface of the second chip, and the second conductive pillar is connected to the front surface of the third chip; Forming an encapsulant on the surface of the substrate, and the encapsulant wraps the first chip, the second chip, the third chip, the first heat dissipation pillar, the second heat dissipation pillar, and the chip stacking module; Wherein, a first photosensitive channel corresponding to the first photosensitive area is further provided on the encapsulant, and a first photosensitive opening corresponding to the first photosensitive area is also provided on the chip stacking module. The first photosensitive opening corresponds to the first photosensitive channel and exposes the first photosensitive area.

[0021] The beneficial effects of the embodiments of the present invention include: The high-density chip packaging structure and its manufacturing method provided by the embodiments of the present invention attach the front side of the first chip to the first substrate, attach the back side of the second chip to the back side of the first chip, arrange the first heat dissipation column on the first substrate and at intervals on one side of the first chip, arrange the back side of the third chip on the first heat dissipation column, and one side edge of the third chip corresponds to the back side of the second chip. On the other side edge of the back side of the third chip, a first photosensitive area is also arranged, and on the front side of the second chip, a second heat dissipation column is also arranged, and the second heat dissipation column can support the second chip. The chip stacking module is stacked on the second chip and the third chip, and on the bottom side of the chip stacking module, a first conductive column and a second conductive column are arranged. The first conductive column is connected to the second chip, and the second conductive column is connected to the third chip. The plastic package is arranged on the first substrate and covers the first chip, the second chip, the third chip, the first heat dissipation column, the second heat dissipation column, and the chip stacking module. Compared with the prior art, in the present invention, the first conductive column and the second conductive column are designed on the chip stacking module in advance, and the electrical connection between the chip stacking module and the second chip and the third chip is realized through the first conductive column and the second conductive column. Adopting modular packaging can greatly improve the stacking density and packaging integration degree. Moreover, the arrangement of the first heat dissipation column and the second heat dissipation column can greatly improve the heat dissipation effect of the overall structure, and improve the bonding force between the plastic package and the chip, and improve the structural stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 Schematic diagram of the first high-density chip packaging structure provided by the embodiments of the present invention; Figure 2 is Figure 1 structural schematic diagram of the chip stacking module in Figure 3 Schematic diagram of the second high-density chip packaging structure provided by the embodiments of the present invention; Figure 4a Schematic diagram of the third high-density chip packaging structure provided by the embodiments of the present invention; Figure 4b Schematic diagram of the fourth high-density chip packaging structure provided by the embodiments of the present invention; Figure 5 Schematic diagram of the fifth high-density chip packaging structure provided by the embodiments of the present invention; Figures 6 to 15Process flow chart of the preparation method of the high-density chip packaging structure provided by the embodiment of the present invention; Figures 16 to 19 is Figure 1 The process flow chart of the preparation of the chip stacking module in

[0024] Icons: 100 - High-density chip packaging structure; 110 - First substrate; 111 - First heat dissipation column; 120 - First chip; 121 - First glue filling layer; 122 - Second glue filling layer; 123 - First glue film layer; 124 - Second glue film layer; 130 - Second chip; 131 - Second heat dissipation column; 140 - Third chip; 141 - First photosensitive area; 142 - Second photosensitive area; 150 - Chip stacking module; 151 - First photosensitive port; 152 - First photosensitive channel; 1521 - Optical fiber module; 153 - Second substrate; 154 - Fourth chip; 155 - Fifth chip; 1551 - Third heat dissipation column; 156 - Sixth chip; 1561 - Third conductive column; 157 - First conductive column; 158 - Second conductive column; 159 - First cylinder; 1591 - First transparent glue layer; 160 - Plastic package; 170 - Stacked wiring layer; 171 - Seventh chip; 172 - Fourth conductive column; 173 - Third glue film layer; 174 - Third glue filling layer; 1741 - Colloid flow channel; 175 - Second photosensitive port; 176 - Second cylinder; 1761 - Leg; 177 - Second transparent glue layer; 178 - Reflection module; 179 - Second photosensitive channel; 180 - Eighth chip; 190 - Ninth chip. Detailed implementation manners

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0027] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0028] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0029] In addition, if terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0030] As disclosed in the background art, in the multi-chip stacking packaging technology in the prior art, its stacking density is relatively low. For conductive pillars, usually, metal pillars are electroplated on the surface of the substrate wiring layer first, and then plastic encapsulation is carried out, and then the grinding process is carried out to expose the metal pillars. However, during the grinding process, the metal pillars are easily subjected to shear force, resulting in cracks at the bottom of the metal pillars and the chip pads, thereby causing problems such as electrical failure.

[0031] Moreover, in the existing stacking packaging structure, the increase in the number of stacked chips leads to an increase in heat generation, and the existing heat dissipation structure is difficult to meet the heat dissipation requirements, resulting in a relatively poor overall heat dissipation effect. At the same time, since the chips mostly adopt a regular vertical stacking method, the bonding force between the plastic encapsulation body and the chips after plastic encapsulation is relatively poor, and the overall structural stability is relatively poor.

[0032] Furthermore, silicon-photonics (SiPh) technology mainly uses laser beams to transmit data instead of electronic signals, and combines optical and electronic components into an independent microchip to improve the communication propagation speed. Using light as the information conduction medium on a silicon wafer can achieve better data transmission performance than traditional optical fibers and reduce energy consumption. However, this method places increasingly stringent requirements on the silicon photon chip packaging process. The traditional packaging process mainly forms an avoidance area (i.e., an optical channel) by laser grooving, and exposes the optical processing part of the silicon photon to the plastic encapsulation body to achieve optical signal transmission. Using laser grooving is bound to have an impact on the optical processing part of the silicon photon, and may cause laser breakdown of the optical processing part, affecting the device performance. Moreover, laser grooving is also prone to generating plastic encapsulation body particles, which cannot be removed by the water washing process, resulting in the particles affecting the structural layer in the optical processing part area during removal, thereby damaging the optical processing part and causing damage.

[0033] To solve the above problems, the embodiments of the present invention provide a novel high-density chip packaging structure and its preparation method. It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0034] An embodiment of the present invention provides a high-density chip packaging structure and a preparation method thereof. A modular stacking structure can be adopted to avoid exposing the metal posts between chips by a grinding process, thereby avoiding problems such as pad cracks and even electrical failures caused by grinding the metal posts. At the same time, the stacking heat dissipation effect can be significantly improved, the bonding force between the plastic package and the chips can be improved, and laser grooving to form an optical channel can be avoided, and the negative effects brought by laser grooving can be solved.

[0035] Referring to Figure 1 and Figure 2 , an embodiment of the present invention provides a high-density chip packaging structure 100, including a first substrate 110, a first chip 120, a second chip 130, a third chip 140, a chip stacking module 150, and a plastic package 160. A first heat dissipation post 111 is provided on the first substrate 110; the front surface of the first chip 120 is attached to one side of the first substrate 110 where the first heat dissipation post 111 is provided and is spaced apart from the first heat dissipation post 111; the back surface of the second chip 130 is attached to the back surface of the first chip 120, and a second heat dissipation post 131 is further provided on the front surface of the second chip 130; the back surface of the third chip 140 is disposed on the first heat dissipation post 111 and the second heat dissipation post 131, and one side edge region of the third chip 140 corresponds to the back surface of the second chip 130, and a first photosensitive region 141 is further provided on the other side edge region of the front surface of the third chip 140; the chip stacking module 150 is stacked on the second chip 130 and the third chip 140, and a first conductive post 157 and a second conductive post 158 are provided on the bottom side of the chip stacking module 150. The first conductive post 157 is connected to the front surface of the second chip 130, and the second conductive post 158 is connected to the front surface of the third chip 140; the plastic package 160 is disposed on the first substrate 110 and covers the first chip 120, the second chip 130, the third chip 140, and the chip stacking module 150; wherein, a first photosensitive channel 152 corresponding to the first photosensitive region 141 is further provided on the plastic package 160, and a first photosensitive port 151 corresponding to the first photosensitive region 141 is also provided on the chip stacking module 150. The first photosensitive port 151 corresponds to the first photosensitive channel 152 and exposes the first photosensitive region 141.

[0036] In the embodiment of the present invention, the front surface of the first chip 120 is attached to the first substrate 110, the back surface of the second chip 130 is attached to the back surface of the first chip 120, the first heat dissipation column 111 is disposed on the first substrate 110 and is spaced apart on one side of the first chip 120, the back surface of the third chip 140 is disposed on the first heat dissipation column 111, and one side edge of the third chip 140 corresponds to the back surface of the second chip 130. A first photosensitive area 141 is further disposed on the other side edge of the back surface of the third chip 140, and a second heat dissipation column 131 is further disposed on the front surface of the second chip 130. The second heat dissipation column 131 can support the second chip 130. The chip stacking module 150 is stacked on the second chip 130 and the third chip 140, and a first conductive column 157 and a second conductive column 158 are disposed on the bottom side of the chip stacking module 150. The first conductive column 157 is connected to the second chip 130, and the second conductive column 158 is connected to the third chip 140. The encapsulant 160 is disposed on the first substrate 110 and covers the first chip 120, the second chip 130, the third chip 140, the first heat dissipation column 111, the second heat dissipation column 131, and the chip stacking module 150. Wherein, the first conductive column 157 and the second conductive column 158 can be pre-designed on the chip stacking module 150, and the electrical connection between the chip stacking module and the second chip 130 and the third chip 140 is realized through the first conductive column 157 and the second conductive column 158. The solution that the metal columns between chips in the traditional process need to be exposed through the grinding process is avoided, thereby avoiding the problems of pad cracks and even electrical failures caused by grinding the metal columns. Moreover, the setting of the first heat dissipation column 111 and the second heat dissipation column 131 can greatly improve the heat dissipation effect of the overall structure, and improve the bonding force between the encapsulant 160 and the chips, and improve the structural stability.

[0037] It should be noted that both the first heat dissipation column 111 and the second heat dissipation column 131 are multiple. The multiple first heat dissipation columns 111 are formed on the first substrate 110 through wire bonding technology and extend upward. The multiple second heat dissipation columns 131 can be disposed on the front surface of the second chip 130, and the tops of the multiple first heat dissipation columns 111 and the multiple second heat dissipation columns 131 are flush, and can jointly support the third chip 140.

[0038] In some embodiments, the chip stacking module includes a second substrate 153, a fourth chip 154, a fifth chip 155, and a sixth chip 156. The second substrate 153 is opposite to the first substrate 110 and is spaced apart. The front side of the fourth chip 154 is attached to one side of the second substrate 153. The back side of the fifth chip 155 is attached to the back side of the fourth chip 154. A second conductive column 158 is disposed on the front side of the fifth chip 155. The fifth chip 155 is electrically connected to the third chip 140 through the second conductive column 158. The third heat dissipation column 1551 is arranged on the front side of the fifth chip 155; the back side of the sixth chip 156 is attached to the end of the third heat dissipation column 1551 away from the fifth chip 155, and the front side of the sixth chip 156 is also provided with a first conductive column 157, and the sixth chip 156 is electrically connected to the second chip 130 through the first conductive column 157; wherein the fourth chip 154, the fifth chip 155, and the sixth chip 156 are all staggered with the first photosensitive area 141, and the first photosensitive port 151 is arranged at the edge of the first substrate 110.

[0039] It should be noted that the chip stacking module is prepared separately here, and the fourth chip 154, the fifth chip 155 and the sixth chip 156 can be mounted on the second substrate 153 in sequence, and the first conductive column 157 and the second conductive column 158 can be prepared. Finally, the chip stacking module is mounted on the second chip 130 and the third chip 140 to complete the chip stacking. In addition, the third chip 140 is a photosensitive chip, and its first photosensitive area 141 is located in the edge area, and is staggered with the fourth chip 154, the fifth chip 155 and the sixth chip 156, so that the fourth chip 154, the fifth chip 155 and the sixth chip 156 can be effectively prevented from interfering with the first photosensitive area 141, and the first photosensitive port 151 is ensured to be directly opposite to the first photosensitive area 141.

[0040] In some embodiments, the chip stack module further includes a first cylinder 159. The first cylinder 159 is disposed on one side of the second substrate 153 and surrounds the first photosensitive opening 151. One end of the first cylinder 159 away from the second substrate 153 is connected to the front surface of the third chip 140 and surrounds the first photosensitive area 141. The encapsulant 160 is coated around the first cylinder 159 to form a first photosensitive channel 152 inside the first cylinder 159. Specifically, the first cylinder 159 is made of a light-shielding material, which can achieve sidewall light shielding and avoid the diffraction effect of light from affecting the normal light incident on the first photosensitive area 141. Moreover, through the first cylinder 159, the structure of the first photosensitive channel 152 can be made more stable, and the encapsulant can be prevented from entering the first photosensitive channel 152 during encapsulation, thereby affecting the normal photosensitivity of the first photosensitive area 141. In addition, using the first cylinder 159 to surround and form the first photosensitive channel 152 can avoid the solution of exposing the photosensitive area by laser grooving in the conventional technology, avoid laser damage to the photosensitive area, and at the same time avoid the influence of the particulate matter generated by laser grooving.

[0041] In some embodiments, a first transparent adhesive layer 1591 is further disposed at one end of the first cylinder 159 close to the second substrate 153. The first transparent adhesive layer 1591 covers the first photosensitive opening 151, and the first cylinder 159 is fixed to the second substrate 153 through the first transparent adhesive layer 1591. Specifically, the first transparent adhesive layer 1591 can achieve light transmission and cover the bottom end of the first photosensitive opening 151, so as to isolate the photosensitive opening and the first photosensitive channel 152 while ensuring light transmission, and prevent external impurities from entering the first photosensitive channel 152 and affecting the first photosensitive area 141.

[0042] In some embodiments, a third conductive pillar 1561 is further disposed on the back surface of the sixth chip 156. The third conductive pillar 1561 is connected to the front surface of the third chip 140 to electrically connect the sixth chip 156 and the third chip 140. By providing the third conductive pillar 1561, a direct electrical connection between the third chip 140 and the sixth chip 156 can be achieved. At the same time, the third conductive pillar 1561 can also play a role in supporting the sixth chip 156. Among them, the third heat dissipation pillar 1551, the first conductive pillar 157, the second conductive pillar 158, and the third conductive pillar 1561 can all be copper pillars, which can connect the sixth chip 156, the third chip 140, the second chip 130, and the fifth chip 155 into a whole, improving the overall structural stability.

[0043] It should be noted that here the third chip 140 is a silicon photonics chip, the sixth chip 156 can be a memory chip, both the third chip 140 and the sixth chip 156 can form bridge chips, and the third conductive pillar 1561 is used to realize the interconnection between the bridge chips, so that the overall electrical connection characteristics are better.

[0044] Furthermore, the projections of the first chip 120, the second chip 130, the fourth chip 154, and the fifth chip 155 on the first substrate 110 overlap, and the projections of the third chip 140 and the seventh chip 171 on the first substrate 110 partially overlap. Specifically, the second chip 130 is disposed back-to-back with the first chip 120, the fourth chip 154 and the fifth chip 155 are disposed back-to-back, the third chip 140 is disposed on the flank of the second chip 130, and the seventh chip 171 is disposed on the flank of the fifth chip 155, thereby realizing flank stacking. Compared with the face-to-face stacking process, flank stacking can reduce the height of the heat dissipation metal posts, thereby improving the chip stacking integration.

[0045] In some embodiments, a first glue filling layer 121 is disposed between the first chip 120 and the first substrate 110, and the first glue filling layer 121 is spaced apart from the first heat dissipation post 111. A second glue filling layer 122 is disposed between the fourth chip 154 and the second substrate 153. Specifically, the first chip 120 is flip-chip bonded to the first substrate 110, and the fourth chip 154 is flip-chip bonded to the second substrate 153. The first glue filling layer 121 can protect the welding structure of the first chip 120, and the second glue filling layer 122 can protect the welding structure of the fourth chip 154, thereby ensuring the welding reliability.

[0046] It should be noted that in the embodiments of the present invention, the front side of the chip mentioned refers to the side surface of the chip with bumps, which has electrical connection characteristics. And the back side of the chip refers to the side surface of the chip without bumps, which does not have electrical connection characteristics.

[0047] In some embodiments, a first glue film layer 123 is disposed on the back side of the first chip 120, and the back side of the first chip 120 and the back side of the second chip 130 are bonded together through the first glue film layer 123; a second glue film layer 124 is disposed on the back side of the fourth chip 154, and the back side of the fourth chip 154 and the back side of the fifth chip 155 are bonded together through the second glue film layer 124. Among them, the first chip 120 and the second chip 130 are bonded back-to-back and bonded through the first glue film layer 123. At the same time, the fourth chip 154 and the fifth chip 155 are bonded back-to-back and bonded and fixed through the second glue film layer 124. Among them, the first chip 120 and the second chip 130 have the same width, and the fourth chip 154 and the fifth chip 155 have the same width.

[0048] In some embodiments, the high-density chip packaging structure 100 further includes a stacked wiring layer 170. The stacked wiring layer 170 is disposed on the surface of the plastic package 160 away from the first substrate, and is connected to the second substrate 153, and the first photosensitive opening 151 is exposed from the stacked wiring layer 170. Among them, in the embodiments of the present invention, wiring structures are provided in both the first substrate 110 and the second substrate 153. The stacked wiring layer 170 is disposed on the surface of the plastic package 160 and is in electrical contact with the wiring structure in the second substrate 153, so that the stacked wiring layer 170 is electrically connected to the second substrate 153.

[0049] It should be noted that here the stacked wiring layer 170 does not cover the first photosensitive opening 151, but exposes the first photosensitive opening 151, so as to avoid the interference of the stacked wiring layer 170 on the light incident on the first photosensitive area 141. Preferably, the stacked wiring layer 170 and the second substrate 153 are arranged in a relatively staggered manner, so that the part of the stacked wiring layer 170 away from the first photosensitive opening 151 can directly correspond to the plastic package 160, and the first photosensitive opening 151 on the second substrate 153 can also be arranged in a misaligned manner with the stacked wiring layer 170 and exposed.

[0050] Furthermore, a seventh chip 171 is also attached to the back surface of the sixth chip 156. The plastic package 160 covers the seventh chip 171. The front surface of the seventh chip 171 faces away from the sixth chip 156 and is provided with a fourth conductive pillar 172. The fourth conductive pillar 172 is connected to the stacked wiring layer 170, so that the seventh chip 171 is electrically connected to the stacked wiring layer 170 through the fourth conductive pillar 172. Specifically, the fourth conductive pillar 172 extends upward to the wiring structure in the stacked wiring layer 170, so that the seventh chip 171 is electrically connected to the stacked wiring layer 170 through the fourth conductive pillar 172. Among them, the seventh chip 171 is disposed on the side edge of the sixth chip 156 away from the fifth chip 155, that is, disposed at the flank position of the sixth chip 156. On the one hand, it can increase the number of chips and improve the overall integration, and on the other hand, it can balance the structural stress of the sixth chip 156 and avoid the warping phenomenon of the sixth chip 156.

[0051] It is worth noting that here a third adhesive film layer 173 is provided on the back surface of the sixth chip 156. The third adhesive film layer 173 can realize the bonding of the seventh chip 171, so as to play a role in fixing the seventh chip 171.

[0052] In some embodiments, the high-density chip packaging structure 100 further includes an eighth chip 180 and a ninth chip 190. The eighth chip 180 and the ninth chip 190 are adhesively attached to the side of the stacked wiring layer 170 away from the plastic package 160 at intervals. A third encapsulation layer 174 is further provided on the side of the stacked wiring layer 170 away from the plastic package 160. The third encapsulation layer 174 covers the periphery of the eighth chip 180 and the ninth chip 190. Specifically, both the eighth chip 180 and the ninth chip 190 are flip chips, and both the eighth chip 180 and the ninth chip 190 are in electrical contact with the wiring structure in the stacked wiring layer 170. By providing the eighth chip 180 and the ninth chip 190, the stacking density and integration can be further improved. The third encapsulation layer 174 can effectively protect the welding structures of the eighth chip 180 and the ninth chip 190 and ensure the structural stability.

[0053] See Figure 3 , in some preferred embodiments, a notch can be left during plastic encapsulation to form a first photosensitive channel 152, and a notch is also formed at the edge of the second substrate 153 of the chip stacking module to form a first photosensitive opening 151 to avoid the first photosensitive channel 152. During actual plastic encapsulation, die encapsulation is achieved through the improvement of the plastic encapsulation process, so that neither the first photosensitive channel 152 nor the second photosensitive opening 175 is filled with plastic encapsulation material, and notches are formed at the edges, and the side wall of the third chip 140 is flush with the side wall of the plastic package 160, facilitating the first photosensitive channel 152 and the first photosensitive opening 151 to be directly conducted to the first photosensitive area 141, that is, the first photosensitive area 141 is directly exposed outside the plastic package 160.

[0054] See Figure 4a , in some preferred embodiments, an optical fiber module 1521 is further provided in the first photosensitive channel 152. The plastic package 160 covers the periphery of the optical fiber module 1521. One end of the optical fiber module 1521 is joined to the first photosensitive area 141, and the other end is exposed outside the plastic package 160. Specifically, the optical fiber module 1521 can achieve the transmission of light. During actual preparation, the optical fiber module 1521 is filled in the first photosensitive channel 152. The optical fiber module 1521 can be prepared first and then plastic encapsulated to ensure the filling effect. By providing the optical fiber module 1521, the transmission of light can also be achieved and external impurities can be prevented from entering the first photosensitive area 141 and affecting its photosensitive effect.

[0055] It should be noted that the solutions using the first cylinder 159 and the optical fiber module 1521 can both avoid the solution of laser grooving to expose the photosensitive area. Therefore, laser damage to the photosensitive area can be avoided, and at the same time, the particulate matter generated by laser grooving can also be avoided.

[0056] See Figure 4b, in some preferred embodiments, an optical fiber module 1521 is further disposed in the first photosensitive channel 152. The optical fiber module 1521 extends out of the plastic package 160, and one end of the optical fiber module 1521 is joined to the first photosensitive area 141, and the other end is exposed outside the plastic package 160. Specifically, the optical fiber module 1521 can achieve the transmission of light, and the optical fiber module 1521 is disposed at a gap from the second substrate 153 and the stacked wiring layer 170, thereby forming a gap, and the gap can be filled with a third encapsulation layer 174. During actual preparation, the optical fiber module 1521 is partially filled in the first photosensitive channel 152. The optical fiber module can be prepared first, and then plastic encapsulation is carried out. Grooves or protrusions are further provided on the part of the optical fiber module extending out of the plastic package 160, and the grooves or protrusions can improve the bonding force with the plastic package 160. At the same time, the third encapsulation layer 174 can extend to the top surface of the optical fiber module 1521 and cover the grooves or protrusions, which can further improve the bonding force between the third encapsulation layer 174 and the optical fiber module 1521. Moreover, the grooves located on the optical fiber module 1521 can also form a colloid flow channel 1741, which is convenient for the third encapsulation layer 174 to flow sufficiently, so as to ensure the encapsulation effect by using the capillary effect.

[0057] By providing the optical fiber module 1521, the transmission of light can also be achieved, and external impurities can be prevented from entering the first photosensitive area 141 and affecting its photosensitive effect.

[0058] See Figure 5 , in some other preferred embodiments of the present invention, a second photosensitive area 142 is further provided on the front surface of the sixth chip 156. A second photosensitive channel 179 is further provided in the plastic package 160. A second photosensitive port 175 is further provided on the stacked wiring layer 170. One end of the second photosensitive channel 179 is joined to the second photosensitive area 142, and the other end is joined to the second photosensitive port 175. Specifically, both the sixth chip 156 and the third chip 140 are photosensitive chips. A second photosensitive area 142 is provided on the front surface (i.e., the bottom side) of the sixth chip 156. Since the second photosensitive area 142 is opposite to the second photosensitive port 175, the transmission of light is achieved through the bent second photosensitive channel 179. The second photosensitive port 175 is provided on the side edge of the stacked wiring layer 170 away from the first photosensitive port 151, and the photosensitive direction of the second photosensitive port 175 is parallel to the photosensitive direction of the first photosensitive port 151, so as to achieve co-directional photosensitivity.

[0059] Further, a second cylinder body 176 is provided on the front surface of the sixth chip 156. One end of the second cylinder body 176 is joined around the second photosensitive area 142, and a second transparent adhesive layer 177 is provided at the other end of the second cylinder body 176. The second transparent adhesive layer 177 covers the second photosensitive opening 175. The encapsulant 160 is wrapped around the second cylinder body 176, and a second photosensitive channel 179 is formed inside the second cylinder body 176. Specifically, the second cylinder body 176 is bent, and the bottom end of the second cylinder body 176 is joined to the first substrate 110. Therefore, structural support can be achieved through the first substrate 110 to prevent the second cylinder body 176 from falling off. Similarly, during actual preparation, the mounting of the second cylinder body 176 is completed first, so that both ends of the second cylinder body 176 can be respectively surrounded around the second photosensitive area 142 and the second photosensitive opening 175 and fixed through the second transparent adhesive layer 177, and then encapsulation is performed so that the encapsulant can be wrapped around the second cylinder body 176. Here, the second transparent adhesive layer 177 can block the second photosensitive opening 175 and the second cylinder body 176, thereby avoiding the entry of external impurities while ensuring light entry.

[0060] In some embodiments, the second cylinder body 176 is joined to the surface of the first substrate 110, and a reflection module 178 is provided inside the second cylinder body 176. The reflection module 178 is provided at the bent portion of the second cylinder body 176. Specifically, the reflection module 178 can be a reflector, and there can be two of them. The two reflectors are respectively provided at the two bent portions of the second cylinder body 176 to achieve two reflections and ensure that light can be transmitted from the second photosensitive opening 175 to the second photosensitive area 142.

[0061] It should be noted that here, the third chip 140 and the sixth chip 156 can be silicon optical chips, and the interconnection between the silicon optical chips is achieved through the third conductive posts 1561. At the same time, feet 1761 are formed below the second cylinder body 176. The feet 1761 can abut against the surface of the first substrate 110, which can greatly improve the bonding force between the second cylinder body 176 and the encapsulant 160.

[0062] The embodiment of the present invention also provides a preparation method for a high-density chip packaging structure 100 for preparing the aforementioned high-density chip packaging structure 100. The preparation method includes the following steps: S1: Provide a first substrate 110.

[0063] See Figure 6 , specifically, first, the first substrate 110 is prepared. The substrate can be a substrate, a lead frame, a substrate structure made of an organic wiring layer, etc., and pads are provided on the first substrate 110.

[0064] S2: Form a first heat dissipation post 111 on the first substrate 110.

[0065] See Figure 7, specifically, the first heat dissipation column 111 can be formed by wire bonding technology or electroplating method, and the first heat dissipation column 111 can be a copper column.

[0066] S3: Attach the front side of the first chip 120 to the first substrate 110, and attach the back side of the second chip 130 to the back side of the first chip 120.

[0067] See Figure 8 , specifically, after forming the first heat dissipation column 111 by wire bonding, the first chip 120 can be flip-chip bonded to the first substrate 110 first. The flip-chip bumps and pads are mounted through a reflow soldering process, and then glue is applied to form the first glue filling layer 121 to protect the bottom welding structure. Then, a first glue film layer 123 is coated on the back side of the first chip 120, and the second chip 130 is bonded back-to-back to the first chip 120.

[0068] S4: Form a second heat dissipation column 131 on the front side of the second chip 130.

[0069] See Figure 9 , specifically, the second heat dissipation column 131 is flush with the first heat dissipation column 111, and there can be multiple second heat dissipation columns 131.

[0070] S5: Attach the back side of the third chip 140 to the first heat dissipation column 111 and the second heat dissipation column 131.

[0071] See Figure 10 , specifically, one side edge area of the third chip 140 corresponds to the back side of the second chip 130, and a first photosensitive area 141 is also provided on the other side edge area of the front side of the third chip 140. The third chip 140 is mounted in a face-up manner on the second heat dissipation column 131 and the first heat dissipation column 111, and the first heat dissipation column 111 and the second heat dissipation column 131 are used to achieve common support.

[0072] S6: Stack the chip stacking module 150 on the second chip 130 and the third chip 140.

[0073] See Figure 11 , specifically, the bottom side of the chip stacking module 150 is provided with a first conductive column 157 and a second conductive column 158. The first conductive column 157 is connected to the front side of the second chip 130, and the second conductive column 158 is connected to the front side of the third chip 140. Among them, the chip stacking module 150 can be prepared in advance, and at the same time, the first conductive column 157 and the second conductive column 158 can also be prepared in advance on the chip stacking module 150.

[0074] Regarding the chip stacking module 150, its specific preparation process is as follows: See Figure 16, first, a second substrate 153 is provided, and then the mounting of the fourth chip 154 and the fifth chip 155 is completed on the second substrate 153. Among them, the fourth chip 154 is flip-chip bonded to the second substrate 153, and the soldering protection is realized by the second encapsulant layer 122. The fifth chip 155 is bonded back-to-back to the back of the fourth chip 154 through the second film layer 124.

[0075] See Figure 17 , and then the preparation of the second heat dissipation pillar 131 and the second conductive pillar 158 is completed on the front of the fifth chip 155, where the second heat dissipation pillar 131 is lower than the second conductive pillar 158.

[0076] See Figure 18 , and then the first cylinder 159 is mounted. The first cylinder 159 is fixed at the first photosensitive port 151 of the second substrate 153 through the first transparent adhesive layer 1591 and corresponds to the first photosensitive port 151 on the second substrate 153.

[0077] See Figure 19 , and then, the sixth chip 156 is mounted on the second heat dissipation pillar 131. The back of the sixth chip 156 is bonded to the second heat dissipation pillar 131 to achieve support and fixation. The first conductive pillar 157 and the third conductive pillar 1561 are formed on the front of the sixth chip 156, where the third conductive pillar 1561 is lower than the first conductive pillar 157. Finally, the cutting is completed to obtain a single-chip stacked module 150.

[0078] After the chip stacked module 150 is formed, the chip stacked module 150 can be inverted and mounted on the second chip 130 and the third chip 140. Among them, the first conductive pillar 157 is connected to the second chip 130, the second conductive pillar 158 is connected to the third chip 140, and the third conductive pillar 1561 is connected to the third chip 140. At the same time, the first cylinder 159 corresponds to the first photosensitive area 141. Among them, the first photosensitive port 151 corresponding to the first photosensitive area 141 is also provided on the chip stacked module 150. The first photosensitive port 151 corresponds to the first photosensitive channel 152 and exposes the first photosensitive area 141.

[0079] See Figure 12 , it should be noted that after the bonding of the chip stacked module 150 is completed, the mounting of the seventh chip 171 can be completed on the front of the sixth chip 156, and the fourth conductive pillar 172 is formed, and the fourth conductive pillar 172 extends upward.

[0080] S7: A molding body 160 is formed on the surface of the first substrate 110.

[0081] See Figure 13, specifically, the encapsulant 160 encapsulates the first chip 120, the second chip 130, the third chip 140, the first heat dissipation column 111, the second heat dissipation column 131, and the chip stacking module 150. Using the encapsulation process, the encapsulant 160 is formed by encapsulation on the first substrate 110, and the encapsulant 160 can encapsulate the first chip 120, the second chip 130, the third chip 140, the fourth chip 154, the fifth chip 155, and the sixth chip 156 therein. After encapsulation, the encapsulant 160 can be wrapped around the first cylinder 159, so that a first photosensitive channel 152 corresponding to the first photosensitive area 141 is formed in the first cylinder 159.

[0082] Due to the provision of the fourth conductive column 172, the fourth conductive column 172 can be exposed by a conventional thinning process.

[0083] S8: Form a stacked wiring layer 170 on the encapsulant 160.

[0084] See Figure 14 , specifically, through a wiring process, a multi-layer dielectric layer or a multi-layer wiring layer can be formed on the encapsulant 160 to form the stacked wiring layer 170. The stacked wiring layer 170 is directly electrically connected to the second substrate 153 and the fourth conductive column 172.

[0085] S9: Mount the eighth chip 180 and the ninth chip 190 on the stacked wiring layer 170.

[0086] See Figure 15 , specifically, the eighth chip 180 and the ninth chip 190 can be flip-chip bonded to the stacked wiring layer 170, and then glue is applied to form a third glue filling layer 174 to achieve welding protection. Finally, single products are obtained after cutting.

[0087] In summary, for the high-density chip packaging structure 100 and its manufacturing method provided by the embodiments of the present invention, the front side of the first chip 120 is attached to the first substrate 110, the back side of the second chip 130 is attached to the back side of the first chip 120, the first heat dissipation column 111 is disposed on the first substrate 110 and spaced on one side of the first chip 120, the back side of the third chip 140 is disposed on the first heat dissipation column 111, and one side edge of the back side of the third chip 140 corresponds to the back side of the second chip 130. A first photosensitive area 141 is further disposed on the other side edge of the back side of the third chip 140, and a second heat dissipation column 131 is disposed on the front side of the second chip 130. The second heat dissipation column 131 can support the second chip 130. The chip stacking module 150 is stacked on the second chip 130 and the third chip 140, and a first conductive column 157 and a second conductive column 158 are disposed on the bottom side of the chip stacking module 150. The first conductive column 157 is connected to the second chip 130, and the second conductive column 158 is connected to the third chip 140. The encapsulant 160 is disposed on the first substrate 110 and covers the first chip 120, the second chip 130, the third chip 140, the first heat dissipation column 111, the second heat dissipation column 131, and the chip stacking module 150. Compared with the prior art, in the present invention, the first conductive column 157 and the second conductive column 158 are designed on the chip stacking module 150 in advance, and the electrical connection between the chip stacking module and the second chip 130 and the third chip 140 is realized through the first conductive column 157 and the second conductive column 158. The solution that the metal columns between chips in the traditional process need to be exposed through a grinding process is avoided, thereby avoiding the problems of pad cracks and even electrical failures caused by grinding the metal columns. Moreover, the setting of the first heat dissipation column 111 and the second heat dissipation column 131 can greatly improve the heat dissipation effect of the overall structure, and improve the bonding force between the encapsulant 160 and the chips, and improve the structural stability.

[0088] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A high-density chip packaging structure, characterized in that, include: a first substrate, on which a first heat dissipation column is disposed; A first chip, wherein the front side of the first chip is attached to a side of the first substrate where the first heat dissipation column is provided, and the first chip is spaced apart from the first heat dissipation column; A second chip, wherein the back side of the second chip is attached to the back side of the first chip, and a second heat dissipation column is further provided on the front side of the second chip; a third chip, wherein the back side of the third chip is arranged on the first heat dissipation column and the second heat dissipation column, and an edge area on one side of the third chip corresponds to the back side of the second chip, and a first photosensitive area is further arranged on the edge area on the other side of the front side of the third chip; A chip stacking module, wherein the chip stacking module is stacked on the second chip and the third chip, and a first conductive column and a second conductive column are disposed on the bottom side of the chip stacking module, wherein the first conductive column is connected to the front side of the second chip, and the second conductive column is connected to the front side of the third chip; A plastic package, which is disposed on the first substrate and covers the first chip, the second chip, the third chip and the chip stacking module; Among them, the plastic package is also provided with a first photosensitive channel corresponding to the first photosensitive area, and the chip stacking module is also provided with a first photosensitive port corresponding to the first photosensitive area. The first photosensitive port corresponds to the first photosensitive channel and exposes the first photosensitive area.

2. The high-density chip packaging structure according to claim 1, characterized in that, The chip stacking module comprises: a second substrate; a fourth chip, wherein a front surface of the fourth chip is attached to one side of the second substrate; a fifth chip, wherein the back side of the fifth chip is attached to the back side of the fourth chip, and the front side of the fifth chip is provided with the second conductive column and the third heat dissipation column, and the fifth chip is electrically connected to the third chip through the second conductive column; a sixth chip, wherein the back side of the sixth chip is attached to an end of the third heat dissipation column away from the fifth chip, and the first conductive column is further disposed on the front side of the sixth chip, and the sixth chip is electrically connected to the second chip through the first conductive column; The fourth chip, the fifth chip and the sixth chip are all staggered with respect to the first photosensitive area, and the first photosensitive port is arranged at an edge of the first substrate.

3. The high-density chip packaging structure according to claim 2, characterized in that, The chip stacking module also includes a first cylinder, which is arranged on one side of the second substrate and surrounds the first photosensitive port. The end of the first cylinder away from the second substrate is connected to the front of the third chip and surrounds the first photosensitive area. The plastic package is wrapped around the outer periphery of the first cylinder to form the first photosensitive channel in the first cylinder.

4. The high-density chip packaging structure according to claim 3, characterized in that, A first transparent adhesive layer is further provided at one end of the first cylinder close to the second substrate. The first transparent adhesive layer covers the first photosensitive port. The first cylinder is fixed to the second substrate through the first transparent adhesive layer.

5. The high-density chip packaging structure according to claim 2, wherein A third conductive column is further disposed on the back side of the sixth chip, and the third conductive column is connected to the front side of the third chip, so that the sixth chip is electrically connected to the third chip.

6. The high-density chip packaging structure according to claim 2, wherein A fiber optic module is further disposed in the first photosensitive channel, the encapsulant is wrapped around the fiber optic module, and one end of the fiber optic module is joined to the first photosensitive area and the other end is exposed outside the encapsulant.

7. The high-density chip packaging structure according to claim 2, characterized in that, A first glue filling layer is disposed between the first chip and the first substrate, the first glue filling layer is spaced from the first heat dissipation post, and a second glue filling layer is disposed between the fourth chip and the second substrate.

8. The high-density chip packaging structure according to claim 2, wherein The projections of the first chip, the second chip, the fourth chip, and the fifth chip on the first substrate overlap, and the projections of the third chip and the sixth chip on the first substrate partially overlap.

9. The high-density chip packaging structure according to claim 8, wherein A first glue film layer is disposed on the back surface of the first chip, and the back surface of the first chip and the back surface of the second chip are bonded together through the first glue film layer; a second glue film layer is disposed on the back surface of the fourth chip, and the back surface of the fourth chip and the back surface of the fifth chip are bonded together through the second glue film layer.

10. The high-density chip packaging structure according to claim 2, wherein The high-density chip packaging structure further includes a stacked wiring layer, the stacked wiring layer is disposed on a surface of the encapsulant away from the first substrate and is connected to the second substrate, and the first photosensitive port is exposed outside the stacked wiring layer.

11. The high-density chip packaging structure according to claim 10, wherein, A seventh chip is further attached to the back surface of the sixth chip, the encapsulant is wrapped around the seventh chip, the front surface of the seventh chip faces away from the sixth chip and is provided with a fourth conductive post, the stacked wiring layer partially covers the side wall of the second substrate, and the fourth conductive post is connected to the stacked wiring layer so that the seventh chip is electrically connected to the stacked wiring layer through the fourth conductive post.

12. The high-density chip packaging structure according to claim 10, wherein The high-density chip packaging structure further includes an eighth chip and a ninth chip, the eighth chip and the ninth chip are attached to the side of the stacked wiring layer away from the encapsulant at intervals, and a third glue filling layer is further disposed on the side of the stacked wiring layer away from the encapsulant, and the third glue filling layer is wrapped around the eighth chip and the ninth chip.

13. The high-density chip packaging structure according to claim 10, characterized in that, A second photosensitive area is further disposed on the front surface of the sixth chip, a second photosensitive channel is further disposed in the encapsulant, the stacked wiring layer is further provided with a second photosensitive port, one end of the second photosensitive channel is joined to the second photosensitive area and the other end is joined to the second photosensitive port.

14. The high-density chip packaging structure according to claim 13, wherein A second cylinder is disposed on the front surface of the sixth chip, one end of the second cylinder is joined around the second photosensitive area, the other end of the second cylinder is provided with a second transparent glue layer, the second transparent glue layer covers the second photosensitive port, the encapsulant is wrapped around the second cylinder, and the second photosensitive channel is formed in the second cylinder.

15. The high-density chip packaging structure according to claim 14, wherein The second cylinder is joined to the surface of the first substrate, and a reflection module is disposed in the second cylinder, and the reflection module is disposed at the bent portion of the second cylinder.

16. A method for preparing a high-density chip packaging structure, for preparing the high-density chip packaging structure as described in claim 1, characterized in that, The preparation method includes: providing a first substrate; forming a first heat dissipation post on the first substrate; attaching the front surface of the first chip to the first substrate and attaching the back surface of the second chip to the back surface of the first chip; Form a second heat dissipation column on the front surface of the second chip, wherein the second heat dissipation column is flush with the first heat dissipation column; Attach the back surface of the third chip to the first heat dissipation column and the second heat dissipation column, wherein one side edge area of the third chip corresponds to the back surface of the second chip, and a first photosensitive area is further provided on the other side edge area of the front surface of the third chip; Stack the chip stacking module on the second chip and the third chip, wherein a first conductive column and a second conductive column are provided on the bottom side of the chip stacking module, the first conductive column is connected to the front surface of the second chip, and the second conductive column is connected to the front surface of the third chip; Form a plastic package on the surface of the first substrate, and the plastic package covers the first chip, the second chip, the third chip and the chip stacking module; Wherein, a first photosensitive channel corresponding to the first photosensitive area is further provided on the plastic package, and a first photosensitive port corresponding to the first photosensitive area is also provided on the chip stacking module, the first photosensitive port corresponds to the first photosensitive channel and exposes the first photosensitive area.

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