High-density chip packaging structure and preparation method thereof

Abstract

The high-density chip packaging structure and its preparation method provided by the present invention relate to the field of semiconductor technology. The high-density chip packaging structure includes a first substrate, a first chip, a second chip, a third chip, a chip stacking module and a plastic package. The first heat dissipation column is arranged on the first substrate, the back of the third chip is arranged on the first heat dissipation column, and the front of the second chip is also provided with a second heat dissipation column. The chip stacking module is stacked on the second chip and the third chip, and the bottom side of the chip stacking module is provided with a first conductive column and a second conductive column. Compared with the existing technology, the present invention can greatly improve the stacking density and packaging integration by designing the first conductive column and the second conductive column on the chip stacking module in advance and adopting modular packaging. In addition, the provision of the first heat dissipation column and the second heat dissipation column can greatly improve the heat dissipation effect of the overall structure, and improve the bonding force between the plastic package and the chip, thereby improving the structural stability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-density chip packaging structure and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, existing multi-chip packaging stacking technology uses metal pillars formed on a substrate to stack and integrate chips together. Due to process limitations, the integration level and chip stacking density of existing multi-chip packaging stacking technology are low, resulting in excessive overall space occupation and hindering the miniaturization of the packaging structure.

[0003] In addition, the existing stacked packaging structure has an increased number of chips stacked, which leads to an increase in the amount of heat generated, while the existing heat dissipation structure is difficult to meet the heat dissipation requirements, resulting in poor overall heat dissipation effect. Summary of the Invention

[0004] The present invention aims to provide a high-density chip packaging structure and a method for preparing the same, which can adopt a modular stacking structure, significantly improve the stacking density and packaging integration, and at the same time, significantly improve the stacking heat dissipation effect.

[0005] In one aspect, an embodiment of the present invention provides a high-density chip packaging structure, comprising:

[0006] a first substrate, wherein a first heat dissipation column is provided on the first substrate;

[0007] a first chip, wherein the front surface of the first chip is attached to a side of the first substrate where the first heat dissipation column is provided, and is spaced apart from the first heat dissipation column;

[0008] a second chip, wherein the back surface of the second chip is attached to the back surface of the first chip, and a second heat dissipation column is further provided on the front surface of the second chip;

[0009] a third chip, wherein a back surface of the third chip is disposed on the first heat dissipation column and the second heat dissipation column, an edge region on one side of the third chip corresponds to the back surface of the second chip, and a first photosensitive area is further disposed on an edge region on the other side of the front surface of the third chip;

[0010] a chip stacking module, the chip stacking module being stacked on the second chip and the third chip, the bottom side of the chip stacking module being provided with a first conductive pillar and a second conductive pillar, the first conductive pillar being connected to the front side of the second chip, and the second conductive pillar being connected to the front side of the third chip;

[0011] a plastic package, the plastic package being disposed on the first substrate and covering the first chip, the second chip, the third chip and the chip stacking module;

[0012] Among them, the plastic package is also provided with a first photosensitive channel corresponding to the first photosensitive area, and the chip stacking module is also provided with a first photosensitive port corresponding to the first photosensitive area. The first photosensitive port corresponds to the first photosensitive channel and exposes the first photosensitive area.

[0013] In some preferred embodiments, the chip stacking module includes:

[0014] a second substrate;

[0015] a fourth chip, wherein a front surface of the fourth chip is attached to one side of the second substrate;

[0016] a fifth chip, wherein the back surface of the fifth chip is attached to the back surface of the fourth chip, and the second conductive pillar and the third heat dissipation pillar are provided on the front surface of the fifth chip, and the fifth chip is electrically connected to the third chip through the second conductive pillar;

[0017] a sixth chip, wherein the back surface of the sixth chip is attached to an end of the third heat dissipation column away from the fifth chip, and the first conductive column is further provided on the front surface of the sixth chip, and the sixth chip is electrically connected to the second chip through the first conductive column;

[0018] The fourth chip, the fifth chip, and the sixth chip are all staggered with respect to the first photosensitive area, and the first photosensitive port is arranged at an edge of the first substrate.

[0019] In some preferred embodiments, the chip stacking module also includes a first cylinder, which is arranged on one side of the second substrate and surrounds the first photosensitive port. The end of the first cylinder away from the second substrate is connected to the front of the third chip and surrounds the first photosensitive area. The plastic package is wrapped around the outer periphery of the first cylinder to form the first photosensitive channel in the first cylinder.

[0020] In some preferred embodiments, a first transparent adhesive layer is further provided at one end of the first cylinder close to the second substrate, the first transparent adhesive layer covers the first photosensitive port, and the first cylinder is fixed to the second substrate through the first transparent adhesive layer.

[0021] In some preferred embodiments, a third conductive column is further provided on the back side of the sixth chip, and the third conductive column is connected to the front side of the third chip, so that the sixth chip is electrically connected to the third chip.

[0022] In some preferred embodiments, an optical fiber module is further provided in the first photosensitive channel, the plastic package body is wrapped around the optical fiber module, one end of the optical fiber module is connected to the first photosensitive area, and the other end is exposed from the plastic package body.

[0023] In some preferred embodiments, a first filling layer is provided between the first chip and the first substrate, the first filling layer is spaced apart from the first heat dissipation column, and a second filling layer is provided between the fourth chip and the second substrate.

[0024] In some preferred embodiments, the projections of the first chip, the second chip, the fourth chip, and the fifth chip on the first substrate overlap, and the projections of the third chip and the seventh chip on the first substrate partially overlap.

[0025] In some preferred embodiments, a first adhesive film layer is provided on the back of the first chip, and the back of the first chip and the back of the second chip are bonded together through the first adhesive film layer; a second adhesive film layer is provided on the back of the fourth chip, and the back of the fourth chip and the back of the fifth chip are bonded together through the second adhesive film layer.

[0026] In some preferred embodiments, the high-density chip packaging structure further includes a stacked wiring layer, which is arranged on a side surface of the plastic package away from the first substrate and connected to the second substrate, and the first photosensitive port is exposed on the stacked wiring layer.

[0027] In some preferred embodiments, a seventh chip is also attached to the back of the sixth chip, the plastic package body is covered on the seventh chip, the front of the seventh chip is away from the sixth chip, and a fourth conductive column is provided, the stacked wiring layer is partially covered on the side wall of the second substrate, and the fourth conductive column is connected to the stacked wiring layer, so that the seventh chip is electrically connected to the stacked wiring layer through the fourth conductive column.

[0028] In some preferred embodiments, the high-density chip packaging structure also includes an eighth chip and a ninth chip, and the eighth chip and the ninth chip are spaced apart and attached on the side of the stacked wiring layer away from the plastic package body. A third filling layer is also provided on the side of the stacked wiring layer away from the plastic package body, and the third filling layer is wrapped around the eighth chip and the ninth chip.

[0029] In some preferred embodiments, a second photosensitive area is further provided on the front of the sixth chip, a second photosensitive channel is further provided in the plastic package, and a second photosensitive port is further provided in the stacked wiring layer. One end of the second photosensitive channel is connected to the second photosensitive area, and the other end is connected to the second photosensitive port.

[0030] In some preferred embodiments, a second cylinder is provided on the front of the sixth chip, one end of the second cylinder is joined to the periphery of the second photosensitive area, a second transparent adhesive layer is provided at the other end of the second cylinder, the second transparent adhesive layer covers the second photosensitive port, the plastic package is wrapped around the second cylinder, and the second photosensitive channel is formed in the second cylinder.

[0031] In some preferred embodiments, the second cylinder is bonded to the surface of the first substrate, and a reflection module is provided in the second cylinder, and the reflection module is provided at a bend of the second cylinder.

[0032] In a second aspect, an embodiment of the present invention provides a method for preparing a high-density chip packaging structure, which is used to prepare the aforementioned high-density chip packaging structure. The preparation method includes:

[0033] providing a first substrate;

[0034] forming a first heat dissipation column on the first substrate;

[0035] Laying the front side of the first chip on the first substrate, and laminating the back side of the second chip on the back side of the first chip;

[0036] forming a second heat dissipation column on the front surface of the second chip, wherein the second heat dissipation column is flush with the first heat dissipation column;

[0037] The back side of the third chip is attached to the first heat dissipation column and the second heat dissipation column, wherein an edge area on one side of the third chip corresponds to the back side of the second chip, and a first photosensitive area is further provided on an edge area on the other side of the front side of the third chip;

[0038] Stacking a chip stacking module on the second chip and the third chip, wherein a first conductive pillar and a second conductive pillar are provided on the bottom side of the chip stacking module, the first conductive pillar is connected to the front side of the second chip, and the second conductive pillar is connected to the front side of the third chip;

[0039] forming a plastic package on the surface of the substrate, wherein the plastic package covers the first chip, the second chip, the third chip, the first heat dissipation column, the second heat dissipation column and the chip stacking module;

[0040] Among them, the plastic package is also provided with a first photosensitive channel corresponding to the first photosensitive area, and the chip stacking module is also provided with a first photosensitive port corresponding to the first photosensitive area. The first photosensitive port corresponds to the first photosensitive channel and exposes the first photosensitive area.

[0041] The beneficial effects of the embodiments of the present invention include:

[0042] The high-density chip packaging structure and its preparation method provided by the embodiments of the present invention are as follows: the front side of a first chip is attached to a first substrate, the back side of a second chip is attached to the back side of the first chip, a first heat dissipation column is arranged on the first substrate and spaced apart on one side of the first chip, the back side of a third chip is arranged on the first heat dissipation column, and one side edge of the third chip corresponds to the back side of the second chip, and the other side edge of the back side of the third chip is also provided with a first photosensitive area, and the front side of the second chip is also provided with a second heat dissipation column, which can support the second chip. A chip stacking module is stacked on the second and third chips, and a first conductive column and a second conductive column are provided on the bottom side of the chip stacking module, the first conductive column being connected to the second chip, and the second conductive column being connected to the third chip. A plastic package is provided on the first substrate and covers the first, second, third chips, the first heat dissipation column, the second heat dissipation column, and the chip stacking module. Compared with the prior art, the present invention pre-designs the first and second conductive columns on the chip stacking module, and realizes the electrical connection between the chip stacking module and the second and third chips through the first and second conductive columns. The use of modular packaging can significantly increase stacking density and package integration. In addition, the provision of first and second heat dissipation columns can significantly enhance the heat dissipation effect of the overall structure, improve the bonding strength between the plastic package and the chip, and enhance structural stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 A schematic diagram of a first high-density chip packaging structure provided by an embodiment of the present invention;

[0045] Figure 2 for Figure 1 Schematic diagram of the structure of the chip stacking module;

[0046] Figure 3 A schematic diagram of a second high-density chip packaging structure provided by an embodiment of the present invention;

[0047] Figure 4a A schematic diagram of a third high-density chip packaging structure provided by an embodiment of the present invention;

[0048] Figure 4bA schematic diagram of a fourth high-density chip packaging structure provided by an embodiment of the present invention;

[0049] Figure 5 A schematic diagram of a fifth high-density chip packaging structure provided by an embodiment of the present invention;

[0050] Figures 6 to 15 A process flow chart of a method for preparing a high-density chip packaging structure provided by an embodiment of the present invention;

[0051] Figures 16 to 19 for Figure 1 Flow chart of the preparation process of the chip stacking module.

[0052] Icons: 100-high-density chip packaging structure; 110-first substrate; 111-first heat dissipation column; 120-first chip; 121-first glue filling layer; 122-second glue filling layer; 123-first film layer; 124-second film layer; 130-second chip; 131-second heat dissipation column; 140-third chip; 141-first photosensitive area; 142-second photosensitive area; 150-chip stacking module; 151-first photosensitive port; 152-first photosensitive channel; 1521-optical fiber module; 153-second substrate; 154-fourth chip; 155-fifth chip; 1551-third Three heat dissipation columns; 156-sixth chip; 1561-third conductive column; 157-first conductive column; 158-second conductive column; 159-first cylinder; 1591-first transparent adhesive layer; 160-plastic package; 170-stacked wiring layer; 171-seventh chip; 172-fourth conductive column; 173-third adhesive film layer; 174-third filling layer; 1741-colloid flow channel; 175-second photosensitive port; 176-second cylinder; 1761-support foot; 177-second transparent adhesive layer; 178-reflection module; 179-second photosensitive channel; 180-eighth chip; 190-ninth chip. DETAILED DESCRIPTION

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0056] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0057] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0058] As disclosed in the background, conventional multi-chip stacking packaging technology has a low stacking density. For conductive pillars, metal pillars are typically electroplated on the surface of the substrate wiring layer, followed by plastic encapsulation and subsequent grinding to expose the metal pillars. However, during the grinding process, the metal pillars are susceptible to shear forces, causing cracks between the bottom of the metal pillars and the chip pads, leading to electrical failure and other problems.

[0059] Furthermore, in existing stacked packaging structures, increasing the number of chips stacked increases heat generation, which the existing heat dissipation structure cannot meet, resulting in poor overall heat dissipation. Furthermore, because chips are often stacked vertically, the bonding between the plastic package and the chips is weak after encapsulation, resulting in relatively poor overall structural stability.

[0060] Furthermore, silicon photonics (SiPh) technology primarily uses laser beams instead of electronic signals to transmit data, combining optical and electronic components into a single microchip to increase communication speeds. Using light as the information transmission medium on a silicon wafer can achieve superior data transmission performance compared to traditional optical fiber while reducing energy consumption. However, this approach places increasingly stringent demands on the silicon photonic chip packaging process. Traditional packaging processes primarily involve laser grooving to create a clearance zone (i.e., an optical channel) to expose the silicon photonics' optical processing unit to the plastic package, enabling optical signal transmission. Laser grooving inevitably impacts the silicon photonics' optical processing unit, potentially causing laser breakdown and impacting device performance. Furthermore, laser grooving can easily generate plastic package particles, which cannot be removed using water washing processes. As a result, these particles can affect the structural layers in the optical processing area during removal, potentially damaging the optical processing unit.

[0061] In order to solve the above problems, the embodiments of the present invention provide a novel high-density chip packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0062] Embodiments of the present invention provide a high-density chip packaging structure and its fabrication method, utilizing a modular stacking structure to prevent the metal pillars between chips from being exposed during grinding, thereby avoiding the potential for cracks in the solder pads and even electrical failure caused by grinding the metal pillars. Furthermore, the structure significantly improves the heat dissipation of the stack, enhances the bonding strength between the plastic package and the chip, and avoids the formation of optical channels due to laser grooving, thereby addressing the negative effects of laser grooving.

[0063] See also Figure 1 and Figure 2 The embodiment of the present invention provides a high-density chip packaging structure 100, including a first substrate 110, a first chip 120, a second chip 130, a third chip 140, a chip stacking module 150 and a plastic package 160. The first substrate 110 is provided with a first heat dissipation column 111; the front side of the first chip 120 is attached to the side of the first substrate 110 where the first heat dissipation column 111 is provided, and is spaced apart from the first heat dissipation column 111; the back side of the second chip 130 is attached to the back side of the first chip 120, and the front side of the second chip 130 is also provided with a second heat dissipation column 131; the back side of the third chip 140 is provided on the first heat dissipation column 111 and the second heat dissipation column 131, and the edge area on one side of the third chip 140 corresponds to the back side of the second chip 130, and the edge area on the other side of the front side of the third chip 140 is also provided with The first photosensitive area 141; the chip stacking module 150 is stacked on the second chip 130 and the third chip 140, and the bottom side of the chip stacking module 150 is provided with a first conductive column 157 and a second conductive column 158, the first conductive column 157 is connected to the front of the second chip 130, and the second conductive column 158 is connected to the front of the third chip 140; the plastic package 160 is provided on the first substrate 110, and covers the first chip 120, the second chip 130, the third chip 140 and the chip stacking module 150; wherein, the plastic package 160 is also provided with a first photosensitive channel 152 corresponding to the first photosensitive area 141, and the chip stacking module 150 is also provided with a first photosensitive port 151 corresponding to the first photosensitive area 141, the first photosensitive port 151 corresponds to the first photosensitive channel 152, and exposes the first photosensitive area 141.

[0064] In this embodiment of the present invention, the front surface of the first chip 120 is attached to the first substrate 110, the back surface of the second chip 130 is attached to the back surface of the first chip 120, a first heat dissipation column 111 is disposed on the first substrate 110 and spaced apart on one side of the first chip 120, the back surface of the third chip 140 is disposed on the first heat dissipation column 111, and one side edge of the third chip 140 corresponds to the back surface of the second chip 130. The other side edge of the back surface of the third chip 140 is also provided with a first photosensitive area 141, and the front surface of the second chip 130 is also provided with a second heat dissipation column 131, which can support the second chip 130. A chip stacking module 150 is stacked on the second chip 130 and the third chip 140, and a first conductive column 157 and a second conductive column 158 are disposed on the bottom side of the chip stacking module 150. The first conductive column 157 is connected to the second chip 130, and the second conductive column 158 is connected to the third chip 140. The plastic package 160 is arranged on the first substrate 110 and is coated on the first chip 120, the second chip 130, the third chip 140, the first heat dissipation column 111, the second heat dissipation column 131 and the chip stacking module 150. Among them, the first conductive column 157 and the second conductive column 158 can be designed in advance on the chip stacking module 150, and the electrical connection between the chip stacking module and the second chip 130 and the third chip 140 is achieved through the first conductive column 157 and the second conductive column 158. The solution in which the metal columns between the chips need to be exposed through a grinding process in the traditional process is avoided, thereby avoiding the problem of pad cracks or even electrical failure caused by grinding the metal columns. In addition, the provision of the first heat dissipation column 111 and the second heat dissipation column 131 can greatly improve the heat dissipation effect of the overall structure, and enhance the bonding force between the plastic package 160 and the chip, thereby enhancing the structural stability.

[0065] It should be noted that there are multiple first heat dissipation columns 111 and multiple second heat dissipation columns 131 here. Multiple first heat dissipation columns 111 are formed on the first substrate 110 through a wire bonding process and extend upward. Multiple second heat dissipation columns 131 can be arranged on the front of the second chip 130, and the top ends of the multiple first heat dissipation columns 111 and the multiple second heat dissipation columns 131 are flush, which can jointly support the third chip 140.

[0066] In some embodiments, the chip stacking module includes a second substrate 153, a fourth chip 154, a fifth chip 155, and a sixth chip 156. The second substrate 153 is opposite to the first substrate 110 and is spaced apart. The front side of the fourth chip 154 ​​is attached to one side of the second substrate 153. The back side of the fifth chip 155 is attached to the back side of the fourth chip 154. A second conductive column 158 is provided on the front side of the fifth chip 155. The fifth chip 155 is electrically connected to the third chip 140 through the second conductive column 158. Three heat dissipation columns 1551 are arranged on the front of the fifth chip 155; the back of the sixth chip 156 is attached to the end of the third heat dissipation column 1551 away from the fifth chip 155, and a first conductive column 157 is also provided on the front of the sixth chip 156. The sixth chip 156 is electrically connected to the second chip 130 through the first conductive column 157; wherein the fourth chip 154, the fifth chip 155, and the sixth chip 156 are all staggered with the first photosensitive area 141, and the first photosensitive port 151 is arranged at the edge of the first substrate 110.

[0067] It should be noted that the chip stacking module is prepared separately here. It can sequentially complete the mounting of the fourth chip 154, the fifth chip 155, and the sixth chip 156 on the second substrate 153, and complete the preparation of the first conductive pillar 157 and the second conductive pillar 158. Finally, the chip stacking module is mounted on the second chip 130 and the third chip 140 to complete the chip stacking. In addition, the third chip 140 is a photosensitive chip, and its first photosensitive area 141 is located in the edge area and is staggered with the fourth chip 154, the fifth chip 155, and the sixth chip 156. Therefore, it can effectively prevent the fourth chip 154, the fifth chip 155, and the sixth chip 156 from interfering with the first photosensitive area 141, ensuring that the first photosensitive port 151 is aligned with the first photosensitive area 141.

[0068] In some embodiments, the chip stacking module further includes a first barrel 159, which is disposed on one side of the second substrate 153 and surrounds the first photosensitive port 151. The end of the first barrel 159 away from the second substrate 153 is connected to the front of the third chip 140 and surrounds the first photosensitive area 141. The plastic package 160 is wrapped around the outer periphery of the first barrel 159 to form a first photosensitive channel 152 in the first barrel 159. Specifically, the first barrel 159 is made of a light-shielding material, which can achieve side wall light shielding and prevent the diffraction effect of light from affecting the normal light input to the first photosensitive area 141. In addition, the first barrel 159 can make the structure of the first photosensitive channel 152 more stable, preventing the plastic package material from entering the first photosensitive channel 152 during plastic packaging and affecting the normal light sensing of the first photosensitive area 141. Furthermore, the first photosensitive channel 152 is formed by enclosing the first cylinder 159, which can avoid the conventional solution of exposing the photosensitive area by laser grooving, thereby avoiding laser damage to the photosensitive area and also avoiding the impact of particles generated by laser grooving.

[0069] In some embodiments, a first transparent adhesive layer 1591 is further provided at one end of the first barrel 159 near the second substrate 153. The first transparent adhesive layer 1591 covers the first photosensitive port 151, and the first barrel 159 is fixed to the second substrate 153 via the first transparent adhesive layer 1591. Specifically, the first transparent adhesive layer 1591 is light-transmissive and covers the bottom end of the first photosensitive port 151, thereby ensuring light transmission while isolating the photosensitive port and the first photosensitive channel 152, thereby preventing external impurities from entering the first photosensitive channel 152 and affecting the first photosensitive area 141.

[0070] In some embodiments, a third conductive pillar 1561 is further provided on the back side of the sixth chip 156. The third conductive pillar 1561 is connected to the front side of the third chip 140 to electrically connect the sixth chip 156 to the third chip 140. The provision of the third conductive pillar 1561 enables direct electrical connection between the third chip 140 and the sixth chip 156. Furthermore, the third conductive pillar 1561 can also support the sixth chip 156. The third heat dissipation pillar 1551, the first conductive pillar 157, the second conductive pillar 158, and the third conductive pillar 1561 can all be copper pillars, which can connect the sixth chip 156, the third chip 140, the second chip 130, and the fifth chip 155 as a whole, thereby improving the overall structural stability.

[0071] It should be noted that the third chip 140 here is a silicon photonic chip, and the sixth chip 156 can be a memory chip. The third chip 140 and the sixth chip 156 can both form a bridge chip, and the third conductive column 1561 is used to realize the interconnection between the bridge chips, thereby making the overall electrical connection characteristics better.

[0072] Furthermore, the projections of the first chip 120, the second chip 130, the fourth chip 154, and the fifth chip 155 on the first substrate 110 overlap, and the projections of the third chip 140 and the seventh chip 171 on the first substrate 110 partially overlap. Specifically, the second chip 130 and the first chip 120 are arranged back-to-back, the fourth chip 154 ​​and the fifth chip 155 are arranged back-to-back, the third chip 140 is arranged on the flank of the second chip 130, and the seventh chip 171 is arranged on the flank of the fifth chip 155, thereby achieving flank stacking. Compared with the head-on stacking process, flank stacking can reduce the height of the heat dissipation metal pillars, thereby improving the chip stacking integration.

[0073] In some embodiments, a first filler layer 121 is disposed between the first chip 120 and the first substrate 110, and the first filler layer 121 is spaced apart from the first heat dissipation pillar 111. A second filler layer 122 is disposed between the fourth chip 154 ​​and the second substrate 153. Specifically, the first chip 120 is flip-chip mounted on the first substrate 110, and the fourth chip 154 ​​is flip-chip mounted on the second substrate 153. The first filler layer 121 can protect the soldering structure of the first chip 120, and the second filler layer 122 can protect the soldering structure of the fourth chip 154, thereby ensuring soldering reliability.

[0074] It should be noted that in the embodiments of the present invention, the front side of the chip refers to the side of the chip with bumps, which has electrical connection characteristics, while the back side of the chip refers to the side of the chip without bumps, which does not have electrical connection characteristics.

[0075] In some embodiments, a first adhesive film layer 123 is provided on the back side of the first chip 120, and the back side of the first chip 120 and the back side of the second chip 130 are bonded together via the first adhesive film layer 123. A second adhesive film layer 124 is provided on the back side of the fourth chip 154, and the back side of the fourth chip 154 ​​and the back side of the fifth chip 155 are bonded together via the second adhesive film layer 124. The first chip 120 and the second chip 130 are laminated back to back and bonded via the first adhesive film layer 123. Simultaneously, the fourth chip 154 ​​and the fifth chip 155 are laminated back to back and bonded via the second adhesive film layer 124. The first chip 120 and the second chip 130 have the same width, and the fourth chip 154 ​​and the fifth chip 155 have the same width.

[0076] In some embodiments, the high-density chip packaging structure 100 further includes a stacked wiring layer 170, which is disposed on a surface of the plastic package 160 away from the first substrate and connected to the second substrate 153, with the first photosensitive port 151 exposed on the stacked wiring layer 170. In this embodiment of the present invention, both the first substrate 110 and the second substrate 153 are provided with wiring structures, and the stacked wiring layer 170 is disposed on the surface of the plastic package 160 and electrically contacts the wiring structure in the second substrate 153, such that the stacked wiring layer 170 is electrically connected to the second substrate 153.

[0077] It should be noted that the stacked wiring layer 170 does not cover the first photosensitive port 151, but rather exposes the first photosensitive port 151, thereby preventing the stacked wiring layer 170 from interfering with light entering the first photosensitive area 141. Preferably, the stacked wiring layer 170 and the second substrate 153 are arranged in a staggered manner relative to each other, so that the portion of the stacked wiring layer 170 away from the first photosensitive port 151 can directly correspond to the plastic package 160, and the first photosensitive port 151 on the second substrate 153 can also be staggered with the stacked wiring layer 170 and exposed.

[0078] Furthermore, a seventh chip 171 is attached to the back of the sixth chip 156. The plastic package 160 covers the seventh chip 171. The front of the seventh chip 171 faces away from the sixth chip 156 and is provided with a fourth conductive column 172. The fourth conductive column 172 is connected to the stacked wiring layer 170, so that the seventh chip 171 is electrically connected to the stacked wiring layer 170 through the fourth conductive column 172. Specifically, the fourth conductive column 172 extends upward to the wiring structure in the stacked wiring layer 170, so that the seventh chip 171 is electrically connected to the stacked wiring layer 170 through the fourth conductive column 172. Among them, the seventh chip 171 is arranged on the edge of the side of the sixth chip 156 away from the fifth chip 155, that is, at the flank position of the sixth chip 156. On the one hand, it can increase the number of chips and improve the overall integration. On the other hand, it can balance the structural stress of the sixth chip 156 and prevent the sixth chip 156 from warping.

[0079] It is worth noting that a third adhesive film layer 173 is provided on the back surface of the sixth chip 156 . The third adhesive film layer 173 can achieve the adhesion of the seventh chip 171 , thereby fixing the seventh chip 171 .

[0080] In some embodiments, the high-density chip packaging structure 100 further includes an eighth chip 180 and a ninth chip 190. The eighth chip 180 and the ninth chip 190 are spaced apart and attached to the side of the stacked wiring layer 170 away from the plastic package 160. The side of the stacked wiring layer 170 away from the plastic package 160 is further provided with a third filler layer 174, and the third filler layer 174 is wrapped around the eighth chip 180 and the ninth chip 190. Specifically, the eighth chip 180 and the ninth chip 190 are both flip chips, and the eighth chip 180 and the ninth chip 190 are both electrically contacted with the wiring structure in the stacked wiring layer 170. By providing the eighth chip 180 and the ninth chip 190, the stacking density and integration can be further improved. The third filler layer 174 can effectively protect the welding structure of the eighth chip 180 and the ninth chip 190, ensuring structural stability.

[0081] See also Figure 3 In some preferred embodiments, a gap can be left during the plastic encapsulation to form the first photosensitive channel 152, and a gap is also formed at the edge of the second substrate 153 of the chip stacking module to form the first photosensitive port 151 and avoid the first photosensitive channel 152. During the actual plastic encapsulation, the mold packaging is achieved through the improvement of the plastic encapsulation process, so that the first photosensitive channel 152 and the second photosensitive port 175 are not filled with plastic encapsulation material, and a gap is formed at the edge. In addition, the side wall of the third chip 140 is flush with the side wall of the plastic encapsulation body 160, so that the first photosensitive channel 152 and the first photosensitive port 151 can be directly connected to the first photosensitive area 141, that is, the first photosensitive area 141 is directly exposed to the plastic encapsulation body 160.

[0082] See also Figure 4a In some preferred embodiments, an optical fiber module 1521 is further provided in the first photosensitive channel 152, and the plastic encapsulation body 160 is wrapped around the optical fiber module 1521. One end of the optical fiber module 1521 is connected to the first photosensitive area 141, and the other end is exposed to the plastic encapsulation body 160. Specifically, the optical fiber module 1521 can realize the transmission of light. During actual preparation, the optical fiber module 1521 is filled in the first photosensitive channel 152. The optical fiber module 1521 can be prepared first and then plastic encapsulated to ensure the filling effect. By providing the optical fiber module 1521, light transmission can also be achieved and external impurities can be prevented from entering the first photosensitive area 141 and affecting its photosensitivity.

[0083] It should be noted that the solutions using the first cylinder 159 and the optical fiber module 1521 can avoid the solution of laser grooving to expose the photosensitive area, thereby preventing the laser from damaging the photosensitive area and also avoiding the impact of particles generated by laser grooving.

[0084] See also Figure 4bIn some preferred embodiments, an optical fiber module 1521 is further provided in the first photosensitive channel 152, and the optical fiber module 1521 extends out of the plastic package 160, and one end of the optical fiber module 1521 is connected to the first photosensitive area 141, and the other end is exposed to the plastic package 160. Specifically, the optical fiber module 1521 can realize the transmission of light, and the optical fiber module 1521 is provided with a gap between the second substrate 153 and the stacked wiring layer 170, thereby forming a gap, and the gap can be filled with the third filling layer 174. During actual preparation, the optical fiber module 1521 is partially filled in the first photosensitive channel 152, and the optical fiber module 1521 can be prepared first and then plastic packaged. The portion of the optical fiber module extending out of the plastic package 160 is also provided with a groove or a protrusion, and the groove or protrusion can enhance the bonding force between the optical fiber module and the plastic package 160. At the same time, the third glue filling layer 174 can extend to the top surface of the optical fiber module 1521 and cover the grooves or protrusions, which can further enhance the bonding strength between the third glue filling layer 174 and the optical fiber module 1521. In addition, the grooves on the optical fiber module 1521 can also form a glue flow channel 1741 to facilitate the full flow of the third glue filling layer 174, thereby utilizing the capillary effect to ensure glue filling.

[0085] By providing the optical fiber module 1521 , light transmission can also be achieved and external impurities can be prevented from entering the first photosensitive area 141 and affecting its photosensitive effect.

[0086] See also Figure 5 In other preferred embodiments of the present invention, the front surface of the sixth chip 156 is further provided with a second photosensitive region 142, the plastic package 160 is further provided with a second photosensitive channel 179, and the stacked wiring layer 170 is further provided with a second photosensitive port 175. One end of the second photosensitive channel 179 is bonded to the second photosensitive region 142, and the other end is bonded to the second photosensitive port 175. Specifically, the sixth chip 156 and the third chip 140 are both photosensitive chips. The front surface (i.e., bottom side) of the sixth chip 156 is provided with the second photosensitive region 142. Since the second photosensitive region 142 faces away from the second photosensitive port 175, light is transmitted through the curved second photosensitive channel 179. The second photosensitive port 175 is located on an edge of the stacked wiring layer 170 away from the first photosensitive port 151, and the light sensing direction of the second photosensitive port 175 is parallel to that of the first photosensitive port 151, thereby achieving co-directional light sensing.

[0087] Furthermore, a second barrel 176 is provided on the front of the sixth chip 156. One end of the second barrel 176 is bonded to the second photosensitive area 142. A second transparent adhesive layer 177 is provided on the other end of the second barrel 176. The second transparent adhesive layer 177 covers the second photosensitive port 175. The plastic encapsulation body 160 is wrapped around the second barrel 176, and a second photosensitive channel 179 is formed in the second barrel 176. Specifically, the second barrel 176 is bent, and the bottom end of the second barrel 176 is bonded to the first substrate 110. Therefore, structural support can be achieved through the first substrate 110 to prevent the second barrel 176 from falling off. Similarly, in actual preparation, the second barrel 176 is first mounted so that the two ends of the second barrel 176 can be respectively arranged around the second photosensitive area 142 and the second photosensitive port 175, and fixed by the second transparent adhesive layer 177. Then, the plastic encapsulation is performed so that the plastic encapsulation material can cover the second barrel 176. Here, the second transparent adhesive layer 177 can block the second light-sensing port 175 and the second cylinder 176 , thereby preventing external impurities from entering while ensuring light entering.

[0088] In some embodiments, the second barrel 176 is bonded to the surface of the first substrate 110, and a reflective module 178 is disposed within the second barrel 176. The reflective module 178 is disposed at a bend of the second barrel 176. Specifically, the reflective module 178 may be a reflective mirror, and there may be two reflective mirrors disposed at two bends of the second barrel 176, respectively, to achieve double reflection, thereby ensuring that light can be transmitted from the second photosensitive port 175 to the second photosensitive area 142.

[0089] It should be noted that the third chip 140 and the sixth chip 156 can be silicon photonic chips, and the silicon photonic chips are interconnected through the third conductive pillars 1561. Furthermore, a foot 1761 is formed below the second cylinder 176. The foot 1761 can abut against the surface of the first substrate 110, significantly improving the bonding strength between the second cylinder 176 and the plastic package 160.

[0090] An embodiment of the present invention further provides a method for preparing a high-density chip packaging structure 100, which is used to prepare the aforementioned high-density chip packaging structure 100. The method comprises the following steps:

[0091] S1: providing a first substrate 110 .

[0092] See also Figure 6 Specifically, a first substrate 110 is first prepared. The substrate may be a base plate, a lead frame, a substrate structure made of an organic wiring layer, etc. A pad is provided on the first substrate 110 .

[0093] S2 : forming a first heat dissipation column 111 on the first substrate 110 .

[0094] See also Figure 7 Specifically, the first heat dissipation column 111 may be formed by a wire bonding process or an electroplating method, and the first heat dissipation column 111 may be a copper column.

[0095] S3 : attaching the front surface of the first chip 120 to the first substrate 110 , and attaching the back surface of the second chip 130 to the back surface of the first chip 120 .

[0096] See also Figure 8 Specifically, after forming the first heat sink 111 through wire bonding, the first chip 120 can be flip-chip mounted on the first substrate 110. The flip-chip bumps and pads are then reflow soldered to achieve mounting. Glue is then applied to form a first filler layer 121 to protect the bottom solder structure. A first adhesive film layer 123 is then applied to the back of the first chip 120, and the second chip 130 is then bonded back-to-back to the first chip 120.

[0097] S4 : forming a second heat dissipation column 131 on the front surface of the second chip 130 .

[0098] See also Figure 9 Specifically, the second heat dissipation column 131 is flush with the first heat dissipation column 111 , and there may be a plurality of second heat dissipation columns 131 .

[0099] S5 : placing the back surface of the third chip 140 on the first heat dissipation pillars 111 and the second heat dissipation pillars 131 .

[0100] See also Figure 10 Specifically, one edge of the third chip 140 corresponds to the backside of the second chip 130, and the other edge of the front side of the third chip 140 is further provided with a first photosensitive area 141. The third chip 140 is mounted upright on the second heat dissipation column 131 and the first heat dissipation column 111, with the first heat dissipation column 111 and the second heat dissipation column 131 providing joint support.

[0101] S6 : stacking the chip stacking module 150 on the second chip 130 and the third chip 140 .

[0102] See also Figure 11 Specifically, a first conductive pillar 157 and a second conductive pillar 158 are provided on the bottom side of the chip stacking module 150. The first conductive pillar 157 is connected to the front surface of the second chip 130, and the second conductive pillar 158 is connected to the front surface of the third chip 140. The chip stacking module 150 can be prepared in advance, and the first conductive pillar 157 and the second conductive pillar 158 can also be prepared on the chip stacking module 150 in advance.

[0103] The specific preparation process of the chip stacking module 150 is as follows:

[0104] See also Figure 16 First, a second substrate 153 is provided, and then the fourth chip 154 ​​and the fifth chip 155 are mounted on the second substrate 153, wherein the fourth chip 154 ​​is flip-chip mounted on the second substrate 153 and soldered with the second filler layer 122 for protection, and the fifth chip 155 is back-to-back mounted on the back of the fourth chip 154 ​​through the second adhesive film layer 124.

[0105] See also Figure 17 Then, the second heat dissipation column 131 and the second conductive column 158 are prepared on the front side of the fifth chip 155 , wherein the second heat dissipation column 131 is lower than the second conductive column 158 .

[0106] See also Figure 18 , and then the first cylinder 159 is mounted. The first cylinder 159 is fixed to the first photosensitive port 151 of the second substrate 153 through the first transparent adhesive layer 1591 and corresponds to the first photosensitive port 151 on the second substrate 153.

[0107] See also Figure 19 Next, the sixth chip 156 is mounted on the second heat dissipation pillar 131, with the back of the sixth chip 156 attached to the second heat dissipation pillar 131 for support and fixation. The front of the sixth chip 156 is formed with a first conductive pillar 157 and a third conductive pillar 1561, wherein the third conductive pillar 1561 is lower than the first conductive pillar 157. Finally, the chip is cut to obtain a single chip stacking module 150.

[0108] After forming the chip stacking module 150, the chip stacking module 150 can be flipped and mounted on the second chip 130 and the third chip 140, wherein the first conductive pillar 157 is connected to the second chip 130, the second conductive pillar 158 is connected to the third chip 140, and the third conductive pillar 1561 is connected to the third chip 140. At the same time, the first barrel 159 corresponds to the first photosensitive area 141. The chip stacking module 150 is also provided with a first photosensitive port 151 corresponding to the first photosensitive area 141. The first photosensitive port 151 corresponds to the first photosensitive channel 152 and exposes the first photosensitive area 141.

[0109] See also Figure 12 It should be noted that after the chip stacking module 150 is assembled, the seventh chip 171 can be mounted on the front of the sixth chip 156 to form a fourth conductive column 172 extending upward.

[0110] S7 : forming a plastic package 160 on the surface of the first substrate 110 .

[0111] See also Figure 13Specifically, the plastic package 160 is coated on the first chip 120, the second chip 130, the third chip 140, the first heat dissipation column 111, the second heat dissipation column 131, and the chip stacking module 150. Using a plastic packaging process, the plastic package 160 is formed on the first substrate 110 by plastic packaging. The plastic package 160 can encapsulate the first chip 120, the second chip 130, the third chip 140, the fourth chip 154, the fifth chip 155, and the sixth chip 156. After plastic packaging, the plastic package 160 can be wrapped around the first cylinder 159, so that a first photosensitive channel 152 corresponding to the first photosensitive area 141 is formed in the first cylinder 159.

[0112] Since the fourth conductive pillar 172 is provided, the fourth conductive pillar 172 can be exposed through a conventional thinning process.

[0113] S8 : forming a stacked wiring layer 170 on the plastic package body 160 .

[0114] See also Figure 14 Specifically, a wiring process can be used to form multiple dielectric layers or multiple wiring layers on the plastic package 160 to form a stacked wiring layer 170 . The stacked wiring layer 170 is directly electrically connected to the second substrate 153 and the fourth conductive pillars 172 .

[0115] S9 : Mounting the eighth chip 180 and the ninth chip 190 on the stacked wiring layer 170 .

[0116] See also Figure 15 Specifically, the eighth chip 180 and the ninth chip 190 can be flip-chip mounted on the stacked wiring layer 170, and then glue is applied to form a third filler layer 174 to achieve solder joint protection. Finally, the single product is obtained after cutting.

[0117] In summary, the high-density chip package structure 100 and its manufacturing method provided by the embodiments of the present invention include: the front surface of the first chip 120 is attached to the first substrate 110; the back surface of the second chip 130 is attached to the back surface of the first chip 120; first heat dissipation pillars 111 are disposed on the first substrate 110 and spaced apart on one side of the first chip 120; the back surface of the third chip 140 is disposed on the first heat dissipation pillars 111, with one side edge of the third chip 140 corresponding to the back surface of the second chip 130; the other side edge of the back surface of the third chip 140 is further provided with a first photosensitive area 141; and the front surface of the second chip 130 is further provided with a second heat dissipation pillar 131, which can support the second chip 130. A chip stacking module 150 is stacked on the second chip 130 and the third chip 140, and a first conductive pillar 157 and a second conductive pillar 158 are disposed on the bottom side of the chip stacking module 150. The first conductive pillar 157 is connected to the second chip 130, and the second conductive pillar 158 is connected to the third chip 140. The plastic package 160 is arranged on the first substrate 110 and covers the first chip 120, the second chip 130, the third chip 140, the first heat dissipation column 111, the second heat dissipation column 131 and the chip stacking module 150. Compared with the existing technology, the present invention pre-designs the first conductive column 157 and the second conductive column 158 on the chip stacking module 150, and realizes the electrical connection between the chip stacking module and the second chip 130 and the third chip 140 through the first conductive column 157 and the second conductive column 158. The solution in which the metal columns between the chips need to be exposed through a grinding process in the traditional process is avoided, thereby avoiding the problem of pad cracks or even electrical failure caused by grinding the metal columns. In addition, the provision of the first heat dissipation column 111 and the second heat dissipation column 131 can greatly improve the heat dissipation effect of the overall structure, and enhance the bonding force between the plastic package 160 and the chip, thereby improving the structural stability.

[0118] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A high-density chip packaging structure, characterized in that: include: a first substrate, wherein a first heat dissipation column is provided on the first substrate; a first chip, wherein the front surface of the first chip is attached to a side of the first substrate where the first heat dissipation column is provided, and is spaced apart from the first heat dissipation column; a second chip, wherein the back surface of the second chip is attached to the back surface of the first chip, and a second heat dissipation column is further provided on the front surface of the second chip; a third chip, wherein a back surface of the third chip is disposed on the first heat dissipation column and the second heat dissipation column, an edge region on one side of the third chip corresponds to the back surface of the second chip, and a first photosensitive area is further disposed on an edge region on the other side of the front surface of the third chip; a chip stacking module, the chip stacking module being stacked on the second chip and the third chip, the bottom side of the chip stacking module being provided with a first conductive pillar and a second conductive pillar, the first conductive pillar being connected to the front side of the second chip, and the second conductive pillar being connected to the front side of the third chip; a plastic package, the plastic package being disposed on the first substrate and covering the first chip, the second chip, the third chip and the chip stacking module; The plastic package is further provided with a first photosensitive channel corresponding to the first photosensitive area, and the chip stacking module is also provided with a first photosensitive port corresponding to the first photosensitive area. The first photosensitive port corresponds to the first photosensitive channel and exposes the first photosensitive area. The first conductive pillar and the second conductive pillar are pre-arranged on the chip stacking module, and electrical connection between the chip stacking module and the second chip and the third chip is achieved through the first conductive pillar and the second conductive pillar.

2. The high-density chip packaging structure according to claim 1, characterized in that: The chip stacking module includes: a second substrate; a fourth chip, wherein a front surface of the fourth chip is attached to one side of the second substrate; a fifth chip, wherein the back surface of the fifth chip is attached to the back surface of the fourth chip, and the second conductive pillar and the third heat dissipation pillar are provided on the front surface of the fifth chip, and the fifth chip is electrically connected to the third chip through the second conductive pillar; a sixth chip, wherein the back surface of the sixth chip is attached to an end of the third heat dissipation column away from the fifth chip, and the first conductive column is further provided on the front surface of the sixth chip, and the sixth chip is electrically connected to the second chip through the first conductive column; The fourth chip, the fifth chip, and the sixth chip are all staggered with respect to the first photosensitive area, and the first photosensitive port is arranged at an edge of the first substrate.

3. The high-density chip packaging structure according to claim 2, characterized in that: The chip stacking module also includes a first cylinder, which is arranged on one side of the second substrate and surrounds the first photosensitive port. The end of the first cylinder away from the second substrate is connected to the front of the third chip and surrounds the first photosensitive area. The plastic package is wrapped around the outer periphery of the first cylinder to form the first photosensitive channel in the first cylinder.

4. The high-density chip packaging structure according to claim 3, characterized in that: A first transparent adhesive layer is further provided on one end of the first cylinder close to the second substrate. The first transparent adhesive layer covers the first photosensitive port. The first cylinder is fixed to the second substrate through the first transparent adhesive layer.

5. The high-density chip packaging structure according to claim 2, wherein: A third conductive column is further provided on the back side of the sixth chip. The third conductive column is connected to the front side of the third chip, so that the sixth chip is electrically connected to the third chip.

6. The high-density chip packaging structure according to claim 2, wherein: An optical fiber module is further provided in the first photosensitive channel. The plastic package body covers the optical fiber module. One end of the optical fiber module is connected to the first photosensitive area, and the other end is exposed from the plastic package body.

7. The high-density chip packaging structure according to claim 2, characterized in that: A first filling layer is provided between the first chip and the first substrate, and the first filling layer is spaced apart from the first heat dissipation column. A second filling layer is provided between the fourth chip and the second substrate.

8. The high-density chip packaging structure according to claim 2, wherein: Projections of the first chip, the second chip, the fourth chip, and the fifth chip on the first substrate overlap, and projections of the third chip and the sixth chip on the first substrate partially overlap.

9. The high-density chip packaging structure according to claim 8, characterized in that: A first adhesive film layer is provided on the back of the first chip, and the back of the first chip and the back of the second chip are bonded together through the first adhesive film layer; a second adhesive film layer is provided on the back of the fourth chip, and the back of the fourth chip and the back of the fifth chip are bonded together through the second adhesive film layer.

10. The high-density chip packaging structure according to claim 2, wherein: The high-density chip packaging structure further includes a stacked wiring layer, which is arranged on a surface of the plastic package away from the first substrate and connected to the second substrate, and the first photosensitive port is exposed on the stacked wiring layer.

11. The high-density chip packaging structure according to claim 10, characterized in that: A seventh chip is also attached to the back of the sixth chip, the plastic package body covers the seventh chip, the front of the seventh chip faces away from the sixth chip, and is provided with a fourth conductive column, the stacked wiring layer partially covers the side wall of the second substrate, and the fourth conductive column is connected to the stacked wiring layer, so that the seventh chip is electrically connected to the stacked wiring layer through the fourth conductive column.

12. The high-density chip packaging structure according to claim 10, wherein: The high-density chip packaging structure also includes an eighth chip and a ninth chip, and the eighth chip and the ninth chip are spaced apart and attached on the side of the stacked wiring layer away from the plastic package body. A third filling layer is also provided on the side of the stacked wiring layer away from the plastic package body, and the third filling layer is wrapped around the eighth chip and the ninth chip.

13. The high-density chip packaging structure according to claim 10, characterized in that: A second photosensitive area is further provided on the front of the sixth chip, a second photosensitive channel is further provided in the plastic package, and a second photosensitive port is further provided in the stacked wiring layer. One end of the second photosensitive channel is connected to the second photosensitive area, and the other end is connected to the second photosensitive port.

14. The high-density chip packaging structure according to claim 13, wherein: A second cylinder is provided on the front of the sixth chip, one end of the second cylinder is joined to the second photosensitive area, and a second transparent adhesive layer is provided on the other end of the second cylinder. The second transparent adhesive layer covers the second photosensitive port, the plastic package is wrapped around the second cylinder, and the second photosensitive channel is formed in the second cylinder.

15. The high-density chip packaging structure according to claim 14, characterized in that: The second cylinder is bonded to the surface of the first substrate, and a reflection module is disposed in the second cylinder. The reflection module is disposed at a bend of the second cylinder.

16. A method for preparing a high-density chip packaging structure, for preparing the high-density chip packaging structure according to claim 1, characterized in that: The preparation method comprises: providing a first substrate; forming a first heat dissipation column on the first substrate; Laying the front side of the first chip on the first substrate, and laminating the back side of the second chip on the back side of the first chip; forming a second heat dissipation column on the front surface of the second chip, wherein the second heat dissipation column is flush with the first heat dissipation column; The back side of the third chip is attached to the first heat dissipation column and the second heat dissipation column, wherein an edge area on one side of the third chip corresponds to the back side of the second chip, and a first photosensitive area is further provided on an edge area on the other side of the front side of the third chip; Stacking a chip stacking module on the second chip and the third chip, wherein a first conductive pillar and a second conductive pillar are provided on the bottom side of the chip stacking module, the first conductive pillar is connected to the front side of the second chip, and the second conductive pillar is connected to the front side of the third chip; forming a plastic package on the surface of the first substrate, wherein the plastic package covers the first chip, the second chip, the third chip and the chip stacking module; The plastic package is further provided with a first photosensitive channel corresponding to the first photosensitive area, and the chip stacking module is also provided with a first photosensitive port corresponding to the first photosensitive area. The first photosensitive port corresponds to the first photosensitive channel and exposes the first photosensitive area. The first conductive pillar and the second conductive pillar are pre-arranged on the chip stacking module, and electrical connection between the chip stacking module and the second chip and the third chip is achieved through the first conductive pillar and the second conductive pillar.

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