Line repairing method and device, circuit, equipment, storage medium and program product

Abstract

The invention relates to the technical field of integrated circuits, in particular to a line repairing method and device, a circuit, equipment, a storage medium and a program product. The method comprises the following steps: determining a to-be-repaired packaging layer in the integrated circuit and a wrong connection pin pair between the to-be-repaired packaging layer and an external component, the wrong connection pin pair comprises a first pin and a second pin which are arranged on the outer surface of the substrate, and a first signal transmission pin and a second signal transmission pin of an external assembly, the second pin is in contact connection with the first signal transmission pin, and the first pin is in contact connection with the second signal transmission pin; and modifying the first transmission path and the second transmission path on the outer surface of the substrate to obtain the integrated circuit after line repair. By the adoption of the scheme, the technical problem that chip circuit repairing is limited by a complex metal interconnection wiring layer and chip module layout can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and particularly to a circuit repair method, apparatus, circuit, device, storage medium, and program product. Background Art

[0002] During the process of a chip from front-end design, mid-end manufacturing to mass production, in addition to screening out defective chips, a series of tests and verifications are also required to ensure that the quality and reliability of the chip itself meet the standards. During the functional and performance verification process, the process is often blocked due to chip design problems or hardware design mismatches. In severe cases, it is necessary to re-manufacture the board and re-tape the chip to correct the design defects. However, before re-taping, the feasibility of the design scheme needs to be verified, or some functional verifications need to be carried out at the current chip level. Therefore, the chip can be repaired by circuit repair to meet the verification requirements.

[0003] In the related art, for the internal structure of a chip, a focused ion beam (FIB) can be used for circuit editing and wire repair. However, it is necessary to perform preliminary layout positioning on the sample, perform local grinding and directional FIB cutting, and then perform re-wiring, local deposition of metal and dielectric layers to modify the wiring structure. This solution is limited by the complex metal interconnection wiring layer and the chip module layout. If the positioning operation area cannot avoid metal traces, this solution cannot be used for verification. Summary of the Invention

[0004] The present disclosure aims to at least solve one of the technical problems in the related art to some extent.

[0005] To this end, the first object of the present disclosure is to propose a circuit repair method to solve the technical problem that the chip circuit repair is limited by the complex metal interconnection wiring layer and the chip module layout.

[0006] The second object of the present disclosure is to propose a circuit repair apparatus.

[0007] The third object of the present disclosure is to propose an integrated circuit after circuit repair.

[0008] The fourth object of the present disclosure is to propose an electronic device.

[0009] The fifth object of the present disclosure is to propose a computer-readable storage medium.

[0010] The sixth object of the present disclosure is to propose a computer program product.

[0011] To achieve the above object, an embodiment of the first aspect of the present disclosure proposes a circuit repair method, including:

[0012] Identify the encapsulation layer to be repaired in the integrated circuit, as well as the misconnected pin pairs between the encapsulation layer to be repaired and the external components. The encapsulation layer to be repaired includes a substrate. The misconnected pin pairs include a first pin and a second pin provided on the outer surface of the substrate, and a first signal transmission pin and a second signal transmission pin of the external component. Among them, the second pin is in contact connection with the first signal transmission pin, and the first pin is in contact connection with the second signal transmission pin;

[0013] Modify the first transmission path and the second transmission path on the outer surface of the substrate to obtain the integrated circuit after line repair. The first transmission path is composed of the first signal transmission pin and the second pin, and the second transmission path is composed of the second signal transmission pin and the first pin.

[0014] Optionally, modifying the first transmission path and the second transmission path on the outer surface of the substrate includes:

[0015] Cut the first transmission path at a first cutting position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path. The third transmission path includes the first signal transmission pin;

[0016] Cut the second transmission path at a second cutting position corresponding to the first cutting position in the second transmission path to obtain a fifth transmission path and a sixth transmission path. The fifth transmission path includes the second signal transmission pin. The fifth transmission path corresponds to the third transmission path, and the fourth transmission path corresponds to the sixth transmission path;

[0017] Connect the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material, and / or connect the fourth transmission path and the fifth transmission path on the outer surface of the substrate through a conductive material.

[0018] Optionally, cutting the first transmission path at a first cutting position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path, and cutting the second transmission path at a second cutting position corresponding to the first cutting position in the second transmission path to obtain a fifth transmission path and a sixth transmission path includes:

[0019] Disconnect the contact between the second pin and the first signal transmission pin to obtain a third transmission path and a fourth transmission path;

[0020] Disconnect the contact between the first pin and the second signal transmission pin to obtain a fifth transmission path and a sixth transmission path.

[0021] Optionally, connecting the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material includes:

[0022] Cut the second pin and set an insulating material at the third cutting position corresponding to the second pin to obtain the processed second pin, where the height corresponding to the processed second pin is determined by the maximum height threshold corresponding to the first signal transmission pin;

[0023] Connect the first pin and the processed second pin on the outer surface of the substrate using a conductive material so that the first signal transmission pin is connected to the first pin through the conductive material.

[0024] Optionally, cutting the second pin and setting an insulating material at the third cutting position corresponding to the second pin includes:

[0025] Cut the second pin completely and set an insulating material at the third cutting position corresponding to the second pin; or,

[0026] Partially cut the second pin to obtain the cut second pin, set an insulating material at the third cutting position corresponding to the second pin, and wrap the cut second pin with the insulating material.

[0027] Optionally, the insulating material includes a first insulating material and a second insulating material. Setting the insulating material at the third cutting position corresponding to the second pin includes:

[0028] Set the first insulating material and the second insulating material in sequence at the third cutting position corresponding to the second pin, where the stiffness of the first insulating material is less than that of the second insulating material.

[0029] Optionally, setting the insulating material at the cutting position corresponding to the second pin to obtain the processed second pin includes:

[0030] Set the insulating material at the third cutting position corresponding to the second pin and set a third pin on the insulating material to obtain the processed second pin.

[0031] Optionally, cutting the first transmission path at the first cutting position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path, and cutting the second transmission path at the second cutting position corresponding to the first cutting position in the second transmission path to obtain a fifth transmission path and a sixth transmission path includes:

[0032] Determine the first area to be cut corresponding to the first cutting position and the second area to be cut corresponding to the second cutting position, where the first cutting position is located on any section of the first transmission path other than the second pin on the outer surface of the substrate, and the second cutting position is located on any section of the second transmission path other than the first pin on the outer surface of the substrate;

[0033] Perform windowing on the first area to be cut and the second area to be cut, exposing the conductive layers of the first area to be cut and the second area to be cut, obtaining a first conductive window and a second conductive window, where the area of the first conductive window is the same as the area of the first area to be cut, and the area of the second conductive window is the same as the area of the second area to be cut;

[0034] Perform etching and cutting on the first conductive window to obtain a third transmission path and a fourth transmission path;

[0035] Perform etching and cutting on the second conductive window to obtain a fifth transmission path and a sixth transmission path.

[0036] Optionally, connect the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material, including:

[0037] Perform windowing on the sixth transmission path disposed on the outer surface of the substrate, exposing the conductive layer inside the sixth transmission path, obtaining a third conductive window;

[0038] Connect the third conductive window and the second pin through a conductive material, so that the first signal transmission pin is connected to the sixth transmission path through the second pin and the conductive material.

[0039] Optionally, apply an insulating material at at least one of the following locations:

[0040] The cutting position after performing etching and cutting on the first conductive window;

[0041] The cutting position after performing etching and cutting on the second conductive window;

[0042] The outer surface of the conductive material.

[0043] Optionally, connect the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material, including:

[0044] Determine the circuit interconnection line pattern between the third transmission path and the sixth transmission path;

[0045] Set a conductive material on the outer surface of the substrate according to the circuit interconnection line pattern to connect the third transmission path and the sixth transmission path through the conductive material, and / or connect the fourth transmission path and the fifth transmission path through the conductive material.

[0046] To achieve the above object, an embodiment of the second aspect of the present disclosure provides a circuit repair device, including:

[0047] A pin determination unit is configured to determine a package layer to be repaired in an integrated circuit, and a pair of misconnected pins between the package layer to be repaired and an external component. The package layer to be repaired includes a substrate. The pair of misconnected pins includes a first pin and a second pin disposed on an outer surface of the substrate, and a first signal transmission pin and a second signal transmission pin of the external component. The second pin is in contact connection with the first signal transmission pin, and the first pin is in contact connection with the second signal transmission pin.

[0048] A path modification unit is configured to modify a first transmission path and a second transmission path on the outer surface of the substrate to obtain an integrated circuit with repaired wiring. The first transmission path is formed by the first signal transmission pin and the second pin, and the second transmission path is formed by the second signal transmission pin and the first pin.

[0049] To achieve the above object, an embodiment of the third aspect of the present disclosure provides an integrated circuit with repaired wiring, where the integrated circuit with repaired wiring is an integrated circuit obtained by repairing the wiring of an integrated circuit by using the method shown in any one of the foregoing first aspects.

[0050] To achieve the above object, an embodiment of the fourth aspect of the present disclosure provides an electronic device, including: an integrated circuit with repaired wiring as shown in the foregoing third aspect.

[0051] To achieve the above object, an embodiment of the fifth aspect of the present disclosure provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method shown in any one of the foregoing first aspects.

[0052] To achieve the above object, an embodiment of the sixth aspect of the present disclosure provides a computer program product, including a computer program, which when executed by a processor, implements the method shown in any one of the foregoing first aspects.

[0053] In summary, the wiring repair method, device, circuit, equipment, storage medium, and program product provided by the present disclosure can achieve the function of local circuit modification only from the external package level without opening the cover, without changing the internal interconnection lines, without performing destructive operations on the chip, or only performing semi-destructive operations on the chip. It can be unrestricted by complex metal interconnection wiring layers and chip module layouts, and effectively avoid excessive damage to the chip.

[0054] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of embodiments in conjunction with the accompanying drawings, where:

[0056] Figure 1 Schematic diagram of the structure of a finished FIB circuit editing product provided by an embodiment of the present disclosure;

[0057] Figure 2 Schematic diagram of the process flow of a line repair method provided by an embodiment of the present disclosure;

[0058] Figure 3 Schematic diagram of the connection of an integrated circuit before line repair provided by an embodiment of the present disclosure;

[0059] Figure 4 Schematic diagram of the structure of a package layer to be repaired provided by an embodiment of the present disclosure;

[0060] Figure 5 Schematic diagram of the process flow of a line repair method provided by another embodiment of the present disclosure;

[0061] Figure 6 Schematic diagram of the cutting of a transmission path provided by an embodiment of the present disclosure;

[0062] Figure 7 Display diagram of a circuit interconnect pattern provided by an embodiment of the present disclosure;

[0063] Figure 8 Schematic diagram of the process flow of a line repair method provided by yet another embodiment of the present disclosure;

[0064] Figure 9 Display diagram of a pair of misconnected pins provided by an embodiment of the present disclosure;

[0065] Figure 10 Cross-sectional view of an integrated circuit after line repair provided by an embodiment of the present disclosure;

[0066] Figure 11 Cross-sectional view of an integrated circuit after line repair provided by another embodiment of the present disclosure;

[0067] Figure 12 Top view of an integrated circuit after line repair provided by an embodiment of the present disclosure;

[0068] Figure 13 Schematic diagram of the process flow of a line repair method provided by yet another embodiment of the present disclosure;

[0069] Figure 14 Display diagram of internal wiring errors in a package layer to be repaired provided by another embodiment of the present disclosure;

[0070] Figure 15 A display diagram of a conductive window provided by another embodiment of the present disclosure;

[0071] Figure 16 A top view of an integrated circuit after wire repair provided by another embodiment of the present disclosure;

[0072] Figure 17 A top view of an integrated circuit after wire repair provided by yet another embodiment of the present disclosure;

[0073] Figure 18 A structural schematic diagram of a wire repair device provided by an embodiment of the present disclosure. Detailed implementation manners

[0074] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0075] In the related art, wire repair technology focuses on FIB circuit editing and modification of the metal interconnection wiring structure in the back-end of the chip. The process flow of the FIB circuit editing scheme for the internal structure of the chip is as follows:

[0076] S1. Determine the wire modification route of the chip through layout layout positioning, including the positions to be cut and the connections that need to be reconnected to achieve the modification goal;

[0077] S2. Collect information such as the chip size and appearance, and perform imaging processing on the chip through devices such as a scanning electron microscope (SEM) and an optical microscope (OM) to ensure that the operation area to be modified coincides with the imaging;

[0078] S3. Use a focused ion beam with a large beam current of 20 nA (the ion beam diameter can be less than 1 μm) in combination with a high beam current etching assist gas XeF2 to quickly perform the first etching on the silicon chip for about 20 minutes, thinning it to a thickness of 2 - 6 μm. The purpose of the first etching is to expose the wire cutting area;

[0079] S4. Image the chip after the first etching, and further determine the position of the area to be modified based on the circuit image obtained from the imaging. The method for determining the position of the area to be modified is as follows: Deposit a reflective coating (hydrocarbon polymer) with a beam current of 4 nA using FIB to enhance the image contrast of subsequent imaging, making the diffraction fringes clearer. Overlay and correlate the layout of the chip's Graphic Data System (GDS) with the imaging on the back of the chip, thereby revealing the area to be modified. Navigate the FIB to this position to prepare for the second etching, and the purpose of the second etching is to expose the area to be repaired.

[0080] S5. Perform a second etching on the chip after the first etching using FIB with a beam current of 250 pA in combination with XeF2 etching assist gas to expose the area to be modified.

[0081] S6. Finally, use FIB to cut the circuit in the area to be modified, and then perform metal deposition to reconnect the target circuit.

[0082] Among them, Figure 1 is a schematic structural diagram of a finished FIB circuit editing product provided by an embodiment of the present disclosure. As Figure 1 shown, the size of the area to be modified involved is 6 μm * 3 μm. To connect part of the metal circuit, FIB with a beam current of 250 pA is used for deposition. After the modification is completed, a protective layer is further deposited. The size of the deposition interval is 12 μm * 12 μm, and the beam current used is 1 nA to prevent the modified part from being oxidized. Thus, the circuit modification is completed. And during the modification process, passive voltage contrast imaging combined with secondary electron signal flow is used to monitor the end point of the circuit modification to avoid over-etching or under-etching during the FIB etching or circuit modification process, so that the target position is damaged or incompletely exposed, affecting the circuit modification effect.

[0083] It can be seen from steps S1 to S6 that using FIB for circuit editing operation is difficult, requires high requirements for equipment and operators, has a long operation cycle, and has a low yield. That is to say, the FIB solution is only suitable for a small number of sample operations, has a low success rate, and is expensive and cannot meet the batch verification requirements.

[0084] In addition, FIB for wire connection mainly relies on depositing tungsten metal. When the distance between two connection points is relatively close and the signal transmission path is short, the performance requirements can be met. However, when the distance between two connection points is far, the connecting wire becomes longer accordingly, and the impedance will show a sharp increase trend. For example, when the length of the deposited metal wire is 1000 μm, the connecting wire resistance will reach 10 kΩ. During the test phase, a large resistance may be misidentified as an open circuit. Especially for the current advanced processes that require a low resistance-capacitance delay (RC delay), this is undoubtedly unacceptable.

[0085] The present disclosure will be described in detail below with reference to specific embodiments.

[0086] As Figure 2 shown, Figure 2 FIG. is a schematic flowchart of a circuit repair method provided by an embodiment of the present disclosure. This method can be implemented depending on a computer program and can run on a circuit repair device. This computer program can be integrated in an application or run as an independent tool-like application.

[0087] Exemplarily, the circuit repair method may include the following steps:

[0088] S101, determine a package layer to be repaired in an integrated circuit, and a pair of misconnected pins between the package layer to be repaired and an external component;

[0089] According to some embodiments, the integrated circuit refers to, for example, an integrated circuit in a chip. The integrated circuit may include, for example, at least one package layer. The package layer to be repaired refers to a package layer in the integrated circuit that has a pair of misconnected pins with an external component.

[0090] In some embodiments, the package layer internally includes a substrate, pins disposed on the substrate, Redistribution Layer (RDL), BUMP, and other structures.

[0091] In some embodiments, the external component refers to a component connected to the package layer to be repaired. This component may be another package layer in the integrated circuit that is connected to the package layer to be repaired; this component may also be an external device connected to the integrated circuit, such as a Printed Circuit Board (PCB).

[0092] According to some embodiments, the package layer to be repaired includes a substrate. The pair of misconnected pins includes a first pin and a second pin disposed on the outer surface of the substrate, and a first signal transmission pin and a second signal transmission pin of the external component. Among them, the second pin is in contact connection with the first signal transmission pin, and the first pin is in contact connection with the second signal transmission pin. However, in the correct connection circuit, the first pin should be in contact connection with the first signal transmission pin, and the second pin should be in contact connection with the second signal transmission pin. Therefore, it is necessary to repair the circuit so that the first pin is in contact connection with the first signal transmission pin and / or the second pin is in contact connection with the second signal transmission pin.

[0093] In some embodiments, the types of the first pin, the second pin, the first signal transmission pin, and the second signal transmission pin include, but are not limited to, ball, Flip Chip Chip Scale Package ball (FCCSP ball), socket pin, socket probe pin, etc.

[0094] Among them, the alloy composition of the ball can be, for example, a eutectic tin-lead, including but not limited to SAC305 (Sn96.5Ag3Cu0.5), SAC0307, SAC3505, SA3.5, etc.

[0095] Taking one scenario as an example, Figure 3 is a schematic connection diagram of an integrated circuit before line repair provided by an embodiment of the present disclosure. As Figure 3 shown, there is a misconnected pin pair between the integrated circuit 10 and the external component 20. Among them, the integrated circuit 10 includes multiple packaging layers, and each packaging layer includes a substrate. There is a misconnected pin pair between the packaging layer 11 to be repaired in the multiple packaging layers and the external component 20. The misconnected pin pair includes a first pin 111 and a second pin 112 provided on the outer surface of the substrate 113 in the packaging layer 11 to be repaired, and a first signal transmission pin 121 and a second signal transmission pin 122 of the external component 20. The second pin 112 is in contact connection with the first signal transmission pin 121, and the first pin 111 is in contact connection with the second signal transmission pin 122.

[0096] Among them, the misconnected pin pair may be caused by incorrect internal wiring of the external component 20 or incorrect internal wiring of the packaging layer 11 to be repaired.

[0097] Exemplarily, Figure 4 is a schematic structural diagram of a packaging layer to be repaired provided by an embodiment of the present disclosure. As Figure 4 shown, there is incorrect RDL, that is, Incorrect RDL, on the outer surface 1131 of the substrate 113 in the packaging layer to be repaired, resulting in a misconnected pin pair between this packaging layer and the external component (including an adjacent packaging layer, or an external device connected to the integrated circuit). Therefore, it is necessary to repair the Incorrect RDL on the outer surface 1131 to the correct RDL, that is, RepairRDL.

[0098] S102. Modify the first transmission path and the second transmission path on the outer surface of the substrate to obtain an integrated circuit after line repair.

[0099] According to some embodiments, the first transmission path is constituted by a first signal transmission pin and a second pin, and the second transmission path is constituted by a second signal transmission pin and a first pin.

[0100] In some embodiments, when modifying the first transmission path and the second transmission path on the outer surface of the substrate, the modification methods include but are not limited to modifying the pin body, modifying the outer surface body of the substrate, etc. The specific operation process is not limited. Finally, it is only necessary to make the first pin in contact connection with the first signal transmission pin and / or the second pin in contact connection with the second signal transmission pin.

[0101] In summary, the method provided in this embodiment can, by performing circuit repair on the outer surface of the substrate, achieve the function of local circuit modification only from the external packaging level without opening the cover, without changing the internal interconnection lines, without performing destructive operations on the chip, or only performing semi-destructive operations on the chip. It can be unrestricted by complex metal interconnection wiring layers and chip module layouts, effectively avoiding excessive damage to the chip.

[0102] Exemplarily, Figure 5 is a schematic flowchart of a circuit repair method provided by an embodiment of the present disclosure.

[0103] As Figure 5 shown, the circuit repair method may include the following steps:

[0104] S201, determine the package layer to be repaired in the integrated circuit, and the pair of misconnected pins between the package layer to be repaired and the external components;

[0105] S202, cut the first transmission path at a first cut position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path;

[0106] According to some embodiments, the first cut position refers to any position on the outer surface body of the substrate or on the first transmission path outside the outer surface of the substrate.

[0107] In some embodiments, the third transmission path refers to a part of the first transmission path including the first signal transmission pin obtained after cutting the first transmission path.

[0108] In some embodiments, the fourth transmission path refers to the part of the first transmission path other than the third transmission path obtained after cutting the first transmission path.

[0109] S203, cut the second transmission path at a second cut position corresponding to the first cut position in the second transmission path to obtain a fifth transmission path and a sixth transmission path;

[0110] According to some embodiments, Figure 6 is a schematic diagram of cutting off a transmission path provided by an embodiment of the present disclosure. As Figure 6 shown, the correspondence between the second cutting position and the first cutting position means that the second cutting position and the first cutting position are at the same level, and their specific positions on the transmission path may be the same or different.

[0111] For example, when the first cutting position is at any position on the first transmission path outside the outer surface of the substrate, the second cutting position is also at any position on the second transmission path outside the outer surface of the substrate; or, when the first cutting position is at any position on the first transmission path on the outer surface body of the substrate, the second cutting position is also at any position on the second transmission path on the outer surface body of the substrate.

[0112] In some embodiments, the fifth transmission path refers to a part of the second transmission path obtained after cutting off the second transmission path and including the second signal transmission pin. As Figure 6 shown, the fifth transmission path corresponds to the third transmission path.

[0113] In some embodiments, the sixth transmission path refers to the part of the second transmission path obtained after cutting off the second transmission path except the fifth transmission path. As Figure 6 shown, the fourth transmission path corresponds to the sixth transmission path.

[0114] S204, connect the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material, and / or connect the fourth transmission path and the fifth transmission path on the outer surface of the substrate through a conductive material to obtain an integrated circuit with repaired wiring.

[0115] According to some embodiments, the circuit interconnection line pattern between the third transmission path and the sixth transmission path can be determined; arrange the conductive material on the outer surface of the substrate according to the circuit interconnection line pattern to connect the third transmission path and the sixth transmission path through the conductive material, and / or connect the fourth transmission path and the fifth transmission path through the conductive material.

[0116] In some embodiments, the line width in the circuit interconnection line pattern can be constrained by the sizes of the first pin and the second pin. The sizes include but are not limited to the spacing between the pins, the size of the pin body, etc.

[0117] In some embodiments, after arranging the conductive material, an insulating material can also be coated on the outer surface of the conductive material to avoid being contaminated by the outside world or contacting the surrounding pins due to improper operation, resulting in a short - circuit phenomenon.

[0118] Taking a scenario as an example, Figure 7A display diagram of a circuit interconnection line pattern provided by an embodiment of the present disclosure. As Figure 7 shown, the line modification path in its circuit interconnection line pattern is relatively long, and the pins use solder balls. The standard value of the solder ball diameter (ball size) b is 0.21 mm, and the fluctuation range is 0.16 - 0.26 mm; the standard value of the ball pitch a is 0.35 mm, then the standard distance between solder balls is 0.35 - 0.21 = 0.14 mm, and its fluctuation range is 0.19 - 0.09 mm. Based on this, some constraints and requirements can be put forward for the width of the line modification path. Among them, the line width standard of the line modification path c composed of insulating material can be 0.03 mm, and the fluctuation range is 0.02 - 0.06 mm; to ensure signal stability, the line width standard of the line modification path d composed of conductive material can be line width ≥ 0.05 mm.

[0119] According to some embodiments, in order to connect different circuit elements, transmit electronic signals and supply power to circuit elements, the conductive material can use conductive metal. The conductive metal includes but is not limited to conductive glue, pure metal with good conductivity, alloy materials, etc.

[0120] Among them, gold (Au) is favored because of its excellent conductivity, chemical stability and compatibility with many semiconductor materials, but the cost is relatively high; aluminum (AL) and copper (Cu) have high electrical conductivity, high melting point and high resistance to electron migration, and have become the main back-end interconnection materials in semiconductor manufacturing. In addition, the metal materials used for packaging, including traditional lead-based alloys and lead-free antimony, tin, silver, indium-based alloys, etc., can all be used as conductive materials; the above-mentioned metals and alloy materials that can be used for conductive interconnection can be arbitrarily combined as long as they can meet the conductivity and good adhesion.

[0121] In some embodiments, based on cost considerations, conductive glue can be selected as the bonding conductive material for line repair. Conductive glue is a mixture of silver powder and polymer (such as epoxy resin). Silver powder plays a conductive role, while the polymer plays a bonding role. According to different requirements of signal transmission, conductive glue with at least one of the following formulas can be used:

[0122] Isotropic material, which can conduct electricity in all directions;

[0123] Conductive silicone rubber, which can isolate the device from the environment, prevent the influence of water vapor on the device, and at the same time can also shield electromagnetic interference;

[0124] Anisotropic conductive polymer, which can make the current flow only in one direction.

[0125] In some embodiments, when using a low-temperature conductive silver paste as a key conductive material, the adhesive can be coated onto the modified route corresponding to the circuit interconnection line pattern on the outer surface of the substrate using a syringe or a syringe, and cured at a preset temperature.

[0126] Among them, if only the need for line interconnection exists, an insulating material, such as a coating adhesive, can be first coated on the modified line as insulation to prevent silver migration.

[0127] Among them, when performing the curing treatment at the preset temperature, for example, it can be a curing treatment at 150 °C for not less than 1 hour.

[0128] According to some embodiments, when setting the conductive material on the outer surface of the substrate according to the circuit interconnection line pattern, the methods that can be adopted include but are not limited to electroless plating, electroplating, vacuum deposition coating, etc.

[0129] In some embodiments, electroless plating refers to a redox reaction in which metal ions are deposited on the specified modified route area on the outer surface of the substrate through a solution containing a certain amount of metal ions under the action of a reducing agent, and the metal ions are attached and deposited on the surface to form a dense metal coating. In this way, a metal interconnection modified route with good conductivity can be obtained at a temperature of 100 °C. In addition, for a specified line, a catalyst can be first coated to make the metal ions selectively deposited on the surface adsorbed with the catalyst. For example, when plating copper, a metal that can continuously perform chemical deposition can be selected as the catalyst, such as elements like platinum (Pt), palladium (Pd), Au, silver (Ag), etc., and formaldehyde can be used as the reducing agent.

[0130] In some embodiments, electroplating utilizes the principle of electrochemistry to deposit metal on the outer surface of the substrate. The electroplating bath types include but are not limited to simple substances such as Cu, nickel (Ni), Au, tin (Sn), and their alloys.

[0131] In some embodiments, vacuum deposition coating is a widely used thin film and coating preparation technology, mainly including physical vapor deposition (PVD) and chemical vapor deposition (CVD). It can rapidly and efficiently prepare a thin film with high density and strong bonding force on the outer surface of the substrate. In addition, deposition thin film methods derived from CVD, such as plasma-enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD), can also be adopted. In a high-vacuum working environment, it can effectively prevent adverse effects such as oxidation and corrosion of the workpiece surface or coating by air or other gases, improve the surface finish and adhesion of the sample, and can form a good interface with many other materials.

[0132] It should be noted that the interconnect materials and metallization schemes selected in the above embodiments can be arbitrarily combined according to actual needs. In this case, only the conductive silver paste with lower cost is taken as an example for illustration. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. As long as the combinations of these technical features do not conflict and can achieve the goal of circuit repair and circuit reconnect through conductive materials, they should be considered within the scope recorded in this disclosure.

[0133] In summary, the method provided in this embodiment has a relatively low operation difficulty for circuit repair. In the actual operation process, only insulating materials and conductive materials are required, which greatly saves costs compared with the FIB solution that uses a focused ion beam for circuit cutting and metal deposition.

[0134] Exemplarily, Figure 8 is a schematic flow chart of a circuit repair method provided by an embodiment of the present disclosure.

[0135] As Figure 8 shown, the circuit repair method may include the following steps:

[0136] S301, determine the encapsulation layer to be repaired in the integrated circuit, and the pair of misconnected pins between the encapsulation layer to be repaired and the external components;

[0137] Exemplarily, taking the typical scenario of verification blockage caused by hardware mismatch after the chip is returned as an example, Figure 9 is a display diagram of a pair of misconnected pins provided by an embodiment of the present disclosure. As Figure 9As shown, the chip commonly uses the Mobile Industry Processor Interface (MIPI) as a high-speed serial interface protocol. Its data transmission method with low power consumption and simplified design has gradually become a common interface for mobile devices. Figure 8 The Power Management IC (PMIC) involved in Figure 8 is a flip-chip. It uses the System Power Management Interface (SPMI) in the MIPI protocol as the hardware interface between the processor and external components, supporting better power management technology through this interface. However, in the hardware design stage, there is a situation where the SPMI interface test point (socket pin: SPMI_CLK) on the hardware PCB does not match the chip pin (FCCSP ball). The main manifestation is that the signal traces of SPMI_CLK and DGND are reversed in the inner layer of the hardware PCB. Due to the misalignment of the internal connections of SPMI_CLK and DGND and the socket pins, the excitation signal cannot be injected into the chip through the vector.

[0138] That is to say, Figure 9 In Figure 9 , the FCCSP ball: SPMI_CLK pin is the first pin, the FCCSP ball: DGND pin is the second pin, the socket pin: SPMI_CLK is the first signal transmission pin, and the socket pin: DGND is the second signal transmission pin. It is necessary to use the external solder balls of the chip to reconnect the signals to ensure the uniqueness of the SPMI_CLK pin during vector use. However, the SPMI_CLK trace in the hardware PCB is in the interlayer. Cutting the two traces and swapping them on the single hardware PCB will damage other signal traces, and it is also impossible to reconnect the two signal lines through external flying wires. Therefore, it is necessary to block the FCCSP ball: DGND pin on the chip, unplug the socket pin: DGND pin on the hardware PCB, and create a new path through rewiring to successfully transmit the SPMI_CLK signal of the socket pin: SPMI_CLK on the hardware PCB to the corresponding pin FCCSP ball: SPMI_CLK on the chip.

[0139] S302, disconnect the contact between the second pin and the first signal transmission pin to obtain a third transmission path and a fourth transmission path;

[0140] According to some embodiments, when disconnecting the contact between the second pin and the first signal transmission pin, the second pin can be completely cut off or partially cut off.

[0141] Exemplarily, Figure 10 is a cross-sectional view of an integrated circuit after line repair provided by an embodiment of the present disclosure. As Figure 10 shown, when performing line repair on the encapsulation layer to be repaired as Figure 9 shown, all the FCCSP ball: DGND pins soldered on the outer surface of the substrate 113 can be cut off, and only the pads on the solder mask (SM) on the outer surface of the substrate 113 are retained to disconnect the contact between the second pin and the first signal transmission pin.

[0142] Among them, when cutting the solder balls corresponding to the FCCSP ball: DGND pins, a hot air gun can be used for hot air blowing operation, and an electric soldering iron can be used to clean the excess residual solder.

[0143] Among them, the solder mask is a thin polymer coating that can be coated on the outer surface of the substrate, aiming to prevent oxidation and avoid forming solder bridges between closely spaced pads.

[0144] Exemplarily, Figure 11 is a cross-sectional view of an integrated circuit after line repair provided by an embodiment of the present disclosure. As Figure 10 shown, when performing line repair on the encapsulation layer to be repaired as Figure 9 shown, the FCCSP ball: DGND pins soldered on the outer surface of the substrate 113 can be partially cut off.

[0145] S303, disconnect the contact between the first pin and the second signal transmission pin to obtain a fifth transmission path and a sixth transmission path;

[0146] Exemplarily, as Figure 10 and Figure 11 shown, when performing line repair on the encapsulation layer to be repaired as Figure 9 shown, the socket pin: DGND pin in the hardware PCB can be pulled out to disconnect the contact between the first pin and the second signal transmission pin.

[0147] Among them, since there are more than one FCCSP ball: DGND pins soldered on the outer surface of the substrate 113 during chip design, and the DGND signal transmission is not required during verification, the socket pin: DGND pin in the hardware PCB can be pulled out. For other pins except the DGND pin, the line repair scheme can be adjusted according to the actual application scenario.

[0148] S304, perform a cutting process on the second pin, and set an insulating material at the third cutting position corresponding to the second pin to obtain a processed second pin;

[0149] According to some embodiments, the height corresponding to the processed second pin is determined by the maximum height threshold corresponding to the first signal transmission pin, so as to ensure the overall contact height when the external component is connected to the package layer to be repaired, and ensure the contact between the package layer to be repaired and the first signal transmission pin.

[0150] In some embodiments, the maximum height threshold does not specifically refer to a certain fixed threshold. The maximum height threshold can be determined according to the type of pins in the external component. For example, when the type of pins in the external component is socket pin, the maximum height threshold can be determined by the length and press travel of the socket pin itself.

[0151] According to some embodiments, when cutting the second pin, the second pin can be completely cut or partially cut.

[0152] In some embodiments, when the second pin is partially cut to obtain the cut second pin, in order to prevent short - circuit, an insulating material can be used to wrap the cut second pin.

[0153] According to some embodiments, the insulating material includes a first insulating material and a second insulating material. When setting the insulating material at the third cutting position corresponding to the second pin, the first insulating material and the second insulating material can be sequentially set at the third cutting position corresponding to the second pin, wherein the stiffness of the first insulating material is less than that of the second insulating material.

[0154] In some embodiments, the first insulating material can be a flexible substrate material commonly used in the back - end packaging of chips. It can be set at the third cutting position by coating. Its advantages lie in its flexibility and bending ability, light weight and low price, and it still has excellent physical and mechanical properties within a wide temperature range. It can ensure complete blocking of the transmission of the original error signal, and has good flexibility and ductility to achieve better coverage of the third cutting position.

[0155] Among them, the first insulating material includes but is not limited to polyimide (PI), polyether - ether - ketone (PEEK), polyethylene glycol terephthalate (PET), etc.

[0156] In some embodiments, the second insulating material is an insulating substrate material different from the first insulating material, which is used to ensure the overall contact height when an external component is connected to the package layer to be repaired. A rigid material with a fixed shape and form can be selected as the second insulating material to raise the height on the basis of the first insulating material. The additional advantages of the rigid material are high mechanical strength, excellent electrical insulation performance, good thermal stability, fatigue resistance, and wear resistance.

[0157] Among them, the second insulating material includes, but is not limited to, "Flame Retardant Type 4" (FR4) composite material, highly rigid and highly durable material (Ajinomoto Build-up Film, ABF), epoxy resin substrate material, Bismaleimide&Triazine (BT), ceramic material, etc.

[0158] Among them, the ceramic material includes, but is not limited to, aluminum oxide (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), silicon carbide (SiC), etc.

[0159] It should be noted that in the case where the insulating material cannot ensure the overall contact height when an external component is connected to the package layer to be repaired, a third pin can also be provided on the insulating material to obtain a processed second pin.

[0160] For example, as Figure 10 shown, after disconnecting the contact between the second pin and the first signal transmission pin, and the contact between the first pin and the second signal transmission pin, the first insulating material 114 (using PI coating glue) can be coated at the third cutting position corresponding to the FCCSP ball: DGND pin, and the second insulating material 115 (using BT) can be supplemented; then, a third pin 116 is implanted on the second insulating material 115 to obtain a processed second pin, where the third pin 116 uses a solder ball.

[0161] Among them, when implanting the solder ball on the second insulating material 115, the methods that can be used include, but are not limited to, reflow soldering process, evaporation, electroplating, screen printing, needle depositing, etc.

[0162] Among them, Figure 10 in the integrated circuit after the circuit repair shown, the heights of the first pin and the processed second pin are approximately 0.13 mm (the fluctuation range is 0.08 - 0.18 mm).

[0163] For example, as Figure 11As shown, after disconnecting the contact between the second pin and the first signal transmission pin, and the contact between the first pin and the second signal transmission pin, the first insulating material 114 (using PI coating glue) can be applied at the third cutting position, and the first insulating material 114 completely wraps the cut FCCSP ball: DGND pin; then, on the basis of the first insulating material 114, the second insulating material 115 (using BT) is supplemented to obtain the processed second pin.

[0164] S305, on the outer surface of the substrate, the first pin and the processed second pin are connected using a conductive material, so that the first signal transmission pin is connected to the first pin through the conductive material, to obtain an integrated circuit with repaired wiring.

[0165] For example, Figure 10 As shown, after obtaining the processed second pin, the third pin 116 and the FCCSP ball: SPMI_CLK pin can be connected through a conductive material 117 (using conductive silver glue), so that when the hardware PCB is connected to the package layer to be repaired, the socket pin: SPMI_CLK pin can be connected to the FCCSP ball: SPMI_CLK pin through the conductive material 117, to obtain an integrated circuit with repaired wiring as shown in Figure 10 As shown, and finally, it is verified by an oscilloscope that the originally misaligned SMPI_CLK signal has been successfully transmitted to the package layer to be repaired.

[0166] For example, Figure 11 As shown, after obtaining the processed second pin, a conductive material 116 can be provided on the second insulating material 115, so that when the hardware PCB is connected to the package layer to be repaired, the socket pin: SPMI_CLK pin can be connected to the FCCSP ball: SPMI_CLK pin through the conductive material 117 (using conductive silver glue), to obtain an integrated circuit with repaired wiring as shown in Figure 10 As shown, and finally, it is verified by an oscilloscope that the originally misaligned SMPI_CLK signal has been successfully transmitted to the package layer to be repaired.

[0167] For example, Figure 12 This is a top view of an integrated circuit with repaired wiring provided by an embodiment of the present disclosure. As shown in Figure 12 (a) therein, on the outer surface of the substrate of the package layer to be repaired, there are two pairs of misconnected pin pairs, and the first pin and the processed second pin are connected using conductive silver glue on the outer surface of the substrate; as shown in Figure 12 (b) therein, one pair of misconnected pin pairs is magnified, where position 1 is the first insulating material, position 2 is the second insulating material, and position 3 is the conductive material.

[0168] It should be noted that the above-described embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the present invention.

[0169] In summary, the method provided in this embodiment can achieve circuit cutting and reconnecting by operating on the pins, without performing destructive operations on the chip, with low operation difficulty, high circuit modification efficiency and high success rate. For cases with a short modification path, the operation can be completed in only 1-2 hours, and batch production can be carried out. Without the need for re-spinning production, it can meet a wide range of verification requirements. In addition, it is not only applicable to large-scale chip transformation verification, but also can specifically solve some problems where certain hardware designs do not match the chip.

[0170] For example, Figure 13 is a schematic flowchart of a circuit repair method provided by an embodiment of the present disclosure.

[0171] As Figure 13 shown, the circuit repair method may include the following steps:

[0172] S401, determine the encapsulation layer to be repaired in the integrated circuit, and the pair of misconnected pins between the encapsulation layer to be repaired and the external components;

[0173] For example, different from Figure 9 the signal mistransmission scenario caused by the hardware design defect shown, that is, the internal wiring error scenario of the external component, Figure 14 is a display diagram of a pair of misconnected pins provided by an embodiment of the present disclosure, which is reflected in the chip modification due to the chip's own design error or certain special verification requirements, that is, the internal wiring error of the encapsulation layer to be repaired. Its main difference from Figure 14 the circuit repair method is that it is not limited to cutting and reconnecting the pins, but operates on the outer surface of the substrate to connect the internal circuit of the substrate to the solder balls outside the substrate and the SM.

[0174] S402, determine the first area to be cut corresponding to the first cutting position and the second area to be cut corresponding to the second cutting position;

[0175] According to some embodiments, the first cutting position is located on any section of the first transmission path on the outer surface of the substrate except the second pin, and the second cutting position is located on any section of the second transmission path on the outer surface of the substrate except the first pin.

[0176] In some embodiments, the first cutting position and the second cutting position can be observed and confirmed under OM.

[0177] Exemplarily, Figure 14 Position 1 in it is the second cutting position, the area outlined by position 1 is the first area to be cut, position 2 is the first cutting position, and the area outlined by position 2 is the second area to be cut.

[0178] S403. Perform a windowing process on the first area to be cut and the second area to be cut, exposing the conductive layers in the first area to be cut and the second area to be cut, to obtain a first conductive window and a second conductive window;

[0179] Exemplarily, as Figure 14 shown, the traces of the transmission path on the outer surface of the substrate are more obvious, and the upper layer is covered by SM. Therefore, the next step to achieve the cutting target is to etch away the SM on the surfaces of the first area to be cut and the second area to be cut.

[0180] According to some embodiments, a laser device can be used to expose the areas to be operated, that is, the conductive layers in the first area to be cut and the second area to be cut. It should be noted that if the single laser area is small, the operation can be repeated multiple times.

[0181] In some embodiments, the area of the first conductive window is the same as the area of the first area to be cut, and the area of the second conductive window is the same as the area of the second area to be cut. Therefore, it can be ensured that there is no electrical connection between the third transmission path and the fourth transmission path, and between the fifth transmission path and the sixth transmission path.

[0182] S404. Perform an etching and cutting process on the first conductive window to obtain a third transmission path and a fourth transmission path;

[0183] According to some embodiments, the laser device can continue to be used to adjust the laser energy for the etching and cutting process.

[0184] S405. Perform an etching and cutting process on the second conductive window to obtain a fifth transmission path and a sixth transmission path;

[0185] Exemplarily, as Figure 14 shown, continue to use the laser device to adjust the laser energy to perform an etching and cutting process on the copper wire (Cutrace) in the areas outlined by position 1 and position 2.

[0186] S406. Perform a windowing process on the sixth transmission path provided on the outer surface of the substrate, exposing the conductive layer in the sixth transmission path, to obtain a third conductive window;

[0187] According to some embodiments, the area of the third conductive window is not greater than the area of the sixth transmission path provided on the outer surface of the substrate.

[0188] Exemplarily, asFigure 14 As shown, the area outlined by the position 3 is the third conductive window, and its upper layer is covered by SM. Therefore, the next step to achieve the interconnection goal is to etch away the SM on the surface of the third conductive window.

[0189] In some embodiments, the third conductive window can be exposed by a laser device.

[0190] It should be noted that steps S403 and S406 can be executed first to expose the first conductive window, the second conductive window, and the third conductive window, as Figure 15 shown. Then steps S404 and S405 are executed to perform an etching and cutting process on the first conductive window and the second conductive window.

[0191] S407, connect the third conductive window and the second pin through a conductive material, so that the first signal transmission pin is connected to the sixth transmission path through the second pin and the conductive material, to obtain an integrated circuit after line repair.

[0192] According to some embodiments, when connecting the third conductive window and the second pin through a conductive material, a material with fluidity such as conductive silver paste can be used, or wire bonding can also be selected.

[0193] Exemplarily, Figure 14 the arrow connected to the position 3 is used to indicate that the position 3 needs to be connected to the solder ball indicated by the arrow. Figure 16 This is a schematic diagram of line repair provided by an embodiment of the present disclosure. As Figure 15 shown, it selects conductive silver paste to connect the third conductive window and the second pin.

[0194] In some embodiments, when wire bonding is selected, solderable points can be made in the third conductive window. One end of a metal wire is first soldered to the solderable point, and the other end is bonded to any position on the edge of the substrate. The metal wire is cut to the required length, and a small amount of conductive silver paste is used to bond the metal wire to the chip solder ball and press and fix it.

[0195] Exemplarily, Figure 17 This is a schematic diagram of line repair provided by an embodiment of the present disclosure. As Figure 17 shown, it uses Au wire to connect the third conductive window and the second pin.

[0196] According to some embodiments, an insulating material can be coated at least at one of the following locations:

[0197] The cut-off position after the etching and cutting process of the first conductive window;

[0198] The cut-off position after the etching and cutting process of the second conductive window;

[0199] The outer surface of the conductive material.

[0200] Among them, applying an insulating material at the cut opening position can prevent the internal material from being contaminated by the outside world, or from coming into contact with the surrounding solder balls due to improper operation, resulting in a short - circuit phenomenon.

[0201] Among them, when the conductive material is a material with fluidity such as conductive silver paste, applying an insulating material on the outer surface of the conductive material can prevent the conductive material from being contaminated by the outside world, or from coming into contact with the surrounding solder balls due to improper operation, resulting in a short - circuit phenomenon.

[0202] The above - described embodiments only represent several implementation manners of the present disclosure. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can be made, and these all belong to the protection scope of the present invention.

[0203] In summary, the method provided in this embodiment realizes circuit cutting and reconnecting by operating on the outer surface of the substrate, only performs semi - destructive operations on the chip, has a low operation difficulty, and at the same time has a high efficiency and success rate in circuit modification, can be mass - produced, and can meet a wide range of verification requirements in the stage of not re - taping. In addition, it is not only applicable to large - scale chip modification verification, but also can specifically solve chip modification problems.

[0204] To implement the above - mentioned embodiment, the present disclosure also proposes a circuit repair device.

[0205] As Figure 18 shown, the circuit repair device 1800 includes:

[0206] A pin determination unit 1801, configured to determine the encapsulation layer to be repaired in the integrated circuit, and the pair of misconnected pins between the encapsulation layer to be repaired and the external component. Among them, the encapsulation layer to be repaired includes a substrate, and the pair of misconnected pins includes a first pin and a second pin provided on the outer surface of the substrate, and a first signal transmission pin and a second signal transmission pin of the external component. Among them, the second pin is in contact connection with the first signal transmission pin, and the first pin is in contact connection with the second signal transmission pin;

[0207] A path modification unit 1802, configured to modify the first transmission path and the second transmission path on the outer surface of the substrate to obtain the integrated circuit after circuit repair. Among them, the first transmission path is constituted by the first signal transmission pin and the second pin, and the second transmission path is constituted by the second signal transmission pin and the first pin.

[0208] Optionally, when the path modification unit 1802 is configured to modify the first transmission path and the second transmission path on the outer surface of the substrate, it is specifically configured to:

[0209] Cut the first transmission path at a first cutting position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path, where the third transmission path includes a first signal transmission pin;

[0210] Cut the second transmission path at a second cutting position corresponding to the first cutting position in the second transmission path to obtain a fifth transmission path and a sixth transmission path, where the fifth transmission path includes a second signal transmission pin, the fifth transmission path corresponds to the third transmission path, and the fourth transmission path corresponds to the sixth transmission path;

[0211] Connect the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material, and / or connect the fourth transmission path and the fifth transmission path on the outer surface of the substrate through a conductive material.

[0212] Optionally, when the path modification unit 1802 is used to cut the first transmission path at a first cutting position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path, and cut the second transmission path at a second cutting position corresponding to the first cutting position in the second transmission path to obtain a fifth transmission path and a sixth transmission path, it is specifically used for:

[0213] Disconnect the contact between the second pin and the first signal transmission pin to obtain a third transmission path and a fourth transmission path;

[0214] Disconnect the contact between the first pin and the second signal transmission pin to obtain a fifth transmission path and a sixth transmission path.

[0215] Optionally, when the path modification unit 1802 is used to connect the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material, it is specifically used for:

[0216] Cut the second pin and set an insulating material at a third cutting position corresponding to the second pin to obtain a processed second pin, where the height corresponding to the processed second pin is determined by the maximum height threshold corresponding to the first signal transmission pin;

[0217] Connect the first pin and the processed second pin on the outer surface of the substrate with a conductive material so that the first signal transmission pin is connected to the first pin through the conductive material.

[0218] Optionally, when the path modification unit 1802 is used to cut the second pin and set an insulating material at a third cutting position corresponding to the second pin, it is specifically used for:

[0219] Cut the second pin completely and set an insulating material at a third cutting position corresponding to the second pin; or,

[0220] Partially cut the second pin to obtain the cut second pin. Set an insulating material at the third cut position corresponding to the second pin, and wrap the cut second pin with the insulating material.

[0221] Optionally, the path modification unit 1802 is used for the insulating material including a first insulating material and a second insulating material. When setting the insulating material at the third cut position corresponding to the second pin, it is specifically used for:

[0222] Set the first insulating material and the second insulating material in sequence at the third cut position corresponding to the second pin, wherein the stiffness of the first insulating material is less than that of the second insulating material.

[0223] Optionally, when the path modification unit 1802 is used to set the insulating material at the cut position corresponding to the second pin to obtain the processed second pin, it is specifically used for:

[0224] Set the insulating material at the third cut position corresponding to the second pin, and set the third pin on the insulating material to obtain the processed second pin.

[0225] Optionally, when the path modification unit 1802 is used to cut the first transmission path at the first cut position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path, and cut the second transmission path at the second cut position corresponding to the first cut position in the second transmission path to obtain a fifth transmission path and a sixth transmission path, it is specifically used for:

[0226] Determine a first to-be-cut area corresponding to the first cut position and a second to-be-cut area corresponding to the second cut position, wherein the first cut position is located on any section of the first transmission path other than the second pin on the outer surface of the substrate, and the second cut position is located on any section of the second transmission path other than the first pin on the outer surface of the substrate;

[0227] Perform a window opening process on the first to-be-cut area and the second to-be-cut area to expose the conductive layers of the first to-be-cut area and the second to-be-cut area, obtaining a first conductive window and a second conductive window, wherein the area of the first conductive window is the same as the area of the first to-be-cut area, and the area of the second conductive window is the same as the area of the second to-be-cut area;

[0228] Perform an etching and cutting process on the first conductive window to obtain a third transmission path and a fourth transmission path;

[0229] Perform an etching and cutting process on the second conductive window to obtain a fifth transmission path and a sixth transmission path.

[0230] Optionally, when the path modification unit 1802 is used to connect the third transmission path and the sixth transmission path through a conductive material on the outer surface of the substrate, it is specifically configured to:

[0231] Perform a windowing process on the sixth transmission path provided on the outer surface of the substrate to expose the conductive layer inside the sixth transmission path, obtaining a third conductive window;

[0232] Connect the third conductive window and the second pin through a conductive material, so that the first signal transmission pin is connected to the sixth transmission path through the second pin and the conductive material.

[0233] Optionally, apply an insulating material at least at one of the following locations:

[0234] The cut-off position after the etching cut-off process of the first conductive window;

[0235] The cut-off position after the etching cut-off process of the second conductive window;

[0236] The outer surface of the conductive material.

[0237] Optionally, when the path modification unit 1802 is used to connect the third transmission path and the sixth transmission path through a conductive material on the outer surface of the substrate, it is specifically configured to:

[0238] Determine the circuit interconnection line pattern between the third transmission path and the sixth transmission path;

[0239] Arrange a conductive material on the outer surface of the substrate according to the circuit interconnection line pattern to connect the third transmission path and the sixth transmission path through the conductive material, and / or connect the fourth transmission path and the fifth transmission path through the conductive material.

[0240] It should be noted that the foregoing explanation of the embodiment of the line repair method also applies to the line repair device of this embodiment, and will not be repeated here.

[0241] In summary, the device provided by the embodiments of the present disclosure can perform line repair on the outer surface of the substrate, and can realize the local circuit modification function only from the external packaging level without opening the cover, without changing the internal interconnection lines, without performing destructive operations on the chip or only performing semi-destructive operations on the chip. It can be unrestricted by complex metal interconnection wiring layers and chip module layouts, effectively avoiding excessive damage to the chip.

[0242] To implement the above embodiments, the present disclosure also proposes a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method provided by the foregoing embodiments.

[0243] To implement the above embodiments, the present disclosure also provides a computer program product, including a computer program which, when executed by a processor, implements the method provided by the foregoing embodiments.

[0244] The present disclosure also provides an electronic device, including: an integrated circuit obtained by performing circuit repair on an integrated circuit by using the method provided by the embodiments. Among them, the electronic device includes but is not limited to devices such as mobile terminals and vehicles.

[0245] The collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved in the present disclosure and other processing are all in compliance with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0246] It should be noted that personal information from users should be collected for legal and reasonable purposes and should not be shared or sold outside of these legal uses. In addition, such collection / sharing should be carried out after obtaining the informed consent of the user, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization including authorizing relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0247] The present disclosure anticipates providing embodiments that allow users to selectively block the use or access of personal information data. That is, the present disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, the risk can be minimized by restricting data collection and deleting the data. In addition, when applicable, personal identifiers are removed from such personal information to protect the privacy of users.

[0248] In the description of the foregoing embodiments, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0249] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0250] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations, where functions may be performed in a substantially simultaneous manner or in an order opposite to that shown or discussed, according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0251] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function and can be specifically implemented in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0252] It should be understood that various parts of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one of the following techniques known in the art or a combination thereof can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with suitable combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0253] Those of ordinary skill in the art can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0254] In addition, in each embodiment of the present disclosure, each functional unit can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0255] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A circuit repair method, characterized in that, Including: Determine a package layer to be repaired in an integrated circuit, and a pair of misconnected pins between the package layer to be repaired and an external component, where the package layer to be repaired includes a substrate, and the pair of misconnected pins includes a first pin and a second pin provided on an outer surface of the substrate, and a first signal transmission pin and a second signal transmission pin of the external component, where the second pin is in contact connection with the first signal transmission pin, and the first pin is in contact connection with the second signal transmission pin; Modify a first transmission path and a second transmission path on the outer surface of the substrate to obtain an integrated circuit with repaired wiring, where the first transmission path is constituted by the first signal transmission pin and the second pin, and the second transmission path is constituted by the second signal transmission pin and the first pin.

2. The method according to claim 1, wherein The modifying the first transmission path and the second transmission path on the outer surface of the substrate includes: Cut the first transmission path at a first cutting position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path, where the third transmission path includes the first signal transmission pin; Cut the second transmission path at a second cutting position corresponding to the first cutting position in the second transmission path to obtain a fifth transmission path and a sixth transmission path, where the fifth transmission path includes the second signal transmission pin, the fifth transmission path corresponds to the third transmission path, and the fourth transmission path corresponds to the sixth transmission path; Connect the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material, and / or connect the fourth transmission path and the fifth transmission path on the outer surface of the substrate through a conductive material.

3. The method according to claim 2, wherein Cutting the first transmission path at a first cutting position on the outer surface of the substrate to obtain a third transmission path and a fourth transmission path, and cutting the second transmission path at a second cutting position corresponding to the first cutting position in the second transmission path to obtain a fifth transmission path and a sixth transmission path includes: Disconnect the contact between the second pin and the first signal transmission pin to obtain a third transmission path and a fourth transmission path; Disconnect the contact between the first pin and the second signal transmission pin to obtain a fifth transmission path and a sixth transmission path.

4. The method according to claim 3, wherein The connecting the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material includes: Cut the second pin and set an insulating material at a third cutting position corresponding to the second pin to obtain a processed second pin, where the height corresponding to the processed second pin is determined by a maximum height threshold corresponding to the first signal transmission pin; Connect the first pin and the processed second pin on the outer surface of the substrate by using a conductive material, so that the first signal transmission pin is connected to the first pin through the conductive material.

5. The method according to claim 4, characterized in that, Cutting the second pin and disposing an insulating material at a third cutting position corresponding to the second pin includes: Fully cutting the second pin and disposing an insulating material at a third cutting position corresponding to the second pin; or Partially cutting the second pin to obtain a cut second pin, disposing an insulating material at a third cutting position corresponding to the second pin, and wrapping the cut second pin with the insulating material.

6. The method according to claim 4, wherein The insulating material includes a first insulating material and a second insulating material. Disposing the insulating material at a third cutting position corresponding to the second pin includes: Sequentially disposing the first insulating material and the second insulating material at a third cutting position corresponding to the second pin, wherein the stiffness of the first insulating material is less than that of the second insulating material.

7. The method according to claim 4, characterized in that, Disposing an insulating material at a cutting position corresponding to the second pin to obtain a processed second pin includes: Disposing an insulating material at a third cutting position corresponding to the second pin, and disposing a third pin on the insulating material to obtain a processed second pin.

8. The method according to claim 2, characterized in that The first cutting transmission path and the sixth transmission path on the outer surface of the substrate include: Determining a first to-be-cut area corresponding to a first cutting position and a second to-be-cut area corresponding to a second cutting position, wherein the first cutting position is located on any section of a first transmission path other than the second pin on the outer surface of the substrate, and the second cutting position is located on any section of a second transmission path other than the first pin on the outer surface of the substrate; Performing a windowing process on the first to-be-cut area and the second to-be-cut area to expose the conductive layers of the first to-be-cut area and the second to-be-cut area, obtaining a first conductive window and a second conductive window, wherein the area of the first conductive window is the same as the area of the first to-be-cut area, and the area of the second conductive window is the same as the area of the second to-be-cut area; Performing an etching and cutting process on the first conductive window to obtain a third transmission path and a fourth transmission path; Performing an etching and cutting process on the second conductive window to obtain a fifth transmission path and a sixth transmission path.

9. The method according to claim 8, wherein Connecting the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material includes: Performing a windowing process on the sixth transmission path disposed on the outer surface of the substrate to expose the conductive layer inside the sixth transmission path, obtaining a third conductive window; Connecting the third conductive window and the second pin through a conductive material, so that the first signal transmission pin is connected to the sixth transmission path through the second pin and the conductive material.

10. The method according to claim 9, wherein Coating an insulating material at at least one of the following locations: The cutting position after performing the etching and cutting process on the first conductive window; The cutting position after performing the etching and cutting process on the second conductive window; The outer surface of the conductive material.

11. The method according to claim 2, wherein Connecting the third transmission path and the sixth transmission path on the outer surface of the substrate through a conductive material includes: Determine the circuit interconnection line pattern between the third transmission path and the sixth transmission path; Arrange a conductive material on the outer surface of the substrate according to the circuit interconnection line pattern, so as to connect the third transmission path and the sixth transmission path through the conductive material, and / or connect the fourth transmission path and the fifth transmission path through the conductive material.

12. A circuit repair device, characterized in that, Comprising: A pin determination unit, configured to determine a to-be-repaired package layer in an integrated circuit and an incorrect connection pin pair between the to-be-repaired package layer and an external component, wherein the to-be-repaired package layer includes a substrate, and the incorrect connection pin pair includes a first pin and a second pin arranged on the outer surface of the substrate, and a first signal transmission pin and a second signal transmission pin of the external component, wherein the second pin is in contact connection with the first signal transmission pin, and the first pin is in contact connection with the second signal transmission pin; A path modification unit, configured to modify a first transmission path and a second transmission path on the outer surface of the substrate to obtain an integrated circuit after line repair, wherein the first transmission path is constituted by the first signal transmission pin and the second pin, and the second transmission path is constituted by the second signal transmission pin and the first pin.

13. An integrated circuit after circuit repair, characterized in that, Wherein, The integrated circuit after line repair is an integrated circuit obtained by performing line repair on an integrated circuit by using the method according to any one of claims 1 to 11.

14. An electronic device, characterized in that, Comprising: The integrated circuit after line repair according to claim 13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the method according to any one of claims 1 to 11.

16. A computer program product, characterized in that, Comprising a computer program, which when executed by a processor, implements the method according to any one of claims 1 to 11.

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