Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes forming a wafer and etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer. A first portion of the second dielectric layer of the wafer is directly under the first trench. A laser grooving process is then performed to remove the first portion of the second dielectric layer of the wafer to form a second trench below the first trench and connected to the first trench. The second dielectric layer includes a corner region at which the first trench and the second trench are joined. A portion of a top surface of the corner region near a center line of the second trench is gradually lower than a corresponding portion of the top surface of the corner region away from the center line. The embodiment of the invention also discloses a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The packaging of integrated circuits is becoming increasingly complex, with more device dies integrated in the same package to achieve more functions. For example, a package can be formed to include multiple device dies in the same package, such as a processor and a memory cube. The package can include device dies formed using different technologies and having different functions bonded to the same device die, thereby forming a system. This can save manufacturing costs and achieve optimized device performance.

[0003] In a package, a die can be bonded to a package component die by bonding. A chip is a part of a wafer, and the wafer is sawed into multiple identical dies. The bonding of the die to the package component can be performed by one of various bonding schemes, such as solder bonding, direct metal-to-metal bonding, hybrid bonding (including dielectric-to-dielectric bonding and metal-to-metal bonding), etc. Summary of the Invention

[0004] According to one aspect of embodiments of the present application, a method of forming a semiconductor structure is provided, including: forming a wafer; etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer, wherein a first portion of a second dielectric layer of the wafer is directly located under the first trench; and performing a laser grooving process to remove the first portion of the second dielectric layer of the wafer, wherein a second trench is formed, the second trench is located under the first trench and joined to the first trench, wherein the second dielectric layer includes a corner region, the first trench and the second trench are joined at the corner region, and wherein a portion of the top surface of the corner region close to the center median line of the second trench is gradually lower than a corresponding portion of the top surface of the corner region away from the center median line.

[0005] According to another aspect of embodiments of the present application, a method of forming a semiconductor structure is provided, including: forming a wafer; etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer, wherein a first portion of a second dielectric layer of the wafer is directly located under the first trench; and performing a laser grooving process to remove the first portion of the second dielectric layer and form a second trench, wherein the laser grooving process is performed using a picosecond laser beam.

[0006] According to yet another aspect of embodiments of the present application, a semiconductor structure is provided, including: a device die, the device die including: a semiconductor substrate including a first edge; a first dielectric layer located below the semiconductor substrate, wherein the first dielectric layer includes: a bottom surface; and a corner surface connecting the bottom surface to the first edge, wherein a portion of the corner surface closer to the first edge is gradually higher than a corresponding portion of the corner surface closer to the bottom surface; and a second dielectric layer located below and in contact with the first dielectric layer, wherein the second dielectric layer includes a second edge that is laterally recessed from the first edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 - 4 、 Figure 5A 、 Figure 5B and Figure 6 show cross-sectional views of an intermediate stage of wafer dicing and die packaging according to some embodiments.

[0009] Figure 7 show enlarged views of die corner portions according to some embodiments.

[0010] Figure 8 show a plan view of the roughness of a die corner portion according to some embodiments.

[0011] Figures 9 - 17 show enlarged views of die corner portions according to some embodiments.

[0012] Figure 18 show a top view of a wafer according to some embodiments.

[0013] Figures 19 - 22 illustrate the relationship between laser pulse count and the position of a laser grooved portion according to some embodiments.

[0014] Figure 23 show a process flow for forming a package according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0016] Furthermore, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientations shown in the figures, the spatial relationship terms are intended to encompass different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0017] A wafer dicing process, corresponding die, and encapsulation process are provided. According to some embodiments of the present disclosure, the wafer dicing process includes an etching process for etching a scribe region of the wafer. A laser grooving process is performed on the etched portion of the wafer. The laser grooving process is controlled to form a gradually changing angle. The laser grooving process may be performed by low-power laser pulses, thereby reducing the roughness of the corner portion. Since the corner portion of the die has a gradually changing and less rough corner portion, the die can be encapsulated in a molding compound without generating voids.

[0018] The embodiments discussed herein are intended to provide examples to enable the making or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0019] Figures 1 to 6 Shown are intermediate stages during a wafer dicing process, corresponding die, and cross-sectional views of a package formed using the die, according to some embodiments of the present disclosure. As Figure 23 shown, the corresponding process is also schematically reflected in process flow 200.

[0020] Figure 1Shows a cross-sectional view of the packaged component 2. According to some embodiments, the packaged component 2 is a device wafer including active devices (such as transistors and / or diodes) and possibly passive devices (such as capacitors, inductors, resistors, etc.). Multiple device dies 4 can be included in the packaged component 2, and the edge portions of two device dies 4 are shown therein. The device die 4 may alternatively be referred to as a chip hereinafter. According to some embodiments, the device die 4 is a memory die, such as a dynamic random access memory (DRAM) die or a static random access memory (SRAM) die. The device die 4 can also be a logic chip, which can be a central processing unit (CPU) chip, a microcontroller unit (MCU) chip, an input / output (IO) chip, a baseband (BB) chip, an application processor (AP) chip, etc.

[0021] According to some embodiments, the wafer 2 includes a semiconductor substrate 20 and features formed on the top surface of the semiconductor substrate 20. The semiconductor substrate 20 can be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, etc. The semiconductor substrate 20 can also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) can be formed in the semiconductor substrate 20 to isolate the active regions within the semiconductor substrate 20. Although not shown, vias can (or may not) be formed to extend into the semiconductor substrate 20, and the vias are used to electrically interconnect components on opposite sides of the wafer 2.

[0022] According to some embodiments, the wafer 2 includes integrated circuit devices 28, which can be formed on the top surface of the semiconductor substrate 20. Example integrated circuit devices can include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit devices are not shown here. According to alternative embodiments, the wafer 2 is used to form an interposer without active and passive devices.

[0023] An interconnect structure 30 is formed on the integrated circuit and can include an interlayer dielectric (ILD, one of the dielectric layers 32) formed on the semiconductor substrate 20. The ILD fills the space between the gate stacks of transistors (not shown) in the integrated circuit devices. According to some embodiments, the ILD is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, etc. The ILD can be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0024] Contact plugs (not shown) are formed in the ILD for electrically connecting the integrated circuit device to the overlying metal lines and vias 34. According to some embodiments, the contact plugs are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys, and / or their multilayers. The formation of the contact plugs can include forming a contact opening in the ILD, filling the contact opening with the conductive material, and performing a planarization process (such as a chemical mechanical polishing (CMP) process) to make the top surface of the contact plug flush with the top surface of the ILD.

[0025] The interconnect structure 30 includes a dielectric layer 32, which includes an ILD and a dielectric layer on the ILD. Hereinafter, the dielectric layer 32 on the ILD may alternatively be referred to as an intermetal dielectric (IMD) layer 32. According to some embodiments, some of the lower dielectric layers in the dielectric layer 32 are formed of a low-k dielectric material having a dielectric constant (k value) lower than about 3.8, and may be lower than about 3.5 or about 3.0. Thus, the IMD can be an extremely low-k dielectric layer. The dielectric layer 32 can be formed of a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0026] According to an alternative embodiment of the present disclosure, some or all of the dielectric layers 32 are formed of a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), etc. An etch stop layer (not shown), which can be formed of silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, etc. or their multilayers, can be formed between the IMD layers 32 and is not shown for simplicity.

[0027] Metal lines and vias 34 are formed in the dielectric layer 32. Hereinafter, the metal lines 34 at the same level are collectively referred to as metal layers. According to some embodiments, the interconnect structure 30 includes a plurality of metal layers interconnected by vias. The metal lines and vias 34 can be formed by a single damascene and / or dual damascene process. The metal lines and vias 34 can include a diffusion barrier layer and a copper-containing metal material located above the corresponding diffusion barrier layer. The diffusion barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0028] The metal line 34 includes a metal line / pad 34A, which is sometimes referred to as the top metal line / pad. The top metal line / pad 34A is also collectively referred to as the top metal layer. The corresponding dielectric layer 38 can be formed of a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc.

[0029] According to some embodiments, a dielectric layer 40 is formed on the top metal layer. It should be understood that the illustrated dielectric layers 38, 40, and 42 are examples, and the wafer 2 may include different materials and layers than those shown. The dielectric layer 40 represents a dielectric layer that may be employed in the wafer 2. According to some embodiments, the dielectric layer 40 is formed of or includes an inorganic dielectric material, such as silicon oxide, silicon oxynitride, silicon carbonitride, USG, etc.

[0030] According to some embodiments, a dielectric layer 42 is formed as the top layer of the wafer 2. The dielectric layer 42 can be used for fusion bonding and may thus be alternatively referred to as the bonding layer 42 hereinafter. The bonding layer 42 can be deposited using plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), plasma enhanced ALD (PEALD), etc. The bonding layer 42 can be formed of or include a silicon-containing dielectric material. According to some embodiments, the material of the bonding layer 42 can be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, SiO2, etc. The bonding layer 42 can be formed of a dielectric material different from or the same as the dielectric material of the dielectric layer 40.

[0031] As Figure 1 shown, vias 44 and pads 46 are formed. According to some embodiments, the formation process of the vias 44 and pads 46 can include two single damascene processes or a dual damascene process. The damascene process can include etching the dielectric layers 42 and 40 to form trenches and via openings, and filling the trenches and via openings with a conformal barrier layer and a metal material. According to some embodiments, the barrier layer includes Ti, TiN, Ta, TaN, etc. The metal material can include copper. Then, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, can be performed to remove the excess portions of the barrier layer and the metal material. The remaining portions of the barrier layer and the metal material are the vias 44 and pads 46. Thus, the top surface of the bonding pad 46 is coplanar with the top surface of the bonding layer 42.

[0032] Referring Figure 18 , which shows a top view of the wafer 2, a plurality of device dies 4 are arranged in an array including a plurality of rows and columns. A plurality of scribe lines 6 are located between the device dies 4. According to some embodiments, a seal ring 50 is formed to surround the active region 49 of the device die 4. The active region 49 is used to form functional integrated circuits (active devices and passive devices) and interconnect structures. The seal ring 50 can be formed as a complete ring without breaks in the top view.

[0033] Before the wafer 2 is diced, the outer edge of the sealing ring 50 can be regarded as the outer boundary of the device die 4. However, it can be understood that some portions of the scribe line 6 will remain outside the sealing ring 50 of the discrete device die 4 in the subsequent die sawing process. Therefore, after the singulation process of sawing the wafer 2 into discrete device dies 4, the discrete device die 4 can also include some portions outside the corresponding sealing ring 50. Therefore, the discrete device die 4 generated by sawing the wafer 2 is larger than the portion within the outer edge of the sealing ring 50.

[0034] According to some embodiments, each device die 4 can include a single sealing ring. Alternatively, each device die 4 can include multiple sealing rings, with an outer sealing ring surrounding a corresponding inner sealing ring. When multiple sealing rings are formed for each device die 4, the shown sealing ring 50 is the outermost sealing ring closest to the scribe line.

[0035] Reference Figure 1 , an etch mask 58 is formed on the wafer 2 and patterned, and a trench 60 is formed in the etch mask 50 to expose the underlying wafer 2. As Figure 23 shown, in process 200, the corresponding process is shown as process 202. The patterned etch mask 58 covers the entire device die 4 and further directly extends onto (and overlaps with) some portions of the scribe line 6. The etch mask 58 can include photoresist and can include or not include an anti-reflective coating. The etch mask 58 can also be a single-layer etch mask, a double-layer etch mask, or a triple-layer etch mask. According to some embodiments, there is a single trench 60 above the scribe line 6. According to alternative embodiments, there are two trenches 60 above the scribe line 6, and a portion of the etch mask 58 (as shown by the dashed line) remains between the two trenches 60.

[0036] Reference Figure 2 , and then an anisotropic etching process is performed to etch the wafer 2, causing the trench 60 to extend further downward to the top of the wafer 2. The bonding layer 42 is etched through. According to some embodiments, the trench 60 extends to the same level as the bottom surface of the bonding layer 42 (within the process variation range). According to some embodiments, the etching includes a dry etching process, which can be a plasma etching process. Depending on the materials of the bonding layer 42 and the dielectric layer 40, the etching gas can include a mixture of NF3 and NH3, a mixture of HF and NH3, CF4, NF3, SF6, CHF3, ClF3, or a combination of one or more of these gases. Other gases such as O2, N2, H2, NO, etc. can also be added. A sputtering gas such as argon can be added, so that some sputtering effects can be utilized to enhance the anisotropic effect.

[0037] In an etching process, according to some embodiments, when the dielectric layer 40 is formed of a dielectric material different from that of the bonding layer 42, the dielectric layer 40 can be used as an etch stop layer. According to some embodiments, where the bonding layer 42 is formed of the same dielectric material as the dielectric layer 40, or the bonding layer 42 and the dielectric layer 40 include different dielectric materials, but the difference is not sufficient to create enough etch selectivity, the etching can also be stopped using a time mode.

[0038] The bottom of the trench 60 can be higher than the top surface of the substrate 20. Thus, a dielectric layer can be left over the underlying trench 60, which can be a remaining portion of the dielectric layer 40. According to some embodiments, the bottom of the trench is flat, as Figure 2 shown. According to an alternative embodiment, the process conditions of the plasma etching process are adjusted such that the middle portion of the bottom of the trench 60 is higher than the edge portion, and the bottom surface is represented by a dashed line labeled 60B. The profile of the bottom 60B can be achieved by utilizing the charging effect due to plasma charge accumulation, for example, by adjusting the height of the etch mask 58 to an appropriate value.

[0039] In addition, as Figure 2 shown, there may be a trench 60 in each scribe line 6. The trench 60 can cross the center line 60M of the scribe line 6, which is in the middle of the scribe line 6 and has an equal distance from the sealing ring 50 in the opposite device die 4. According to an alternative embodiment, there are two trenches 60 extending into the wafer 2, and the unetched portion of the dielectric layer 40 / 42 (as shown by the dashed line) remains between the two trenches 60.

[0040] Referring to Figure 18 the top view of the wafer 2 shown, a plurality of trenches 60 are formed and interconnected as a grid. The scribe lines 6 are also interconnected as a grid, and the grid of the trenches 60 is located within the grid of the scribe lines 6, and the edges of the trenches 60 are spaced apart from the boundaries of the scribe lines 6.

[0041] After the etching process, the etch mask 58 as Figure 2 shown is removed. Next, the front side of the wafer 2 can be attached to a backside grinding tape (not shown). Then a backside grinding process can be performed, thereby thinning the substrate 20 of the wafer 2. After the backside grinding process, the wafer 2 is separated from the backside grinding tape. Next, as Figure 3 shown, the backside of the wafer 2 is attached to a dicing tape 60 fixed to a frame 62.

[0042] Subsequently, as Figure 4 shown, a laser grooving process is performed using a laser beam 68, thereby forming a trench 66 extending downward from the bottom of the trench 60. As Figure 23 shown, in process flow 200, the corresponding process is shown as process 204.

[0043] According to some embodiments, a laser grooving process is performed until the bottom of the trench 66 reaches at least or can extend into the semiconductor substrate 20. In the laser grooving process, the dielectric material and the pseudo-conductive components (not shown) on the path of the trench 66 are removed. According to some embodiments, the trench 66 is located in the middle of the trench 60, and the opposite edges of the trench 66 have equal distances from the nearest opposite edges of the trench 60.

[0044] According to some embodiments, as Figure 18 shown, a plurality of trenches 66 are formed in the wafer 2, and each trench is located in a scribe line 6 and a corresponding trench 60. In a top view of the wafer 2, the trenches 66 are also interconnected in a grid form. In the top view, the trenches 66 are located inside and are narrower than the corresponding trenches 60. The edges of the trenches 66 are spaced apart from the edges of the trenches 60, as Figure 3 and Figure 18 shown.

[0045] According to some embodiments, the laser grooving process is performed by projecting laser pulses onto the wafer 2. Each pulse of the laser pulses has a low power, so more pulses are used, and the surface of the projected part of the resulting wafer 2 is smoother. For example, the laser grooving process can be performed by picosecond laser pulses. Figure 4 An example laser beam generator and projector 72 are shown, which generates a laser beam 68 and projects the laser beam 68 onto the wafer 2. The lens 70 is also used to focus the laser beam 68 and generate a small laser beam spot.

[0046] According to some embodiments, the wafer 2 has trenches 66 with continuously increasing depth, where the depth of the trenches 66 gradually and continuously increases from the region far from the midline 6M of the scribe line 6 to the regions closer to the suddenly deepened part of the trenches 66. The midline 6M of the scribe line 6 can also be the midline 66M of the trenches 66. The suddenly deepened part of the trenches 66 has formed steep sidewalls 66SW1 and SW2 (collectively referred to as sidewalls 66SW), and these sidewalls can be vertical or slightly inclined, which will be discussed in more detail in the following paragraphs.

[0047] According to some embodiments, in the laser grooving process, the laser beam 68 is projected onto the part of the scribe line 6 between the end points (positions) 66E1 and 66E2, and the part outside the part between the end points 66E1 and 66E2 of the scribe line 6 is not grooved. The points 66D1 and 66D2 mark the positions where the sidewalls 66SW1 and 66SW2 are to be formed.

[0048] The surface 74 is formed between the end point 66E1 and the side wall 66SW1, and between the end point 66E2 and the side wall 66SW2. In one embodiment, from the end point 66E1 to the point 66D1, and from the end point 66E2 to the point 66D2, the depth of the groove 66 (measured from the height of the end point 66El) gradually and continuously increases (with a small roughness due to process variations). The points (positions) 66D1 and 66D2 are the points where the depth of the groove 66 suddenly increases. According to some embodiments, the surface 74 is curved. According to alternative embodiments, the surface 74 is straight. Reference Figures 12 - 17 The profile of the surface 74 is discussed in detail.

[0049] According to some embodiments, the laser generator and the projector 72 generate and project a plurality of laser pulses to ablate the wafer 2. Each laser pulse removes a portion of the material that receives the laser pulse. According to some embodiments, the laser pulses have the same energy. According to alternative embodiments, the laser pulses have different energies. For example, the end points 66E1 and 66E2 can be formed by laser pulses with energies lower than the portion of the groove 66 between the side walls 66SW1 and 66SW2, so that the desired profile can be formed without sacrificing the efficiency of the laser grooving process.

[0050] To form the surface 74 with small roughness and an ideal profile, the power carried by each laser pulse is small. This can be achieved by reducing the length of a single pulse. For example, picosecond laser pulses can be used, where the duration of each laser pulse can be in the range of about 1 picosecond to about 100 picoseconds. The power carried by each pulse can be determined according to the desired small roughness discussed. For example, different power levels can be used to experiment on multiple samples with the same structure. Higher power will result in higher roughness, and vice versa. Measure the roughness of multiple samples. Use a small enough power to achieve the desired roughness, but not too small to unnecessarily reduce throughput.

[0051] The gradually varying surface 74 is achieved by adjusting the power of the laser pulses used to ablate different parts of the wafer 2. The deeper part of the groove 66 can be formed by more laser pulses, and vice versa. Figure 19 The line 77 according to some embodiments is shown, which represents the count of laser pulses projected onto each point between the end points 66E1 and 66E2 (marked in Figure 19 and also referenced in Figure 4 ), and this count is a function of the point position. The X-axis represents the position in the arrow 76 in Figure 4 , and the Y-axis represents the number of laser pulses projected onto each position.

[0052] According to some embodiments, points 66E1 and 66E2 receive a minimum number of laser pulses, and the number of laser pulses gradually increases when the ablation portion is located closer to points 66D1 and 66D2. A deep portion between points 66D1 and 66D2 may receive a suddenly increased number of laser pulses, as shown in portions 77B1, 77B2, and 77C of Figure 19 . In addition, the slopes of portions 77A1 and 77A2 can gradually increase. Alternatively, according to some embodiments, the number of pulses increases exponentially from position 66E1 to position 66D1. According to some embodiments, the final profile of surface 74 may be similar to the profile shown in Figure 7 , Figure 12 and Figure 17 .

[0053] Figure 20 shows the relationship of laser pulse count as a function of position according to an alternative embodiment. The slope of the line remains constant from position 66E1 to position 66D1. Alternatively, the number of pulses increases linearly from position 66E1 to position 66D1. At point 66D1, a suddenly greater number of laser pulses are employed to form the deepened portion of trench 66.

[0054] Referring to Figure 5A or Figure 5B , the wafer 2 is sawed (singulated) in a die sawing process. As shown in Figure 23 , in process 200, the corresponding process is shown as process 206. The die sawing process can be performed using a blade. Thereby, cutting lines 76 are formed. Multiple cutting lines 76 are formed, each cutting line extending downward from one of the trenches 66, as shown in Figure 18 . Thus, the wafer 2 is cut into a plurality of identical discrete device dies 4. According to some embodiments, as shown in Figure 5A , the outer boundaries of the cutting lines 76 are aligned with the sidewalls 66SW1 and / or 66SW2. Thus, one or two gradually varying surfaces 74 extend to the tops of the corresponding sidewalls 66SW1 and / or 66SW2, and these sidewalls 66SW1 and / or 66 further form the sidewalls of the final device die 4.

[0055] According to an alternative embodiment, as shown in Figure 5B , the cutting lines 76 are narrower than the corresponding trenches 66 and may be located in the middle of the trenches 66, which means that the distance (width) from the cutting lines 76 to the nearest edges of the trenches 66 is equal. Thus, the gradually varying surface 74 extends to the tops of the corresponding sidewalls 66SW1 and / or 66SW2, and these sidewalls also terminate at the bottoms of the trenches 66. Thus, the top surface 22T of the semiconductor substrate 22 can form the bottom of the trench 66, and the top surface 22T of the semiconductor substrate 22 extends laterally to the edges of the resulting device die 4.

[0056] Figure 6Shows a package of device die 4 (including device die 4A and 4B) according to some embodiments, where device die 4A and 4B are encapsulated to form package 78. As Figure 23 shown, in process 200, the corresponding process is shown as process 208. Each of device die 4A and 4B can have the structure described above and can be formed by the same process as that shown in Figures 1 - 4 and Figure 5A (or Figure 5B ). According to some embodiments, device die 4A is bonded to package assembly 80. Package assembly 80 can include device die, a package including device die encapsulated therein, an interposer, a package substrate, a printed circuit board, a blank silicon carrier, etc. According to some embodiments, an electrical connector 82 can be formed and connected to device die 4A. Device die 4B is bonded to device die 4A. Although not shown, through-silicon vias (TSVs) can be included in device die 4A to electrically connect device die 4B to package assembly 80. The dashed line (bottom surface marked as 22T) also indicates that device die 4A and 4B have the structure shown in Figure 5B .

[0057] A sealant 84 (which can be a molding compound, a molded underfill, etc.) is used to encapsulate device die 4A and 4B. The molding compound 84 can include filler particles in a base material and a filler. The base material can include polymers, resins, epoxy resins, etc. The filler particles can be spherical particles of silica, alumina, etc. The encapsulation process can include dispensing the molding compound in a flowable form and then curing the molding compound into a solid. The sealant 84 can flow into trenches 60 and 66 (if present in device die 4A and / or 4B) through capillary action. An advantageous feature of the present disclosure is that by forming a tapered surface 74 with a small roughness, the molding compound easily flows into trench 60, so voids are not formed, or if voids are formed, the voids are reduced.

[0058] Figure 7 and Figures 9 - 17 show a schematic enlarged view of the surface 74 of the corner portion of device die 4 according to some embodiments. The shown enlarged view can be obtained from region 86 in Figure 6 . Endpoint 66E1 and point 66D1 ( Figure 4 , Figure 19 and Figure 20 ) and sidewall 66SW1 are also shown.

[0059] Refer to Figure 7, the corner portion of the device die having the surface 74 can also be referred to as the eave portion of the device die 4. From point 66E1 to point 66D1, the depth of the trench 66 gradually increases. For example, the depth DA1 < DA2 < DA3 < DA4. Thus, the surface 74 is referred to as the tapered surface 74. As the depth of the surface 74 gradually increases, the molding compound 84 can more easily flow into the trench 60, which is also the gap between the encapsulation assembly 80 ( Figure 6 ) and the device die 4A, or the gap between the device dies 4A and 4B. The lateral length L1 ( Figure 7 ) of the corner portion cannot be too large or too small. If the lateral length L1 is too small, the edge portion is too steep and the corner is too sharp, and it is difficult for the sealant 84 ( Figure 6 ) to flow into the trench 60. Voids may be formed in the trench 60. If the lateral length L1 is too large, the capillary effect is small, and voids may also be formed in the trench 60. According to some embodiments, the lateral length L1 can be equal to or greater than about 2 μm and can be in the range between about 2 μm - about 4 μm.

[0060] The vertical length D1 of the corner portion cannot be too large or too small. If the vertical length D1 is too small, the corner is too sharp, and it is difficult for the sealant 84 ( Figure 6 ) to flow into the trench 60. Voids may be formed in the trench 60. If the vertical length D1 is too large, due to the high gap, it is difficult for the capillary effect to occur. Voids may also be formed in the trench 60. According to some embodiments, the vertical length D1 can be equal to or greater than about 2 μm and can be in the range between about 2 μm - about 4 μm. In addition, to ensure the balance of the corner surface 74, the lateral length L1 and the vertical length D1 can be equal to or close to each other. For example, the difference is less than about 20% of the lateral length L1 and less than about 20% of the vertical length D1.

[0061] Reference Figure 7 , the tapered surface 74 is schematically shown as having roughness. Since the sealant 84 contains fillers, if the roughness is very high, the roughness provides a greater resistance to the flow of the molding compound 84 and the capillary. Therefore, it is more difficult for the sealant 84 to flow into the trench 60, resulting in the formation of voids in the trench 60 and possibly cracks in the final package. According to an embodiment, the roughness of the surface 74 is less than about 1.5 μm, less than about 0.5 μm, greater than about 0.2 μm or less than about 0.1 μm. According to some embodiments, the roughness can be the root mean square roughness Rq. The reduction of the roughness is achieved by reducing the power of the laser pulse, shortening the duration of each laser pulse, increasing the number of laser pulses (so that each laser pulse produces a smaller indentation), and overlapping the laser pulse spots.

[0062] According to some embodiments, the connection lines of points 66E1 and 66D1 form an inclination angle θ1 with the horizontal line. It should be understood that if the inclination angle θ1 is too large or too small, the vertical length L1 and the vertical length D1 will be correspondingly too large or too small. Therefore, it is more difficult for the sealant 84 to flow into the groove 60, resulting in voids being formed in the groove 60 and possibly cracks being generated in the final package. According to an embodiment, the inclination angle θ1 is in the range between about 20 degrees and about 60 degrees.

[0063] Figure 8 The surface 74 is graphically shown, where different parts with different gray levels represent the higher and lower parts of the surface 74.

[0064] Figure 9 An embodiment is shown in which the side wall 66SW1 is not vertical. Instead, the side wall 66SW1 is slightly inclined. For example, this can be achieved by making Figure 19 part 77B1 in have a high slope instead of being vertical. According to some embodiments, the side wall 66SW1 forms an inclination angle θ2 with the vertical line. It can be understood that if Figure 9 the inclination angle θ2 in is too high, an obvious gap will be formed below the inclined side wall 66SW1. The gap is too high, making it difficult for the capillary action of the sealant 84 to occur, resulting in voids being formed in the groove 60 and possibly cracks being generated in the final package. According to an embodiment, the inclination angle θ2 is less than about 20 degrees.

[0065] Figure 10 An embodiment is shown in which the bottom surface 60B (see the dashed surface 60B in Figure 2 ) is not horizontal. According to some embodiments, the outside of the bottom surface 60B (the part on the right, also see Figure 6 ) is lower than the inside (the part on the left). This results in the height of the outside of the groove 60 ( Figure 6 ) being less than the corresponding inside. This is similar to the embodiment where the bottom surface 60B is horizontal, and the smaller entrance of the groove 60 can contribute to the capillary effect. Therefore, voids are less likely to occur in the groove 60. It should be understood that if the inclination angle θ3 of the bottom surface 60B is too large, it is difficult for the molding compound to pass through the entrance of the groove 60. According to an embodiment, the inclination angle θ3 is less than about 20 degrees.

[0066] According to an alternative embodiment, as shown in Figure 11 , the outside of the bottom surface 60B is higher than the corresponding inside. It can be understood that if the inclination angle θ4 is too large, the entrance of the groove 60 is too wide, which may make it difficult for the capillary action to occur. According to an embodiment, the inclination angle θ4 is less than about 20 degrees.

[0067] Figures 12 to 17 Some profiles of the surface 74 according to some embodiments are shown. Figure 12 Similar to Figure 7The illustrated embodiment, where surface 74 is raised, curved, and rounded. This embodiment can be formed by Figure 19 the laser pulse profile shown.

[0068] Figure 13 Shows an embodiment where surface 74 is straight and trench 66 is triangular. This embodiment can be formed by Figure 20 the laser pulse profile shown.

[0069] Figure 14 Shows an embodiment where the sidewall view of surface 74 has a concave and curved shape. This embodiment can be formed by a laser pulse profile 77D as shown in Figure 19 Figure.

[0070] Figure 15 Shows an embodiment where the sidewall view of surface 74 has a concave and straight edge. This embodiment can be formed by a laser pulse profile 77E as shown in Figure 20 Figure.

[0071] Figure 16 Shows another profile where a portion of surface 74 is substantially aligned with a straight line with only a small offset.

[0072] Figure 17 Shows another profile with a convex and curved surface 74 where process variations result in unexpected dimples.

[0073] Embodiments of the present disclosure have some advantageous features. By gradually changing the corner portions of the device die through low-power laser pulses, the packaging process is easier. By shortening the duration of the laser pulse, such as using picosecond laser pulses, more laser pulses can be employed, and each laser pulse will create a smaller dimple on the wafer. This results in a smoother surface roughness generated by laser grooving.

[0074] According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes forming a wafer; etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer, where a first portion of a second dielectric layer of the wafer is directly located below the first trench; and performing a laser grooving process to remove the first portion of the second dielectric layer of the wafer, where a second trench is formed, the second trench is located below the first trench and joins with the first trench, where the second dielectric layer includes a corner region, the first trench joins with the second trench at the corner region, and a portion of the top surface of the corner region near the center median line of the second trench is gradually lower than a corresponding portion of the top surface of the corner region away from the center median line.

[0075] In one embodiment, a laser grooving process is performed using a picosecond laser beam. In one embodiment, the top surface has a roughness of less than about 1.5 μm. In one embodiment, in the laser grooving process, more laser pulses are projected onto a portion closer to the central median line than a portion of the second dielectric layer away from the central median line. In one embodiment, in the laser grooving process, the laser pulses are projected onto an area between a first point away from the central median line and a second point closer to the central median line, and wherein, from the first point to the second point, the number of laser pulses gradually increases.

[0076] In one embodiment, from the first point to the second point, the number of laser pulses increases linearly. In one embodiment, from the first point to the second point, the number of laser pulses increases exponentially. In one embodiment, the method further includes sawing the wafer through the second trench, wherein the wafer is divided into a plurality of die. In one embodiment, the method further includes bonding a die among the plurality of die to a packaging component; and molding the die in a molding compound, wherein the molding compound fills the first trench.

[0077] According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes forming a wafer, etching a first dielectric layer of the wafer to form a first trench between two die of the wafer, wherein a first portion of a second dielectric layer of the wafer is directly located under the first trench; and performing a laser grooving process to remove the first portion of the second dielectric layer and form a second trench, wherein the laser grooving process is performed using a picosecond laser beam. In one embodiment, the surface of the wafer formed by the laser grooving process is rounded. In one embodiment, the method further includes sawing the wafer through the second trench, wherein the wafer is divided into a plurality of die.

[0078] According to some embodiments of the present disclosure, a semiconductor structure includes a device die, the device die including a semiconductor substrate including a first edge; a first dielectric layer located under the semiconductor substrate, wherein the first dielectric layer includes a bottom surface; and a corner surface connecting the bottom surface to the first edge, wherein a portion of the corner surface closer to the first edge is gradually higher than a corresponding portion of the corner surface closer to the bottom surface; and a second dielectric layer, located under and in contact with the first dielectric layer, wherein the second dielectric layer includes a second edge recessed laterally from the first edge.

[0079] In one embodiment, the corner surface is rounded. In one embodiment, the corner surface is straight. In one embodiment, the corner surface has a roughness of less than about 1.5 μm. In one embodiment, the corner surface has a lateral length and a vertical length, and the difference between the lateral length and the vertical length is less than about 20% of both the lateral length and the vertical length. In one embodiment, the outer portion of the bottom surface extends laterally beyond the second edge, and the outer portion of the bottom surface is inclined, wherein the portion of the bottom surface remote from the second edge is lower than the corresponding portion near the second edge.

[0080] In one embodiment, the outer portion of the bottom surface has an inclination angle of less than about 20%. In one embodiment, the semiconductor structure further includes a packaging component located under and bonded to the second dielectric layer; and a molding compound that includes a first portion surrounding the device die; and a second portion overlapping the device die and interfacing with the bottom surface of the first dielectric layer.

[0081] According to some embodiments of the present disclosure, a semiconductor structure includes a packaging component; a device die disposed over and connected to the packaging component; and a sealant, wherein the device die is located within the sealant, and wherein the sealant contacts the device die to form an edge interface formed between the sealant and the edge of the device die; a first bottom surface formed between the sealant and the bottom of the device die; and a corner interface connecting the edge interface to the first bottom interface, wherein the corner interface is rounded and continuous.

[0082] In one embodiment, the roughness of the corner interface is less than about 1.5 μm. In one embodiment, the device die further includes a second bottom surface in physical contact with the packaging component, and the height of the second bottom surface is lower than that of the first bottom surface.

[0083] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations therein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: Forming a wafer; Etching a first dielectric layer of the wafer to form a first trench between two die of the wafer, wherein a first portion of a second dielectric layer of the wafer is directly located under the first trench; and Performing a laser grooving process to remove the first portion of the second dielectric layer of the wafer, wherein a second trench is formed, the second trench is located under the first trench and joined with the first trench, wherein the second dielectric layer includes a corner region, the first trench and the second trench are joined at the corner region, wherein a portion of the top surface of the corner region near the center median line of the second trench is gradually lower than a corresponding portion of the top surface of the corner region away from the center median line.

2. The method according to claim 1, wherein Performing the laser grooving process using a picosecond laser beam.

3. The method according to claim 1, wherein, The top surface has a roughness of less than 1.5 μm.

4. The method according to claim 1, wherein In the laser grooving process, more laser pulses are projected onto a portion closer to the center median line than a portion of the second dielectric layer away from the center median line.

5. The method according to claim 1, wherein In the laser grooving process, laser pulses are projected onto a region between a first point away from the center median line and a second point closer to the center median line, and wherein, from the first point to the second point, the number of laser pulses gradually increases.

6. The method according to claim 1, further comprising: Bonding a die of the plurality of die to a package assembly; And Molding the die in a molding compound, wherein the molding compound fills the first trench.

7. A method of forming a semiconductor structure, comprising: Forming a wafer; Etching a first dielectric layer of the wafer to form a first trench between two die of the wafer, wherein a first portion of a second dielectric layer of the wafer is directly located under the first trench; and Performing a laser grooving process to remove the first portion of the second dielectric layer and form a second trench, wherein the laser grooving process is performed using a picosecond laser beam.

8. A semiconductor structure, comprising: A device die, the device die comprising: A semiconductor substrate, including a first edge; A first dielectric layer, located under the semiconductor substrate, wherein the first dielectric layer includes: A bottom surface; and A corner surface, connecting the bottom surface to the first edge, wherein a portion of the corner surface closer to the first edge is gradually higher than a corresponding portion of the corner surface closer to the bottom surface; and A second dielectric layer, located under and in contact with the first dielectric layer, wherein the second dielectric layer includes a second edge that is laterally recessed from the first edge.

9. The semiconductor structure according to claim 13, wherein, The corner surface has a lateral length and a vertical length, and a difference between the lateral length and the vertical length is less than 20% of both the lateral length and the vertical length.

10. The semiconductor structure according to claim 8, further comprising: A package assembly, located under and joined with the second dielectric layer; And A molding compound, the molding compound comprising: A first portion, surrounding the device die; And The second part overlaps with the device die and interfaces with the bottom surface of the first dielectric layer.

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