Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate which is internally provided with a plurality of contact holes; forming a metal material layer on the substrate by adopting a physical vapor deposition process; etching the metal material layer by adopting an etching process to form a plurality of metal connecting layers which are electrically connected with the contact holes; cleaning the surface of the metal connecting layer by adopting a wet cleaning process; and cleaning the metal connecting layer by adopting an oxidation pretreatment process. After a plurality of metal connecting layers are formed, the surfaces of the metal connecting layers are cleaned by adopting two cleaning processes, the cleaning effect of the surfaces of the metal connecting layers is improved, and the problem of organic matter residues on the surfaces of the metal connecting layers can be reduced by cleaning the surfaces of the metal connecting layers by utilizing a wet cleaning process and an oxidation pretreatment process; and the adhesive force between the metal connecting layer and the subsequent passivation layer is increased, so that the falling defect of the semiconductor structure is reduced, the yield and the performance of the semiconductor structure are improved, and the service life of the semiconductor structure is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] The back end of line (BEOL) process of semiconductor integrated circuits mainly forms metal interconnect layers for connecting the devices formed by the front end of line (FEOL) process. After the metal interconnect layers are formed, a patterned pad structure needs to be formed. The pad structure is formed on the metal interconnect layers to provide connections for input / output (I / O) or power / ground signals. After the pads are formed, a redistribution layer can be formed on the basis of the pads to meet the packaging requirements.

[0003] However, there are still peeling defects in the current wafer, which reduces the yield rate in the chip manufacturing process and also affects the performance and service life of the chips. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the yield rate, performance and service life of the semiconductor structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate with a plurality of contact holes therein; forming a metal material layer on the substrate by physical vapor deposition; etching the metal material layer by an etching process to form a plurality of metal connection layers, the metal connection layers being electrically connected to the contact holes; cleaning the surface of the metal connection layers by a wet cleaning process; and performing an oxidation pretreatment process on the metal connection layers.

[0006] Optionally, the process parameters of the oxidation pretreatment process include: an oxygen flow rate range of 100 sccm to 150 sccm, a plasma power range of 400 w to 500 w, and a reaction time range of 40 s to 50 s.

[0007] Optionally, the process parameters of the wet cleaning process are: the cleaning solution type includes one or a combination of deionized water, organic solvents, acidic solutions, and alkaline solutions; the cleaning solution concentration range is 5% to 20%; the cleaning temperature range is 30°C to 80°C, and the cleaning time range is 1 min to 10 min.

[0008] Optionally, in the step of etching the metal material layer by an etching process to form a plurality of metal connection layers, the steps include: forming a first photoresist layer on the metal material layer; performing exposure and development on the first photoresist layer to form a first photoresist layer with a metal connection layer pattern; etching the metal material layer using the first photoresist layer with the metal connection layer pattern as a mask to form a metal connection layer; and removing the first photoresist layer with the metal connection layer pattern.

[0009] Optionally, after the step of cleaning the surface of the metal connection layer by an oxidation pretreatment, the method further includes: performing a first alloying treatment on the metal connection layer to form a metal alloy layer.

[0010] Optionally, the process parameters of the first alloying treatment include: the reaction temperature ranges from 450°C to 550°C, the reaction atmosphere includes one or a combination of two of N2 and H2, the reaction time ranges from 30 min to 40 min, and the doping materials include: silicon, copper or titanium.

[0011] Optionally, after the step of forming the metal alloy layer, the method further includes: forming a passivation layer on the plurality of metal alloy layers by a chemical vapor deposition process.

[0012] Optionally, the process parameters of the chemical vapor deposition process are: the reaction gases include one or a combination of more of SiH4, NH3, O2, and TEOS, the reaction temperature ranges from 300°C to 900°C, the deposition time ranges from 30 min to 60 min, and the material of the passivation layer is one or a combination of two of SiO2 and SiN.

[0013] Optionally, after the step of forming a passivation layer on the plurality of metal alloy layers, the method further includes: forming a pad material layer on the passivation layer; forming a second photoresist layer on the pad material layer; performing exposure and development on the second photoresist layer to form a second photoresist layer with a pad pattern; etching the pad material layer using the second photoresist layer with the pad pattern as a mask to form a plurality of pads; and removing the second photoresist layer with the pad pattern until the surface of the pads is exposed.

[0014] Optionally, the etching process is a plasma etching process, and the plasma gas is C x H y F z .

[0015] Optionally, after the step of removing the second photoresist layer with the pad pattern until the surface of the pads is exposed, the method further includes: cleaning the surface of the pads by a first wet cleaning process; and cleaning the surface of the pads by a first oxidation pretreatment process.

[0016] Optionally, after the step of forming the pad opening, the method further includes: performing a second alloy treatment on the pad to form a pad alloy layer.

[0017] Optionally, the process parameters of the second alloy treatment include: the reaction temperature ranges from 450°C to 550°C, the reaction atmosphere includes one or a combination of two of N2 and H2, the reaction time ranges from 60 min to 70 min, and the doping materials include: silicon, copper, or titanium.

[0018] Optionally, the material of the metal connection layer includes aluminum, copper, silver, gold, or tin.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0020] In the technical solution of the present invention, after forming a plurality of metal connection layers, two cleaning processes are used to clean the surface of the metal connection layer, improving the cleaning effect of the surface of the metal connection layer. Moreover, by using a wet cleaning process and an oxidation pretreatment process to clean the surface of the metal connection layer, the problem of organic matter residue on the surface of the metal connection layer can be reduced, the adhesion between the metal connection layer and the subsequent passivation layer can be increased, and the problem of peeling or cracking between the passivation layer and the metal connection layer in the subsequent process can be avoided. Furthermore, the peeling defects of the semiconductor structure are reduced, and the yield, performance, and service life of the semiconductor structure are improved.

[0021] Furthermore, in the technical solution of the present invention, after forming the metal connection layer, a first alloy treatment is performed on the metal connection layer. The alloy treatment can form alloy strengthening phases in the metal connection layer, hinder the movement of dislocations, thereby improving the hardness and strength of the material, enabling the metal connection layer to withstand the mechanical stress in the subsequent process and the external force during use. Moreover, through the alloy treatment, a low-resistance alloy interface can be formed between the metal connection layer and the substrate, thereby reducing the contact resistance and achieving good ohmic contact.

[0022] Furthermore, in the technical solution of the present invention, after forming a plurality of pads, two cleaning processes are used to clean the surface of the pads, improving the cleaning effect of the surface of the pads. Moreover, by using a first wet cleaning process and a first oxidation pretreatment process to clean the pads, the problem of organic matter residue on the surface of the pads can be reduced, the reliability of subsequent bonding can be ensured, and the flatness and conductivity of the pads can be improved, enabling the subsequent probe card to improve the test accuracy when performing electrical performance tests on individual chips by contacting the pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0024] Figures 2 to 11It is a schematic diagram of the formation process of a semiconductor structure in an embodiment of the present invention. Detailed implementation manners

[0025] It should be noted that the "surface" and "on" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0026] For the current method of forming a semiconductor structure, please refer to Figure 1 , the method of forming the semiconductor structure includes: providing a substrate 100 with a plurality of contact holes (not shown in the figure) therein; forming a metal material layer (not shown in the figure) on the substrate 100 by physical vapor deposition; etching the metal material layer to form a plurality of metal connection layers 101; cleaning the surface of the metal connection layers 101 by wet cleaning process; and forming a passivation layer 102 on the metal connection layers 101.

[0027] In this embodiment, the wet cleaning process steps are used to remove contaminants, residues and particulate matters generated during the processing.

[0028] In the above solution, the wet cleaning process can effectively remove most of the inorganic substances and metal impurities, but in terms of treating organic matter 103 particles, the effect is relatively limited. Especially at the interface between the surface of the metal connection layer 101 and the passivation layer 102, the problem of residue of organic matter 103 particles is particularly prominent. When the organic matter 103 particles adhere to the interface between the metal connection layer 101 and the passivation layer 102, it is difficult to be completely removed by conventional wet cleaning, and these residual organic matter 103 particles will become weak points of the adhesion force between the metal connection layer 101 and the passivation layer 102. With the change of environmental temperature, humidity or stress, it is easy to cause the peeling or delamination of the passivation layer 102, increasing the defect rate in the chip manufacturing process and affecting the final performance and service life of the chip.

[0029] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure. After forming a plurality of metal connection layers, two cleaning processes are used to clean the surface of the metal connection layers, improving the cleaning effect of the surface of the metal connection layers. And by using the wet cleaning process and the oxidation pretreatment process to clean the surface of the metal connection layers, the problem of organic matter residue on the surface of the metal connection layers can be reduced, the adhesion force between the metal connection layer and the subsequent passivation layer is increased, and the problem of peeling or cracking between the passivation layer and the metal connection layer in the subsequent process is avoided. Furthermore, the peeling defect of the semiconductor structure is reduced, and the yield, performance and service life of the semiconductor structure are improved.

[0030] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0031] Please refer to Figure 2 , a substrate 200 is provided, and a plurality of contact holes 201 are formed in the substrate 200; a metal material layer 2021 is formed on the substrate 200 by physical vapor deposition.

[0032] In some embodiments of the present invention, the material of the substrate 200 is silicon.

[0033] In other embodiments, the material of the substrate 200 can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate 200 can also be a silicon-on-insulator substrate 200 or a germanium-on-insulator substrate 200.

[0034] In some embodiments of the present invention, the material of the contact hole 201 includes one or more combinations of copper, titanium, tantalum, and tungsten.

[0035] In some embodiments of the present invention, the contact hole 201 is filled with metal by electroplating.

[0036] In some embodiments of the present invention, the material of the metal material layer 2021 includes aluminum, copper, silver, gold, or tin.

[0037] Please refer to Figure 3 , an etching process is used to etch the metal material layer 2021 to form a plurality of metal connection layers 202, and the metal connection layers 202 are electrically connected to the contact holes 201.

[0038] In some embodiments of the present invention, the step of etching the metal material layer 2021 to form a plurality of metal connection layers 202 includes: forming a first photoresist layer 203 on the metal material layer 2021; exposing and developing the first photoresist layer 203 to form a first photoresist layer 203 with a pattern of the metal connection layer 202; using the first photoresist layer 203 with the pattern of the metal connection layer 202 as a mask to etch the metal material layer 2021 to form the metal connection layer 202.

[0039] In this embodiment, the process of etching the metal material layer 2021 is dry etching, and the process parameters of the dry etching include: the pressure of the chamber is 50 mtorr to 150 mtorr, the source power is 150 W to 350 W, the bias power is 100 W to 300 W, the gas flow rate is 50 sccm to 300 sccm, and the etching time is 50 s to 100 s.

[0040] In other embodiments of the present invention, the process of etching the metal material layer 2021 is wet etching, and the process parameters of the wet etching process include: the reaction temperature range is from 20°C to 60°C.

[0041] Please refer to Figure 4 , and a wet cleaning process is used to clean the surface of the metal connection layer 202.

[0042] In some embodiments of the present invention, before the step of cleaning the surface of the metal connection layer 202 by using a wet cleaning process, it further includes: removing the first photoresist layer 203 having the pattern of the metal connection layer 202.

[0043] In a specific embodiment, the process parameters of the wet cleaning process are: the types of cleaning solutions include: one or a combination of deionized water, organic solvents, acidic solutions, and alkaline solutions; the concentration range of the cleaning solution is from 5% to 20%; the cleaning temperature range is from 30°C to 80°C, and the cleaning time range is from 1 minute to 10 minutes.

[0044] It can be seen from Figure 4 that after the photoresist removal and wet cleaning of the surface of the metal connection layer 202, since the wet cleaning has a good cleaning effect on the inorganic substances and metal impurities on the surface of the metal connection layer 202, but the effect is relatively limited in dealing with organic matter particles, there is still organic matter residue 2031 on the surface of the metal connection layer 202.

[0045] Among them, the organic matter residue 2031 is photoresist.

[0046] Please refer to Figure 5 , and an oxidation pretreatment process is used to clean the metal connection layer 202.

[0047] In some embodiments of the present invention, the process parameters of the oxidation pretreatment process include: the oxygen flow rate range is from 100 sccm to 150 sccm, the plasma power range is from 400 w to 500 w, and the reaction time range is from 40 s to 50 s.

[0048] In a specific embodiment of the present invention, the specific process of the oxidation pretreatment process is as follows: Remove moisture through a drying process to ensure that the surface of the metal connection layer is clean and dry, preparing for subsequent oxygen treatment; Place the semiconductor structure with the metal connection layer into a reaction chamber with specific atmosphere control. The reaction chamber is usually made of high-temperature and corrosion-resistant materials, capable of withstanding certain pressure and temperature conditions. At the same time, the chamber has good sealing performance to ensure the stability of the atmosphere during the treatment process; Before introducing oxygen, the reaction chamber needs to be pumped to a certain vacuum degree to remove the air and other residual gases in the chamber, preventing these gases from reacting with oxygen or the surface of the metal connection layer and affecting the treatment effect. For example, use a vacuum pump system to achieve the vacuum extraction of the chamber and reduce the pressure in the chamber to the specified value; When the chamber reaches the required vacuum degree, start introducing high-purity oxygen into the chamber; While introducing oxygen, heat the semiconductor structure to activate the chemical reaction between oxygen and the surface of the metal connection layer, enabling oxygen to more effectively act on the organic residues on the surface of the metal connection layer and achieve the removal of organic residues; When the predetermined treatment time is reached, stop heating and let the semiconductor structure cool naturally in the chamber or quickly cool to room temperature through a cooling system. The cooling rate needs to be controlled during the cooling process to avoid stress or other defects in the semiconductor structure caused by too rapid temperature changes. After cooling is completed, take out the semiconductor structure from the reaction chamber to complete the oxidation pretreatment process.

[0049] Please refer to Figure 6 , after the step of cleaning the surface of the metal connection layer 202 in the oxidation pretreatment, the following steps are further included: Perform a first alloying treatment on the metal connection layer 202 to form a metal alloy layer 2022.

[0050] In some embodiments of the present invention, the process parameters of the first alloying treatment include: the reaction temperature range is 450°C to 550°C, the reaction atmosphere includes one or a combination of two of N2 and H2, the reaction time range is 30 min to 40 min, and the doping materials include: silicon, copper, or titanium.

[0051] In a specific embodiment of the present invention, the specific process of the first alloying treatment is as follows: Place the doped material into a high-temperature furnace for melting. The furnace usually adopts a vacuum or inert gas protection atmosphere to prevent the material from being oxidized at high temperature. Various materials gradually melt and diffuse with each other to form a uniform metal alloy layer; After melting is completed, rapid solidification needs to be performed on the metal alloy layer to obtain a fine grain structure and a uniform composition distribution. Among them, the rapid solidification methods include spray forming or melt spinning.

[0052] In the above solution, after forming the metal connection layer 202, a first alloy treatment is performed on the metal connection layer 202. The alloy treatment can form alloy strengthening phases within the metal connection layer 202, hinder the movement of dislocations, thereby increasing the hardness and strength of the material, enabling the metal connection layer 202 to withstand the mechanical stress in subsequent processes and the external forces during use. Moreover, through the alloy treatment, a low-resistance alloy interface can be formed between the metal connection layer 202 and the substrate 200, thereby reducing the contact resistance and achieving good ohmic contact.

[0053] Please refer to Figure 7 , after the step of forming the metal alloy layer 2022, it further includes: using a chemical vapor deposition process to form a passivation layer 204 on a plurality of the metal alloy layers 2022.

[0054] In some embodiments of the present invention, the process parameters of the chemical vapor deposition process are: the reaction gas includes one or a combination of SiH4, NH3, O2, and TEOS, the reaction temperature range is from 300°C to 900°C, the deposition time range is from 30 min to 60 min, and the material of the passivation layer 204 is one or a combination of SiO2 and SiN.

[0055] In a specific embodiment of the present invention, the gas flow rate of silane is from 5 sccm to 50 sccm, and the gas flow rate of ammonia is from 50 sccm to 500 sccm; the temperature range for depositing the silicon nitride passivation layer 204 is from 300°C to 800°C, and the temperature range for depositing the silicon dioxide passivation layer 204 is from 400°C to 900°C.

[0056] In the above solution, after forming a plurality of metal connection layers 202, two cleaning processes are used to clean the surface of the metal connection layer 202, improving the cleaning effect of the surface of the metal connection layer 202. Moreover, using a wet cleaning process and an oxidation pretreatment process to clean the surface of the metal connection layer 202 can reduce the problem of organic matter residue on the surface of the metal connection layer 202, increase the adhesion between the metal connection layer 202 and the subsequent passivation layer 204, avoid the problem of peeling or cracking between the passivation layer 204 and the metal connection layer 202 in subsequent processes, and thus reduce the peeling defects of the semiconductor structure, improving the yield, performance, and service life of the semiconductor structure.

[0057] Please refer to Figure 8 , after the step of forming the passivation layer 204 on a plurality of the metal alloy layers 2022, it further includes: forming a pad material layer 2051 on the passivation layer 204.

[0058] In some embodiments of the present invention, the method for forming the pad material layer 2051 is a physical vapor deposition process.

[0059] Please refer to Figure 9 , a second photoresist layer 206 is formed on the pad material layer 2051; the second photoresist layer 206 is exposed and developed to form a second photoresist layer 206 having a pad 205 pattern; the pad material layer 2051 is etched using the second photoresist layer 206 having the pad 205 pattern as a mask to form a plurality of pads 205.

[0060] Among them, in the step of etching the pad material layer 2051, it further includes: etching the passivation layer 204 until the surface of the metal connection layer 202 is exposed.

[0061] In some embodiments of the present invention, the etching process is a plasma etching process, and the plasma gas is C x H y F z .

[0062] In this embodiment, the process of etching the pad material layer 2051 is dry etching, and the process parameters of the dry etching include: the pressure of the chamber is 50 mtorr to 150 mtorr, the source power is 150 W to 350 W, the bias power is 100 W to 300 W, the gas flow rate is 50 sccm to 300 sccm, and the etching time is 50 s to 100 s.

[0063] In other embodiments of the present invention, the process of etching the pad material layer 2051 is wet etching, and the process parameters of the wet etching process include: the reaction temperature range is 20°C to 60°C.

[0064] Please refer to Figure 10 , the second photoresist layer 206 having the pad 205 pattern is removed until the surface of the pad 205 is exposed; a first wet cleaning process is used to clean the surface of the pad 205.

[0065] In a specific embodiment, the process parameters of the wet cleaning process are: the types of cleaning solutions include: one or a combination of deionized water, organic solvents, acidic solutions, and alkaline solutions; the concentration range of the cleaning solution is 5% to 20%; the cleaning temperature range is 30°C to 80°C, and the cleaning time range is 1 min to 10 min.

[0066] It can be Figure 10 seen that after the degluing and wet cleaning of the surface of the pad 205, since the first wet cleaning has a good cleaning effect on the inorganic substances and metal impurities on the surface of the pad 205, but has relatively limited effect in dealing with organic particle matters, there is still organic residue 2061 on the surface of the pad 205.

[0067] Among them, the organic residue 2061 is photoresist.

[0068] In the above solution, after forming a plurality of pads 205, two cleaning processes are used to clean the surface of the pads 205, improving the cleaning effect of the surface of the pads 205. Moreover, by using the first wet cleaning process and the first oxidation pretreatment process to clean the pads 205, the problem of organic residue on the surface of the pads 205 can be reduced, ensuring the reliability of subsequent bonding. In addition, the flatness and conductivity of the pads 205 can be improved, enabling the subsequent probe card to improve the test accuracy when electrically testing a single chip by contacting the pads 205.

[0069] Please refer to Figure 11 , and use the first oxidation pretreatment process to clean the surface of the pads 205; perform a second alloying treatment on the pads 205 to form a pad alloy layer 2052.

[0070] In some embodiments of the present invention, the process parameters of the first oxidation pretreatment process include: the oxygen flow rate ranges from 100 sccm to 150 sccm, the plasma power ranges from 400 w to 500 w, and the reaction time ranges from 40 s to 50 s.

[0071] In a specific embodiment of the present invention, the specific process of the first oxidation pretreatment process is as follows: remove moisture through a drying process to ensure that the pad surface is clean and dry, preparing for subsequent oxygen treatment; place the semiconductor structure with pads into a reaction chamber with specific atmosphere control. The reaction chamber is usually made of high-temperature and corrosion-resistant materials, capable of withstanding certain pressure and temperature conditions. At the same time, the chamber has good sealing performance to ensure the stability of the atmosphere during the treatment process. Before introducing oxygen, the reaction chamber needs to be pumped to a certain vacuum degree to remove the air and other residual gases in the chamber, preventing these gases from reacting with oxygen or the pad surface unnecessarily and affecting the treatment effect. For example, use a vacuum pump system to achieve the vacuum extraction of the chamber and reduce the pressure in the chamber to the specified value; when the chamber reaches the required vacuum degree, start introducing high-purity oxygen into the chamber; while introducing oxygen, heat the semiconductor structure to activate the chemical reaction between oxygen and the pad surface, enabling oxygen to more effectively react with the organic residue on the pad surface and achieving the removal of the organic residue; when the predetermined treatment time is reached, stop heating and let the semiconductor structure cool naturally in the chamber or quickly cool to room temperature through a cooling system. The cooling process needs to control the cooling rate to avoid stress or other defects in the semiconductor structure caused by too rapid temperature changes. After cooling is completed, take out the semiconductor structure from the reaction chamber to complete the oxidation pretreatment process.

[0072] In some embodiments of the present invention, the process parameters of the second alloy treatment include: the reaction temperature ranges from 450 °C to 550 °C, the reaction atmosphere includes one or a combination of two of N2 and H2, the reaction time ranges from 60 min to 70 min, and the doping materials include: silicon, copper or titanium.

[0073] In this embodiment, after forming the pad 205, the second alloy treatment is performed on the pad 205. The alloy treatment can form alloy strengthening phases within the pad 205, hinder the movement of dislocations, thereby improving the hardness and strength of the material, enabling the pad alloy layer 2052 to withstand the mechanical stress in the subsequent processes and the external forces during use.

[0074] In a specific embodiment of the present invention, the specific process of the second alloy treatment is as follows: the doped material is put into a high-temperature furnace for melting. Usually, the furnace adopts a vacuum or inert gas protection atmosphere to prevent the material from being oxidized at high temperatures. Various materials gradually melt and diffuse with each other to form a uniform metal alloy layer; after melting is completed, rapid solidification needs to be performed on the metal alloy layer to obtain fine grain structures and uniform composition distributions. Among them, the rapid solidification methods include spray forming or melt spinning.

[0075] In summary, after forming a plurality of metal connection layers 202 and a plurality of pads 205, two cleaning processes are used to clean the surfaces of the metal connection layer 202 and the pad 205, improving the cleaning effect of the surfaces of the metal connection layer 202 and the pad 205. Moreover, by using wet cleaning processes and oxidation pretreatment processes to clean the surfaces of the metal connection layer 202 and the pad 205, the problem of organic matter residues on the surfaces of the metal connection layer 202 and the pad 205 can be reduced, the adhesion between the metal connection layer 202 and the subsequent passivation layer 204 can be increased, avoiding the problems of peeling or cracking between the passivation layer 204 and the metal connection layer 202 in the subsequent processes. Furthermore, the peeling defects of the semiconductor structure are reduced, the yield, performance, and service life of the semiconductor structure are improved, and the reliability of the subsequent bonding of the pad 205 is ensured. Also, the flatness and conductivity of the pad 205 can be improved, enabling the subsequent probe card to improve the test accuracy when performing electrical performance tests on individual chips by contacting the pad 205.

[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate with a plurality of contact holes therein; Forming a metal material layer on the substrate by physical vapor deposition; Etching the metal material layer by an etching process to form a plurality of metal connection layers, the metal connection layers being electrically connected to the contact holes; Cleaning the surface of the metal connection layers by a wet cleaning process; Performing an oxidation pretreatment process to clean the metal connection layers.

2. The method for forming a semiconductor structure according to claim 1, wherein, The process parameters of the oxidation pretreatment process include: the oxygen flow rate ranges from 100 sccm to 150 sccm, the plasma power ranges from 400 w to 500 w, and the reaction time ranges from 40 s to 50 s.

3. The method for forming a semiconductor structure according to claim 1, wherein, The process parameters of the wet cleaning process are: the types of cleaning solutions include one or a combination of more of deionized water, organic solvents, acidic solutions, and alkaline solutions; the cleaning solution concentration ranges from 5% to 20%; the cleaning temperature ranges from 30 °C to 80 °C, and the cleaning time ranges from 1 min to 10 min.

4. The method for forming a semiconductor structure according to claim 1, wherein, The steps of etching the metal material layer by an etching process to form a plurality of metal connection layers include: Forming a first photoresist layer on the metal material layer; Exposing and developing the first photoresist layer to form a first photoresist layer with a metal connection layer pattern; Etching the metal material layer using the first photoresist layer with the metal connection layer pattern as a mask to form metal connection layers; Removing the first photoresist layer with the metal connection layer pattern.

5. The method for forming a semiconductor structure according to claim 1, wherein After the step of performing an oxidation pretreatment to clean the surface of the metal connection layers, it further includes: Performing a first alloying treatment on the metal connection layers to form a metal alloy layer.

6. The method for forming a semiconductor structure according to claim 5, wherein, The process parameters of the first alloying treatment include: the reaction temperature ranges from 450 °C to 550 °C, the reaction atmosphere includes one or a combination of two of N2 and H2, the reaction time ranges from 30 min to 40 min, and the doping materials include silicon, copper, or titanium.

7. The method for forming a semiconductor structure as described in claim 5, wherein, After the step of forming the metal alloy layer, it further includes: Forming a passivation layer on a plurality of the metal alloy layers by chemical vapor deposition.

8. The method for forming a semiconductor structure according to claim 7, wherein, The process parameters of the chemical vapor deposition process are: the reaction gases include one or a combination of more of SiH4, NH3, O2, and TEOS, the reaction temperature ranges from 300 °C to 900 °C, the deposition time ranges from 30 min to 60 min, and the material of the passivation layer is one or a combination of two of SiO2 and SiN.

9. The method for forming a semiconductor structure according to claim 7, wherein, After the step of forming a passivation layer on a plurality of the metal alloy layers, it further includes: Forming a pad material layer on the passivation layer; Forming a second photoresist layer on the pad material layer; Exposing and developing the second photoresist layer to form a second photoresist layer with a pad pattern; Etching the pad material layer using the second photoresist layer with the pad pattern as a mask to form a plurality of pads; Removing the second photoresist layer with the pad pattern until the pad surface is exposed.

10. The method for forming a semiconductor structure according to claim 9, wherein, The etching process is a plasma etching process, and the plasma gas is C x H y F z .

11. The method for forming a semiconductor structure as claimed in claim 9, wherein, After the step of removing the second photoresist layer with the pad pattern until the pad surface is exposed, it further includes: The first wet cleaning process is adopted to clean the surface of the pad; The first oxidation pretreatment process is adopted to clean the surface of the pad.

12. The method for forming a semiconductor structure according to claim 9, wherein, After the step of forming the pad opening, the following steps are further included: The pad is subjected to a second alloying treatment to form a pad alloy layer.

13. The method for forming a semiconductor structure according to claim 12, wherein, The process parameters of the second alloying treatment include: the reaction temperature ranges from 450°C to 550°C, the reaction atmosphere includes one or a combination of two of N2 and H2, the reaction time ranges from 60 min to 70 min, and the doping materials include: silicon, copper or titanium.

14. The method for forming a semiconductor structure according to claim 1, wherein, The material of the metal connection layer includes aluminum, copper, silver, gold or tin.

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