Chip packaging structure and chip packaging method

Abstract

The invention relates to a chip packaging structure and a chip packaging method. The chip packaging structure comprises a substrate, a chip, a heat dissipation layer and a plastic packaging layer, the chip comprises a first surface and a second surface which are oppositely arranged, the first surface is arranged close to the substrate and connected with the substrate, and the second surface is arranged far away from the substrate; the heat dissipation layer covers the second surface; the plastic package layer is arranged on one side, close to the chip, of the substrate, the plastic package layer covers at least part of the side face of the chip, the surface, away from the substrate, of the plastic package layer is not higher than the surface, away from the substrate, of the heat dissipation layer, and a closed cavity for containing the chip is defined by the substrate, the heat dissipation layer and the plastic package layer. According to the chip packaging structure disclosed by the invention, the effective protection of the chip can be realized, the risk of fracture and rupture of the chip when the chip is extruded by external force in the packaging, testing, transporting and assembling processes is reduced, and the reliability of the chip packaging structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip packaging, and particularly to a chip packaging structure and a chip packaging method. Background Art

[0002] The heat dissipation and yield of chips have always been important topics in the field of chip packaging. Summary of the Invention

[0003] The present disclosure provides a chip packaging structure to improve the reliability of the chip packaging structure, reduce the chip crack risk and improve the heat dissipation efficiency.

[0004] The chip packaging structure of the present disclosure includes:

[0005] A substrate;

[0006] A chip, the chip includes a first surface and a second surface arranged opposite to each other, the first surface is close to the substrate and connected to the substrate, and the second surface is far from the substrate;

[0007] A heat dissipation layer, the heat dissipation layer covers the second surface;

[0008] A plastic encapsulation layer, the plastic encapsulation layer is arranged on one side of the substrate close to the chip, the plastic encapsulation layer covers at least part of the side surface of the chip, and the surface of the plastic encapsulation layer far from the substrate is not higher than the surface of the heat dissipation layer far from the substrate. A closed cavity for accommodating the chip is formed between the substrate, the heat dissipation layer and the plastic encapsulation layer.

[0009] Optionally, the surface of the plastic encapsulation layer far from the substrate is lower than the surface of the heat dissipation layer far from the substrate, and the surface of the plastic encapsulation layer far from the substrate is higher than the second surface.

[0010] Optionally, the distance between the surface of the heat dissipation layer far from the substrate and the surface of the plastic encapsulation layer far from the substrate is 3μm - 10μm.

[0011] Optionally, the surface of the plastic encapsulation layer far from the substrate is lower than the second surface, and the plastic encapsulation layer covers a part of the side surface of the chip;

[0012] The heat dissipation layer includes a main body part and an edge part, the edge part surrounds the main body part, the main body part covers the second surface, the surface of the edge part close to the substrate is lower than the second surface, and the edge part covers another part of the side surface of the chip.

[0013] Optionally, the edge part covers the surface of the plastic encapsulation layer far from the substrate.

[0014] Optionally, the side surface of the main body portion close to the substrate is attached to the second surface, and the side surface of the edge portion close to the main body portion is attached to the side surface of the chip.

[0015] Optionally, the surface of the edge portion away from the substrate is higher than the second surface and lower than the surface of the main body portion away from the substrate.

[0016] Optionally, the distance between the second surface and the surface of the encapsulation layer away from the substrate is 3 μm to 10 μm.

[0017] Optionally, the heat dissipation layer is a metal layer.

[0018] Optionally, the thickness of the heat dissipation layer is 5 μm to 10 μm; and / or, the heat dissipation layer includes a plurality of metal sub-layers arranged in a stacked manner, and the materials of two adjacent metal sub-layers are different.

[0019] The present disclosure also provides a chip packaging method.

[0020] The chip packaging method of the present disclosure includes the following steps:

[0021] Form a heat dissipation layer on the second surface of the chip, wherein the heat dissipation layer covers the second surface, the first surface of the chip is arranged close to the substrate and connected to the substrate, and the second surface is arranged away from the substrate;

[0022] Form an encapsulation layer on one side of the substrate close to the chip, wherein the encapsulation layer covers at least part of the side surface of the chip, the surface of the encapsulation layer away from the substrate is not higher than the surface of the heat dissipation layer away from the substrate, and a closed cavity for accommodating the chip is formed between the substrate, the heat dissipation layer and the encapsulation layer.

[0023] Optionally, after forming the heat dissipation layer on the second surface of the chip and before forming the encapsulation layer on one side of the substrate close to the chip, the chip packaging method further includes:

[0024] Set a covering film on the surface of the heat dissipation layer away from the substrate;

[0025] After forming the encapsulation layer on one side of the substrate close to the chip, the chip packaging method further includes:

[0026] Remove the covering film from the heat dissipation layer;

[0027] Wherein, the surface of the substrate is lower than the surface of the heat dissipation layer away from the substrate, and the encapsulation layer covers a part of the side surface of the chip.

[0028] Optionally, before forming the encapsulation layer on the side of the substrate close to the chip, the chip encapsulation method further includes:

[0029] Providing a cover film on the second surface;

[0030] Before forming the heat dissipation layer on the second surface of the chip, the chip encapsulation method further includes:

[0031] Removing the cover film from the second surface;

[0032] Wherein, the surface of the encapsulation layer away from the substrate is lower than the second surface, and the encapsulation layer covers a part of the side surface of the chip;

[0033] The heat dissipation layer includes a main body portion and an edge portion. The edge portion is disposed around the main body portion. The main body portion covers the second surface. The surface of the edge portion close to the substrate is lower than the second surface, and the edge portion covers another part of the side surface of the chip.

[0034] Optionally, after forming the encapsulation layer on the side of the substrate close to the chip and before removing the cover film from the heat dissipation layer, the chip encapsulation method further includes:

[0035] Applying a preset pressure to the encapsulation layer in the direction towards the substrate.

[0036] Optionally, the heat dissipation layer is a metal layer, and the metal layer is formed by one or more of physical vapor deposition, chemical vapor deposition, and electroplating.

[0037] In the chip encapsulation structure of the present disclosure, by providing a heat dissipation layer covering the second surface of the chip, and setting the surface of the encapsulation layer away from the substrate to be not higher than the surface of the heat dissipation layer away from the substrate, the heat generated when the chip operates can be transferred to the outside through the heat dissipation layer, improving the heat dissipation effect of the chip. By enclosing a closed cavity for accommodating the chip between the substrate, the heat dissipation layer, and the encapsulation layer, effective protection of the chip can be achieved, reducing the risk of breakage and cracking when the chip is externally pressed during encapsulation, testing, transportation, and assembly, and improving the reliability of the chip encapsulation structure. Description of the Drawings

[0038] Figure 1 is a schematic structural diagram of one of the chip encapsulation structures in the related art.

[0039] Figure 2 is a schematic structural diagram of another chip encapsulation structure in the related art.

[0040] Figure 3 is a schematic structural diagram of the chip encapsulation structure according to an embodiment of the present disclosure.

[0041] Figure 4 It is a schematic structural diagram of a chip packaging structure before removing the covering film according to an embodiment of the present disclosure.

[0042] Figure 5 It is a schematic structural diagram of a chip packaging structure according to another embodiment of the present disclosure.

[0043] Figure 6 It is a schematic structural diagram of a chip packaging structure before removing the covering film according to another embodiment of the present disclosure.

[0044] Figure 7 It is a schematic structural diagram of a chip packaging structure after removing the covering film and before forming a heat dissipation layer according to another embodiment of the present disclosure.

[0045] Figure 8 It is a schematic structural diagram of a connection between a metal layer and a chip according to an embodiment of the present disclosure.

[0046] Figure 9 It is a schematic structural diagram of a connection between a metal layer and a chip according to another embodiment of the present disclosure.

[0047] Figure 10 It is a flowchart of a chip packaging method according to an embodiment of the present disclosure.

[0048] Figure 11 It is a flowchart of a chip packaging method according to an embodiment of the present disclosure.

[0049] Reference numerals:

[0050] 10. Chip;

[0051] 20. Substrate;

[0052] 30. Encapsulation material;

[0053] 100. Chip packaging structure;

[0054] 1. Substrate;

[0055] 2. Chip; 21. First surface; 22. Second surface;

[0056] 3. Heat dissipation layer; 31. Main body part; 32. Edge part; 33. First metal sub-layer; 34. Second metal sub-layer; 35. Third metal sub-layer;

[0057] 4. Encapsulation layer;

[0058] 5. Covering film;

[0059] 6. First pin;

[0060] 7. Second pin. Detailed implementation manners

[0061] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation to the present disclosure.

[0062] As Figure 1 shown, the chip packaging structure in the related art mainly adopts the FCCSP (Flip-Chip Chip Scale Package) structure. Among them, one side of the chip 10 is connected to the substrate 20, and the rest of the chip 10 is completely wrapped by the encapsulation material 30. Due to the poor thermal conductivity of the encapsulation material 30, the heat dissipation effect of the chip 10 is poor, and it is difficult to meet the heat dissipation requirements of the high-power chip 10. To solve the above problems, as Figure 2 shown, the encapsulation material 30 only covers the side surface of the chip 10, and the surface of the chip 10 facing away from the substrate 20 is exposed to the outside to improve the heat dissipation effect of the chip 10. Figure 2 For the chip packaging structure shown, although the heat dissipation effect of the chip can be improved, when the chip is externally squeezed during packaging, testing, transportation, and assembly, the risk of fracture and rupture is relatively large, resulting in poor reliability of the chip packaging structure.

[0063] As Figures 3 to 7 shown, the chip packaging structure 100 of the embodiment of the present disclosure includes a substrate 1, a chip 2, a heat dissipation layer 3, and an encapsulation layer 4. The chip 2 includes a first surface 21 and a second surface 22 that are oppositely arranged. The first surface 21 is close to the substrate 1 and is connected to the substrate 1. The second surface 22 is far from the substrate 1. The heat dissipation layer 3 covers the second surface 22. The encapsulation layer 4 is provided on the side of the substrate 1 close to the chip 2. The encapsulation layer 4 covers at least part of the side surface of the chip 2. The surface of the encapsulation layer 4 away from the substrate 1 is not higher than the surface of the heat dissipation layer 3 away from the substrate 1. A closed cavity for accommodating the chip 2 is formed between the substrate 1, the heat dissipation layer 3, and the encapsulation layer 4.

[0064] For the chip packaging structure 100 of the embodiment of the present disclosure, by providing the heat dissipation layer 3 covering the second surface 22 of the chip 2, and setting the surface of the encapsulation layer 4 away from the substrate 1 to be not higher than the surface of the heat dissipation layer 3 away from the substrate 1, the heat generated when the chip 2 works can be transferred to the outside through the heat dissipation layer 3, improving the heat dissipation effect of the chip 2. By forming a closed cavity for accommodating the chip 2 between the substrate 1, the heat dissipation layer 3, and the encapsulation layer 4, effective protection of the chip 2 can be achieved, reducing the risk of fracture and rupture when the chip 2 is externally squeezed during packaging, testing, transportation, and assembly, and improving the reliability of the chip packaging structure 100.

[0065] To make the technical solution of the present disclosure easier to understand, the technical solution of the present disclosure will be further described below by taking the thickness direction of the chip 2 as being consistent with the up and down directions as an example. Among them, the up and down directions are asFigures 3 to 7 as shown

[0066] For example, as Figures 3 to 7 shown, the chip 2 is disposed on the upper side of the substrate 1, and the heat dissipation layer 3 is disposed on the upper side of the chip 2. The lower surface of the chip 2 is the first surface 21, and the lower surface of the chip 2 is connected to the substrate 1; the upper surface of the chip 2 is the second surface 22, and the heat dissipation layer 3 covers the upper surface of the chip 2. The encapsulation layer 4 is disposed on the upper side of the substrate 1 and surrounds the chip 2.

[0067] In some embodiments, as Figure 3 and Figure 4 shown, in the direction perpendicular to the plane where the chip is located, the surface of the encapsulation layer 4 away from the substrate 1 is lower than the surface of the heat dissipation layer 3 away from the substrate 1, and the surface of the encapsulation layer 4 away from the substrate 1 is higher than the second surface 22.

[0068] For example, as Figure 3 and Figure 4 shown, in the direction perpendicular to the plane where the chip is located, the upper surface of the encapsulation layer 4 is lower than the upper surface of the heat dissipation layer 3, and the upper surface of the encapsulation layer 4 is higher than the second surface 22 of the chip 2.

[0069] By setting the surface of the encapsulation layer 4 away from the substrate 1 to be lower than the surface of the heat dissipation layer 3 away from the substrate 1, more parts of the heat dissipation layer 3 are exposed to the outside, improving the heat exchange effect between the heat dissipation layer 3 and the external environment, thereby further improving the heat dissipation effect of the chip 2 and improving the reliability of the chip packaging structure 100; by setting the surface of the encapsulation layer 4 away from the substrate 1 to be higher than the second surface 22, the chip 2 is more effectively wrapped by the encapsulation layer 4, improving the protection effect of the encapsulation layer 4 on the chip 2 and improving the reliability of the chip packaging structure 100.

[0070] Of course, in some other embodiments, the surface of the encapsulation layer 4 away from the substrate 1 may also be set lower than the second surface 22.

[0071] Optionally, the distance between the surface of the heat dissipation layer 3 away from the substrate 1 and the surface of the encapsulation layer 4 away from the substrate 1 is 3 μm to 10 μm. That is to say, the protruding height of the heat dissipation layer 3 relative to the encapsulation layer 4 is 3 μm to 10 μm.

[0072] As Figure 3 shown, the distance between the upper surface of the heat dissipation layer 3 and the upper surface of the encapsulation layer 4 is H1, and H1 is 3 μm to 10 μm.

[0073] It can be understood that when the thickness of the heat dissipation layer 3 is fixed, the greater the distance between the surface of the heat dissipation layer 3 away from the substrate 1 and the surface of the plastic encapsulation layer 4 away from the substrate 1, the less the portion of the heat dissipation layer 3 covered by the plastic encapsulation layer 4, and the more the portion of the heat dissipation layer 3 exposed to the outside, which is more conducive to improving the heat dissipation effect of the chip 2. However, the reliability of the connection between the heat dissipation layer 3 and the plastic encapsulation layer 4 is worse; the smaller the distance between the surface of the heat dissipation layer 3 away from the substrate 1 and the surface of the plastic encapsulation layer 4 away from the substrate 1, the more the portion of the heat dissipation layer 3 covered by the plastic encapsulation layer 4, the better the reliability of the connection between the heat dissipation layer 3 and the plastic encapsulation layer 4. However, the portion of the heat dissipation layer 3 exposed to the outside is less, which is not conducive to the heat dissipation of the chip 2.

[0074] By setting the distance between the surface of the heat dissipation layer 3 away from the substrate 1 and the surface of the plastic encapsulation layer 4 away from the substrate 1 to be 3 μm to 10 μm, while ensuring the connection reliability between the heat dissipation layer 3 and the plastic encapsulation layer 4, the heat dissipation effect of the chip 2 can be improved, and the reliability of the chip packaging structure 100 can be enhanced.

[0075] In addition, by setting the distance between the surface of the heat dissipation layer 3 away from the substrate 1 and the surface of the plastic encapsulation layer 4 away from the substrate 1 to be 3 μm to 10 μm, while ensuring the heat dissipation effect, the relationship between the stress on the chip and the yield of the entire chip packaging structure can be balanced.

[0076] In some other embodiments, as Figure 5 shown, the surface of the plastic encapsulation layer 4 away from the substrate 1 is lower than the second surface 22, and the plastic encapsulation layer 4 covers a part of the side surface of the chip 2. The heat dissipation layer 3 includes a main body portion 31 and an edge portion 32. The edge portion 32 is disposed around the main body portion 31, and the main body portion 31 covers the second surface 22. The surface of the edge portion 32 close to the substrate 1 is lower than the second surface 22, and the edge portion 32 covers another part of the side surface of the chip 2.

[0077] For example, as Figure 5 shown, the main body portion 31 is disposed directly above the chip 2, and the edge portion 32 is disposed directly above the plastic encapsulation layer 4. For the side surface of the chip 2, the lower part is covered by the plastic encapsulation layer 4, and the upper part is covered by the edge portion 32.

[0078] By setting the heat dissipation layer 3 to include the main body portion 31 and the edge portion 32, using the plastic encapsulation layer 4 to cover a part of the side surface of the chip 2, and using the edge portion 32 to cover another part of the side surface of the chip 2. The portion of the chip 2 wrapped by the plastic encapsulation layer 4 can be reduced, thereby using the heat dissipation layer 3 to improve the heat dissipation effect of the chip 2 and further enhancing the reliability of the chip packaging structure 100.

[0079] Optionally, the edge portion 32 covers the surface of the plastic encapsulation layer 4 away from the substrate 1.

[0080] For example, the edge portion 32 covers the upper surface of the plastic encapsulation layer 4.

[0081] Covering the surface of the encapsulation layer 4 away from the substrate 1 with the edge portion 32 can improve the connection reliability between the heat dissipation layer 3 and the encapsulation layer 4, and further improve the reliability of the chip packaging structure 100.

[0082] Optionally, the distance between the second surface 22 and the surface of the encapsulation layer 4 away from the substrate 1 is 3 μm to 10 μm.

[0083] For example, as Figure 5 shown, the distance between the second surface 22 and the upper surface of the encapsulation layer 4 is 3 μm to 10 μm.

[0084] It can be understood that the larger the distance between the second surface 22 and the surface of the encapsulation layer 4 away from the substrate 1, the less the part of the chip 2 covered by the encapsulation layer 4, and the more the part of the chip 2 exposed outside the encapsulation layer 4, which is more conducive to improving the heat dissipation effect of the chip 2. However, the protection effect of the encapsulation layer 4 on the chip 2 is also worse; the smaller the distance between the second surface 22 and the surface of the encapsulation layer 4 away from the substrate 1, the more the part of the chip 2 covered by the encapsulation layer 4, and the better the protection effect of the encapsulation layer 4 on the chip 2. However, the part of the chip 2 exposed outside the encapsulation layer 4 is less, which is not conducive to the heat dissipation of the chip 2.

[0085] By setting the distance between the second surface 22 and the surface of the encapsulation layer 4 away from the substrate 1 to be 3 μm to 10 μm, while ensuring the heat dissipation effect of the chip 2, the protection effect of the encapsulation layer 4 on the chip 2 can be improved, and the reliability of the chip packaging structure 100 can be improved.

[0086] Optionally, as Figure 5 shown, the side of the main body portion 31 close to the substrate 1 is attached to the second surface 22. The side of the edge portion 32 close to the main body portion 31 is attached to the side of the chip 2.

[0087] By attaching the side of the main body portion 31 close to the substrate 1 to the second surface 22 and attaching the side of the edge portion 32 close to the main body portion 31 to the side of the chip 2, the heat of the chip 2 can be directly conducted to the heat dissipation layer 3 and conducted to the external environment through the heat dissipation layer 3, which is beneficial to further improving the heat dissipation effect of the chip 2.

[0088] Optionally, as Figure 5 shown, the surface of the edge portion 32 away from the substrate 1 is higher than the second surface 22 and lower than the surface of the main body portion 31 away from the substrate 1.

[0089] Thus, while ensuring the heat dissipation effect of the chip 2, it is beneficial to further improve the protection effect of the heat dissipation layer 3 on the chip 2.

[0090] Optionally, the heat dissipation layer 3 is a metal layer.

[0091] By setting the heat dissipation layer 3 as a metal layer, the heat dissipation layer 3 has good ductility, reducing the risk of fracture and rupture when the chip packaging structure 100 is extruded by external force, and further improving the reliability of the chip packaging structure 100.

[0092] Optionally, the thickness of the heat dissipation layer 3 is 5μm to 10μm.

[0093] It can be understood that the greater the thickness of the heat dissipation layer 3, the better the reliability and the higher the cost; the smaller the thickness of the heat dissipation layer 3, the lower the cost and the worse the reliability.

[0094] By setting the thickness of the heat dissipation layer 3 to 5μm to 10μm, while ensuring the reliability of the heat dissipation layer 3, the cost of the heat dissipation layer 3 can be reduced. Thus, while improving the reliability of the chip packaging structure 100, the cost of the chip packaging structure 100 can be reduced.

[0095] Optionally, as Figure 8 and Figure 9 shown, the heat dissipation layer 3 includes a plurality of metal sub-layers arranged in a stack, and the materials of two adjacent metal sub-layers are different.

[0096] For example, as Figure 8 shown, the heat dissipation layer 3 includes two metal sub-layers arranged in a stack, and the two metal sub-layers are the first metal sub-layer 33 and the second metal sub-layer 34 respectively. Among them, the first metal sub-layer 33 can be Ti, TiN, Ta, TaN; the second metal sub-layer 34 can be Cu, Au, SuS, NiV. Or, as Figure 9 shown, the heat dissipation layer 3 includes three metal sub-layers arranged in a stack, and the three metal sub-layers are the first metal sub-layer 33, the second metal sub-layer 34 and the third metal sub-layer 35 respectively. Among them, the first metal sub-layer 33 can be Ti, TiN, Ta, TaN, the second metal sub-layer 34 can be Cu, and the third metal sub-layer 35 can be Au; or, the first metal sub-layer 33 can be SuS, the second metal sub-layer 34 can be Cu, and the third metal sub-layer 35 can be SuS; or, the first metal sub-layer 33 can be Al, the second metal sub-layer 34 can be Ti, and the third metal sub-layer 35 can be Ni, NiV.

[0097] It can be understood that the chip 2 is usually made of a silicon substrate. Among them, Ti, TiN, Ta, TaN have good adhesion to the Si substrate; Cu has a lower cost and good thermal conductivity, and is suitable for mass production; Au has better ductility, can better disperse external forces, and is oxidation-resistant to prevent the bonding force from deteriorating; SuS has better stability and is suitable for harsh environments.

[0098] By setting the heat dissipation layer 3 to include a plurality of metal sub-layers arranged in a stacked manner, it is convenient to set the types of the metal sub-layers according to requirements, so as to improve the reliability of the chip packaging structure 100 and reduce the cost of the chip packaging structure 100.

[0099] As Figures 3 to 7 shown, the chip packaging structure 100 further includes a first pin 6 and a second pin 7. Both ends of the first pin 6 are respectively connected to the chip 2 and the substrate 1; one end of the second pin 7 is connected to the substrate 1, and the other end is used for connection to a circuit board.

[0100] Among them, the first pin 6 can be a solder bump, a copper core ball or a Cu piller. The second pin 7 can be a solder ball, etc.

[0101] Next, refer to Figures 3 to 11 to describe the chip packaging method of the embodiments of the present disclosure. The chip packaging method of the embodiments of the present disclosure includes the following steps:

[0102] Form a heat dissipation layer 3 on the second surface 22 of the chip 2. Among them, the heat dissipation layer 3 covers the second surface 22. The first surface 21 of the chip 2 is disposed close to the substrate 1 and connected to the substrate 1, and the second surface 22 is disposed away from the substrate 1;

[0103] Form a plastic encapsulation layer 4 on the side of the substrate 1 close to the chip 2. Among them, the plastic encapsulation layer 4 covers at least part of the side surface of the chip 2. The surface of the plastic encapsulation layer 4 away from the substrate 1 is not higher than the surface of the heat dissipation layer 3 away from the substrate 1. A closed cavity for accommodating the chip 2 is formed between the substrate 1, the heat dissipation layer 3 and the plastic encapsulation layer 4.

[0104] In the chip packaging method of the embodiments of the present disclosure, by setting the heat dissipation layer 3 covering the second surface 22 of the chip 2, and setting the surface of the plastic encapsulation layer 4 away from the substrate 1 to be not higher than the surface of the heat dissipation layer 3 away from the substrate 1, the heat generated when the chip 2 works can be transferred to the outside through the heat dissipation layer 3, improving the heat dissipation effect of the chip 2. By forming a closed cavity for accommodating the chip 2 between the substrate 1, the heat dissipation layer 3 and the plastic encapsulation layer 4, effective protection of the chip 2 can be achieved, reducing the risk of fracture and breakage of the chip 2 when it is externally squeezed during transportation and assembly, and improving the reliability of the chip packaging structure 100.

[0105] Optionally, the plastic encapsulation layer 4 is formed by injecting a plastic encapsulation material into a plastic encapsulation mold.

[0106] In some embodiments, as Figure 4 and Figure 10 shown, the chip packaging method includes the following steps:

[0107] S1. Form a heat dissipation layer 3 on the second surface 22 of the chip 2;

[0108] S2. Provide a covering film 5 on the surface of the heat dissipation layer 3 away from the substrate 1;

[0109] S3. Form a plastic encapsulation layer 4 on the side of the substrate 1 close to the chip 2; wherein, the surface of the plastic encapsulation layer 4 away from the substrate 1 is lower than the surface of the heat dissipation layer 3 away from the substrate 1, and the surface of the plastic encapsulation layer 4 away from the substrate 1 is higher than the second surface 22;

[0110] S4. Apply a preset pressure to the plastic encapsulation layer 4 in the direction towards the substrate 1;

[0111] S5. Remove the covering film 5 from the heat dissipation layer 3.

[0112] Wherein, the covering film 5 is closely attached to the heat dissipation layer 3.

[0113] By providing the covering film 5 on the surface of the heat dissipation layer 3 away from the substrate 1 after forming the heat dissipation layer 3 on the second surface 22 of the chip 2 and before forming the plastic encapsulation layer 4 on the side of the substrate 1 close to the chip 2, and removing the covering film 5 from the heat dissipation layer 3 after forming the plastic encapsulation layer 4, it is possible to prevent the plastic encapsulation layer 4 from covering the surface of the heat dissipation layer 3 and affecting the heat dissipation effect of the heat dissipation layer 3.

[0114] After the injection molding of the plastic encapsulation material is completed, by applying a preset pressure to the plastic encapsulation layer 4 in the direction towards the substrate 1, the density of the plastic encapsulation material can be made greater and the encapsulation effect can be better. Among them, the preset pressure can be determined according to the type of the plastic encapsulation material, etc.

[0115] After applying the preset pressure to the plastic encapsulation layer 4 in the direction towards the substrate 1, then removing the covering film 5 from the heat dissipation layer 3 can prevent the pressure from directly acting on the heat dissipation layer 3 and being transmitted to the chip 2 through the heat dissipation layer 3, further reducing the risk of the chip 2 breaking and cracking and improving the reliability of the chip 2.

[0116] In some other embodiments, as Figure 6 , Figure 7 and Figure 11 shown, the chip packaging method includes the following steps:

[0117] S01. Provide a covering film 5 on the second surface 22;

[0118] S02. Form a plastic encapsulation layer 4 on the side of the substrate 1 close to the chip 2; wherein, the surface of the plastic encapsulation layer 4 away from the substrate 1 is lower than the second surface 22, and the plastic encapsulation layer 4 covers a part of the side surface of the chip 2;

[0119] S03. Apply a preset pressure to the plastic encapsulation layer 4 in the direction towards the substrate 1;

[0120] S04. Remove the covering film 5 from the second surface 22;

[0121] S05. Form a heat dissipation layer 3 on the second surface 22 of the chip 2; wherein, the heat dissipation layer 3 includes a main body portion 31 and an edge portion 32, the edge portion 32 is disposed around the main body portion 31, the main body portion 31 covers the second surface 22, the surface of the edge portion 32 close to the substrate 1 is lower than the second surface 22, and the edge portion 32 covers another side surface of the chip 2.

[0122] Wherein, the covering film 5 is closely attached to the second surface 22.

[0123] By disposing the covering film 5 on the second surface 22 and then forming the encapsulation layer 4 on the side of the substrate 1 close to the chip 2, it is possible to prevent the encapsulation layer 4 from covering the second surface 22, which affects the formation of the heat dissipation layer 3 and the heat dissipation effect of the heat dissipation layer 3.

[0124] After the injection molding of the encapsulation material is completed, by applying a preset pressure in the direction of the substrate 1 to the encapsulation layer 4, the density of the encapsulation material can be made greater and the encapsulation effect can be better. Wherein, the preset pressure can be determined according to the type of the encapsulation material, etc.

[0125] After applying the preset pressure in the direction of the substrate 1 to the encapsulation layer 4, and then removing the covering film 5 from the heat dissipation layer 3, it is possible to prevent the pressure from directly acting on the chip 2, further reducing the risk of the chip 2 breaking and cracking, and improving the reliability of the chip 2.

[0126] Optionally, the heat dissipation layer 3 is a metal layer, and the metal layer is formed by one or more of physical vapor deposition, chemical vapor deposition, and electroplating.

[0127] In other embodiments, other typical methods such as electrosputtering can also be used to form the metal layer.

[0128] Forming the heat dissipation layer 3 in the above manner makes the formed heat dissipation layer 3 have higher precision, which is beneficial to further improving the reliability of the chip packaging structure 100.

[0129] When specifically manufacturing the chip 2, the wafer can be ground first, then the heat dissipation layer 3 is formed on the silicon-based side of the wafer, and then operations such as laser grooving and dicing are performed on the wafer, and then the chip 2 is connected to the substrate 1, and then the encapsulation layer 4 is formed subsequently; or the wafer can be ground first, then operations such as laser grooving and dicing are performed on the wafer, and then the chip 2 is connected to the substrate 1, and then the heat dissipation layer 3 and the encapsulation layer 4 are formed subsequently, etc.

[0130] Wherein, after the chip 2 and the substrate 1 are bonded through the first pin 6, glue is dot-filled between the chip 2 and the substrate 1, so that the filled glue fills the gap between the chip 2 and the substrate 1 and covers the first pin 6.

[0131] The chip packaging structure 100 and the chip packaging method according to the embodiments of the present disclosure can effectively reduce the risk of the chip 2 breaking and cracking, and prevent the chip 2 from generating cracks due to the influence of packaging, testing, transportation, and assembly; the process of the chip packaging method is relatively flexible, and the heat dissipation layer 3 can be formed before the formation of the plastic encapsulation layer 4 or after the formation of the plastic encapsulation layer 4; the selection of the heat dissipation layer 3 is flexible, and two metals or three metals can be selected according to requirements; the formation method of the heat dissipation layer 3 is flexible, and physical vapor deposition, chemical vapor deposition, electroplating, etc. can be used.

[0132] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Any changes, modifications, substitutions, and variations made by those of ordinary skill in the art to the above embodiments are within the protection scope of the present disclosure.

Claims

1. A chip packaging structure, characterized in that, Comprising: A substrate; A chip, the chip includes a first surface and a second surface which are oppositely arranged, the first surface is close to the substrate and connected to the substrate, and the second surface is far from the substrate; A heat dissipation layer, the heat dissipation layer covers the second surface; A plastic encapsulation layer, the plastic encapsulation layer is arranged on one side of the substrate close to the chip, the plastic encapsulation layer covers at least part of the side surface of the chip, and the surface of the plastic encapsulation layer far from the substrate is not higher than the surface of the heat dissipation layer far from the substrate. A closed cavity for accommodating the chip is formed between the substrate, the heat dissipation layer and the plastic encapsulation layer.

2. The chip packaging structure according to claim 1, wherein The surface of the plastic encapsulation layer far from the substrate is lower than the surface of the heat dissipation layer far from the substrate, and the surface of the plastic encapsulation layer far from the substrate is higher than the second surface.

3. The chip package structure according to claim 2, wherein The distance between the surface of the heat dissipation layer far from the substrate and the surface of the plastic encapsulation layer far from the substrate is 3μm - 10μm.

4. The chip packaging structure according to claim 1, wherein, The surface of the plastic encapsulation layer far from the substrate is lower than the second surface, and the plastic encapsulation layer covers a part of the side surface of the chip; The heat dissipation layer includes a main body part and an edge part, the edge part surrounds the main body part, the main body part covers the second surface, the surface of the edge part close to the substrate is lower than the second surface, and the edge part covers another part of the side surface of the chip.

5. The chip packaging structure according to claim 4, wherein The edge part covers the surface of the plastic encapsulation layer far from the substrate.

6. The chip packaging structure according to claim 4, wherein The side surface of the main body part close to the substrate fits with the second surface, and the side surface of the edge part close to the main body part fits with the side surface of the chip.

7. The chip packaging structure according to claim 4, wherein, The surface of the edge part far from the substrate is higher than the second surface and lower than the surface of the main body part far from the substrate.

8. The chip packaging structure according to claim 4, wherein, The distance between the second surface and the surface of the plastic encapsulation layer far from the substrate is 3μm - 10μm.

9. The chip packaging structure according to any one of claims 1-8, characterized in that, The heat dissipation layer is a metal layer.

10. The chip package structure according to claim 8, wherein, The thickness of the heat dissipation layer is 5μm - 10μm; and / or The heat dissipation layer includes a plurality of metal sub-layers arranged in a stacked manner, and the materials of adjacent two metal sub-layers are different.

11. A chip packaging method, characterized in that, Including the following steps: Forming a heat dissipation layer on the second surface of the chip, wherein the heat dissipation layer covers the second surface, the first surface of the chip is close to the substrate and connected to the substrate, and the second surface is far from the substrate; Forming a plastic encapsulation layer on one side of the substrate close to the chip, wherein the plastic encapsulation layer covers at least part of the side surface of the chip, and the surface of the plastic encapsulation layer far from the substrate is not higher than the surface of the heat dissipation layer far from the substrate. A closed cavity for accommodating the chip is formed between the substrate, the heat dissipation layer and the plastic encapsulation layer.

12. The chip packaging method according to claim 11, wherein After forming the heat dissipation layer on the second surface of the chip and before forming the plastic encapsulation layer on the side of the substrate close to the chip, the chip packaging method further includes: Setting a covering film on the surface of the heat dissipation layer far from the substrate; After forming the plastic encapsulation layer on the side of the substrate close to the chip, the chip packaging method further includes: Removing the covering film from the heat dissipation layer; Wherein, the surface of the substrate is lower than the surface of the heat dissipation layer away from the substrate, and the encapsulation layer covers a part of the side surface of the chip.

13. The chip packaging method according to claim 11, wherein Before forming the encapsulation layer on the side of the substrate close to the chip, the chip packaging method further includes: Providing a cover film on the second surface; Before forming the heat dissipation layer on the second surface of the chip, the chip packaging method further includes: Removing the cover film from the second surface; Wherein, the surface of the encapsulation layer away from the substrate is lower than the second surface, and the encapsulation layer covers a part of the side surface of the chip; The heat dissipation layer includes a main body part and an edge part. The edge part is disposed around the main body part. The main body part covers the second surface. The surface of the edge part close to the substrate is lower than the second surface, and the edge part covers another part of the side surface of the chip.

14. The chip packaging method according to claim 12 or 13, characterized in that, After forming the encapsulation layer on the side of the substrate close to the chip and before removing the cover film from the heat dissipation layer, the chip packaging method further includes: Applying a preset pressure in the direction towards the substrate to the encapsulation layer.

15. The chip packaging method according to claim 11, wherein The heat dissipation layer is a metal layer, and the metal layer is formed by one or more of physical vapor deposition, chemical vapor deposition, and electroplating.

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