Semiconductor stack package and manufacturing method thereof
By introducing a silicon perforated structure as an anti-fuse structure in the semiconductor stacking package, the problem of insufficient memory capacity and assembly density in the prior art is solved, and stable electrical isolation and data storage functions are realized.
Patent Information
- Application Number
- CN202510506378.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-09
- Filing Date
- 2025-04-22
- Publication Date
- 2025-07-25
AI Technical Summary
The existing semiconductor stacking packaging technology is difficult to effectively improve memory capacity and assembly density. At the same time, the existing anti-fuse structure has the problem of electrical isolation in high-density integrated circuits.
A silicon perforated structure formed in the substrate is adopted, including a dielectric layer sandwiched between two conductive layers, as an anti-fuse structure, and the data storage function is realized through breakdown of the dielectric layer.
Potential options for memory applications in semiconductor stacked packages are realized, memory capacity and assembly density are improved, and stable electrical isolation is achieved through controlled breakdown of the dielectric layer.
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Figure CN120376536A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor stacked package and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor stacked package structure. Background Art
[0002] Semiconductor devices are indispensable for many modern applications. With the advancement of electronic technology, the size of semiconductor devices is becoming smaller and smaller, while having stronger functionality and higher density integrated circuits. Due to the miniaturization of semiconductor devices, wafer stacking technology is now widely used in the manufacture of semiconductor packages.
[0003] In some existing methods, by stacking at least two wafers (or dies) in a 3D package to form, for example, a memory device, a product with a memory capacity twice that achievable by other semiconductor integration processes can be produced. In addition to increasing the memory capacity, stacked packages can also improve the assembly density and the utilization efficiency of the assembly area. Due to these advantages, the research and development of stacked package technology have been accelerated. Summary of the Invention
[0004] The present invention provides a through-silicon-via (TSV) structure in a substrate. The through-silicon-via structure includes a dielectric layer sandwiched between two conductive layers. With this configuration, the through-silicon-via structure can be used as an antifuse structure, making it a possible option for memory applications in semiconductor stacked packages.
[0005] One aspect of the present invention provides a semiconductor stacked package including a semiconductor die. The semiconductor die includes a substrate, transistors, and a through-silicon-via structure. The transistors are disposed on the substrate. The through-silicon-via structure is perpendicular to the substrate and includes a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is located between the first conductive layer and the second conductive layer.
[0006] In some embodiments, the dielectric layer has a rod-shaped cross-sectional profile.
[0007] In some embodiments, the first conductive layer and the second conductive layer have substantially the same width.
[0008] In some embodiments, the dielectric layer includes an oxide.
[0009] In some embodiments, the dielectric layer is an oxide of the material of the first conductive layer.
[0010] In some embodiments, the first conductive layer and the second conductive layer have different widths.
[0011] In some embodiments, the semiconductor die further includes an insulating layer surrounding the through-silicon-via structure.
[0012] In some embodiments, the first conductive layer, the second conductive layer, and the dielectric layer are in contact with the insulating layer.
[0013] In some embodiments, the insulating layer and the dielectric layer are made of the same material.
[0014] In some embodiments, the semiconductor stacked package further includes a package substrate. The semiconductor die is stacked on the package bottom plate, and the through-silicon via structure of the semiconductor die is electrically connected to the package bottom plate.
[0015] Another aspect of the present invention provides a method for manufacturing a semiconductor stacked package, including the following steps: forming a through hole in a substrate; forming a first conductive layer in the through hole; forming a dielectric layer in the through hole and on the first conductive layer; forming a second conductive layer in the through hole and on the dielectric layer; forming a transistor on the substrate. The first conductive layer, the second conductive layer, and the dielectric layer together form a through-silicon via structure.
[0016] In some embodiments, forming the dielectric layer includes depositing a dielectric material on the inner surface of the through hole.
[0017] In some embodiments, forming the dielectric layer includes oxidizing the exposed surface of the first conductive layer in the through hole.
[0018] In some embodiments, the method for manufacturing a semiconductor stacked package further includes forming an insulating layer on the inner surface of the through hole before forming the first conductive layer.
[0019] In some embodiments, the method for manufacturing a semiconductor stacked package further includes performing a grinding process on the back surface of the substrate until the first conductive layer is exposed.
[0020] In some embodiments, forming the first conductive layer includes: depositing an excessive amount of conductive material in the through hole; performing a grinding process on the conductive material until the substrate is exposed; and etching back the conductive material to reduce the surface of the conductive material.
[0021] In some embodiments, the method for manufacturing a semiconductor stacked package further includes forming an interconnect structure that is electrically connected to the through-silicon via structure and the transistor.
[0022] In some embodiments, the method for manufacturing a semiconductor stacked package further includes forming a conductive bump on the interconnect structure; and connecting the conductive bump to the package bottom plate.
[0023] In some embodiments, the method for manufacturing a semiconductor stacked package further includes stacking semiconductor dies on the substrate. The semiconductor dies are electrically connected to the through-silicon via structure.
[0024] In some embodiments, the method of manufacturing a semiconductor stacked package further includes, after forming transistors on the substrate, applying a voltage to the first conductive layer or the second conductive layer to break the dielectric layer to form a conductive path between the first conductive layer and the second conductive layer.
[0025] It should be understood that the above general description and the following detailed description are merely exemplary and are intended to further explain the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The present invention can be more fully understood by reading the detailed description of the embodiments herein with reference to the following drawings:
[0027] Figure 1 A cross-sectional view of a semiconductor stacked package according to some embodiments of the present invention.
[0028] Figure 2A is Figure 1 A partial enlarged view of the semiconductor device shown in part A of the semiconductor stacked package in
[0029] Figure 2B A partial enlarged view of a semiconductor device according to some embodiments of the present invention.
[0030] Figures 3A to 3O Schematic diagrams of the steps of a method for manufacturing a semiconductor stacked package according to some embodiments of the present invention.
[0031] Figures 4A to 4D Schematic diagrams of the steps of a method for manufacturing a semiconductor stacked package according to some embodiments of the present invention.
[0032] Figure 5A and Figure 5B Schematic diagrams of operating the through-silicon via structure of a semiconductor stacked package under different conditions according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0033] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
[0034] Numerous different embodiments or examples are provided below for implementing different functions of the provided subject matter. To simplify the present invention, specific examples of elements and arrangements are described below. These examples are of course only examples and are not intended to be limiting. For example, in the following description, when it is mentioned that a first feature is formed on or above a second feature, embodiments may include those in which the first feature is in direct contact with the second feature, and may also include those in which other features are formed between the first feature and the second feature without direct contact. In addition, the present invention may reuse reference numerals and / or letters in various examples, and this repetition is for the purpose of simplicity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed per se.
[0035] In addition, for ease of description, spatially relative terms such as "below", "beneath", "bottom", "above", "top", etc. may be used in this document to describe the relationship of one element or feature to another element or feature as shown in the drawings. These spatially relative terms are intended to cover different orientations of the device during use or operation and are not limited to the orientations shown in the drawings. For example, the device may be operated in different orientations (such as rotated 90 degrees or other orientations), and thus the spatially relative descriptive terms in this document should be interpreted accordingly.
[0036] It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled, or there may be intervening elements or layers.
[0037] Unless the context otherwise indicates, terms such as "same", "equal", "planar", or "coplanar" mentioned in this document, when referring to directions, layouts, positions, shapes, sizes, quantities, or other measurements, do not necessarily mean exactly the same directions, layouts, positions, shapes, sizes, quantities, or other measurements, but are intended to cover those that are approximately the same within an acceptable error range, such as variations that may occur due to the manufacturing process. The term "substantially" may be used here to reflect this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable range of variations that may occur during the manufacturing process.
[0038] Please refer to Figure 1 , Figure 1is a cross-sectional view of a semiconductor stack package 400 according to some embodiments of the present invention. The semiconductor stack package 400 may include a semiconductor die 500, a semiconductor die 100, and a package substrate 200. The semiconductor die 100 is stacked on the package substrate 200 and is electrically connected to the package substrate 200 through corresponding connecting conductive bumps 138. The semiconductor die 500 is stacked on the semiconductor die 100 and is electrically connected to the semiconductor die 100 through corresponding connecting conductive bumps 538. In some embodiments, the spaces between the semiconductor die 100 and the package substrate 200, and between the semiconductor die 100 and the semiconductor die 500 may be filled with filling materials 141, 541 respectively. The filling materials 141, 541 surround the corresponding connecting conductive bumps 138, 538 and can serve as protective layers for the connecting conductive bumps 138, 538.
[0039] Regarding the package substrate 200, in some embodiments, the package substrate 200 may include, for example, a printed circuit board. For example, the package substrate 200 may include a multi-layer printed circuit board. The package substrate 200 may include a substrate base 201, a lower substrate conductive gasket 206 disposed on the lower surface of the substrate base 201, an upper substrate conductive gasket 209 disposed on the upper surface of the substrate base 201, and external connecting conductive bumps 203 disposed on the lower substrate conductive gasket 206.
[0040] In some embodiments, the substrate base 201 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. The external connecting conductive bumps 203 are configured to electrically connect an external device and the semiconductor stack package 400. The external connecting conductive bumps 203 may include, for example, solder balls.
[0041] As Figure 1 shown, two semiconductor dies are vertically stacked on the package substrate 200. However, the present invention is not limited thereto. For example, three or more semiconductor dies may be stacked on the package substrate 200 in the vertical direction.
[0042] Please refer to Figure 1 and Figure 2A , Figure 2A is a partial enlarged view of the semiconductor die 100 shown by the dashed line A of the semiconductor stack package 400 in Figure 1 . The semiconductor die 100 may include a substrate 110, a through-silicon via structure 101, transistors 122, an interlayer dielectric layer 125, and an inter-metal dielectric layer 128 on the interlayer dielectric layer 125. The through-silicon via structure 101 may be disposed in the substrate 110 and perpendicular to the substrate 110. The transistors 122 may be disposed on the surface 110a of the substrate 110 and covered by the interlayer dielectric layer 125. The inter-metal dielectric layer 128 may be disposed on the interlayer dielectric layer 125.
[0043] Regarding the through-silicon via structure 101, each through-silicon via structure 101 may include a first conductive layer 113, a second conductive layer 119, and a dielectric layer 116 interposed between the first conductive layer 113 and the second conductive layer 119. The dielectric layer 116 may include a rod-shaped cross-sectional profile. The first conductive layer 113 and the second conductive layer 119 substantially have the same width. The insulating layer 105 may surround the respective corresponding through-silicon via structure 101. For example, the insulating layer 105 may extend along opposite sidewalls of the through-silicon via structure 101 and separate the through-silicon via structure 101 from the substrate 110.
[0044] In some embodiments, the first conductive layer 113 and the second conductive layer 119 may include a metal, such as copper or other suitable conductive metals. In some embodiments, the insulating layer 105 may include a dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the dielectric layer 116 may include an oxide. In some embodiments, the dielectric layer 116 may include silicon oxide. In some embodiments, the dielectric layer 116 may include an oxide of the material of the first conductive layer 113. In some embodiments, the insulating layer 105 and the dielectric layer 116 may have the same material, such as silicon oxide.
[0045] In some embodiments, the substrate 110 may include a semiconductor substrate. In some embodiments, the substrate 110 may include, for example, silicon. Alternatively, the substrate 110 may include semiconductor elements, such as germanium (Ge), or compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may include a conductive region, such as a doped impurity well or a doped impurity structure. In addition, the substrate 110 may have various device isolation structures, such as a shallow trench isolation (STI) structure.
[0046] In some embodiments, the transistor 122 may include, for example, a metal oxide semiconductor field effect transistor (MOSFET). For example, the transistor 122 may include an n-type metal oxide semiconductor (NMOS), a p-type metal oxide semiconductor (PMOS), or a similar structure. Other devices, such as a system large scale integration (LSI), an image sensor (e.g., a complementary metal oxide semiconductor (CMOS) image sensor (CIS)), a microelectromechanical system (MEMS), an active element, a passive element, or a similar device, may also be disposed on the substrate 110.
[0047] In Figure 2A some embodiments, the transistor 122 may include a gate structure on the substrate 110, and source / drain regions in the substrate 110 and located on opposite sides of the gate structure. Gate spacers may be disposed on opposite sidewalls of the gate structure.
[0048] In some embodiments, the interlayer dielectric layer 125 may include a dielectric material and conductive vias 1315 (also referred to as first conductive vias). The dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, PSG, BPSG, low-k dielectric material, and / or other suitable dielectric materials. In some embodiments, the conductive vias 1315 may include tungsten (W), copper (Cu), aluminum (Al), or similar materials.
[0049] In some embodiments, the intermetal dielectric layer 128 may include an interconnect structure 131 located therein. For example, the interconnect structure 131 may include conductive lines 1311 and conductive vias 1313 (also referred to as second conductive vias). In some embodiments, the intermetal dielectric layer 128 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, PSG, BPSG, low-k dielectric material, and / or other suitable dielectric materials. In some embodiments, the conductive lines 1311 and conductive vias 1313 may include tungsten (W), copper (Cu), aluminum (Al), or similar materials.
[0050] In some embodiments, the semiconductor die 100 may further include a lower conductive pad 134 that extends along the surface of the intermetal dielectric layer 128 and is electrically connected to the interconnect structure 131. A connecting conductive bump 138 may be electrically connected to the lower conductive pad 134. The semiconductor die 100 further includes an upper conductive pad 148 that extends along the surface 110b of the substrate 110 and contacts the first conductive layer 113 of the silicon through via structure 101. In some embodiments, the lower conductive pad 134 and the upper conductive pad 148 may include tungsten (W), copper (Cu), aluminum (Al), or similar materials.
[0051] Regarding the semiconductor die 500, its structure is similar to that of the semiconductor die 100. For example, the semiconductor die 500 may include a substrate 510, transistors 522 on the substrate 510, an interlayer dielectric layer 525 on the substrate 510 and covering the transistors 522, conductive vias 5315 in the interlayer dielectric layer 525 and electrically connected to the transistors 522, an intermetal dielectric layer 528 on the interlayer dielectric layer 525, and an interconnect structure 531 in the intermetal dielectric layer 528 and electrically connected to the intermetal dielectric layer 528. The semiconductor die 500 further includes a lower conductive pad 534 that extends along the surface of the intermetal dielectric layer 528 and is electrically connected to the interconnect structure 531. A connecting conductive bump 538 contacts the lower conductive pad 534.
[0052] Please refer to Figure 2B , Figure 2BIt is a partial enlarged view of the semiconductor die 100 according to some embodiments of the present invention in other embodiments.
[0053] It should be noted that Figure 2B Some of the elements in Figure 2A are similar to the elements described in Figure 2A and have the same element symbols. For the sake of brevity, the relevant details will not be repeated. Figure 2B The difference from
[0054] Please refer to Figure 3A where a patterned mask MP may be formed on the surface 110a of the substrate 110. The patterned mask MP may include a mask opening MO that exposes a partial area of the substrate 110. The patterned mask MP can be, for example, a photoresist. The mask opening MO can be formed in the patterned mask MP through an appropriate lithography process.
[0055] Please refer to Figure 3B where a lithography process is performed to remove a partial area of the substrate 110 through the mask opening MO of the patterned mask MP, thereby forming a through hole 102 in the substrate 110. Although the through hole 102 is described in the text as being formed by a lithography process, the present invention is not limited thereto. In some embodiments, the through hole 102 can be formed by a laser drilling process.
[0056] Please refer to Figure 3C where after the through hole 102 is formed, the patterned mask MP is removed. Subsequently, an insulating layer 105 is formed to cover the substrate 110 and the through hole 102. Specifically, the insulating layer 105 can cover the inner sidewall and the bottom surface of each through hole 102. In some embodiments, the insulating layer 105 can be formed through an appropriate deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or other similar processes.
[0057] Please refer to Figure 3D where a layer of conductive material layer 108 is formed on the substrate 110 and fills the through hole 102. The conductive material layer 108 can be formed through an appropriate deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes.
[0058] Please refer to Figure 3E and perform a polishing process (such as chemical mechanical polishing (CMP)) on the structure of Figure 3D to remove the excess materials of the conductive material layer 108 and the insulating layer 105 until the substrate 110 is exposed. After the polishing process is completed, the portion of the conductive material layer 108 remaining in the via 102 can be referred to as the first conductive layer 113.
[0059] Please refer to Figure 3F and perform an etch-back process to reduce the top surface of the first conductive layer 113, thereby forming a via 103 in the substrate 110 and above the first conductive layer 113. The etch-back process can include dry etching, wet etching, or a combination of both.
[0060] Please refer to Figure 3G and form a dielectric layer 116 in the via 103 and above each first conductive layer 113. In some embodiments, the dielectric layer 116 can be formed by a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. In some embodiments, the dielectric layer 116 can be formed by oxidizing the exposed surface of the first conductive layer 113. In this case, the dielectric layer 116 can be an oxide of the material of the first conductive layer 113. The dielectric layer 116 can have a rod-shaped cross-sectional profile in the via 103.
[0061] Please refer to Figure 3H and form a second conductive layer 119 in the via 103 and above each dielectric layer 116. The second conductive layer 119 can be formed by a process similar to the way the first conductive layer 113 is formed, such as first forming a conductive material layer filling the via 103 and then removing the excess conductive material layer by a polishing process until the substrate 110 is exposed. Subsequently, a through-silicon via structure 101 is formed in the substrate 110. The through-silicon via structure 101 can include the first conductive layer 113, the dielectric layer 116, and the second conductive layer 119. The widths of the first conductive layer 113 and the second conductive layer 119 are substantially the same.
[0062] Please refer to Figure 3I and form a transistor 122 on the substrate 110. The transistor 122 can be formed by a suitable process known in the art, and thus the related details are omitted here for simplicity of description.
[0063] Please refer to Figure 3J, an interlayer dielectric layer 125 is formed on the substrate 110 to cover the transistor 122, and a conductive via 1315 is formed within the interlayer dielectric layer 125. Subsequently, an inter-metal dielectric layer 128 is formed on the interlayer dielectric layer 125, and an interconnect structure 131 is formed within the inter-metal dielectric layer 128. Then, a lower conductive pad 134 is formed on the inter-metal dielectric layer 128 and electrically connected to the interconnect structure 131, and a connecting conductive bump 138 is formed on the lower conductive pad 134.
[0064] Please refer to Figure 3K , subsequently, the substrate 110 is flipped (e.g., rotated 180 degrees) and attached to the carrier substrate 144 by an adhesive tape 142. Specifically, the connecting conductive bump 138 adheres to the adhesive tape 142. In some embodiments, the adhesive tape 142 can be a UV tape and can be easily separated by ultraviolet (UV) irradiation.
[0065] Please refer to Figure 3L , a grinding process is performed to thin the substrate 110 until the through-silicon via structure 101 is exposed. Specifically, after the grinding process is completed, the surface of the first conductive layer 113 of the through-silicon via structure 101 can be exposed through the surface 110b of the substrate 110.
[0066] Please refer to Figure 3M , an upper conductive pad 148 is formed on the surface 110b of the substrate 110 and connected to the through-silicon via structure 101. In some embodiments, after the upper conductive pad 148 is formed, the semiconductor die 100 can be formed.
[0067] Please refer to Figure 3N , the semiconductor die 100 is separated from the carrier substrate 144. Subsequently, the semiconductor die 100 can be stacked on the package substrate 200. In some embodiments, the semiconductor die 100 is stacked by bonding the connecting conductive bump 138 of the semiconductor die 100 to the corresponding upper substrate conductive pad 209 on the package substrate 200. After that, a filling material 141 fills the gap between the semiconductor die 100 and the package substrate 200.
[0068] Please refer to Figure 3O , another semiconductor die 500 is stacked on the semiconductor die 100. In some embodiments, the semiconductor die 500 is stacked by bonding the connecting conductive bump 538 of the semiconductor die 500 to the corresponding upper conductive pad 148 on the semiconductor die 100. After that, a filling material 141 fills the gap between the semiconductor die 500 and the semiconductor die 100.
[0069] Please refer to Figure 4A, a dielectric layer 116 is formed within the through-hole 103, on each of the first conductive layers 113, and on the surface 110a of the substrate 110. In some embodiments, the dielectric layer 116 may be formed by a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. The dielectric layer 116 may have a U-shaped cross-sectional profile within the through-hole 103.
[0070] Please refer to Figure 4B , a second conductive layer 119 is formed within the through-hole 103 and on the dielectric layer 116. The second conductive layer 119 may be formed by a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes.
[0071] Please refer to Figure 4C , for Figure 4B the structure, a polishing process, such as chemical mechanical polishing (CMP), is performed to remove the excess second conductive layer 119 and dielectric layer 116 materials until the substrate 110 is exposed. After the polishing process is completed, the through-silicon via structure 101 is formed in the substrate 110. The through-silicon via structure 101 may include the first conductive layer 113, the dielectric layer 116, and the second conductive layer 119. In some embodiments, the first conductive layer 113 and the second conductive layer 119 may have different widths.
[0072] Please refer to Figure 4D , a semiconductor die 500 is stacked on top of the semiconductor die 100. In some embodiments, the die stacking is completed by bonding the connecting conductive bumps 538 of the semiconductor die 500 to the corresponding upper conductive pads 148 on the semiconductor die 100. Subsequently, the filling material 141 fills the void between the semiconductor die 500 and the semiconductor die 100.
[0073] Figure 5A and Figure 5B illustrate the through-silicon via structure 101 of the semiconductor stacked package 400 operating under different conditions. In some embodiments, the through-silicon via structure 101 may be used as an antifuse structure, Figure 1 and Figure 5A and Figure 5B show different operating procedures for the through-silicon via structure 101. For simplicity, Figure 1 certain elements in
[0074] In Figure 5A , under a first condition, a voltage V1 and a voltage V2 are applied across the through-silicon via structure 101. For example, the voltage V1 is applied to the first conductive layer 113, and the voltage V2 is applied to the second conductive layer 119. In some embodiments, the voltage V1 may be applied through Figure 1The semiconductor die 500 in is applied to the first conductive layer 113, and the voltage V2 can be applied to the second conductive layer 119 through Figure 1 The encapsulation substrate 200 in. In some embodiments, the voltage V1 can be a high voltage level, while the voltage V2 can be a low voltage level (e.g., ground voltage). In some embodiments, the voltage V2 can be a high voltage level, while the voltage V1 can be a low voltage level (e.g., ground voltage).
[0075] In Figure 5A In the illustrated embodiment, the voltage difference between the voltage V1 and the voltage V2 is large enough to break down the dielectric layer 116 (e.g., cause it to break down). When the dielectric layer 116 is broken down, a current path is formed between the first conductive layer 113 and the second conductive layer 119. The resulting circuit can be considered to have a resistance between the first conductive layer 113 and the second conductive layer 119.
[0076] In Figure 5B Under the second condition, the voltages V3 and V4 are applied across the through-silicon via structure 101. For example, the voltage V3 is applied to the first conductive layer 113, and the voltage V4 is applied to the second conductive layer 119. Similarly, the voltage V3 can be applied to the first conductive layer 113 through Figure 1 the semiconductor die 500 in, and the voltage V4 can be applied to the second conductive layer 119 through Figure 1 the encapsulation substrate 200 in. In some embodiments, the voltage V3 can be a high voltage level, while the voltage V4 can be a low voltage level (e.g., ground voltage). In some embodiments, the voltage V4 can be a high voltage level, while the voltage V3 can be a low voltage level (e.g., ground voltage).
[0077] Different from Figure 5A In Figure 5B the embodiment, the voltage difference between the voltage V3 and the voltage V4 may not be sufficient to break down the dielectric layer 116. Therefore, the first conductive layer 113 and the second conductive layer 119 remain electrically isolated from each other through the dielectric layer 116.
[0078] After completing Figure 5A the operation procedure shown, since the dielectric layer 116 has been broken down, current can flow through the through-silicon via structure 101, so the data can be determined as "1". On the other hand, after completing Figure 5BAfter the operation procedure shown, the dielectric layer 116 remains substantially intact, and current cannot flow through the silicon via structure 101. Therefore, the data can be determined as "0". In other words, if the dielectric layer 116 is broken down, the logic level of the silicon via structure 101 is "1"; if the dielectric layer 116 is not broken down, the logic level of the silicon via structure 101 is "0". According to the above discussion, it can be seen that the silicon via structure 101 can be used as a fuse-link structure, which makes it a potential candidate for memory applications in the semiconductor stack package 400.
[0079] Although the present invention has been described in detail with reference to certain of its embodiments, other embodiments are possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.
[0080] Those skilled in the art will appreciate that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations within the scope of the appended claims.
[0081]
Symbol Description
[0082] 100, 500: Semiconductor die
[0083] 101: Silicon via structure
[0084] 102, 103: Through hole
[0085] 105: Insulating layer
[0086] 108: Conductive material layer
[0087] 110, 510: Substrate
[0088] 110a, 110b: Surface
[0089] 113: First conductive layer
[0090] 116: Dielectric layer
[0091] 119: Second conductive layer
[0092] 122, 522: Transistor
[0093] 125, 525: Interlayer dielectric layer
[0094] 128, 528: Metallization dielectric layer
[0095] 131, 531: Interconnect structure
[0096] 1311, 5311: Conductive line
[0097] 1313, 5313: Conductive via / Second conductive via
[0098] 1315,5315: Conductive via / First conductive via
[0099] 134,534: Lower conductive gasket
[0100] 138,538: Connecting conductive bump
[0101] 141,541: Filling material
[0102] 142: Adhesive tape
[0103] 144: Carrier substrate
[0104] 148: Upper conductive gasket
[0105] 200: Encapsulation substrate
[0106] 201: Substrate base
[0107] 203: External connection conductive bump
[0108] 206: Lower substrate conductive gasket
[0109] 209: Upper substrate conductive gasket
[0110] 400: Semiconductor stacked package
[0111] MP: Mask
[0112] MO: Mask opening
[0113] V1, V2, V3, V4: Voltage
[0114] A: Dashed line.
Claims
1. A semiconductor stacked package, characterized in that, Comprising: A semiconductor die, comprising: A substrate; Transistors disposed on the substrate; And Through-silicon via structure perpendicular to the substrate, comprising a first conductive layer, a second conductive layer, and a dielectric layer located between the first conductive layer and the second conductive layer.
2. The semiconductor stacked package according to claim 1, wherein The dielectric layer has a rod-shaped cross-sectional profile.
3. The semiconductor stacked package according to claim 1, wherein The first conductive layer and the second conductive layer have substantially the same width.
4. The semiconductor stack package according to claim 1, wherein, The dielectric layer comprises an oxide.
5. The semiconductor stack package according to claim 1, wherein The dielectric layer is an oxide of the material of the first conductive layer.
6. The semiconductor stack package according to claim 1, wherein The first conductive layer and the second conductive layer have different widths.
7. The semiconductor stacked package according to claim 1, wherein The semiconductor die further comprises an insulating layer surrounding the through-silicon via structure.
8. The semiconductor stack package according to claim 7, wherein The first conductive layer, the second conductive layer, and the dielectric layer contact the insulating layer.
9. The semiconductor stacked package according to claim 8, wherein The insulating layer and the dielectric layer are made of the same material.
10. The semiconductor stacked package according to claim 1, characterized in that, Further comprising: A package bottom plate, wherein the semiconductor die is stacked on the package bottom plate, and the through-silicon via structure of the semiconductor die is electrically connected to the package bottom plate.
11. A method for manufacturing a semiconductor stacked package, characterized in that, Comprising: Forming a via hole in the substrate; Forming a first conductive layer in the via hole; Forming a dielectric layer in the via hole and on the first conductive layer; Forming a second conductive layer in the via hole and on the dielectric layer, wherein the first conductive layer, the dielectric layer, and the second conductive layer together form a through-silicon via structure; Forming transistors on the substrate.
12. The method of manufacturing a semiconductor stacked package according to claim 11, wherein, Forming the dielectric layer includes depositing dielectric material on the inner surface of the via hole.
13. The method of manufacturing a semiconductor stacked package according to claim 11, wherein Forming the dielectric layer includes oxidizing the exposed surface of the first conductive layer in the via hole.
14. The method of manufacturing a semiconductor stacked package according to claim 11, wherein, Before forming the first conductive layer, forming an insulating layer on the inner surface of the via hole.
15. The method for manufacturing a semiconductor stacked package according to claim 11, characterized in that, Further comprising performing a grinding process on the back surface of the substrate until the first conductive layer is exposed.
16. The method for manufacturing a semiconductor stacked package according to claim 11, wherein, Forming the first conductive layer includes: Depositing an excessive amount of conductive material in the via hole; Performing a grinding process on the conductive material until the substrate is exposed; and Etching back the conductive material to reduce the surface of the conductive material.
17. The method for manufacturing a semiconductor stacked package according to claim 11, wherein Further comprising forming an interconnect structure electrically connected to the through-silicon via structure and the transistors.
18. The method for manufacturing a semiconductor stacked package according to claim 17, wherein, Further comprising: Forming conductive bumps on the interconnect structure; and Connecting the conductive bumps to the package bottom plate.
19. The method of manufacturing a semiconductor stacked package according to claim 11, wherein Further comprising stacking semiconductor dies on the substrate such that the semiconductor dies are electrically connected to the through-silicon via structure.
20. The method of manufacturing a semiconductor stacked package according to claim 11, wherein, Further comprising, after forming the transistors on the substrate, applying a voltage to the first conductive layer or the second conductive layer to break the dielectric layer, such that a conductive path is formed between the first conductive layer and the second conductive layer.