Packaging structure and packaging method thereof
By first encapsulating on one side of the substrate and stress distribution using a dielectric layer of thermosetting resin material, warping and wiring density problems are solved, and a high-density chip stacking and a low-cost packaging structure are realized.
Patent Information
- Application Number
- CN202510700643.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2025-07-25
AI Technical Summary
The existing fan-out wafer-level packaging structure has poor substrate support when packaged on both sides, resulting in warping problems and limited wiring density, which cannot meet the requirements of high density, and is also highly packaged.
A dielectric layer of first encapsulated on one side of the substrate and then laminated a thermosetting resin material to achieve frontal pressure on the chip, prevent damage and reduce packaging difficulty. At the same time, stress redistribution of the dielectric layer on the other side of the substrate is laminated to improve warpage, and improve wiring density.
It effectively reduces packaging costs, reduces warpage risks, improves wiring density, and achieves higher density chip stacking and signal transmission.
Smart Images
Figure CN120376542A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a packaging structure and a packaging method thereof. Background Art
[0002] With the rapid development of 5G / 6G communication, the fan-out wafer level package (FOWLP) packaging structure is widely used in the semiconductor industry. Generally, a single chip is cut from a wafer and then flip-chip packaged onto a carrier wafer. The main advantages are high-density integration, small size of the packaged product, excellent product performance, fast signal transmission frequency, etc. The fan out technology mainly realizes multi-pin output and the smaller the output pin pitch. Conventional double-sided packaging product structures or fan-out packaging product structures mainly form packaging structures on the front and back sides of the same substrate. Since the same substrate is used for plastic encapsulation, the wiring density of the substrate is limited, and higher-density wiring requirements cannot be achieved. Moreover, since the packaging is performed on both sides of a single substrate, the substrate support is poor, and warping problems are likely to occur when the other side is processed after one side of the process is completed. Summary of the Invention
[0003] The purpose of the present invention is to provide a packaging structure and a packaging method thereof to improve the wiring density, reduce the packaging process, and increase the number of stacked chips, and ultimately reduce the risk of warping and the packaging cost.
[0004] In a first aspect, to solve the above technical problems, the present invention provides a packaging structure, including:
[0005] A first substrate having a first surface and a second surface disposed opposite to each other;
[0006] A first metal layer disposed on the first surface of the first substrate;
[0007] A first encapsulation layer disposed on the first metal layer and including at least one first chip buried therein, with a first gap between the first chip and the first metal layer;
[0008] A second metal layer disposed on the first encapsulation layer and having a second gap with the first chip;
[0009] A first dielectric layer disposed on the second metal layer.
[0010] Optionally, the packaging structure may further include:
[0011] A third metal layer disposed on the second surface of the first substrate;
[0012] A second dielectric layer disposed on the third metal layer.
[0013] Optionally, the encapsulation structure may further include:
[0014] A fourth metal layer disposed on the first dielectric layer;
[0015] A second encapsulation layer located on the fourth metal layer.
[0016] Optionally, the encapsulation structure may further include:
[0017] At least one first conductive pillar located within the first substrate and passing through the first substrate to be in direct contact with the first metal layer and / or the third metal layer on the first substrate.
[0018] Optionally, the encapsulation structure may further include:
[0019] At least one second conductive pillar located within the first encapsulation layer on at least one side of the first chip and passing through the first encapsulation layer to be in direct contact with the first metal layer and the second metal layer.
[0020] Optionally, the encapsulation structure may further include:
[0021] At least one solder ball located within the first encapsulation layer on at least one side of the first chip and passing through the first encapsulation layer to be in direct contact with the first metal layer and the second metal layer.
[0022] Optionally, the encapsulation structure may further include:
[0023] At least one third conductive pillar disposed in the first dielectric layer and / or the second dielectric layer and passing through the first dielectric layer and / or the second dielectric layer to be in direct contact with the second metal layer, the fourth metal layer, and / or the third metal layer.
[0024] Optionally, the encapsulation structure may further include:
[0025] A plurality of bumps or a plurality of solder joints located in the first gap or the second gap to mount the first chip within the first encapsulation layer.
[0026] The material of the first dielectric layer and / or the second dielectric layer includes a thermosetting resin.
[0027] Optionally, the encapsulation structure may further include:
[0028] A second chip disposed within the second encapsulation layer.
[0029] In a second aspect, based on the same inventive concept, the present invention further provides a method for encapsulating an encapsulation structure, including:
[0030] Provide a first substrate having a first surface and a second surface disposed opposite to each other;
[0031] Form a first metal layer on the first surface of the first substrate;
[0032] Form a first encapsulation layer on the first metal layer, the first encapsulation layer including at least one first chip buried therein, and having a first gap between the first chip and the first metal layer;
[0033] Form a second metal layer on the first encapsulation layer, having a second gap between the second metal layer and the first chip;
[0034] Form a first dielectric layer on the second metal layer.
[0035] Optionally, before or after forming the first metal layer, it may further include:
[0036] Form a third metal layer on the second surface of the first substrate;
[0037] Form at least one first conductive pillar within the first substrate and passing through the first substrate to be in direct contact with the first metal layer and / or the third metal layer on the first substrate.
[0038] Optionally, before or after forming the second metal layer, it may further include:
[0039] Form at least one second conductive pillar within the first encapsulation layer on at least one side of the first chip and passing through the first encapsulation layer to be in direct contact with the first metal layer and the second metal layer.
[0040] Optionally, during the process of forming the first dielectric layer, a second dielectric layer is simultaneously formed on the third metal layer.
[0041] Optionally, the material of the first dielectric layer and / or the second dielectric layer includes a thermosetting resin.
[0042] Optionally, before or after forming the first dielectric layer and the second dielectric layer, it may further include:
[0043] At least one third conductive pillar is disposed in the first dielectric layer and / or the second dielectric layer and passes through the first dielectric layer and / or the second dielectric layer to be in direct contact with the second metal layer, the fourth metal layer, and / or the third metal layer.
[0044] As described above, in the encapsulation structure and its encapsulation method provided by the present invention, unilateral encapsulation can be first performed on the first substrate. For example, a first encapsulation layer with a first chip disposed therein is formed on the first surface of the first substrate, and then at least one dielectric layer, such as a first dielectric layer, is laminated on the first encapsulation layer. The unexpected effect obtained is that since the first chip has been pre-mounted, when the first dielectric layer is laminated to form, positive pressure can be applied to the first encapsulation layer, which can not only prevent the first chip from being damaged, but also reduce the encapsulation difficulty and cost. Moreover, while laminating the first dielectric layer on the first encapsulation layer, a second dielectric layer can be laminated on the second surface (the surface without the first encapsulation layer) of the first substrate. The unexpected effect obtained is that by utilizing the characteristics of the first dielectric layer and the second dielectric layer made of thermosetting resin, which can be subjected to uniform pressure during the thermosetting process, stress redistribution can be achieved, that is, stress can be offset, so as to achieve the purpose of improving warpage. Secondly, the purpose of increasing the wiring density can also be achieved by adding the first dielectric layer or the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] The drawings are used to provide a further understanding of the present application, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application, but do not constitute a limitation to the present application. In the drawings:
[0046] Figure 1 is a schematic cross-sectional view of an example of the encapsulation structure in the first embodiment of the present invention.
[0047] Figure 2 is a schematic evolution diagram of a first chip encapsulation method in the first embodiment of the present invention.
[0048] Figure 3 is another schematic evolution diagram of a first chip encapsulation method in the first embodiment of the present invention.
[0049] Figure 4 is a schematic evolution diagram of a shape structure of a first conductive pillar in the first embodiment of the present invention.
[0050] Figure 5 is another schematic evolution diagram of a shape structure of a first conductive pillar in the first embodiment of the present invention.
[0051] Figure 6 is a schematic cross-sectional view of an example of the encapsulation structure in the second embodiment of the present invention.
[0052] Figures 7 to 11 For Figure 1 is a schematic structural diagram corresponding to the corresponding steps of the encapsulation method of the encapsulation structure provided in the first embodiment of the present invention shown.
[0053] Among them, the reference numerals are explained as follows:
[0054] 100 - First substrate, 100a - First surface, 100b - Second surface, 111 - First metal layer, 112 - First encapsulation layer, 113 - First chip, 113a - Bump, 113b - Solder joint, 114 - Second metal layer, 115 - First dielectric layer, 116 - Fourth metal layer, 117 - Second encapsulation layer, 118 - First conductive pillar, 119 - Second conductive pillar, 119a - Solder ball, 120 - Third conductive pillar, 131 - Third metal layer, 132 - Second dielectric layer, 133 - Fifth metal layer.
[0055] In the drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn to actual scale. Detailed implementation manners
[0056] The following further elaborates on the packaging structure and its packaging method proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited by the specific embodiments disclosed below.
[0057] It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead..." in the present invention should be interpreted in the broadest manner, so that "on..." not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of having intervening features or layers between something "on". In the embodiments of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence. And, among the technical solutions described in the embodiments of the present invention, they can be combined arbitrarily without conflict.
[0058] Please refer to Figure 1 , which shows a cross-sectional schematic diagram of an example of the packaging structure in the first embodiment of the present invention. The packaging structure of the present invention can be used to prepare a fan-out double-sided packaging structure. Without departing from the spirit of the present invention, the present invention can also be applied to other types of packaging structures or double-sided packaging structures, such as in a PLP (Panel Level Packaging) packaging structure, and the features in the embodiments of the present invention can be combined with each other without conflict.
[0059] As shown Figure 1 in the figure, the packaging structure in the first embodiment of the present invention may include: a first substrate 100, a first metal layer 111, a first encapsulation layer 112, a first chip 113, a second metal layer 114, a first dielectric layer 115, a fourth metal layer 116, a second encapsulation layer 117, a third metal layer 131, a second dielectric layer 132, a fifth metal layer 133, etc. Among them, the first substrate 100 may be formed of at least one of insulating materials or include at least one of insulating materials. For example, the first substrate 100 may include photosensitive epoxy resin or PP fiberglass cloth. More specifically, the first substrate 100 may include photoimageable dielectric (PID), and is not limited thereto. The first substrate 100 may include two opposite surfaces, for example, a first surface 100a facing the first dielectric layer 115 and a second surface 100b facing the second dielectric layer 132, and is not limited thereto. The first metal layer 111 covers the first surface 100a of the first substrate 100, while the third metal layer 131 covers the second surface 100b of the first substrate 100 to form a separable substrate structure. In one embodiment, the materials of the first metal layer 111 and the third metal layer 131 may be copper, and the thickness is preferably 15 μm to 35 μm (more preferably 20 μm or 30 μm), and is not limited thereto; and at least one first conductive post 118 is further provided in the first substrate 100, and the end portions of the first conductive post 118 are respectively connected to the first metal layer 111 and the third metal layer 131 covering the first surface 100a and the second surface 100b of the first substrate 100, so as to realize the electrical connection (physical contact) between multiple film layers in the packaging structure. Preferably, the number of the first conductive posts 118 provided in the first substrate 100 may be determined based on the number of chips encapsulated in the packaging structure, such as the first chip 113, so as to realize the partition shielding of multiple chips. Exemplarily, only one first chip 113 is illustrated in the first embodiment of the present invention Figure 1 and thus only two first conductive posts 118 are provided in the first substrate 100, and is not limited thereto. Exemplarily, the first conductive post 118 is in a long strip shape extending along a direction perpendicular to the first surface 100a of the first substrate 100 (hereinafter simply referred to as the vertical direction), and in other embodiments, the shape of the first conductive post 118 may also be other irregular shapes (not shown), such as trapezoid, etc., and is not limited thereto.
[0060] The first encapsulation layer 112 covers the first metal layer 111, and at least one first chip 113 is buried inside the first encapsulation layer 112; As Figure 1As shown, the first chip 113 can be mounted face-up in the first encapsulation layer 112 through a plurality of bumps 113a, and the bottoms of the plurality of bumps 113a are in direct contact with the first metal layer 111; in other alternative examples, such as Figure 2 As shown, the first chip 113 can also be flip-chip mounted face-down in the first encapsulation layer 112 through a plurality of bumps 113a, or, as Figure 3 As shown, it can be encapsulated in the first encapsulation layer 112 face-up or face-down through a plurality of solder joints 113b; in one embodiment, the material of the first encapsulation layer 112 can be a plastic encapsulation material, for example, a thermoplastic encapsulant containing inorganic fillers, and is not limited thereto; the first chip 120 can also be a WB chip or an FC chip, and is not limited thereto; a second metal layer 114 is covered on the first encapsulation layer 112; due to the certain height of the bumps 113a or the solder joints 113b, there is a gap between the front or back surface of the first chip 113 and the first metal layer 111 on the first substrate 100 or the second metal layer 114 on the first encapsulation layer 112, that is, the first gap between the first metal layer 111, or the second gap between the second metal layer 114. The material of the second metal layer 114 can be the same as the material of the first metal layer 111 and / or the third metal layer 131, such as metallic copper, to serve as a carrier connecting the first encapsulation layer 112 and the first dielectric layer 115, and is not limited thereto.
[0061] Furthermore, at least one conductive post, such as the second conductive post 119, can also be provided in the first encapsulation layer 112. The second conductive post 119 can be located in the first encapsulation layer 112 on both sides of different first chips 113, and its ends are in direct contact with the first metal layer 111 and the second metal layer 114 on the two side surfaces of the first encapsulation layer 112 respectively; as Figures 1 to 3 As shown, the shape of the second conductive post 119 in the first embodiment of the present invention can be a long strip extending in the vertical direction, and in other alternative examples, the second conductive post 119 can also be other irregular shapes, such as Figure 4 As shown, an irregular polygon closed structure composed of a trapezoid-inverted part near the second metal layer 114 and a rectangular part (similar to the long strip) near the first metal layer 111, and as long as the upper and lower two ends (or end faces) of the second conductive post 119 with an irregular shape are in corresponding contact with the second metal layer 114 and the first metal layer 111.
[0062] Even further, in other embodiments, instead of providing conductive posts in the first encapsulation layer 112 to achieve physical connection between multiple film layers, a plurality of solder balls can also be provided, such as Figure 5The solder ball 119a shown; since the solder ball 119a serves the same function as the second conductive post 119, the installation position of the solder ball 119a is also the same as that of the second conductive post 119. For example, it is located in the first encapsulation layer 112 on at least one side of the first chip 113 and passes through the first encapsulation layer 112 to directly contact the first metal layer 111 and the second metal layer 114.
[0063] Continue to refer to Figure 1 or Figures 2 to 5 In the first embodiment of the present invention, the first dielectric layer 115 is specifically disposed on the front surface of the first encapsulation layer 112 to be physically connected (electrically connected) through the second metal layer 114 located between the first dielectric layer 115 and the first encapsulation layer 112, and is physically connected to the second encapsulation layer 117 through the fourth metal layer 116 on its top surface; while the second dielectric layer 132 can be located on the second surface 100b of the first substrate 100 to add a dielectric layer on both sides of the structure encapsulating the first chip 113; and at least one conductive post, such as the third conductive post 120, can also be disposed in the first dielectric layer 115 and the second dielectric layer 132; specifically, at least one of the third conductive posts 120 can pass through the first dielectric layer 115 or the second dielectric layer 132 to directly contact (physically connect) the second metal layer 114 and the fourth metal layer 116, or directly contact the third metal layer 131. It should be understood that the first conductive post 118, the second conductive post 119, and the third conductive post 120 in the embodiments of the present invention can overlap in the vertical projection, or it can be understood that the first conductive post 118, the second conductive post 119, and the third conductive post 120 are aligned in the vertical direction to achieve electrical connection between multiple mold layers in the encapsulation structure of the present invention, but not limited thereto. In one embodiment, the materials of the first dielectric layer 115 and the second dielectric layer 132 can be thermosetting resins, and since the first chip 113 has been pre-mounted, positive pressure can be applied to the first encapsulation layer 112 when laminating to form the first dielectric layer 115, that is, to prevent the first chip 112 from being damaged, and at the same time, the purpose of reducing the encapsulation difficulty and cost can be achieved; secondly, since the materials of the first dielectric layer 115 and the second dielectric layer 132 in the embodiments of the present invention are thermosetting resins, and thermosetting resins have the characteristic of being able to proceed under uniform pressure during the thermal curing process, stress redistribution can also be achieved during the formation of the first dielectric layer 115 and the second dielectric layer 132 in the embodiments of the present invention, thereby achieving the purpose of offsetting stress and improving warpage. And the purpose of improving the wiring density can also be achieved by using the method of adding dielectric layers on both sides.
[0064] In addition, in the first embodiment of the present invention, since a first dielectric layer 115 is provided on one side of the first encapsulation layer 112, and a first substrate 100 is provided on the other side thereof, and the material of the first encapsulation layer 112 is a plastic encapsulation material, therefore, in the embodiment of the present invention, the first plastic encapsulation layer 112 can also be used as the dielectric layer between the first substrate 100 and the first dielectric layer 115, thereby achieving the purpose of improving the wiring density.
[0065] Continuing to refer to Figure 1 , or Figures 2 to 5 , in the encapsulation structure of the first embodiment of the present invention, after the first dielectric layer 115 and the second dielectric layer 132 are synchronously formed, a second encapsulation layer 117 can be further formed in a conformal manner on the fourth metal layer 116 on the surface of the first dielectric layer 115, and other chips, such as a second chip (not shown), are also encapsulated in the second encapsulation layer 117 to achieve single-sided multi-layer stacked encapsulation, but not limited thereto. It should be understood that in the encapsulation structure of the first embodiment of the present invention, a metal layer, such as a fifth metal layer 133, can be further provided on the other surface of the second dielectric layer 132 away from the first substrate 100, and the material of the fifth metal layer 133 can also be the same as the materials of the foregoing first to fourth metal layers, such as copper, but not limited thereto.
[0066] Those of ordinary skill in the art to which the present invention pertains should easily understand that, in order to meet the requirements of actual products, there may be other aspects of the encapsulation structure of the present invention and are not limited to the foregoing. Other embodiments or variations of the encapsulation structure of the present invention will be further described below. And for the sake of simplicity in description, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.
[0067] Please refer to Figure 6 , which shows a cross-sectional schematic diagram of an example of the encapsulation structure in the second embodiment of the present invention. As Figure 6As shown, the structure of the packaging structure in the second embodiment of the present invention is generally the same as that of the packaging structure in the foregoing first embodiment. For example, it includes the first substrate 100, the first metal layer 111, the first packaging layer 112, the first chip 113, the second metal layer 114, the first dielectric layer 115, the fourth metal layer 116, the second packaging layer 117, and the third metal layer 131. At least one first conductive post 118 can also be provided in the first substrate 100, so as to realize the electrical connection (physical contact) between multiple film layers in the packaging structure by connecting the end portions of the first conductive posts 118 to the first metal layer 111 and the third metal layer 131 covering the first surface 100a and the second surface 100b of the first substrate 100 respectively. At least one second conductive post 119 can be provided in the first packaging layer 112, and at least one third conductive post 120 can be provided in the first dielectric layer 115, etc. The same parts will not be described in detail here. The main difference between the packaging structure of the second embodiment of the present invention and the foregoing first embodiment is that: a second dielectric layer 132 is not provided on the side of the second surface 100b of the first substrate 100, that is, only one dielectric layer is provided in the second embodiment of the present invention. For example, only a first dielectric layer 115 is formed on the second metal layer 114 on the first packaging layer 112; however, since the material of the first dielectric layer 115 is still a thermosetting resin, the second embodiment of the present invention can still achieve positive pressure on the first packaging layer 112 when laminating to form the first dielectric layer 115, that is, to prevent the first chip 112 from being damaged, and can also achieve the purpose of reducing the packaging difficulty and cost, and achieving the purpose of stress redistribution, stress cancellation, warpage improvement, and wiring density improvement.
[0068] It should be understood that "conformal" in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the similarity and relevance in the morphology between two or more shapes.
[0069] In order to enable those of ordinary skill in the technical field to which the present invention pertains to easily understand the packaging structures in the first to sixth embodiments of the present invention, the present invention also provides a packaging method for the packaging structure. The following will be described Figure 1 by taking the
[0070] aforementioned packaging structure as an example, and further explaining the packaging method of the packaging structure proposed by the present invention in combination with the schematic diagrams of each structure in the preparation process of the packaging method of the packaging structure. Figures 7 to 11 Among them, Figure 1 it is the schematic diagram corresponding to the corresponding steps of the packaging method of the packaging structure provided in the first embodiment of the present invention shown
[0071] Please refer to Figure 7, first, a first substrate 100 is provided. Circuit structures such as a piezoelectric layer (not shown), interdigital transducers (not shown), a substrate (not shown), a trap layer (not shown), and one or more dielectric layers (not shown) may be provided in the first substrate 100, and are not limited thereto. Specifically, the first substrate 100 may be formed of at least one of insulating materials or include at least one of insulating materials. For example, the first substrate 100 may include photosensitive epoxy resin or PP fiberglass cloth. More specifically, the first substrate 100 may include photoimageable dielectric (PID), and is not limited thereto. Other components and / or devices may be provided in the first substrate 100, such as circuit structures like a piezoelectric layer (not shown), etc., and wiring layers for electrically connecting different circuit structures, and are not limited thereto. Then, processes such as deposition (e.g., by sputtering, printing, electroplating, electroless plating, CVD, etc.), photolithography, and etching (dry etching or wet etching) are used to form a first metal layer 111 and a third metal layer 132 on the first surface 100a and the second surface 100b opposite to this surface of the first substrate 100 respectively, and at least one first conductive post 118 is formed in the first substrate 100; in one embodiment, the materials of the first metal layer 111 and the third metal layer 132 may be the same, for example, may include but are not limited to metal materials such as copper, titanium, nickel, gold, and their combinations or alloys, preferably metal copper, and the material of the first conductive post 118 may also be the same as the materials of the first metal layer 111 and / or the third metal layer 132, and are not limited thereto.
[0072] Please refer to Figure 8 and Figure 9 , then, on the first metal layer 111 on the side of the first surface 100a of the first substrate 100, at least one bump 113a on the front or back of the first chip 113 is mounted on the first metal layer 111 of the first substrate 100 by means of flip-chip die bonding or the like, and then a first encapsulation layer 112 that encapsulates or buries the first chip 113 is formed by using the C-mold process; then, processes such as etching, sputtering, printing, electroplating, electroless plating, CVD, etc. are used to form a plurality of second conductive posts 119 on both sides of the first chip 113 in the first encapsulation layer 112, and a second metal layer 114 is formed on the top surface of the first encapsulation layer 112. In one embodiment, the material of the second metal layer 114 may be the same as the material of the first metal layer 111, and the material of the first encapsulation layer 112 may be a thermoplastic encapsulant, and are not limited thereto.
[0073] Please refer to Figure 10 and Figure 11, the first dielectric layer 115 and the second dielectric layer 132 made of thermosetting resin can be formed simultaneously on the surface of the second metal layer 114 on the first encapsulation layer 112 and on the third metal layer 131 on the second surface 100b of the first substrate 100 by using a thermal curing method. Subsequently, a fourth metal layer 116 and a fifth metal layer 133 are respectively formed on the first dielectric layer 115 or the second dielectric layer 132 by using the same method as forming the first metal layer 111 or the second metal layer 114. Finally, a second encapsulation layer 117 is formed on the top surface of the fourth metal layer 114, and at least one other chip, such as a second chip, but not limited thereto, can be encapsulated in the second encapsulation layer 117. Moreover, the materials of the fourth metal layer 116 and the fifth metal layer 133 can be the same as the material of the first metal layer 111, but not limited thereto.
[0074] In summary, in the encapsulation structure and its encapsulation method provided by the present invention, unilateral encapsulation can be first performed on the first substrate. For example, a first encapsulation layer with a first chip disposed therein is formed on the first surface of the first substrate, and then at least one dielectric layer, such as the first dielectric layer, is laminated on the first encapsulation layer. The unexpected effects are as follows: Since the first chip has been pre-mounted, when the first dielectric layer is laminated and formed, the first encapsulation layer can be pressed from the front, which can not only prevent the first chip from being damaged, but also reduce the encapsulation difficulty and cost; and, while the first dielectric layer is laminated on the first encapsulation layer, a second dielectric layer can be laminated on the second surface (the surface without the first encapsulation layer) of the first substrate. The unexpected effects are as follows: By using the first dielectric layer and the second dielectric layer made of thermosetting resin, the characteristic that they can be under uniform pressure during the thermal curing process is utilized to realize stress redistribution, that is, to offset stress, so as to achieve the purpose of improving warpage. Secondly, the purpose of increasing the wiring density can also be achieved by adding the first dielectric layer or the second dielectric layer.
[0075] In this application, the reference to "one embodiment" or "some embodiments" means that the features, structures or characteristics described in connection with the embodiment are included in at least one embodiment or at least some embodiments of this application. Therefore, the appearances of the phrases "in one embodiment" or "in some embodiments" throughout this application are not necessarily referring to the same or the same group of embodiments. In addition, in one or more embodiments, the features, structures or characteristics can be combined in any suitable combination and / or sub-combination.
[0076] Although some specific embodiments of the present application have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present application. The embodiments of the present application can be combined arbitrarily without departing from the spirit and scope of the present application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.
Claims
1. An encapsulation structure, characterized in that, Comprising: A first substrate having a first surface and a second surface disposed opposite to each other; A first metal layer disposed on the first surface of the first substrate; A first encapsulation layer disposed on the first metal layer and including at least one first chip embedded therein, with a first gap between the first chip and the first metal layer; A second metal layer disposed on the first encapsulation layer and having a second gap with the first chip; A first dielectric layer disposed on the second metal layer.
2. The encapsulation structure according to claim 1, wherein, Further comprising: A third metal layer disposed on the second surface of the first substrate; A second dielectric layer disposed on the third metal layer.
3. The encapsulation structure according to claim 2, wherein Further comprising: A fourth metal layer disposed on the first dielectric layer; A second encapsulation layer located on the fourth metal layer.
4. The encapsulation structure according to claim 2, wherein, Further comprising: At least one first conductive pillar located within the first substrate and passing through the first substrate to be in direct contact with the first metal layer and / or the third metal layer on the first substrate.
5. The encapsulation structure according to claim 1, characterized in that Further comprising: At least one second conductive pillar located within the first encapsulation layer on at least one side of the first chip and passing through the first encapsulation layer to be in direct contact with the first metal layer and the second metal layer.
6. The encapsulation structure according to claim 1, characterized in that Further comprising: At least one solder ball located within the first encapsulation layer on at least one side of the first chip and passing through the first encapsulation layer to be in direct contact with the first metal layer and the second metal layer.
7. The encapsulation structure according to claim 3, wherein Further comprising: At least one third conductive pillar disposed in the first dielectric layer and / or the second dielectric layer and passing through the first dielectric layer and / or the second dielectric layer to be in direct contact with the second metal layer, the fourth metal layer and / or the third metal layer.
8. The encapsulation structure according to claim 1, wherein Further comprising: A plurality of bumps or a plurality of solder joints located in the first gap or the second gap to mount the first chip within the first encapsulation layer.
9. The encapsulation structure according to claim 2, characterized in that, The material of the first dielectric layer and / or the second dielectric layer includes a thermosetting resin.
10. The encapsulation structure according to claim 3, characterized in that, Further comprising: A second chip disposed within the second encapsulation layer.
11. A packaging method for a packaging structure, characterized in that, Comprising: Providing a first substrate having a first surface and a second surface disposed opposite to each other; Forming a first metal layer on the first surface of the first substrate; Forming a first encapsulation layer on the first metal layer, the first encapsulation layer including at least one first chip embedded therein, with a first gap between the first chip and the first metal layer; Forming a second metal layer on the first encapsulation layer, the second metal layer having a second gap with the first chip; Forming a first dielectric layer on the second metal layer.
12. The encapsulation method of the encapsulation structure according to claim 11, wherein Before or after forming the first metal layer, further comprising: Forming a third metal layer on the second surface of the first substrate; Forming at least one first conductive pillar within the first substrate and passing through the first substrate to be in direct contact with the first metal layer and / or the third metal layer on the first substrate.
13. The encapsulation method of the encapsulation structure according to claim 12, characterized in that, Before or after forming the second metal layer, further comprising: Forming at least one second conductive pillar within the first encapsulation layer on at least one side of the first chip and passing through the first encapsulation layer to be in direct contact with the first metal layer and the second metal layer.
14. The encapsulation method of the encapsulation structure according to claim 13, characterized in that, During the process of forming the first dielectric layer, a second dielectric layer is also simultaneously formed on the third metal layer.
15. The encapsulation method of the encapsulation structure according to claim 14, characterized in that, The material of the first dielectric layer and / or the second dielectric layer includes a thermosetting resin.
16. The encapsulation method of the encapsulation structure according to claim 14, characterized in that, Before or after forming the first dielectric layer and the second dielectric layer, it further includes: At least one third conductive post, disposed in the first dielectric layer and / or the second dielectric layer, and passing through the first dielectric layer and / or the second dielectric layer to be in direct contact with the second metal layer, the fourth metal layer, and / or the third metal layer.