Conductive feature formation and structure using bottom-up fill deposition

Abstract

Exemplary embodiments related to conductive features, such as metal contacts, vias, wires, and the like, and methods for forming those conductive features are provided. In some embodiments, a structure includes a first dielectric layer over a substrate; a first conductive feature passing through the first dielectric layer, the first conductive feature including a first metal; a second dielectric layer over the first dielectric layer; and a second conductive feature through the second dielectric layer having a lower convex surface extending to the first conductive feature, where the lower convex surface of the second conductive feature has a tip extending laterally below a bottom boundary of the second dielectric layer. Embodiments of the invention also relate to conductive feature formation and structures using bottom-up fill deposition.

Description

[0001] This application is a divisional application of the invention patent application with the application number 201810937837.7 and the title of "Formation and Structure of Conductive Components Using Bottom-Up Filling Deposition" submitted on August 17, 2018. Technical Field

[0002] Embodiments of the present invention relate to the formation and structure of conductive components using bottom-up filling deposition. Background Art

[0003] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, with each generation having smaller and more complex circuits than the previous one. During the evolution of ICs, the functional density (e.g., the number of interconnect devices per chip area) generally increases, while the geometric dimensions (e.g., the smallest component (or line) that can be produced using the manufacturing process) decrease. This scaling process typically provides benefits by increasing production efficiency and reducing associated costs.

[0004] As devices are scaled down, manufacturers have started using new and different materials and / or combinations of materials to facilitate device scaling. Scaling itself, along with the use of new and different materials, has presented challenges that may not have existed in previous generations with larger geometric dimensions. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor structure, comprising: a first dielectric layer located above a substrate; a first conductive component passing through the first dielectric layer, the first conductive component comprising a first metal; a second dielectric layer located above the first dielectric layer; and a second conductive component passing through the second dielectric layer, having a lower convex surface extending to the first conductive component, wherein the lower convex surface of the second conductive component has a tip that extends laterally below the bottom boundary of the second dielectric layer.

[0006] Another embodiment of the present invention provides a method for a semiconductor process, the method comprising: forming a first conductive component in a first dielectric layer; forming a concave surface on the first conductive component; and forming a second conductive component in a second dielectric layer located above the first dielectric layer, the second conductive component having a convex surface that matches the concave surface of the first conductive component, wherein the convex surface of the second conductive component has a tip that extends laterally below the bottom surface of the second dielectric layer.

[0007] Another embodiment of the present invention provides a method for a semiconductor process, the method comprising: performing an isotropic etching process through a second dielectric layer to form a concave surface on a first conductive component in a first dielectric layer, wherein the second dielectric layer is located above the first dielectric layer; and forming a second conductive component in the second dielectric layer using a bottom-up deposition process, the second conductive component having a convex surface that matches the concave surface on the first conductive component, wherein the convex surface of the second conductive component has a tip that extends laterally below the bottom surface of the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figures 1 to 12 are views of various intermediate structures at various stages during an exemplary method for forming a conductive component according to some embodiments.

[0010] Figure 13 is a flowchart of an exemplary method for forming a conductive component according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] Generally, the present invention provides exemplary embodiments related to conductive components (such as metal contacts, vias, wires, etc.) and methods for forming those conductive components. The upper conductive component formed in the upper dielectric layer is formed to have a convex structure to match the concave surface of the lower conductive component. The convex structure of the upper conductive component may further have a tip that aids in adhesion to the lower conductive component formed in the underlying dielectric structure, wherein the lower conductive component is formed in the underlying dielectric structure. Thus, adhesion and interface management can be better controlled. The total contact surface area of the second conductive component is also increased, thereby effectively improving electrical performance and reducing contact resistance.

[0014] The exemplary embodiments described herein are described in the context of forming conductive components in a back-end-of-line (BEOL) and / or middle-end-of-line (MEOL) process for a fin field-effect transistor (FinFET). Other embodiments may be employed in other contexts such as other devices having different devices, such as planar field-effect transistors (FETs), vertical gate-all-around (VGAA) FETs, horizontal gate-all-around (HGAA) FETs, bipolar junction transistors (BJTs), diodes, capacitors, inductors, resistors, etc. In some instances, the conductive component may be part of a device, such as a plate of a capacitor or a wire of an inductor. Additionally, some embodiments may be employed in a front-end-of-line (FEOL) process and / or for forming any conductive component. Implementations of some aspects of the present invention may be used in other processes and / or other devices.

[0015] Some variations of the exemplary methods and structures are described. Those skilled in the art will readily understand that other variations that can be made are expected to be within the scope of other embodiments. Although method embodiments may be described in a particular order, each of the other method embodiments may be implemented in any logical order and may include fewer or more steps than those described herein. In some figures, some reference numerals of the components or parts shown herein may be omitted to avoid obscuring other components or parts; this is for ease of describing the drawings.

[0016] Figures 1 to 12 is a view of various intermediate structures at various stages during an exemplary method for forming a conductive component according to some embodiments. Figure 1 A perspective view of an intermediate structure at one stage of an exemplary method is shown. The intermediate structure described below is for an implementation of a FinFET. Other structures may be employed in other exemplary embodiments.

[0017] The intermediate structure includes a first fin and a second fin 46 formed on a semiconductor substrate 42, and corresponding isolation regions 44 on the semiconductor substrate 42 located between adjacent fins 46. First and second dummy gate stacks are along respective sidewalls of the fins 46 and above the fins 46. Each of the first and second dummy gate stacks includes an interface dielectric 48, a dummy gate 50, and a mask 52.

[0018] The semiconductor substrate 42 can be or include a doped (e.g., doped with p-type or n-type dopants) or undoped bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc. In some embodiments, the semiconductor material of the semiconductor substrate 42 can include elemental semiconductors such as silicon (Si) or germanium (Ge); compound semiconductors; alloy semiconductors; combinations thereof.

[0019] The fins 46 are formed in the semiconductor substrate 42. For example, by suitable lithography and etching processes, the semiconductor substrate 42 can be etched such that trenches are formed between adjacent fins 46 and such that the fins 46 protrude from the semiconductor substrate 42. Respective isolation regions 44 are formed in the corresponding trenches. The isolation regions 44 can include or be an insulating material such as an oxide (such as silicon oxide), a nitride, etc. or a combination thereof. After deposition, the insulating material can be recessed to form the isolation regions 44. The insulating material is recessed using an acceptable etching process such that the fins 46 can protrude at least partially between adjacent isolation regions 44, thereby describing the fins 46 as active regions on the semiconductor substrate 42. For example, the fins 46 can be formed by other processes and can include homoepitaxial and / or heteroepitaxial structures.

[0020] The dummy gate stacks are formed on the fins 46. In a replacement gate process as described herein, for example, the respective layers can be sequentially formed by appropriate deposition processes and then patterned into the dummy gate stacks by appropriate lithography and etching processes to form the interface dielectric 48, the dummy gate 50, and the mask 52 for the dummy gate stacks. For example, the interface dielectric 48 can include or be silicon oxide, silicon nitride, etc. or a multi-layer thereof. The dummy gate 50 can include or be silicon (e.g., polysilicon) or other materials. The mask 52 can include or be silicon nitride, silicon oxynitride, silicon carbonitride, etc. or a combination thereof.

[0021] In other instances, instead of and / or in addition to the dummy gate stack, the gate stack can be the gate stack (or more generally, the gate structure) of the operations in the pre-gate process. In the pre-gate process, the interface dielectric 48 can be the gate dielectric layer, and the dummy gate 50 can be the gate electrode. The corresponding layers can be formed sequentially by appropriate deposition processes, and then those layers can be patterned into the gate stack by appropriate lithography and etching processes to form the gate dielectric layer, the gate electrode, and the mask 52 of the gate stack for operation. For example, the gate dielectric layer can include or be silicon oxide, silicon nitride, a high-k dielectric material, etc. or a multi-layer thereof. The high-k dielectric material can have a k value greater than about 7.0 and can include metal oxides or metal silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), multi-layers thereof, or combinations thereof. The gate electrode can include or be silicon (e.g., polysilicon, which can be doped or undoped), a metal-containing material (such as titanium, tungsten, aluminum, ruthenium, etc.), combinations thereof (such as silicides (which can be formed subsequently)), or multi-layers thereof. The mask 52 can include or be silicon nitride, silicon oxynitride, silicon carbonitride, etc. or combinations thereof.

[0022] Figure 1 Also shown are reference cross-sections used in subsequent figures. For example, cross-section A-A is in the plane of the channel in the fin 46 between the opposing source / drain regions. Figures 2 to 12 Cross-sectional views are shown at various stages of the process in various exemplary methods corresponding to cross-section A-A. Figure 2 Shown is at cross-section A-A Figure 1 of the intermediate structure.

[0023] Figure 3 Shown is the formation of the gate spacer 54, the epitaxial source / drain region 56, the contact etch stop layer (CESL) 60, and the first interlayer dielectric (ILD) 62. The gate spacer 54 is formed along the sidewalls of the dummy gate stack (e.g., the sidewalls of the dielectric 48, the dummy gate 50, and the mask 52) and over the fin 46. For example, the gate spacer 54 can be formed by conformally depositing one or more layers for the gate spacer 54 by an appropriate deposition process and anisotropically etching the one or more layers. The one or more layers for the gate spacer 54 can include or be silicon carbon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., multi-layers thereof, or combinations thereof.

[0024] Then, trenches are formed in the fins 46 on opposite sides of the dummy gate stack (e.g., using the dummy gate stack and the gate spacers 54 as a mask) through an etching process. The etching process can be isotropic or anisotropic, or can be selective with respect to one or more crystal planes of the semiconductor substrate 42. Thus, based on the etching process employed, the trenches can have respective cross-sectional profiles. Epitaxial source / drain regions 56 are formed in the trenches. The epitaxial source / drain regions 56 can include or be silicon germanium, silicon carbide, silicon phosphorus, silicon carbon phosphorus, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. The epitaxial source / drain regions 56 can be formed in the trenches through a suitable epitaxial growth or deposition process. In some instances, the epitaxial source / drain regions 56 can protrude with respect to the fins 46 and can have facets that can correspond to the crystal planes of the semiconductor substrate 42.

[0025] Those skilled in the art will also readily understand that the recessing and epitaxial growth can be omitted, and the source / drain regions can be formed by implanting dopants into the fins 46 using the dummy gate stack and the gate spacers 54 as a mask. In some instances where the epitaxial source / drain regions 56 are employed, the epitaxial source / drain regions 56 can also be doped, such as by in-situ doping during epitaxial growth and / or by implanting dopants into the epitaxial source / drain regions 56 after epitaxial growth. Thus, the source / drain regions can be delineated by doping (e.g., by implantation and / or in-situ doping during epitaxial growth if appropriate) and / or by epitaxial growth, and if appropriate, the active regions (in which the source / drain regions are delineated) can be further delineated.

[0026] The CESL 60 is conformally deposited on the surface of the epitaxial source / drain regions 56, the sidewalls and top surfaces of the gate spacers 54, the top surface of the mask 52, and the top surface of the isolation regions 44 through a suitable deposition process. Generally, when forming, for example, contacts or vias, an etch stop layer (ESL) can provide a mechanism for stopping the etching process. The ESL can be formed of a dielectric material having an etching selectivity different from that of adjacent layers or components. The CESL 60 can include or be silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, etc. or a combination thereof.

[0027] The first ILD 62 is deposited on the CESL 60 through a suitable deposition process. The first ILD 62 can include or be silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon dioxide), silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorosilicate glass (FSG), organosilicate glass (OSG), SiO x C y, spin-on glass, spin-on polymer, silicon carbide material, their compounds, their composites, etc., or combinations thereof.

[0028] The first ILD 62 can be planarized after deposition, such as by chemical mechanical planarization (CMP). In the prior gate process, the top surface of the first ILD 62 can be located above the CESL 60 and the gate stack, and the processes described below regarding Figure 4 and Figure 5 can be omitted. Thus, the upper portion of the CESL 60 and the first ILD 62 can be retained above the gate stack.

[0029] Figure 4 Shows replacing the dummy gate stack with a replacement gate structure. The top surfaces of the first ILD 62 and the CESL 60 are formed coplanar with the top surface of the dummy gate 50. A planarization process such as CMP can be implemented to make the top surfaces of the first ILD 62 and the CESL 60 flush with the top surface of the dummy gate 50. CMP can also remove the mask 52 on the dummy gate 50 (and, in some cases, the upper portion of the gate spacer 54). Thus, the top surface of the dummy gate 50 is exposed through the first ILD 62 and the CESL 60.

[0030] When the dummy gate 50 is exposed through the first ILD 62 and the CESL 60, the dummy gate 50 is removed, such as by one or more etching processes. The dummy gate 50 can be removed by an etching process selective to the dummy gate 50, where the interface dielectric 48 serves as the ESL, and subsequently, the interface dielectric 48 can be optionally removed by a different etching process selective to the interface dielectric 48. Grooves are formed between the gate spacers 54 (removing the dummy gate stack therein), and the channel region of the fin 46 is exposed through the grooves.

[0031] A replacement gate structure is formed in the groove formed by removing the dummy gate stack. As shown, each replacement gate structure includes an interface dielectric 70, a gate dielectric layer 72, one or more optional conformal layers 74, and a gate conductive fill material 76. The interface dielectric 70 is formed on the sidewalls and top surface of the fin 46 along the channel region. For example, the interface dielectric 70 can be the interface dielectric 48 (if not removed), an oxide (e.g., silicon oxide) formed by thermal oxidation or chemical oxidation of the fin 46, and / or an oxide (e.g., silicon oxide), silicon nitride (e.g., silicon nitride), and / or other dielectric layers.

[0032] A gate dielectric layer 72 is conformally deposited in the recesses formed by removing the dummy gate stack (e.g., on the top surface of the isolation region 44, on the interface dielectric 70, and on the sidewalls of the gate spacers 54) and on the top surfaces of the first ILD 62, the CESL 60, and the gate spacers 54. The gate dielectric layer 72 can be or include silicon oxide, silicon nitride, a high-k dielectric material (examples of high-k dielectric materials are provided above), a multi-layer thereof, or other dielectric materials.

[0033] Then, one or more optional conformal layers 74 can be conformally deposited (sequentially deposited if more than one layer) on the gate dielectric layer 72. The one or more optional conformal layers 74 can include one or more barrier layers and / or capping layers and one or more work function adjustment layers. The one or more barrier layers and / or capping layers can include nitrides, silicon nitrides, carbon nitrides, and / or aluminum nitrides of tantalum and / or titanium; nitrides, carbon nitrides, and / or carbides of tungsten, etc.; or combinations thereof. The one or more work function adjustment layers can include or be nitrides, silicon nitrides, carbon nitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides of titanium and / or tantalum; nitrides, carbon nitrides, and / or carbides of tungsten; cobalt; platinum, etc.; or combinations thereof.

[0034] A layer for the gate conductive fill material 76 is formed above the one or more optional conformal layers 74 (if employed, e.g., above the one or more work function adjustment layers) and / or above the gate dielectric layer 72. The layer for the gate conductive fill material 76 can fill the remaining recesses at the location where the dummy gate stack is removed. The layer for the gate conductive fill material 76 can be or include metal-containing materials such as tungsten, cobalt, aluminum, ruthenium, copper, multi-layers thereof, combinations thereof, etc. Portions of the layer for the gate conductive fill material 76, the one or more optional conformal layers 74, and the gate dielectric layer 72 above the top surfaces of the first ILD 62, the CESL 60, and the gate spacers 54 are removed, for example, by CMP. Thus, as Figure 4 shown, a replacement gate structure including the gate conductive fill material 76, the one or more optional conformal layers 74, the gate dielectric layer 72, and the interface dielectric 70 can be formed.

[0035] Figure 5 The formation of a second ILD 80 located above the first ILD 62, the CESL 60, the gate spacers 54, and the replacement gate structure is shown. Although not shown, in some examples, an ESL can be deposited above the first ILD 62, etc., and the second ILD 80 can be deposited above the ESL. If employed, the ESL can include or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, etc., or combinations thereof. The second ILD 80 can include or be silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOx C y , spin-on glass, spin-on polymer, silicon carbide material, their compounds, their composites, etc., or combinations thereof.

[0036] Figure 6 Shows forming corresponding openings 82 through the second ILD 80, the first ILD 62, and the CESL 60 to expose at least a portion of the epitaxial source / drain region 56 and forming corresponding openings 84 through the second ILD 80 to expose at least a portion of the replacement gate structure. For example, the second ILD 80, the first ILD 62, and the CESL 60 can be patterned to have openings 82 and 84 using photolithography and one or more etching processes.

[0037] Figure 7 Shows forming conductive components 90 and 92 to the epitaxial source / drain region 56 and the replacement gate structure in the openings 82 and 84, respectively. For example, in the illustrated embodiment, the conductive component 90 includes an adhesion layer 94, a barrier layer 96 on the adhesion layer 94, a silicide region 98 on the epitaxial source / drain region 56, and a conductive fill material 100 on the barrier layer 96. For example, in the illustrated embodiment, the conductive component 92 includes an adhesion layer 94, a barrier layer 96 on the adhesion layer 94, and a conductive fill material 100 on the barrier layer 96.

[0038] The adhesion layer 94 can be conformally deposited in the openings 82 and 84 (e.g., on the sidewalls of the openings 82 and 84, the exposed surfaces of the epitaxial source / drain region 56, and the exposed surfaces of the replacement gate structure) and above the second ILD 80. The adhesion layer 94 can be or include titanium, tantalum, etc., or combinations thereof, and can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition techniques. The barrier layer 96 can be conformally deposited on the adhesion layer 94, such as in the openings 82 and 84 and above the second ILD 80. The barrier layer 96 can be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, etc., or combinations thereof, and can be deposited by ALD, CVD, or other deposition techniques. In some instances, at least a portion of the adhesion layer 94 can be processed to form the barrier layer 96. For example, a nitridation process (such as including a nitrogen plasma process) can be performed on the adhesion layer 94 to convert at least a portion of the adhesion layer 94 into the barrier layer 96. In some instances, the adhesion layer 94 can be completely converted such that no adhesion layer 94 remains and the barrier layer 96 is an adhesion / barrier layer, while in other instances, a portion of the adhesion layer 94 remains unconverted such that a portion of the adhesion layer 94 remains with the barrier layer 96 on the adhesion layer 94.

[0039] A silicide region 98 can be formed on the epitaxial source / drain region 56 by reacting the upper portion of the epitaxial source / drain region 56 with the adhesion layer 94 and possibly the barrier layer 96. Annealing can be implemented to promote the reaction of the epitaxial source / drain region 56 with the adhesion layer 94 and / or the barrier layer 96.

[0040] A conductive fill material 100 can be deposited on the barrier layer 96 and fill the openings 82 and 84. The conductive fill material 100 can be or include cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, their alloys, etc. or combinations thereof, and can be deposited by CVD, ALD, PVD or other deposition techniques. For example, after depositing the conductive fill material 100, the excess conductive fill material 100, the barrier layer 96 and the adhesion layer 94 can be removed by a planarization process such as CMP. The planarization process can remove the excess conductive fill material 100, the barrier layer 96 and the adhesion layer 94 from above the top surface of the second ILD 80. Thus, the top surfaces of the conductive components 90 and 92 and the second ILD 80 can be coplanar. The conductive components 90 and 92 can be or can be referred to as contacts, plugs, etc.

[0041] Although Figure 6 and Figure 7 illustrate the simultaneous formation of the conductive component 90 to the epitaxial source / drain region 56 and the conductive component 92 to the replacement gate structure, the conductive components 90 and 92 can be formed separately or sequentially. For example, the opening 82 to the epitaxial source / drain region 56 as Figure 6 shown can be formed first, and the opening 82 can be filled to form the conductive component 90 to the epitaxial source / drain region 56 as Figure 7 shown. Then, the opening 84 to the replacement gate structure as Figure 6 shown can be formed, and the opening 84 can be filled to form the conductive component 92 to the replacement gate structure as Figure 7 shown. Another order of the process can be adopted.

[0042] Figure 8 illustrates the formation of the ESL 110 and the formation of the intermetal dielectric (IMD) 112 above the ESL 110. The ESL 110 is deposited on the top surfaces of the second ILD 80 and the conductive components 90 and 92. The ESL 110 can include or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, etc. or combinations thereof, and can be deposited by CVD, plasma enhanced CVD (PECVD), ALD or other deposition techniques. The IMD 112 can include or be silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiO x C y, spin-on glass, spin-on polymer, silicon carbide material, their compounds, their composites, etc. or combinations thereof. IMD112 can be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD or other deposition techniques. The thickness of ESL110 can be in the range of about 10 nm to about 500 nm, and the thickness of IMD112 can be in the range of about 50 nm to about 800 nm. The combined thickness of IMD112 and ESL110 can be in the range of about 100 nm to about 1000 nm.

[0043] Figure 9 Shows the formation of openings 120 and 122 through IMD112 and ESL110 to conductive components 90 and 92, respectively. For example, IMD112 and ESL110 can be patterned to have openings 120 and 122 using photolithography and one or more etching processes. The etching process can include reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, capacitively coupled plasma (ICP) etching, ion beam etching (IBE), etc. or combinations thereof. The etching process can be anisotropic. In some instances, the etching process can include using a plasma of a first gas, the first gas including carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), fluorinated carbon (e.g., C x F y , where x can be in the range from 1 to 5 and y can be in the range from 4 to 8), etc. or combinations thereof. The plasma can also use a second gas, the second gas including nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), helium (He), carbon monoxide (CO), carbon dioxide (CO2), carbonyl sulfide (COS), etc. or combinations thereof. An inert gas can be optionally supplied during the etching process. In some instances, the ratio of the flow rate of the first gas to the flow rate of the second gas can be in the range from about 1:1000 to about 1000:1, such as from about 1:10 to about 10:1. The pressure of the plasma etching can be in the range from about 0.1 mTorr to about 100 mTorr. The power of the plasma generator for plasma etching can be in the range from about 30 W to about 5000 W. The frequency of the plasma generator for plasma etching can be about 40 KHz, about 2 MHz, or from about 12 MHz to about 100 MHz, such as about 13.56 MHz. The substrate bias voltage of the plasma etching can be in the range from about 10 kV to about 100 kV, and the duty cycle can be in the range from about 5% to about 95%.

[0044] Figure 10Illustrated is the formation of grooves 202, 201 in conductive components 90 and 92, which are formed through openings 120 and 122 in IMD 112 and ESL 110 to conductive components 90 and 92. After forming openings 120 and 122, a wet cleaning process can be implemented to remove residues and native oxides of conductive components 90 and 92. The residues can be from etching by-products during the formation of openings 120, 122 in previous operation steps. The residues can also be from the environment when the substrate is transferred between different process chambers during the formation of IMD 112 and ESL 110. In addition, native oxides are generally formed on the surfaces of conductive components 90, 92. A wet cleaning process is implemented to effectively remove residues and native oxides of conductive components 90, 92. In addition, after removing residues and / or native oxides from the surfaces of conductive components 90, 92, the wet cleaning process also etches the surfaces of conductive components 90, 92 to form grooves 202, 201 on the surfaces of conductive components 90, 92.

[0045] In an example, the wet cleaning process can include immersing semiconductor substrate 42 in deionized (DI) water or another suitable chemical (which can be diluted in DI water). It is believed that DI water can react with native oxides and residues grown on the surfaces of conductive components 90, 92. In an example where conductive components 90, 92 are made of Co-containing materials, DI water can effectively react with x、 CoFx to remove native oxides (e.g., CoO x ), residues (e.g., CoF x ), and a portion of Co thereunder, thereby forming grooves 202, 201 on conductive components 90, 92. Grooves 202, 201 can be formed to have a concave surface (e.g., an upper concave surface on conductive components 90, 92) with tips 203, 205 (as shown in groove 202, formed below the bottom surface of ESL 110). Since the wet cleaning process is an isotropic etching process, when the solution contacts conductive components 90, 92, the chemical reaction between the solution and conductive components 90, 92 proceeds isotropically and continuously until a predetermined process time period is reached. It is believed that tips 203, 205 of groove 202 extend laterally from conductive components 90, 92 and further extend below the bottom surface of ESL 110. Tips 203, 205 can assist materials subsequently formed therein to be anchored and joined in openings 120, 122 in a better bonding and riveting manner.

[0046] After cleaning with DI water, the semiconductor substrate 42 can be further optionally cleaned with a solution including other chemicals in the DI water. Suitable examples of the chemicals include acid chemicals (such as citric acid) or mixtures of acid chemicals. The volume concentration of the chemicals in the DI water can be from about 0.1% to about 20%. During the immersion, the solution can be at a temperature in the range from about 20 °C to about 90 °C. The semiconductor substrate 42 can be immersed in the solution for about 5 seconds to about 120 seconds to form the grooves 202, 201. After the cleaning, the grooves 202, 201 can have a depth 225 from the top surface (horizontal plane) of the second ILD 80 (see Figure 12 ), and the depth 225 is greater than such as from about to about and more specifically, such as from about to about However, other depths can be achieved. After immersion in the solution, the semiconductor substrate 42 can be optionally rinsed with isopropyl alcohol (IPA) to dry the semiconductor substrate 42.

[0047] Figure 11 It is shown that the second conductive components 204, 206 are partially formed in the openings 120 and 122 respectively, and the second conductive components 204, 206 are connected to the conductive components 90, 92. The second conductive components 204, 206 are formed in the grooves 202, 201 on the surfaces of the conductive components 90, 92, fill the grooves 202, 201, and the second conductive components 204, 206 are formed in a bottom-up manner for filling the openings 120, 122.

[0048] By forming the second conductive components 204, 206 in a bottom-up manner, the second conductive components 204, 206 can grow from the bottom surface (e.g., from the grooves 202, 201), and the second conductive components 204, 206 can grow mainly slowly and gradually from the bottom until the desired thickness / depth of the second conductive components 204, 206 is reached in the openings 120, 122. Therefore, undesirable defects such as voids or gaps can be eliminated because the possibility of premature closure of the openings 120, 122 or lateral growth in the openings 120, 122 is greatly reduced. Therefore, the bottom-up deposition process aids in forming the second conductive component into a seamless (or void-free) structure.

[0049] In an example, the second conductive components 204, 206 can be deposited in the openings 120, 122 by CVD, ALD, chemical deposition (ELD), PVD, electroplating, or other deposition techniques. In a specific example, the second conductive components 204, 206 are formed by a thermal CVD process (no plasma is generated during the deposition process). It is believed that the thermal CVD process can provide thermal energy to assist in forming nucleation sites for forming the second conductive components 204, 206. The thermal energy provided by the thermal CVD process can promote the incubation of nucleation sites over a relatively long time period. Since the deposition rate is controlled to be a relatively low deposition rate, such as less than per second, the slow growth process allows the nucleation sites to slowly grow into the second conductive components 204, 206. The low deposition rate can be controlled by supplying a deposition gas mixture (described in detail below) with a relatively low metal precursor ratio in a hydrogen dilution gas mixture, which will be described in detail below. Nucleation sites tend to form at specific locations on a substrate having similar material properties to the nucleation sites. For example, since the nucleation sites include a metal material for forming the second conductive components 204, 206, the nucleation sites tend to adhere and nucleate on a metal material (e.g., the first conductive components 90, 92) on the substrate. Once the nucleation sites are formed at the selected locations, thereafter, elements / atoms can continue to adhere and anchor on the nucleation sites, realizing the stacking of elements / atoms at the selected locations on the substrate, thereby providing a selective deposition process and a bottom-up deposition process. In Figure 11 the example shown, the nucleation sites are selectively incubated at specific locations in the openings 120, 122 (e.g., in the grooves 202, 201 above the first conductive components 90, 92), such that the second conductive components 204, 206 can grow vertically upward from the bottom of the grooves 202, 201 to fill the openings 120, 122.

[0050] The second conductive components 204, 206 can be or include tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, their alloys, etc. or a combination thereof. For ease of explaining the bottom-up deposition process, Figure 11 is shown where the second conductive components 204, 206 partially fill the openings 120, 122 and the deposition process is not completed or terminated. When the second conductive components 204, 206 substantially fill the openings 120, 122 to form complete second conductive components 207, 208, then the deposition process is terminated, as shown in Figure 12As shown. Since the second conductive components 207, 208 grow on the first conductive components 90, 92 and fill the grooves 202, 201, the bottoms of the resulting second conductive components 207, 208 have a substantially circular and / or convex structure 222 (filling the concave surfaces of the grooves 202, 201 having a depth 225). The convex structure 222 extends laterally and outwardly below the ESL 110 and below the top surface (e.g., horizontal plane) of the second ILD 80. The convex structure 222 has a depth 225 (e.g., the same depth as the concave surfaces of the grooves 202, 201), and the depth 225 is greater than such as from about to about and more specifically, such as from about to about However, other depths can be achieved. After the resulting second conductive components 207, 208 fill the grooves 202, 201, the second conductive components 207, 208 include tips 203, 205, respectively. As shown in the enlarged view 240 of Figure 12 , the tips 203, 205 are in direct contact with the bottom surface of the ESL 110 and have a width 250 in the range from about 1 nm to about 10 nm.

[0051] For example, the excess second conductive components 207, 208 growing outwardly from the openings 120, 122 can be removed by a planarization process such as CMP. The planarization process can remove the excess second conductive components 207, 208 from above the top surface of the IMD 112. Thus, the top surfaces of the second conductive components 207, 208 and the IMD 112 can be coplanar. The second conductive components 207, 208 can be or can be referred to as contacts, plugs, wires, conductive pads, vias, etc.

[0052] In addition, the better interface management provided by the convex structure 222 and the tips 203, 205 can also prevent the second conductive components 207, 208 from being undesirably pulled back during subsequent CMP processes.

[0053] In some instances, before depositing the second conductive components 207, 208 in the openings 120 and 122, the barrier and / or adhesion layer is removed in the openings 120 and 122. Since Figure 11 and Figure 12The examples shown herein illustrate a bottom-up deposition process. When nucleation sites are formed on the conductive components 90, 92 with a slow incubation, the second conductive components 207, 208 can grow directly from the underlying conductive components 90, 92 in the grooves 201, 202, and the barrier and / or adhesion layer can be eliminated. In some examples, when different metal materials are used for the conductive components 207, 208, different integration schemes can be utilized, such as additional interface layers or bottom layers. Additionally, as discussed above, the tips 203, 205 formed in the grooves 201, 202 also assist in the mechanical attachment (e.g., anchor pressure and / or riveting) of the second conductive components 207, 208 in the grooves 201, 202 to the underlying conductive components 90, 92, thereby promoting interface adhesion and integration. Moreover, since the conductive material of the second conductive components 207, 208 extends further downward to the conductive components 90, 92 at the interface where the convex structure 222 matches the concave surface of the conductive components 90, 92, the overall surface contact area of the second conductive components 207, 208 in the openings 120, 122 is increased, thus increasing the overall conductive contact surface area, thereby promoting electrical performance and lower interface / contact resistance.

[0054] In an example, a bottom-up thermochemical deposition process can be achieved by controlling the process pressure to be less than about 150 Torr (such as from about 5 Torr to about 100 Torr, for example, about 20 Torr). The process temperature can be controlled within the range from about 200 degrees Celsius to about 400 degrees Celsius. A deposition gas mixture including at least a metal precursor and a reactive gas is used. In a specific example, when the second conductive components 207, 208 are tungsten-containing materials, the metal precursor is a tungsten-containing precursor. Suitable examples of the metal precursor materials include WF6, WC l x R 1-x 、W(CO)6, etc. In an example, the deposition gas mixture includes WF6. Other reactive gases such as H2, N2, NH3, etc. can also be supplied in the deposition gas mixture. In a specific example, the deposition gas mixture includes WF6 and H2. The reactive gas and the metal precursor can be supplied at a ratio greater than 20. For example, WF6 and H2 can be supplied in a hydrogen gas dilution process. For example, the volume flow rate of H2 supplied in the deposition gas mixture is greater than the volume flow rate of the WF6 gas. The volume flow rate of the H2 gas is at least about 20 times greater than the volume flow rate of the WF6 gas (e.g., H2 / WF6 > 20). In a specific example, the ratio of the volume flow rate of the H2 gas to the volume flow rate of the WF6 gas is from about 30 to about 150, such as from about 40 to about 120. When the deposition gas mixture is supplied, the RF source or the bias power is not turned on and / or may not be necessary. Therefore, the deposition process can be a plasma-free deposition process.

[0055] Figure 13is a flowchart of an exemplary method for forming a conductive component according to some embodiments. In operation 502, a first conductive component is formed in a first dielectric layer. In Figure 6 and Figure 7 examples of operation 502 are shown and described. For example, a conductive component 90 is formed in a second ILD 80, a first ILD 62, and a CESL 60.

[0056] In operation 504, a second dielectric layer is formed over the first conductive component and the first dielectric layer. In Figure 8 examples of operation 504 are shown and described. For example, an ESL 110 and an IMD 112 are formed over the conductive component 90, as well as the second ILD 80, the first ILD 62, and the CESL 60.

[0057] In operation 506, an opening is formed through the second dielectric layer to the first conductive component. In Figure 9 examples of operation 506 are shown and described. For example, an opening 120 is formed through the ESL 110 and the IMD 112 to the conductive component 90.

[0058] In operation 508, a groove is formed in the first conductive component exposed by the opening through the second dielectric layer. In Figure 10 examples of operation 508 are shown and described. For example, a groove 201 is formed in the conductive component 90 exposed by the opening 120.

[0059] In operation 510, a second conductive component is formed in the opening through the second dielectric layer, fills the groove, and contacts the underlying first conductive component. The second conductive component is formed by a bottom-up process without the assistance of a barrier / adhesion layer at the interface where the second conductive component is formed and grown. In Figure 11 and Figure 12 examples of operation 510 are shown and described. For example, a second conductive component 208 is formed in the opening 120, fills the groove 202, and contacts the first conductive component 90.

[0060] Thus, by utilizing the groove formed between the first conductive component and the second conductive component and filling the groove with a conductive filling material, better interface management and electrical properties can be achieved. In addition, the bottom-up deposition process of the second conductive component can also assist in forming the second conductive component that directly contacts the underlying conductive component through the groove, without forming a barrier layer / adhesion layer at the interface and sidewalls, so better manufacturing control and device structure and performance can be obtained and achieved.

[0061] In an embodiment, a structure includes: a first dielectric layer located above a substrate; a first conductive component passing through the first dielectric layer, the first conductive component including a first metal; a second dielectric layer located above the first dielectric layer; and a second conductive component passing through the second dielectric layer and having a lower convex surface extending to the first conductive component, wherein the lower convex surface of the second conductive component has a tip extending laterally below the bottom boundary of the second dielectric layer. In an embodiment, the second conductive component is in direct contact with the second dielectric layer. In an embodiment, the second dielectric layer includes an etch stop layer. In an embodiment, the tip is in direct contact with the bottom surface of the etch stop layer. In an embodiment, the tip has a width in the range from 1 nm to about 10 nm. In an embodiment, the lower convex surface has a depth greater than . In an embodiment, the second conductive component includes a second metal different from the first metal. In an embodiment, the second conductive component is a seamless structure. In an embodiment, the first conductive component includes cobalt and the second conductive component includes tungsten.

[0062] In another embodiment, a method includes: forming a first conductive component in a first dielectric layer, forming a concave surface on the first conductive component, and forming a second conductive component in a second dielectric layer. The second dielectric layer is located above the first dielectric layer. The second conductive component has a convex surface matching the concave surface of the first conductive component. The convex surface of the second conductive component has a tip extending laterally below the bottom surface of the second dielectric layer. In an embodiment, the convex surface has a depth greater than . In an embodiment, the second conductive component is formed by a bottom-up deposition process. In an embodiment, the bottom-up deposition process further includes supplying a deposition gas mixture including a metal-containing gas and a reactive gas and maintaining the process pressure at less than 150 Torr. In an embodiment, the ratio of the flow rate of the reactive gas to the corresponding flow rate of the metal-containing gas is greater than 20. In an embodiment, the bottom-up deposition process is a thermal CVD process without plasma. In an embodiment, the concave surface of the first conductive component is formed by a wet cleaning process. In an embodiment, the second conductive component is in direct contact with the second dielectric layer, and there is no barrier layer and adhesion layer between the second conductive component and the second dielectric layer.

[0063] In yet another embodiment, a method for a semiconductor process includes: forming a concave surface on a first conductive component in a first dielectric layer by performing an isotropic etching process through a second dielectric layer, the second dielectric layer being located above the first dielectric layer, and forming a second conductive component in the second dielectric layer using a bottom-up deposition process. The second conductive component has a convex surface that matches the concave surface on the first conductive component. The convex surface of the second conductive component has a tip that extends laterally below the bottom surface of the second dielectric layer. In an embodiment, the second conductive component is not formed using plasma. In an embodiment, the isotropic etching process includes a wet etching process using a wet solution that removes native oxide from the first conductive component to form the concave surface.

[0064] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, comprising: A gate structure located above a substrate; A first dielectric layer located above and covering the gate structure; A first conductive component passing through the first dielectric layer to contact the gate structure, the first conductive component including a first metal, a first barrier layer surrounding the first metal, and a first adhesion layer surrounding the first barrier layer, wherein the first barrier layer is spaced apart from the gate structure by the adhesion layer; An epitaxial source / drain region located on the substrate and around the gate structure; A third conductive component passing through the first dielectric layer to contact the epitaxial source / drain region, wherein the third conductive component includes a third metal, a second barrier layer surrounding the third metal, and a second adhesion layer provided on a sidewall of the first barrier layer; A silicide region located on the epitaxial source / drain region and in direct contact with a bottom of the second barrier layer, wherein the first barrier layer, the first adhesion layer, the second barrier layer, the second adhesion layer, and the silicide region include the same metal; A second dielectric layer located above the first dielectric layer; and A second conductive component passing through the second dielectric layer, having a lower convex surface extending to the first conductive component, wherein a central axis of the second conductive component is offset from a central axis of the gate structure, and the lower convex surface of the second conductive component has a tip extending laterally below a bottom boundary of the second dielectric layer; wherein the first conductive component has a concave top surface, the concave top surface of the first conductive component continuously extends from a first sidewall of the first barrier layer to a second sidewall of the first barrier layer opposite to the first sidewall, the first sidewall has a first portion extending above a point where the concave top surface physically contacts the first sidewall, and the second sidewall has a second portion extending above a point where the concave top surface physically contacts the second sidewall; wherein the lower convex surface is a bottom surface of the second conductive component, and the lower convex surface continuously extends from the first sidewall to the second sidewall, and the lower convex surface physically contacts the first portion of the first sidewall and the second portion of the second sidewall.

2. The semiconductor structure according to claim 1, wherein, The second conductive component is in direct contact with the second dielectric layer.

3. The semiconductor structure according to claim 1, wherein, The second dielectric layer includes an etch stop layer.

4. The semiconductor structure according to claim 3, wherein, The tip is in direct contact with a bottom surface of the etch stop layer.

5. The semiconductor structure according to claim 1, wherein, The tip has a width in a range from 1 nm to 10 nm.

6. The semiconductor structure according to claim 1, wherein, The lower convex surface has a depth greater than .

7. The semiconductor structure according to claim 1, wherein, The second conductive component includes a second metal different from the first metal.

8. The semiconductor structure according to claim 1, wherein, The second conductive component is a seamless structure.

9. A method for a semiconductor process, the method comprising: Forming a gate structure above a substrate; Forming an epitaxial source / drain region around the gate structure; Forming a first dielectric layer above the gate structure and the epitaxial source / drain region to cover the gate structure; A first conductive component and a third conductive component are formed in a first dielectric layer, the first conductive component contacting the gate structure, the third conductive component passing through the first dielectric layer to contact the epitaxial source / drain region, wherein the first conductive component includes a first metal, a first barrier layer surrounding the first metal, and a first adhesion layer surrounding the first barrier layer, wherein the first barrier layer is spaced apart from the gate structure by the adhesion layer, wherein the third conductive component includes a third metal, a second barrier layer surrounding the third metal, and a second adhesion layer disposed on a sidewall of the first barrier layer, and wherein a silicide region is located on the epitaxial source / drain region and is in direct contact with a bottom of the second barrier layer, wherein the first barrier layer and the second barrier layer are respectively obtained by subjecting the first adhesion layer and the second adhesion layer to a nitridation process to respectively convert at least a portion of the first adhesion layer and the second adhesion layer, and wherein the first barrier layer, the first adhesion layer, the second barrier layer, the second adhesion layer, and the silicide region include the same metal; A concave surface is formed on the first conductive component, the concave surface continuously extending from a first sidewall of the first barrier layer of the first conductive component to a second sidewall of the first barrier layer opposite the first sidewall, wherein the step of forming the concave surface includes immersing the first conductive component in a solution including deionized water; and Using a thermal chemical vapor deposition process without plasma, nucleation sites are formed on the concave surface of the first conductive component, and then elements / atoms continue to adhere and anchor on the nucleation sites, so as to achieve growth vertically rather than laterally from the concave surface, to form a second conductive component in a second dielectric layer by a bottom-up deposition process, the second dielectric layer being located above the first dielectric layer, the second conductive component having a convex surface matching the concave surface of the first conductive component, the convex surface being a bottom surface of the second conductive component, and the lower convex surface continuously extending from the first sidewall to the second sidewall, wherein a central axis of the second conductive component is offset from a central axis of the gate structure, and the convex surface of the second conductive component has a tip extending laterally below a bottom surface of the second dielectric layer.

10. A method for a semiconductor process, the method comprising: An isotropic etching process is implemented through the second dielectric layer to form concave surfaces on the first and third conductive components in the first dielectric layer. The first conductive component includes a first metal, a first barrier layer surrounding the first metal, and a first adhesion layer surrounding the first barrier layer. The first barrier layer is spaced apart from the gate structure through the adhesion layer. The concave surface continuously extends from the first sidewall of the first barrier layer to the second sidewall of the first barrier layer opposite to the first sidewall. The first dielectric layer is located above and covers the gate structure. The first conductive component contacts the gate structure. The second dielectric layer is located above the first dielectric layer. The third conductive component passes through the first dielectric layer to contact the epitaxial source / drain region around the gate structure. The third conductive component includes a third metal, a second barrier layer surrounding the third metal, and a second adhesion layer disposed on the sidewall of the first barrier layer. A silicide region is located on the epitaxial source / drain region and is in direct contact with the bottom of the second barrier layer. The first barrier layer and the second barrier layer are respectively obtained by nitriding the first adhesion layer and the second adhesion layer to convert at least part of the first adhesion layer and the second adhesion layer. The first barrier layer, the first adhesion layer, the second barrier layer, the second adhesion layer, and the silicide region include the same metal; and A second conductive component is formed in the second dielectric layer using a bottom-up deposition process. The second conductive component has a convex surface that matches the concave surface on the first conductive component. The convex surface is the bottom surface of the second conductive component. The convex surface continuously extends from the first sidewall to the second sidewall. The central axis of the second conductive component is offset from the central axis of the gate structure. The convex surface of the second conductive component has a tip that laterally extends below the bottom surface of the second dielectric layer. The bottom-up deposition process is implemented as follows: a thermal chemical vapor deposition process without plasma is used to form nucleation sites on the concave surface of the first conductive component. Then, elements / atoms continue to adhere and anchor to the nucleation sites, thereby realizing the growth of the second conductive component vertically rather than laterally from the concave surface.

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