Positive and negative sequence current amplitude limiting method and system under asymmetric fault

Abstract

The invention relates to a positive and negative sequence current amplitude limiting method and system under an asymmetric fault, and belongs to the field of power grid stability control. When an asymmetric fault occurs in a power grid, a positive-sequence active current reference value, a positive-sequence reactive current reference value, a negative-sequence reactive current reference value and a negative-sequence active current reference value are obtained, then a minimum included angle is obtained according to a positive-sequence phasor and a negative-sequence phasor, then an amplitude limiting value is obtained according to the minimum included angle, and when a total current module value is larger than the amplitude limiting value, the amplitude limiting value is judged to be smaller than the amplitude limiting value. The positive sequence reactive current and the negative sequence current are subjected to amplitude limiting, and finally fault ride-through is completed according to the positive sequence current and the negative sequence current after amplitude limiting. According to the method, after the total current module value exceeds the limit, the current output by the high-voltage direct-hanging energy storage device is limited, it can be guaranteed that fault ride-through of a power grid is completed, and it can also be guaranteed that the current output by the high-voltage direct-hanging energy storage device is within a safe range.

Description

Technical Field

[0001] The present invention relates to a positive and negative sequence current limiting method and system under asymmetrical faults, belonging to the field of power grid stability control. Background Art

[0002] As Figure 1 shown, the high-voltage directly-connected energy storage device is composed of multiple cascaded H-bridge power modules, with a relatively large single set capacity and the ability to operate in four quadrants, and can play a good supporting role for the power grid during power grid faults. When an asymmetrical fault occurs in the power grid, it is necessary not only for the directly-connected energy storage device to support the positive sequence voltage recovery, but also to suppress the negative sequence voltage. At the same time, in order to avoid frequency fluctuations, it is also hoped that it can maintain the active current output. However, due to the current-carrying capacity limitation of the power electronic devices used in the H-bridge, its output current needs to be within a certain range to ensure the safe operation of the device. Therefore, it is necessary to reasonably distribute the current output. Summary of the Invention

[0003] The purpose of the present invention is to provide a positive and negative sequence current limiting method and system under asymmetrical faults, so as to solve the problem of how to make the current output by the high-voltage directly-connected energy storage device within a safe operating range when an asymmetrical fault occurs in the power grid.

[0004] To achieve the above purpose, the solution of the present invention includes:

[0005] A positive and negative sequence current limiting method under asymmetrical faults of the present invention includes the following steps: 1) When an asymmetrical fault occurs in the power grid, obtain the positive sequence active current reference value I dp_ref , the positive sequence reactive current reference value I qp_ref , the negative sequence reactive current reference value I dn_ref and the negative sequence active current reference value I qn_ref according to the reactive power support formula; 2) Obtain the positive sequence current vector phase dp_ref according to I qp_ref and I ; obtain the negative sequence current vector phase qn_ref according to I dn_ref and I ; obtain the initial phase of the positive sequence phasor of the three-phase current and the initial phase of the negative sequence phasor respectively according to and , and obtain the minimum included angle of the phasors according to the initial phase of the positive sequence phasor and the initial phase of the negative sequence phasor of the three-phase current; 3) Obtain the maximum current modulus value I qp_ref , I dn_ref and I qn_ref according to the minimum included angle, I qpn_mag ; 4) When I qpn_mag is greater than the set transient total current limit value, for I qp_ref , I dn_ref and I qn_refPerform amplitude limiting, and based on the amplitude-limited I qp_ref 、I dn_ref and I qn_ref perform closed-loop control to complete fault ride-through.

[0006] Further, step 2) includes: Based on and respectively obtain the initial phase of the positive-sequence phasor of the phase-A current and the initial phase of the negative-sequence phasor of the phase-A current and Based on respectively obtain the initial phase of the positive-sequence phasor of the phase-B current and the initial phase of the positive-sequence phasor of the phase-C current and Based on and obtain the phase angle difference of phase A, and based on and obtain the phase angle difference of phase B, and based on

[0007] obtain the phase angle difference of phase C; obtain the minimum included angle based on the phase angle differences of phase A, phase B, and phase C.

[0008] Further, after obtaining the phase angle differences of phase A, phase B, and phase C, limit the phase angle differences of phase A, phase B, and phase C within the range of 0 to π, and use the minimum value among the limited phase angle differences of phase A, phase B, and phase C as the minimum included angle.

[0009] Further, the limiting process includes: when the phase angle difference is less than 0, let the phase angle difference accumulate 2π; when the phase angle difference is greater than 2π, let the phase angle difference subtract 2π; when the phase angle difference is greater than π and less than 2π, let 2π subtract the phase angle difference. qp_ref 、I dn_ref and I qn_ref perform equal-proportion amplitude limiting.

[0010] Further, the proportion is the value obtained by dividing the maximum current modulus by the transient total current limit value.

[0011] Further, in step 1), when I qp_ref is greater than the set transient total current limit value, let I qp_ref be equal to the set transient total current limit value, and let I dn_ref and I qn_ref both be 0.

[0012] Further, when I qpn_magWhen the transient total current is less than the set limit value, positive-sequence active current is output, and the limit value of the positive-sequence active current is the set transient total current limit value minus the value of I qpn_mag ; otherwise, no positive-sequence active current is output; the positive-sequence active current is used to complete the fault ride-through.

[0013] Further, I is obtained through the following formula qpn_mag :

[0014]

[0015] where is the minimum angle,

[0016] A positive and negative sequence current limiting system under asymmetrical faults includes a processor, and the processor executes a computer program to implement the steps of the method as described above.

[0017] The beneficial effects of the present invention are as follows: The present invention is an innovative invention. When an asymmetrical fault occurs in the power grid, the present invention obtains the reference values of positive-sequence active current, positive-sequence reactive current, negative-sequence reactive current, and negative-sequence active current, then obtains the minimum angle according to the positive-sequence phasor and the negative-sequence phasor, and further obtains the limit value according to the minimum angle. When the total current modulus is greater than the limit value, the positive-sequence reactive current and the negative-sequence current are limited. After the total current modulus exceeds the limit, the present invention limits the current output by the high-voltage direct-connected energy storage device, which can not only ensure the completion of the power grid fault ride-through but also ensure that the current output by the high-voltage direct-connected energy storage device is within a safe range. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a topological schematic diagram of a high-voltage direct-connected energy storage device of the present invention;

[0019] Figure 2 is a schematic diagram of a current limiting process of the present invention;

[0020] Figure 3 is a vector schematic diagram of voltage phasor and current phasor of the present invention;

[0021] Figure 4 is a vector relationship schematic diagram of positive-sequence current vector and negative-sequence current vector of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments.

[0023] The concept of the present invention is to limit the positive-sequence reactive current and negative-sequence current when an asymmetrical fault occurs in the power grid and the total current command is exceeded, so as to achieve safe and stable fault ride-through.

[0024] Method implementation:

[0025] This implementation provides a method for limiting positive and negative sequence currents under asymmetrical faults, as Figure 2 shown, including the following steps:

[0026] S1. Calculate the dynamic positive and negative sequence current target commands under asymmetrical faults according to the reactive power support formula during asymmetrical faults:

[0027] I dp_ref = 0 (1)

[0028] I qp_ref = I qp0 + K p *ΔU p (2)

[0029] I dn_ref = K n *U qn (3)

[0030] I qn_ref = -K n *U dn (4)

[0031] As another implementation, if I qp_ref > I _limit , then:

[0032] I dp_ref = 0 (5)

[0033] I qp_ref = I _limit (6)

[0034] I dn_ref = 0 (7)

[0035] I qn_ref = 0 (8)

[0036] Among them, I dp_ref and I qp_ref are the per-unit values of the positive-sequence active current target command (positive-sequence active current reference value) and positive-sequence reactive current target command (positive-sequence reactive current reference value) respectively; I dn_ref and I qn_ref are the per-unit values of the negative-sequence active current target command (negative-sequence reactive current reference value) and negative-sequence reactive current target command (negative-sequence active current reference value) respectively; I qp0is the per-unit value of the steady-state positive-sequence reactive current command before grid fault; K p is the set positive-sequence dynamic reactive current proportionality coefficient for asymmetrical faults; K n is the set negative-sequence dynamic reactive current proportionality coefficient for asymmetrical faults; ΔU p is the deviation value of the positive-sequence component of the grid voltage relative to the reference voltage during the set asymmetrical fault; U dn and U qn are the per-unit values of the negative-sequence d and q axes of the grid voltage respectively; I _limit is the set transient total current limit value. The relationship between the positive- and negative-sequence voltage phasors and the current phasors is as Figure 3 shown.

[0037] S2. Obtain the minimum included angle between the positive- and negative-sequence phasors of the three-phase current in the stationary coordinate system

[0038] Positive-sequence current vector phase in the positive-sequence dq coordinate system:

[0039]

[0040] Negative-sequence current vector phase in the negative-sequence dq coordinate system:

[0041]

[0042] According to and respectively obtain the initial phases of the positive-sequence phasor and the negative-sequence phasor of the three-phase current, and obtain the minimum included angle of the phasors based on the initial phases of the positive-sequence phasor and the negative-sequence phasor of the three-phase current As a specific embodiment of the present invention, this process includes:

[0043] The initial phase of the positive-sequence phasor of the A-phase current in the stationary coordinate system (taking the positive-sequence phase of the grid voltage as a reference) is:

[0044]

[0045] The initial phase of the negative-sequence phasor of the A-phase current is:

[0046]

[0047] Then

[0048] The initial phases of the positive- and negative-sequence phasors of the B and C phases are respectively:

[0049]

[0050] The phase angle differences between the positive- and negative-sequence phasors of the A, B, and C phases are:

[0051]

[0052] Meanwhile, the phase angle differences of the three phases are limited within the range of [0, π] through corresponding arithmetic expressions. Taking phase A as an example specifically:

[0053]

[0054] Thus, the minimum included angle is obtained based on the limited phase angle differences of the three phases.

[0055]

[0056] S3. Calculate the maximum modulus value I of the transient positive and negative sequence reactive currents qpn_mag :

[0057] As Figure 4 shown, the positive sequence current vector and the negative sequence current vector satisfy the following vector relationship:

[0058]

[0059] When the included angle between the positive sequence current vector and the negative sequence current vector is the smallest, the superimposed current vector is the largest.

[0060] Therefore, the positive sequence current I p = I qp_ref , and the negative sequence current

[0061] Thus, the maximum modulus value I of the positive and negative sequence reactive currents is obtained qpn_mag :

[0062]

[0063] S4. Calculate the transient positive sequence reactive current command I _limit constrained by the transient total current limit value I qp_ref and the negative sequence current commands I dn_ref 、I qn_ref :

[0064] When I qpn_mag > I _limit , limit I qp_ref 、I dn_ref and I qn_ref . As a specific embodiment of the present invention, these three are limited proportionally, and the maximum modulus value I of the positive and negative sequence reactive currents qpn_mag needs to be constrained by I _limit , and the proportional limit is:

[0065]

[0066] Then the high-voltage direct-connected energy storage device uses the limited I qp_ref 、Idn_ref and I qn_ref Perform closed-loop control to achieve fault ride-through.

[0067] In addition, if I qpn_mag <I _limit When this is the case, it indicates that there is still a certain margin to output positive-sequence active current. At this time, the high-voltage directly-connected energy storage device still outputs positive-sequence active current to assist in achieving fault ride-through, but it also needs to be limited. The limit value I dp_limit is:

[0068] I dp_limit = I _limit - I qpn_mag (20)

[0069] Otherwise, I dp_limit = 0, and no positive-sequence active current is output.

[0070] System implementation method:

[0071] This implementation method provides a positive and negative sequence current limiting system under asymmetrical faults. The computer program executed by the processor in this system is designed using the method introduced in the method implementation method. Since the introduction of this method is clear enough, it will not be elaborated here.

[0072] Finally, it should be noted that the above implementation methods are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above implementation methods, those of ordinary skill in the art should understand that: it is still possible to modify the specific implementation methods of the present invention or make equivalent replacements. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the protection scope of the claims of the present invention.

Claims

1. A positive and negative sequence current limiting method under asymmetrical faults, characterized in that, It includes the following steps: 1) When an asymmetrical fault occurs in the power grid, obtain the positive-sequence active current reference value I dp_ref , the positive-sequence reactive current reference value I qp_ref , the negative-sequence reactive current reference value I dn_ref , and the negative-sequence active current reference value I qn_ref according to the reactive power support formula; 2) Obtain the positive-sequence current vector phase based on I dp_ref and I qp_ref . Obtain the negative-sequence current vector phase based on I qn_ref and I dn_ref . Respectively obtain the initial phases of the positive-sequence phasors and negative-sequence phasors of the three-phase currents according to and , and calculate the minimum included angle of the phasors based on the initial phases of the positive-sequence phasors and negative-sequence phasors of the three-phase currents; 3) Obtain the maximum current modulus I qpn_mag based on the minimum included angle, I qp_ref , I dn_ref , and I qn_ref ; 4) When I qpn_mag is greater than the set transient total current limit value, limit I qp_ref , I dn_ref , and I qn_ref , and perform closed-loop control based on the limited I qp_ref , I dn_ref , and I qn_ref to complete the fault ride-through.

2. The positive and negative sequence current limiting method under asymmetrical faults according to claim 1, wherein The said step 2) includes: According to and respectively obtain the initial phase of the positive-sequence phasor of the A-phase current and the initial phase of the negative-sequence phasor According to respectively obtain the initial phases of the positive-sequence phasors of the B-phase current and the C-phase current and According to respectively obtain the initial phase of the negative-sequence phasor of the B-phase current and the initial phase of the negative-sequence phasor of the C-phase current According to and obtain the phase angle difference of the A-phase. According to and obtain the phase angle difference of the B-phase. According to and obtain the phase angle difference of the C-phase; obtain the said minimum included angle according to the phase angle differences of the A-phase, B-phase and C-phase.

3. The positive and negative sequence current limiting method under asymmetrical faults according to claim 2, wherein After obtaining the phase angle differences of phase A, phase B, and phase C, the phase angle differences of phase A, phase B, and phase C are also limited within the range of 0 to π, and the minimum value among the limited phase angle differences of phase A, phase B, and phase C is used as the minimum included angle.

4. The positive and negative sequence current limiting method under asymmetrical faults according to claim 3, wherein The limiting process includes: when the phase angle difference is less than 0, adding 2π to the phase angle difference; when the phase angle difference is greater than 2π, subtracting 2π from the phase angle difference; when the phase angle difference is greater than π and less than 2π, subtracting the phase angle difference from 2π.

5. The positive and negative sequence current limiting method under asymmetric faults according to claim 1, wherein In step 4), equal-proportion amplitude limiting is performed on I qp_ref , I dn_ref and I qn_ref .

6. The positive and negative sequence current limiting method under asymmetrical faults according to claim 5, characterized in that, The ratio is the value obtained by dividing the maximum current modulus by the transient total current limit value.

7. The positive and negative sequence current limiting method under asymmetrical faults according to claim 1, wherein In step 1), when I qp_ref is greater than the set transient total current limit value, set I qp_ref equal to the set transient total current limit value, and set both I dn_ref and I qn_ref to 0.

8. The positive and negative sequence current limiting method under asymmetrical faults according to claim 1, characterized in that When I qpn_mag is less than the set transient total current limit value, the positive-sequence active current is output, and the limit value of the positive-sequence active current is the value obtained by subtracting I qpn_mag from the set transient total current limit value; otherwise, the positive-sequence active current is not output; the positive-sequence active current is used to complete fault ride-through.

9. The positive and negative sequence current limiting method under asymmetric faults according to claim 1, characterized in that I is obtained through the following formula qpn_mag :[[]]END]] Among them, is the minimum included angle, 10. A positive and negative sequence current limiting system under asymmetrical faults, comprising a processor, characterized in that, The processor executes a computer program to implement the steps of the method according to any one of claims 1 to 9.

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