Chopped wave-based dynamic bias low-offset error amplifier

Abstract

The invention discloses a chopping-based dynamic bias low-offset error amplifier, which relates to a signal error amplifier and comprises a dynamic bias circuit, a low-offset error amplifier, a band-gap reference circuit and a low-pass filter. And the dynamic biasing circuit is used for improving the conversion rate of the operational amplifier. And the low-offset error amplifier eliminates offset voltage through a chopping technology and reduces the influence of the offset voltage on the output of the amplifier. And the low-pass filter is used for filtering out the offset voltage modulated to the high frequency. And the band-gap reference circuit is used for generating reference voltage which does not change along with the temperature. The chopping technology is adopted, the influence of offset voltage on the operational amplifier is greatly reduced, the conversion rate of the error amplifier is improved through the dynamic bias technology, the low-pass filter is introduced, offset voltage signals and high-frequency noise signals modulated to high frequency are eliminated, and output of the high-precision error amplifier is achieved.

Description

Technical Field

[0001] The present invention relates to a signal error amplifier, and more particularly to a dynamic bias low-offset error amplifier based on chopping. Background Art

[0002] The error amplifier plays an indispensable role in the power supply circuit. Its core lies in amplifying the error between the input signal and the reference signal to adjust the output and ensure the stability and accuracy of the system. Therefore, the error amplifier requires high precision and higher response speed. Summary of the Invention

[0003] The object of the present invention is to propose a dynamic bias low-offset error amplifier based on chopping, which reduces the influence of the offset voltage on the output voltage through the chopping technique, thereby making the input voltage more accurate, and making the response speed of the error amplifier faster through dynamic biasing. Finally, the error between the input signal and the reference signal is amplified to adjust the output.

[0004] The technical solution of the present invention is as follows:

[0005] A dynamic bias low-offset error amplifier based on chopping, the dynamic bias low-offset error amplifier based on chopping technology includes: a dynamic bias circuit, a low-offset error amplifier, a low-pass filter, and a bandgap reference circuit.

[0006] Further, the error amplifier circuit includes: an operational amplifier circuit, a dynamic bias circuit, and a low-pass filter circuit.

[0007] Further, the bandgap reference circuit includes: PMOS transistors: MP13, MP14; NPN bipolar transistors: Q1, Q2, Q3; resistors: R2, R3, R4, R5, R6; operational amplifier circuit: OPA1.

[0008] Further, for the bandgap reference circuit, one end of R1 is connected to the power supply VDD, the source of MP1 is connected to the other end of R1, the gate of MP1 is connected to the gate of MP2, the drain of MP1 is connected to the output of OPA1, the gate of MP1 is connected to the drain of MP1 to form a diode connection, the source of MP2 is connected to the power supply, the drain of MP2 is connected to one end of R2, the drain of MP2 is connected to V ref is connected, the other end of R2 is connected to the collector of Q1, the emitter of Q1 is connected to GND, the base of Q1 is connected to the base of Q2, the base and collector of Q1 are connected, the VDD terminal of OPA1 is connected to V refis connected, the drain of MN2 is connected to the output of OPA1, the positive input terminal of OPA1 is connected to one end of R3, the negative input terminal of OPA1 is connected to one end of R4, the GND terminal of OPA1 is connected to GND, and the other end of R3 is connected to V ref is connected, and the other end of R4 is connected to V ref is connected, the negative input terminal of OPA1 is connected to the collector of Q3, the emitter of Q3 is connected to GND, the base of Q3 is connected to the collector of Q2, the base of Q3 is connected to the positive input terminal of OPA1, the emitter of Q2 is connected to one end of R5, and the other end of R5 is connected to GND. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

[0009] Further, the operational amplifier circuit includes: PMOS transistors: MP3, MP4, MP5, MP6; NMOS transistors: MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; resistor: R7; oscillator: M1.

[0010] Further, for the operational amplifier, the source of MP3 is connected to the power supply VDD, the gate of MP3 is connected to V b is connected, and the drain of MP3 is connected to the sources of MP4 and MP5. The gate of MP4 is connected to the drains of MN5 and MN10, and the drain of MP4 is connected to the sources of NMOS transistors MN6, MN8, and the drain of MN3. The gate of PMOS transistor MP5 is connected to the drains of NMOS transistors MN11 and MN12, and the drain of PMOS transistor MP5 is connected to the drains of NMOS transistors MN7, the source of MN9, and the drain of MN4. The NMOS transistors MN5, MN6 - MN12 all act as switches. The gates of NMOS transistors MN6, MN9, MN5, MN12 are connected to the clock signal CK of oscillator M1, and the gates of MN7, MN8, MN11, MN10 are connected to the clock signal CKN of oscillator M1. The drain of NMOS transistor MN6 is connected to the source of NMOS transistor MN7, the gates of MN3 and MN4. The sources of NMOS transistors MN3 and MN4 are grounded. The drains of NMOS transistors MN8 and MN9 are connected to the gate of PMOS transistor MP6. The sources of NMOS transistors MN5 and MN1 are connected to V ref is connected. The sources of NMOS transistors MN10 and MN12 are connected to V-. The source of PMOS transistor MP6 is connected to the source of MP9, and the drain of MP6 is connected to one end of R7. The other end of R7 is connected to GND. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND

[0011] Further, the low-pass filter circuit includes: resistor: R6, capacitor: C1.

[0012] Further, in the low-pass filter circuit, one end of the resistor R6 is connected to the drains of the NMOS transistors MN8 and MN9 and the gate of the PMOS transistor MP6, and the other end of R6 is connected to the positive electrode of the capacitor C1 and the drain of the PMOS transistor MP6. The negative electrode of the capacitor C1 is grounded.

[0013] Further, the dynamic bias circuit includes: PMOS transistors: MP7, MP8, MP9, MP10, MP11, MP12; NMOS transistors: MN1, MN2, MN13, MN14, MN15, MN16, MN17, MN18; capacitor: C2.

[0014] Further, in the dynamic bias circuit, the sources of the PMOS transistors MP7 and MP8 are connected to the power supply VDD, the gates of the PMOS transistors MP7 and MP8 are connected to each other, the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN13 and the gate of the NMOS transistor MN17, and the gate of the PMOS transistor MP7 is connected to its drain to form a diode connection. The source of the PMOS transistor MP9 is connected to the sources of the PMOS transistor MP11 and the gate of the NMOS transistor MN13, the gates of the PMOS transistors MP9 and MP10 are connected to each other, and the drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN1. The gate of the NMOS transistor MN1 is connected to its drain to form a diode connection, the source of the NMOS transistor MN1 is connected to GND, and the gate of the NMOS transistor MN1 is connected to the gate of the NMOS transistor MN2. The source of the NMOS transistor MN2 is connected to GND, and the drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP12. The gate of the PMOS transistor MP12 is connected to the gate of the PMOS transistor MP11, and the source of the PMOS transistor MP12 is connected to the sources of the PMOS transistor MP10 and V out connected. The drain of the PMOS transistor MP11 is connected to the drain of the NMOS transistor MN15, and the gate of the PMOS transistor MP11 is connected to its drain to form a diode connection. The gate of the NMOS transistor MN15 is connected to the gate of the NMOS transistor MN16, the source of the NMOS transistor MN15 is connected to the sources of the NMOS transistor MN13 and the drain of the NMOS transistor MN17. The gate of the NMOS transistor MN16 is connected to the negative electrode of the capacitor C2, the source of the NMOS transistor MN16 is connected to the drain of the NMOS transistor MN18 and the source of the NMOS transistor MN14, and the drain of the NMOS transistor MN16 is connected to the drain of the PMOS transistor MP8 and the gate of the NMOS transistor MN18. The source of the NMOS transistor MN18 is connected to GND. The drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN14, and the gate of the PMOS transistor MP10 is connected to its drain to form a diode connection. The source of the NMOS transistor MN17 is connected to GND. The gate of the NMOS transistor MN13 is connected to the gate of the NMOS transistor MN14. The substrates of all the PMOS transistors are connected to VDD, and the substrates of all the NMOS transistors are connected to GND.

[0015] The beneficial effects of the present invention are as follows:

[0016] 1. The design of the present invention using dynamic biasing and chopping techniques enables the circuit to have a lower offset voltage. The low-offset characteristic is crucial in analog signal processing and high-precision data conversion. It can effectively avoid the error accumulation caused by the offset voltage and improve the linearity and stability of the circuit. The dynamic biasing can effectively address the improvement of the response speed when the load changes.

[0017] 2. The bandgap reference circuit of the present invention also greatly reduces the overall area of the circuit and realizes the light-weighting of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the design flow chart of the dynamic-biased low-offset error amplifier based on chopping technology of the present invention;

[0019] Figure 2 is the circuit diagram of the bandgap reference circuit unit of the dynamic-biased low-offset error amplifier based on chopping technology of the present invention;

[0020] Figure 3 is the dynamic biasing circuit diagram of the dynamic-biased low-offset error amplifier based on chopping technology of the present invention;

[0021] Figure 4 is the circuit diagram of the low-offset operational amplifier of the dynamic-biased low-offset error amplifier based on chopping technology of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention will be further described in detail below with reference to examples, but the embodiments of the present invention are not limited thereto.

[0023] To make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0024] In addition, the diagrams provided in this example only illustrate the basic concept of the present invention schematically. The diagrams only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. The actual form, number and ratio of each component during actual implementation can be arbitrarily changed, and the component layout form may also be more complex.

[0025] Combined with Figure 1 , the design process is as follows: This circuit is provided with a stable voltage V by a bandgap reference circuit ref , and the error value is obtained by operating on the voltage at the negative input terminal of the error amplifier with V ref . In the error amplifier, the input of the operational amplifier is processed by chopping technology, so that its input signal is a square wave input to the operational amplifier. After being amplified by the operational amplifier and then demodulated, the offset voltage of the square wave is removed by a low-pass filter to obtain a more accurate input voltage. Then, through a dynamic bias circuit, the response speed of the operational amplifier is significantly improved when facing different loads

[0026] Combined with Figure 2 Analyze the principle of the bandgap reference circuit unit:

[0027] After the circuit is powered on, the bandgap reference circuit is a self-biased circuit. Therefore, MP1 and MP2 are turned on, and current flows through MP2, causing Q1, Q2, and Q3 to be in the saturation region, and the bandgap reference circuit starts to work

[0028] The triodes Q1, Q2 and the resistors R5, R3, R2 form the main structure of the reference voltage generation circuit, and the output voltage of the bandgap reference is V ref :

[0029] Vref = V BE3 + I C2 R2

[0030] Obtain:

[0031]

[0032] Vref = I C1 R1 + V BE1 ②

[0033] From ① and ②, we get

[0034]

[0035] In this way, the output voltage of the bandgap reference circuit is obtained

[0036] Combined with Figure 3 Analyze the principle of dynamic bias:

[0037] When the load current suddenly decreases, causing the output voltage to rise instantaneously, the change in the output voltage will, through the coupling of capacitor C2, cause the voltages at the gates of MN16 and the sources of MN14 to rise, while the voltages at the gates of MN13 and the sources of MN15 remain unchanged. As a result, the current of MP10 decreases, while the current of MP11 increases. This change causes the gate voltage of MP10 to rise faster, while the gate voltage of MP11 decreases. Similarly, when the load current suddenly increases, the gate voltage of MP10 decreases faster, and the gate voltage of MP11 rises, thus accelerating the current changes of MP12 and MP9. Through this mechanism, the circuit achieves a further improvement in the amplifier slew rate.

[0038] Combined with Figure 4 Provided is an operational amplifier circuit based on chopper technology. The circuit includes: PMOS transistors: MP3, MP4, MP5, MP6; NMOS transistors: MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; a resistor: R7; an oscillator: M1. The source of MP3 is connected to the power supply VDD, the gate of MP3 is connected to V b connected, and the drain of MP3 is connected to the sources of MP4 and MP5. The gate of MP4 is connected to the drains of MN5 and MN10, and the drain of MP4 is connected to the sources of NMOS transistors MN6, MN8, and the drain of MN3. The gate of PMOS transistor MP5 is connected to the drains of NMOS transistors MN11 and MN12, and the drain of PMOS transistor MP5 is connected to the drains of NMOS transistors MN7, the source of MN9, and the drain of MN4. The NMOS transistors MN5, MN6 - MN12 all act as switches. The gates of NMOS transistors MN6, MN9, MN5, and MN12 are connected to the clock signal CK of oscillator M1, and the gates of MN7, MN8, MN11, and MN10 are connected to the clock signal CKN of oscillator M1. The drain of NMOS transistor MN6 is connected to the source of NMOS transistor MN7, the gates of MN3 and MN4. The sources of NMOS transistors MN3 and MN4 are grounded. The drains of NMOS transistors MN8 and MN9 are connected to the gate of the PMOS transistor MP6. The sources of NMOS transistors MN5 and MN1 are connected to V ref connected. The sources of NMOS transistors MN10 and MN12 are connected to V-. The source of PMOS transistor MP6 is connected to the source of MP9, and the drain of MP6 is connected to one end of R7. The other end of R7 is connected to GND. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

[0039] Although the present invention has been described herein with reference to particular embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. Accordingly, it should be understood that numerous modifications may be made to the exemplary embodiments, and other arrangements may be devised, without departing from the spirit and scope of the invention as defined. It should be understood that different dependent claims and the features described herein may be combined in ways different from those described in the original claims. It should also be understood that features described in connection with separate embodiments may be used in other described embodiments.

Claims

1. A chopper-based dynamic bias low-offset error amplifier, characterized in that The amplifier includes a dynamic bias circuit unit, a low-offset error amplifier, a low-pass filter unit, and a bandgap reference circuit unit; the error amplifier includes an operational amplifier circuit, a dynamic bias circuit, and a low-pass filter circuit; the bandgap reference circuit unit includes PMOS transistors: MP13, MP14; NPN bipolar transistors: Q1, Q2, Q3; resistors: R2, R3, R4, R5, R6; and an operational amplifier circuit: OPA1.

2. The dynamic bias low-offset error amplifier based on chopping according to claim 1, wherein One end of the bandgap reference circuit R1 is connected to the power supply VDD, the source of MP1 is connected to the other end of R1, the gate of MP1 is connected to the gate of MP2, the drain of MP1 is connected to the output of OPA1, and the gate of MP1 is connected to the drain of MP1 to form a diode connection. The source of MP2 is connected to the power supply, the drain of MP2 is connected to one end of R2, and the drain of MP2 is connected to V ref connected, the other end of R2 is connected to the collector of Q1, the emitter of Q1 is connected to GND, the base of Q1 is connected to the base of Q2, the base and collector of Q1 are connected, and the VDD terminal of OPA1 is connected to V ref connected, the drain of MN2 is connected to the output of OPA1, the positive input terminal of OPA1 is connected to one end of R3, the negative input terminal of OPA1 is connected to one end of R4, the GND terminal of OPA1 is connected to GND, and the other end of R3 is connected to V ref connected, the other end of R4 is connected to V ref connected, the negative input terminal of OPA1 is connected to the collector of Q3, the emitter of Q3 is connected to GND, the base of Q3 is connected to the collector of Q2, the base of Q3 is connected to the positive input terminal of OPA1, the emitter of Q2 is connected to one end of R5, and the other end of R5 is connected to GND; the substrate of the PMOS transistor is connected to VDD, and the substrate of the NMOS transistor is connected to GND.

3. A dynamic bias low offset error amplifier based on chopping according to claim 1, characterized in that The operational amplifier circuit includes PMOS transistors: MP3, MP4, MP5, MP6; NMOS transistors: MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; a resistor: R7; and an oscillator: M1.

4. A dynamic bias low offset error amplifier based on chopping according to claim 1, characterized in that The source of the operational amplifier MP3 is connected to the power supply VDD, the gate of MP3 is connected to V b and the drain of MP3 is connected to the sources of MP4 and MP5; the gate of MP4 is connected to the drains of MN5 and MN10, and the drain of MP4 is connected to the sources of the NMOS transistors MN6, MN8, and the drain of MN3; the gate of the PMOS transistor MP5 is connected to the drains of the NMOS transistors MN11 and MN12, and the drain of the PMOS transistor MP5 is connected to the drains of the NMOS transistors MN7, the source of MN9, and the drain of MN4; the NMOS transistors MN5, MN6 - MN12 all act as switches, the gates of the NMOS transistors MN6, MN9, MN5, and MN12 are connected to the clock signal CK of the oscillator M1, and the gates of MN7, MN8, MN11, and MN10 are connected to the clock signal CKN of the oscillator M1; the drain of the NMOS transistor MN6 is connected to the source of the NMOS transistor MN7, the gates of MN3 and MN4; the sources of the NMOS transistors MN3 and MN4 are grounded; the drains of the NMOS transistors MN8 and MN9 are connected to the gate of the PMOS transistor MP6; the source of the NMOS transistor MN5 and the source of MN1 are connected to V ref and the source of the NMOS transistor MN10 and the source of MN12 are connected to V-; the source of the PMOS transistor MP6 is connected to the source of MP9, and the drain of MP6 is connected to one end of R7; the other end of R7 is connected to GND; the substrate of the PMOS transistor is connected to VDD, and the substrate of the NMOS transistor is connected to GND.

5. The dynamic bias low-offset error amplifier based on chopping according to claim 1, characterized in that, The low-pass filter circuit includes a resistor: R6 and a capacitor: C1.

6. The dynamic bias low offset error amplifier based on chopping according to claim 1, wherein One end of the resistor R6 of the low-pass filter circuit is connected to the drains of the NMOS transistors MN8 and MN9 and the gate of MP6, and the other end of R6 is connected to the positive electrode of the capacitor C1 and the drain of MP6; the negative electrode of the capacitor C1 is grounded.

7. A dynamic offset low-offset error amplifier based on chopping according to claim 1, characterized in that, The dynamic bias circuit includes PMOS transistors: MP7, MP8, MP9, MP10, MP11, MP12; NMOS transistors: MN1, MN2, MN13, MN14, MN15, MN16, MN17, MN18; and a capacitor: C2.

8. The dynamic bias low offset error amplifier based on chopping according to claim 1, wherein, The sources of the dynamic bias circuits MP7 and MP8 are connected to the power supply VDD. The gates of MP7 and MP8 are connected to each other. The drain of MP7 is connected to the drain of MN13 and the gate of MN17. The gate of MP7 is connected to its drain, forming a diode connection. The source of MP9 is connected to the sources of MP11 and the gate of MN13. The gates of MP9 and MP10 are connected to each other. The drain of MP9 is connected to the drain of MN1. The gate of MN1 is connected to its drain, forming a diode connection. The source of MN1 is connected to GND, and the gate of MN1 is connected to the gate of MN2. The source of MN2 is connected to GND, and the drain of MN2 is connected to the drain of MP12. The gate of MP12 is connected to the gate of MP11, and the source of MP12 is connected to the sources of MP10 and V out connected. The drain of MP11 is connected to the drain of MN15. The gate of MP11 is connected to its drain, forming a diode connection. The gates of MN15 and MN16 are connected to each other. The source of MN15 is connected to the sources of MN13 and the drain of MN17. The gate of MN16 is connected to the negative electrode of C2. The source of MN16 is connected to the drain of MN18 and the source of MN14. The drain of MN16 is connected to the drain of MP8 and the gate of MN18. The source of MN18 is connected to GND. The drain of MP10 is connected to the drain of MN14. The gate of MP10 is connected to its drain, forming a diode connection. The source of MN17 is connected to GND. The gates of MN13 and MN14 are connected to each other. The substrate of the PMOS transistor is connected to VDD, and the substrate of the NMOS transistor is connected to GND.

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