Continuous time increment tracking zoom sensor readout front-end circuit and implementation method thereof

Abstract

The present invention discloses a continuous time increment tracking zoom sensor readout front-end circuit and its implementation method, which belongs to the field of integrated circuit design technology. A floating transconductance amplifier is prepared, and current multiplexing and low output point voltage are simultaneously realized through floating power supply; by directly detecting the output of the fine quantizer, the tracking circuit in the tracking zoom sensor readout front-end is simplified, and no additional input detection circuit is introduced. By using the output of the fine quantizer to adjust the digital code of the coarse quantizer, the dynamic range tracking of the rapidly changing signal is realized. The technical solution of the present invention is adopted to realize a sensor readout front-end circuit with high energy efficiency, low noise, and high dynamic range. It can respond to rapidly changing signals with higher energy efficiency and is adaptable to new edge application scenarios such as the Internet of Things, medical and wearable devices.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design technology, and relates to sensor readout circuit design technology, specifically to a continuous time increment tracking and scaling sensor readout front-end circuit and its implementation method. A high-energy-efficiency, low-noise, and high-dynamic-range sensor readout front-end circuit structure is designed and implemented. Background Art

[0002] In edge applications such as the Internet of Things, medical, and wearable devices, continuous monitoring of sensors is often required, and these devices are often limited by the power of batteries or energy harvesters. Therefore, direct sensor readout front-end circuits are popular because they can significantly simplify signal conditioning circuits and reduce device costs. With the development of sensor technology and the expansion of its application range, emerging edge applications require sensor readout circuits with low input-referred noise (≤10μVrms) and medium conversion speeds (≥10kHz). At the same time, in order to read signals with small changes in amplitude while presenting artifacts and interference in the 100mV range, the readout front-end circuit needs to provide a large dynamic range (DR, Dynamic Range) (≥80dB).

[0003] Delta-Sigma modulators (ΔΣMs) can achieve the desired dynamic range through oversampling and quantization noise shaping. However, achieving a large dynamic range requires a high-order ΔΣ loop or a large over-sampling ratio (OSR), which results in high power consumption. The zoom architecture combines an energy-efficient successive approximation register (SAR) analog-to-digital converter with a high-resolution ΔΣ modulator, offering great potential for edge signal readout. In the zoom architecture, most of the input range is coarsely quantized by the SAR, while the ΔΣ loop input is the smaller residual signal after coarse quantization. Therefore, the zoom architecture can simultaneously provide a large input range, high energy efficiency, and low input-referred noise.

[0004] However, during the scaling architecture's transitions, rapidly changing signals may exceed the fine quantization dynamic range of the ΔΣ loop. Dynamic zoom architectures perform coarse quantization using a successive approximation register (SAR) during each cycle to ensure the input remains within the fine quantization dynamic range. However, the frequent switching of the digital-to-analog converter (DAC) during SAR coarse quantization limits its energy efficiency. To address this issue, recent sensor readout circuits have adopted range tracking techniques. By using a dedicated loop filter monitor or a post-sampling input slope estimator to estimate input value changes and update the fine quantization dynamic range accordingly, the signal can be kept within the fine quantization dynamic range without performing coarse quantization every fine quantization cycle. However, the former requires additional always-on analog comparators with multiple comparison thresholds to estimate the input value range. The latter relies on complex logic and significant inter-stage redundancy to extend the acceptable slope rate. Consequently, both approaches incur significant additional energy and area costs.

[0005] In summary, the sensor readout front-end circuits designed by existing technologies have the disadvantages of low energy efficiency, high noise, and small dynamic range, which makes it difficult to meet the requirements of new edge applications such as the Internet of Things, medical and wearable devices for high-efficiency, low-noise, and high-dynamic range sensor readout front-end circuits. Summary of the Invention

[0006] In response to the shortcomings of the above-mentioned existing technologies, the present invention provides a continuous time increment tracking scaling sensor readout front-end circuit and its implementation method, designs and implements a high-energy-efficiency, low-noise, high-dynamic-range sensor readout front-end circuit, which can respond to rapidly changing signals with higher energy efficiency and can be adapted to new edge application scenarios such as the Internet of Things, medical and wearable devices.

[0007] The proposed continuous time incremental tracking scaling sensor readout front-end circuit is a novel continuous time incremental scaling sensor readout front-end circuit. It employs a fast tracking logic circuit based on fine quantizer output detection to perform low-overhead, high-response fine quantization dynamic range tracking of rapidly changing input signals. Furthermore, a floating transconductance amplifier and a current-controlled ring oscillator (CCO) are designed as integrators. The floating transconductance amplifier is a quasi-static continuous time open-loop transconductance amplifier that can operate in conjunction with a low-voltage current-controlled ring oscillator integrator, thereby improving the energy efficiency of the continuous time incremental tracking scaling sensor readout front-end circuit. Through the above technologies, the present invention can meet the power consumption, noise, and dynamic range requirements of new edge applications such as the Internet of Things, medical devices, and wearable devices for high-efficiency, low-noise, and high-dynamic range sensor readout front-end circuits.

[0008] The technical solutions of the present invention are as follows:

[0009] A method for implementing a continuous time increment tracking and scaling sensor readout front-end circuit is designed. This circuit does not introduce additional input detection circuitry. It continuously tracks the input signal by adjusting the digital code of the coarse quantizer using the output of the fine quantizer. It uses a floating transconductance amplifier and a low-voltage current-controlled ring oscillator as integrators to improve the overall energy efficiency of the circuit. The implementation method includes the following steps:

[0010] 1) Prepare a floating transconductance amplifier. A complementary MOS (Metal Oxide Semiconductor Field Effect Transistor) transistor with its drain connected serves as the input transistor of the floating transconductance amplifier. A floating current source, consisting of a current source transistor and a current source bias capacitor, is added to the power supply side of the input transistor to stabilize the amplifier's operating current and transconductance gain. A power supply capacitor, connected to the input transistor and the floating current source in the operating state, is added to enable the amplifier to operate in a floating voltage domain. A charging current mirror is added to charge the current source bias capacitor in the charging state. A "dummy" transistor with its source and drain shorted is added between the gate and drain of the input transistor to eliminate the effects of kickback noise. A control switch, consisting of a MOS transistor, is added to switch the charging and operating states of the power supply capacitor and the current source bias capacitor. The charging of the power supply capacitor periodically shuts down the amplifier's output, providing an amplifier dead zone that can be used to eliminate chopping artifacts. The resulting floating transconductance amplifier includes an input transistor, a floating current source, a charging current mirror, a "dummy" transistor, a power supply capacitor, and a control switch.

[0011] 2) Prepare a multi-bit SAR sensor readout front-end circuit, consisting of a coarse digital-to-analog converter (DAC), a comparator, and coarse digital logic. The coarse digital logic output is connected to the digital input of the coarse DAC. The top plate of the coarse DAC is connected to the comparator input, and the comparator output is connected to the coarse digital logic input. The coarse digital logic includes asynchronous SAR logic and asynchronous counter logic with a shared data register, enabling fast tracking within the fine dynamic range.

[0012] 3) Prepare a multi-bit incremental ΔΣ sensor readout front-end circuit, which includes four parts: a fine quantization DAC, a transconductance amplifier, an integrator, a quantizer, and a fine quantization digital logic. The fine quantization digital logic outputs a digital code connected to the fine quantization DAC input, the top plate of the fine quantization DAC is connected to the transconductance amplifier input, the transconductance amplifier input is connected to the integrator input, the integrator input is connected to the quantizer input, and the quantizer output result is connected to the fine quantization digital logic. Among them, the transconductance amplifier adopts the floating transconductance amplifier proposed in the present invention, and the integrator adopts a low-voltage current-controlled ring oscillator as a time domain integrator. The fine quantization digital logic includes a fine quantization output detection logic circuit and a tracking control logic circuit, which generates a tracking control signal according to the fine quantization output digital code to control the fine quantization dynamic range and fast tracking.

[0013] Steps 2) and 3) above implement rapid tracking of the fine quantization dynamic range and specifically include a control process and an execution process. The control process is implemented in the fine quantization digital logic in step 3), while the execution process is implemented in the coarse quantization digital logic in step 2). In the coarse quantization digital logic, by integrating asynchronous SAR logic and an asynchronous bidirectional counter, SAR conversion and coarse quantization digital code increment and decrement can be controlled, enabling the coarse quantization digital code to track the input signal. In the fine quantization digital logic, the fine quantization output detection and judgment circuit provides the control signal required to enable the coarse quantization level to track the input signal.

[0014] 4) Connect the charge-sharing DAC top plate of the multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit to form a shared DAC assembly. This shared DAC assembly consists of two connected capacitor array top plates of different sizes. The DAC in the multi-bit SAR sensor readout front-end circuit is a coarse quantization DAC, while the DAC in the multi-bit incremental ΔΣ sensor readout front-end circuit is a fine quantization DAC.

[0015] 5) The multi-bit SAR sensor readout front-end circuit serves as the first stage, and the multi-bit incremental ΔΣ sensor readout front-end circuit serves as the second stage. These two stages are connected via a shared DAC component top board. The tracking control logic of the fine quantization digital logic in the second stage (the multi-bit incremental ΔΣ sensor readout front-end circuit) is connected to the tracking execution logic of the coarse quantization digital logic in the first stage (the multi-bit SAR sensor readout front-end circuit). Chopping switches are added before the input, before the shared DAC component input, after the floating transconductance amplifier output, and after the comparator output to create an improved continuous-time incremental tracking and scaling sensor readout front-end circuit.

[0016] The specific method for preparing a floating transconductance amplifier is as follows:

[0017] The transconductance amplifier circuit consists of six parts: input tube, floating current source, charging current mirror, "dummy" transistor (Dummy transistor), power supply capacitor and control switch.

[0018] The input transistor includes an NMOS (N-channel Metal Oxide Semiconductor Field Effect Transistor) transistor and a PMOS (P-channel Metal Oxide Semiconductor Field Effect Transistor) transistor, and the gates of the two transistors are connected together to form the input of the floating transconductance amplifier; the drains of the two transistors are connected together to form the output of the floating transconductance amplifier. Current multiplexing is achieved by connecting two groups of transistors with transconductance gain in series in the current path of the amplifier to improve the noise efficiency of the transconductance amplifier and reduce the operating current required to achieve the target noise range. The input transistor uses a thick-gate transistor to reduce gate leakage and allow the gate to establish a bias voltage through a pseudo-resistance bias circuit composed of transistors in the cut-off region.

[0019] The present invention proposes a floating current source design consisting of a current source tube and a current source bias capacitor. The current source tube is a PMOS transistor operating in the saturation region, limiting the current flowing through the current source tube through high output impedance. The current source bias capacitor is connected between the gate and source of the current source tube, providing a constant gate-source bias voltage for the current source tube during operation. The floating current source is connected in series with the source terminal of the PMOS transistor in the input tube. The current limiting effect of the current source tube maintains a constant current flowing through the input tube during operation, stabilizing the power consumption and transconductance gain of the floating transconductance amplifier. A charging current mirror is designed using a PMOS current mirror, which charges the current source bias capacitor during the charging state.

[0020] The source and drain of the "virtual" transistor are short-circuited, consuming no power. By cross-connecting the gate and drain of the input tube with polarity opposite to that of the input tube, the differential-mode kickback noise generated when the input tube is working is converted into common-mode kickback noise, eliminating the impact of the kickback noise on the operation of the transconductance amplifier.

[0021] In the working state, the power supply capacitor is connected to the floating current source and the input tube to provide power for the two; the control switch connects or disconnects the power supply capacitor, the current source bias capacitor, the input tube and the current source tube through the NMOS transistor and the PMOS transistor working in the linear region and the cut-off region, thereby realizing the switching between different working phases of the floating transconductance amplifier.

[0022] During operation, the floating transconductance amplifier (FTA) supplies power to the input transistors and floating current source through the supply capacitors, which are completely disconnected from the power supply and ground. Due to current continuity, the current flowing out of the supply capacitors is equal to the current flowing into them. Therefore, the input transistors do not generate common-mode current flowing to the output, nor do they change the common-mode bias voltage at the output. Instead, the floating voltage domain provided by the supply capacitors shifts to the output's original common-mode voltage via changes in the supply capacitor's voltage relative to ground. During FTA operation, as the supply capacitors deliver energy, the voltage differential across them gradually decreases. At this point, the current source transistors in the floating current source maintain a stable gate-source voltage differential, maintained in saturation, and exhibiting high output impedance, thanks to the current source bias capacitors connected between their source and gate terminals. This voltage differential change primarily impacts the floating transconductance amplifier by reducing the source-drain voltage difference of the current source transistors. It has little effect on the voltage differential between the input transistors and the operating current flowing through them, allowing the transconductance gain to remain approximately constant during operation.

[0023] In order to implement the fine quantization dynamic range fast tracking method in steps 2) and 3) above, the present invention designs a fine quantization dynamic range fast tracking logic circuit based on fine quantizer output detection, specifically:

[0024] During the fine quantization process, the fine quantizer output digital code is continuously detected to estimate the fine quantizer input signal. Based on this, the fine quantizer dynamic range is adjusted to ensure that the fine quantizer dynamic range follows the input signal. The fine quantization output detection logic, tracking control logic, and tracking execution logic constitute the fine quantization dynamic range fast tracking logic circuit. The detailed implementation of the fine quantization dynamic range fast tracking logic circuit is as follows:

[0025] A. Fine-grained output detection logic

[0026] The present invention proposes to utilize the characteristics of a multi-bit ΔΣ sensor readout front-end circuit, in which the readout digital code is roughly close to the input signal, with only small errors caused by non-ideal factors such as quantization noise after shaping and thermal noise. The output digital code of the fine quantizer can be directly used as an estimated value of the fine quantizer input, and compared with a preset threshold and the maximum output codeword of the fine quantizer in the digital domain, so as to realize the detection of the relationship between the current input signal and the fine quantization dynamic range.

[0027] B. Fast tracking control logic

[0028] The logic overhead of fine quantization output detection is low, so the present invention proposes that fine quantization output detection can be performed in each fine quantization cycle, and the tracking process can be controlled according to the detection result, so as to achieve rapid tracking of the input signal by reducing the tracking interval. When the digital code output by the fine quantizer exceeds the tracking threshold, the digital code of the coarse quantizer is increased or decreased in the direction of the fine quantizer digital code, and the output voltage of the coarse quantization DAC is changed, so as to move the overall dynamic range of the fine quantizer in the direction of the current input signal, and keep the dynamic range of the fine quantizer near the input signal. When the digital code output by the fine quantizer reaches the maximum output codeword of the fine quantizer, it can be determined that the input has exceeded the dynamic range of the fine quantizer. At this time, the fine quantizer is saturated and cannot effectively represent the range of the input signal. In this state, the control will trigger a coarse quantization SAR conversion process when the circuit is reset next time, and the dynamic range of the fine quantizer is reset to be near the input signal by searching within the complete dynamic range of the coarse quantization.

[0029] C. Fast Track Execution Logic

[0030] In order to realize the two functions of digital code increase and decrease and SAR conversion proposed by the coarse quantizer in the above process, the fast tracking execution logic proposed in the present invention uses a coarse quantization digital logic design that integrates asynchronous SAR logic and asynchronous bidirectional counter. Based on the asynchronous SAR logic, the data registers therein are reused, and clock selection logic and bidirectional carry logic are added to the data registers on the basis of the traditional asynchronous SAR logic to form an asynchronous bidirectional SAR counter structure. When performing SAR conversion, the data register clock in the coarse quantization digital logic selects the sampling clock of each bit in the asynchronous SAR logic to control the asynchronous SAR conversion process; when performing fine quantization dynamic range tracking, the data register clock selects the trigger pulse generated by the bidirectional carry logic of the asynchronous counter, and selects the counting direction according to the input control signal, and at the same time generates a low-bit input pulse for asynchronous counting, and increases and decreases the coarse quantization digital code to achieve the goal of fine quantization dynamic range tracking of the input signal.

[0031] The present invention utilizes the above-mentioned method to fabricate a continuous-time incremental tracking and scaling sensor readout front-end circuit, comprising: a multi-bit SAR sensor readout front-end circuit, a multi-bit incremental ΔΣ sensor readout front-end circuit, and a chopper switch. The multi-bit SAR sensor readout front-end circuit, as the first stage of the overall circuit, performs the first coarse quantization step and shifts the dynamic range of the fine quantizer. The multi-bit incremental ΔΣ sensor readout front-end circuit, as the second stage of the overall circuit, performs the second fine quantization step, determines the precise position of the input signal within the dynamic range, and continuously detects changes in the input signal during the fine quantization process. The chopper switch periodically flips the signal polarity. The multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit share a charge-sharing DAC component. The top plate of this component is connected to the input signal via a coupling capacitor. The component consists of two capacitor arrays of different sizes connected to each other on the top plate. The two-stage sensor readout front-end circuit switches the corresponding capacitor arrays during operation. The multi-bit SAR sensor readout front-end circuit controls the coarse quantization DAC, while the multi-bit incremental ΔΣ sensor readout front-end circuit controls the fine quantization DAC.

[0032] A. The multi-bit SAR sensor readout front-end circuit consists of three parts: coarse quantization DAC, comparator, and coarse quantization digital logic. The coarse quantization digital logic includes the fast tracking execution logic in the fast tracking logic circuit, which is implemented by the asynchronous SAR logic and asynchronous counter logic that share the data register.

[0033] B. The multi-bit incremental ΔΣ sensor readout front-end circuit consists of four components: a fine-quantization DAC, a transconductance amplifier, an integrator, a quantizer, and fine-quantization digital logic. The transconductance amplifier uses a floating transconductance amplifier, and the integrator utilizes a low-voltage current-controlled ring oscillator. The fine-quantization digital logic includes the fine-quantization output detection logic and fast-tracking control logic within the fast-tracking logic circuit, implemented using a compressor, a comparator, and a logic judgment circuit.

[0034] C. The chopping switch consists of four parts: input chopping switch, DAC chopping switch, transconductance amplifier output chopping switch, and comparator output chopping switch.

[0035] Furthermore, the readout front-end circuit of the multi-bit SAR sensor is 7 bits, of which 2 bits are redundant; the readout front-end circuit of the multi-bit incremental ΔΣ sensor is 5 bits.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] This invention provides a method for implementing a high-efficiency, high-output common-mode range transconductance amplifier. It proposes a floating transconductance amplifier structure, combined with a low-voltage current-controlled ring oscillator as an integrator for the fine-scale quantization stage. A floating voltage supply is used to prevent common-mode output current, while a floating current source is used to stabilize the amplifier stage operating current. This structure features high noise efficiency, simple biasing, no need for common-mode feedback, and is unaffected by the common-mode voltage at the output point. It can effectively work with a low-voltage current-controlled ring oscillator, further improving the energy efficiency of the overall circuit.

[0038] The present invention provides a continuous time increment tracking scaling sensor readout front-end circuit and its implementation method. A fast tracking logic circuit based on fine quantizer output detection is designed to perform low-overhead, high-response fine quantization dynamic range tracking on rapidly changing input signals, while using a floating transconductance amplifier and a current-controlled ring oscillator as an integrator. The fast tracking logic circuit based on fine quantizer output detection is suitable for scaling data conversion circuits. The fast tracking logic circuit based on fine quantizer output detection does not introduce additional analog circuit units, fully utilizes the low quantization noise characteristics of multi-bit fine quantizers, and directly uses the fine quantizer output codeword to estimate the input signal, avoiding the high power consumption and slow tracking response speed problems of additional analog detection circuits or post-sampling tracking and compensation prediction circuits for high input slopes in traditional tracking technologies. The designed continuous time increment tracking scaling sensor readout front-end circuit simultaneously meets the application requirements of high energy efficiency, low noise, and high dynamic range, and is suitable for new edge application scenarios such as the Internet of Things, medical care, and wearable devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a structural diagram of the readout front-end circuit and the top-level working phase diagram of the continuous time incremental tracking and scaling sensor in the present invention;

[0040] Among them, V in D is the voltage signal input of the sensor to be tested. SAR The output digital code of the front-end circuit is read out for the SAR sensor, i.e. the coarse quantization digital code; D CCO The incremental ΔΣ sensor reads the output digital code from the front-end circuit, known as the fine quantization code. In the top-level operating phase, the clock represents the sampling and control signal for the fine quantization stage. The reset signal resets the integrator and quantizer required for the fine quantization stage to implement incremental conversion. It also serves as the control signal that enables the coarse quantization stage to perform SAR conversion when SAR conversion is required. The reset signal controls the periodic switching between the reset and coarse quantization phases and the fine quantization phase.

[0041] Figure 2 The circuit diagram and working mode diagram of the fine quantization dynamic range fast tracking logic circuit based on fine quantizer output detection proposed by the present invention;

[0042] From left to right, the circuit diagram shows the fine quantization output detection circuit, the fast tracking control circuit, and the fast tracking execution circuit. UP and DN are the original fine quantization digital codes encoded in a three-value thermometer format. The fine quantization digital codes are converted to two's complement encoding via two's complement compressors and a two's complement subtractor. A digital comparator then performs a range check on the two's complement encoded fine quantization digital code. In this design example, the ratio of the coarse quantization level to the fine quantization digital code is set to 8. Therefore, the range check for the fine quantization digital code in the diagram is also set to 8. Different control signals are generated for the coarse quantization logic based on the range of the fine quantization digital code. The coarse quantization logic uses SAR logic that incorporates an asynchronous bidirectional counter. It can perform SAR conversion or add or subtract 1 from the coarse quantization digital code based on the control signal generated by the fine quantization level.

[0043] Figure 3 The circuit structure diagram of the floating transconductance amplifier proposed in the present invention is applied to the transconductance amplifier of the fine quantization stage in the readout front-end circuit of the continuous time increment tracking zoom sensor proposed in the present invention. DDA Indicates analog power supply, C res Represents the power supply capacitor, C b Represents the current tube bias capacitance, M tail Represents the current source tube, V SP With V SN Indicates the source end of the input tube, V IP With V IN Represents the input signal, V CCO Indicates the output bias voltage when the amplifier bias is established, CCO P With CCO N Represents the flow-controlled ring oscillation in the subsequent circuit.

[0044] Figure 4 This is a working diagram of the floating transconductance amplifier proposed in the present invention, including the working phase of the floating transconductance amplifier and the voltage changes of key nodes. Among them, the sampling clock and the setup clock are the actual control signals, and the working phase is the periodic working state generated by the sampling clock and the setup clock. The node labels in the key nodes are shown in Figure 3 Description, V DS，N It represents the voltage difference between the source and drain of the NMOS transistor in the input tube, and ro represents the equivalent output impedance of the entire transconductance amplifier to the subsequent stage. DETAILED DESCRIPTION

[0045] The present invention will be further described below through specific embodiments in conjunction with the accompanying drawings, but the scope of the present invention is not limited in any way.

[0046] This invention provides a method for implementing a high-efficiency, high-output common-mode range transconductance amplifier. It also implements a continuous-time incremental tracking and scaling sensor readout front-end circuit based on the transconductance amplifier. By utilizing floating current source technology, a floating power supply can be used for a continuous-time transconductance amplifier. Once fabricated as a floating transconductance amplifier, the floating power supply simultaneously achieves current multiplexing and a low output point voltage, improving overall energy efficiency. By directly detecting the fine quantizer output, the tracking circuitry in the tracking and scaling sensor readout front-end is simplified, enabling dynamic range tracking of rapidly changing signals with minimal power consumption.

[0047] The overall architecture of the present invention is a continuous time incremental tracking and scaling sensor readout front-end circuit. The continuous time incremental tracking and scaling sensor readout front-end circuit proposed by the present invention is composed of a multi-bit SAR sensor readout front-end circuit, a multi-bit incremental ΔΣ sensor readout front-end circuit, and a chopper switch. The multi-bit SAR sensor readout front-end circuit is the first-stage coarse quantization circuit, the multi-bit incremental ΔΣ sensor readout front-end circuit is the second-stage fine quantization circuit, and the chopper switch periodically flips the signal polarity when the capacitor is working.

[0048] The present invention combines the high energy efficiency of the SAR sensor readout front-end circuit with the low noise of the incremental ΔΣ sensor readout front-end circuit, and expands the overall dynamic range of the circuit through a two-stage combination. Based on the traditional structure, the present invention improves the input signal tracking technology and the transconductance amplifier that determines the noise efficiency in the fine quantization stage to achieve high energy efficiency, low noise and high dynamic range at the same time. The multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit in the present invention share a charge-sharing DAC component. The top plate of the component is connected to the input signal through a coupling capacitor. The component is composed of two parts with capacitor array top plates of different sizes connected together, and the corresponding capacitor arrays are switched separately when the two-stage sensor readout front-end circuit is in operation. The multi-bit SAR sensor readout front-end circuit controls the coarse quantization DAC, and the multi-bit incremental ΔΣ sensor readout front-end circuit controls the fine quantization DAC.

[0049] The components of the continuous time incremental tracking and scaling sensor readout front-end circuit proposed by the present invention (including: a multi-bit SAR sensor readout front-end circuit, a multi-bit incremental ΔΣ sensor readout front-end circuit and a chopper switch) are described in detail below:

[0050] A. Multi-bit SAR sensor readout front-end circuit

[0051] In specific implementation, the present invention designs and uses a traditional SAR sensor readout circuit to perform coarse quantization on the input signal. This circuit includes three parts: coarse quantization DAC, comparator, and coarse quantization digital logic. Figure 1The present invention improves the coarse quantization digital logic based on the traditional structure, including asynchronous SAR logic and asynchronous counter logic sharing a data register, for performing fast tracking of the fine quantization dynamic range.

[0052] During a complete SAR conversion, the coarse quantization digital logic selects each bit sampling clock generated by the asynchronous SAR logic as the trigger clock for the data register. It first resets the coarse quantization DAC and switches the coarse quantization digital code bit by bit. The comparator outputs a valid signal and a delay circuit to achieve asynchronous self-generation of the conversion clock. The comparator then determines the magnitude relationship between the current input signal and the current DAC output voltage. During the conversion process, the DAC output voltage is continuously brought closer to the input signal, while the residual voltage on the DAC top plate gradually decreases, ultimately falling within the input dynamic range of the subsequent circuitry.

[0053] When performing coarse quantization digital code tracking, the coarse quantization digital logic selects the bidirectional carry logic output of the asynchronous counter as the trigger clock of the data register, and uses an asynchronous counter structure in which the low-order register output is connected to the high-order register clock, where the lowest-order register clock is connected to the count trigger signal, and the polarity of the connection between the low and high bits is changed by the direction signal, thereby selecting up counting or down counting.

[0054] B. Multi-bit incremental ΔΣ sensor readout front-end circuit

[0055] In specific implementation, the present invention designs and uses a multi-bit incremental ΔΣ sensor readout front-end circuit to perform fine quantization on the residual voltage after coarse quantization. The multi-bit incremental ΔΣ sensor readout front-end circuit includes four parts: fine quantization DAC, transconductance amplifier, integrator, quantizer, and fine quantization digital logic. Figure 1 Shown above.

[0056] The fine quantization DAC achieves finer, lower-noise quantization by using smaller unit capacitance and ΔΣ modulation than the coarse quantization DAC. By designing the total unit capacitance of the fine quantization DAC to be larger than the individual unit capacitance of the coarse quantization DAC, the dynamic range of the fine quantization is greater than that of the coarse quantization DAC, providing approximately 2 bits of redundancy. This allows the fine quantization process to complete normally even when there is a certain error between the fine quantization dynamic range and the input signal.

[0057] The transconductance amplifier adopts the floating transconductance amplifier proposed in the present invention, which achieves low-noise input signal amplification with high noise efficiency and low power consumption. The specific design of the floating transconductance amplifier is as follows:

[0058] The floating transconductance amplifier consists of six parts: input tube, floating current source, charging current mirror, "virtual" transistor, power supply capacitor, and control switch.

[0059] The input tube is Figure 3The transistors in the lower right corner are composed of NMOS and PMOS transistors. The gates of the two transistors are connected together, forming the input of the floating transconductance amplifier; the drains of the two transistors are connected together, forming the output of the floating transconductance amplifier. The input transistors distribute part of the operating current flowing through the input transistors to the positive or negative output path based on the input voltage difference. This generates a differential-mode output current between the positive and negative output terminals without generating common-mode current, thus achieving the transconductance amplification effect. Current multiplexing is achieved by connecting two sets of transistors with transconductance gain in series in the amplifier's current path, improving the noise efficiency of the transconductance amplifier and reducing the operating current required to achieve the target noise range. The input transistors use thick-gate transistors to reduce gate leakage, allowing the gate to establish a bias voltage through a pseudo-resistor bias circuit formed by transistors in the cutoff region.

[0060] The floating current source consists of two parts: the current source tube and the current source bias capacitor. Figure 3 As shown in the upper right corner, the current source tube is a PMOS transistor operating in the saturation region, which limits the current flowing through the current source tube through high output impedance; the current source bias capacitor C b Connected between the gate and source of the current source tube, it provides a constant gate-source bias voltage for the current source tube in the working state; the floating current source is connected in series with the source terminal of the PMOS transistor in the input tube. In the working state, the current flowing through the input tube is kept constant through the current limiting effect of the current source tube, stabilizing the power consumption and transconductance gain of the floating transconductance amplifier. Figure 3 The PMOS transistor shown on the upper left generates the bias voltage required for the floating current source through the PMOS current mirror structure connected by the diode in the charging current mirror in the charging state, and charges the current source bias capacitor.

[0061] The source and drain of the "dummy" transistor are short-circuited, consuming no power. By cross-connecting the gate and drain of the input tube with polarity opposite to that of the input tube, the differential-mode kickback noise generated when the input tube is working is converted into common-mode kickback noise, eliminating the impact of the kickback noise on the operation of the transconductance amplifier.

[0062] The power supply capacitor is Figure 3 Middle C res , is connected to the floating current source and input tube in the working state, and provides power for both.

[0063] Control switch is Figure 3 The switches in the upper half of the figure are implemented by PMOS transistors, and the switches in the lower half of the figure are implemented by NMOS transistors. They all work in the linear region or the cut-off region, and can connect or disconnect the lines between the power supply capacitor, input tube, current source bias capacitor and current source tube, thereby realizing switching between different working phases of the floating transconductance amplifier.

[0064] During operation, the floating transconductance amplifier (FTA) supplies power to the input transistors and floating current source through the supply capacitors, which are completely disconnected from the power supply and ground. Due to current continuity, the current flowing out of the supply capacitors is equal to the current flowing into them. Therefore, the input transistors do not generate common-mode current flowing to the output, nor do they change the common-mode bias voltage at the output. Instead, the floating voltage domain provided by the supply capacitors shifts to the output's original common-mode voltage via changes in the supply capacitor's voltage relative to ground. During FTA operation, as the supply capacitors deliver energy, the voltage differential across them gradually decreases. At this point, the current source transistors in the floating current source maintain a stable gate-source voltage differential, maintained in saturation, and exhibiting high output impedance, thanks to the current source bias capacitors connected between their source and gate terminals. This voltage differential change primarily impacts the floating transconductance amplifier by reducing the source-drain voltage difference of the current source transistors. It has little effect on the voltage differential between the input transistors and the operating current flowing through them, allowing the transconductance gain to remain approximately constant during operation.

[0065] Compared to existing technologies, the operating voltage domain of the floating transconductance amplifier can freely float with the common-mode voltage at the output point. This prevents the source-drain voltage difference of the input transistor from being limited by excessively high or low common-mode voltage at the output point, thereby maintaining the output impedance of the floating transconductance amplifier. This makes it suitable for subsequent circuits with high input impedance and a fixed input common-mode voltage. For example, a low-voltage current-controlled ring oscillator is biased at an extremely low operating current to achieve a low oscillation frequency, thereby reducing the energy consumption of the ring oscillator itself and the subsequent quantization circuitry, significantly improving the energy efficiency of the fine quantization process. However, the input point of the current-controlled ring oscillator is also biased at an extremely low voltage, and the extremely low operating current results in a higher input impedance. If a transconductance amplifier containing an NMOS transistor input tube is used to drive the current-controlled ring oscillator, the common-mode bias voltage at the output node of the transconductance amplifier will be limited by the current-controlled ring oscillator, thereby limiting the source-drain voltage difference of the NMOS transistor input tube, forcing the NMOS transistor input tube into the linear region, significantly reducing the output impedance. The output current of the transconductance amplifier will be absorbed by the NMOS transistor, and the actual current flowing into the current-controlled ring oscillator is small, that is, the actual gain is small. Traditional solutions use only PMOS transistors as the input tubes of the transconductance amplifier, which can provide higher output impedance but do not reuse the current flowing through the input tube, thus limiting energy efficiency and noise efficiency. The floating transconductance amplifier technology proposed in the present invention can maintain the source-drain voltage difference of the NMOS transistor through a floating voltage domain when the output node voltage is low and the output load input impedance is high, thereby maintaining the overall output impedance of the floating transconductance amplifier. This achieves current reuse without losing effective gain, and significantly improves the energy efficiency of the overall circuit in combination with a low-voltage current-controlled ring oscillator.

[0066] The integrator uses a low-voltage current-controlled ring oscillator as a time-domain integrator, integrating the current signal output by the transconductance amplifier and converting it into the phase difference between the two ring oscillators. Fine-scale digital logic quantizes the phase difference between the ring oscillators into a digital code, which is then output as a fine-scale digital code.

[0067] The fine quantization digital logic also adds the fine quantization output detection logic and the fast tracking control logic in the fast tracking logic circuit, such as Figure 2 As shown, the fine quantization output codeword is extracted, compared and judged to generate the signal required to control the fine quantization dynamic range tracking, which is used to control the fast tracking execution logic of the coarse quantization level, thereby realizing the continuous tracking input of the fine quantization dynamic range.

[0068] C. Chopper switch

[0069] In specific implementation, the present invention adds four chopping switches before the input capacitor, before the DAC switch, after the floating transconductance amplifier, and after the comparator in the proposed continuous time incremental tracking scaling sensor readout front-end circuit, such as Figure 1 By periodically switching the polarity of the chopper switches during the fine quantization cycle and flipping the input signal at each node, the low-frequency input signal can be isolated from the low-frequency flicker noise and DC offset of the DAC switches and floating transconductance amplifier. The effects of flicker noise and DC offset on the output can then be eliminated during subsequent digital processing.

[0070] In a specific implementation of the present invention, the implementation of the continuous time increment tracking zoom sensor readout front-end circuit includes the following steps:

[0071] 1) Prepare a multi-bit SAR sensor readout front-end circuit, consisting of a coarse quantization DAC, a comparator, and coarse quantization digital logic. The output digital code of the coarse quantization digital logic is connected to the digital input of the coarse quantization DAC. The top plate of the coarse quantization DAC is connected to the input of the comparator, and the comparator output is connected to the input of the coarse quantization digital logic. The coarse quantization digital logic includes asynchronous SAR logic and asynchronous counter logic with a shared data register, which is used to perform fast tracking of the fine dynamic range.

[0072] Structurally, a multi-bit SAR sensor readout front-end circuit is used as a coarse quantizer.

[0073] 2) Prepare a floating transconductance amplifier, using complementary MOS transistors connected at their drain terminals as the amplifier input transistors. Add a floating current source consisting of a current source transistor and a current source bias capacitor on the power supply side of the input transistor to stabilize the amplifier's operating current and transconductance gain. Add a power supply capacitor connected to both the input transistor and the floating current source in the operating state, allowing the amplifier to operate in a floating voltage domain. Add a current mirror to charge the current source bias capacitor in the charging state. Add a MOS transistor switch to periodically shut down the amplifier's output, charging the current source bias capacitor via the floating power supply capacitor, and provide a dead zone that eliminates chopping artifacts.

[0074] Structurally, a floating transconductance amplifier is used as the transconductance amplifier in the multi-bit incremental ΔΣ sensor readout front-end circuit, which plays a key role in noise performance and noise efficiency.

[0075] 3) Prepare a multi-bit incremental ΔΣ sensor readout front-end circuit, consisting of a fine-scale DAC, a transconductance amplifier, an integrator, a quantizer, and fine-scale digital logic. The transconductance amplifier uses a floating transconductance amplifier, and the integrator uses a low-voltage current-controlled ring oscillator. The fine-scale digital logic includes a fine-scale output detection logic circuit and a tracking control logic circuit. Based on the fine-scale output digital code, it generates a tracking control signal for fast tracking within the fine-scale dynamic range.

[0076] Structurally, a multi-bit incremental ΔΣ sensor readout front-end circuit is used as a fine quantizer.

[0077] 4) Connect the charge-sharing DAC top plate of the multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit to form a shared DAC assembly. This shared DAC assembly consists of two connected capacitor array top plates of different sizes. The DAC in the multi-bit SAR sensor readout front-end circuit is a coarse quantization DAC, while the DAC in the multi-bit incremental ΔΣ sensor readout front-end circuit is a fine quantization DAC.

[0078] 5) The multi-bit SAR sensor readout front-end circuit is used as the first stage, and the multi-bit incremental ΔΣ sensor readout front-end circuit is used as the second stage. The two stages are connected via a shared DAC component top board. The tracking control logic of the fine quantization digital logic in the second stage is connected to the tracking execution logic of the coarse quantization digital logic in the first stage to form a complete fast tracking logic circuit. Chopping switches are added before the input, before the shared DAC component input, after the floating transconductance amplifier output, and after the comparator output to obtain an improved continuous-time incremental tracking and scaling sensor readout front-end circuit.

[0079] like Figure 1As shown, the present invention's continuous-time incremental tracking and scaling sensor readout front-end circuit, when implemented, uses a 7-bit SAR sensor readout front-end circuit for coarse quantization and a 5-bit incremental ΔΣ sensor readout front-end circuit for fine quantization, including 2 bits of redundancy between the coarse and fine quantization stages. During each operating cycle, the circuit resets the fine quantizer. If the input exceeds the fine quantizer's dynamic range during the previous cycle, a coarse SAR conversion is performed in parallel to search for the input signal. After the reset, fine quantization is performed for multiple clock cycles. During the fine quantization process, a fast tracking logic circuit controls the fine quantizer's dynamic range to continuously track input signal changes. The coarse and fine quantization digital codes obtained during the fine quantization phase are sampled and filtered through a first-order incremental sampling filter, or accumulator, to produce the sensor readout digital output of the entire circuit.

[0080] Specifically, its working mode is as follows:

[0081] 1) Reset and coarse quantization phase

[0082] like Figure 1 As shown in FIG, at the first clock cycle at the beginning of each conversion cycle, the reset signal is high, the integrator and the quantizer output in the fine quantizer will be reset, the residual phase difference in the fine quantizer integrator and the digital code output by the quantizer will be cleared, and the integrator phase difference and the quantizer output digital code will be reset to 0.

[0083] If the input signal to the fine quantizer exceeds its dynamic range during the previous conversion cycle, the fast tracking logic detects this event and generates a SAR enable signal during the reset and coarse quantization phases of the next conversion cycle. The coarse quantizer then switches to SAR mode, searching the input signal through an asynchronous SAR conversion process to bring the fine quantizer's dynamic range closer to the input signal. If the input signal remains within the fine quantizer's dynamic range, the coarse quantizer maintains the original coarse quantization codeword during the current cycle and does not operate, thus reducing power consumption during the SAR conversion process.

[0084] 2) Fine quantization phase

[0085] like Figure 1As shown in the figure, during the remainder of each conversion cycle, starting from the second clock cycle, the reset signal is low, and the fine quantizer operates. A floating transconductance amplifier amplifies the residual input signal into a current signal, which is integrated by a low-voltage current-controlled ring oscillator integrator and converted into an accumulated phase difference. The accumulated phase difference is converted into a phase-difference digital pulse signal by a phase detector in the fine quantization logic. This signal is sampled by a register on the rising clock edge to produce a fine quantization output digital code. The resulting fine quantization output digital code is fed into the fine quantization DAC for feedback and into the fast tracking logic circuit to determine whether a control signal needs to be generated and transmitted to the coarse quantization stage to increase or decrease the coarse quantization codeword.

[0086] like Figure 4 As shown, in the fine quantization phase, the working mode can be further subdivided as follows:

[0087] 1) Charging phase

[0088] During this phase, the floating transconductance amplifier's current source and input transistors are disconnected from the supply capacitors, halting operation. The floating transconductance amplifier's supply capacitors are connected to the analog power supply, charging the supply capacitors until the voltage difference across them approaches the analog power supply voltage. At this point, a static current mirror is connected to the current source bias capacitors, charging the tail current source bias capacitors with the gate-source voltage difference required to provide the desired current. The floating transconductance amplifier is disconnected from the downstream low-voltage current-controlled ring oscillator integrator and generates no output current. An external bias voltage maintains the common-mode voltage at the output, free from parasitic capacitance coupling. During this phase, since the floating transconductance amplifier's output is disconnected from the downstream stage, voltage changes at the input node do not affect the output, creating a dead zone for the amplifier. Therefore, the chopper switch is toggled during this phase. The chopping artifacts generated by the chopper switch toggling are absorbed by the DAC within this dead zone and do not affect the amplifier's output.

[0089] 2) Establish phase

[0090] During this phase, the floating transconductance amplifier's supply capacitors are completely disconnected from the analog power supply and ground, while the current source and input transistors are connected to the supply capacitors. The current source bias capacitors are also disconnected from the static current mirror and connected between the gate and source terminals of the current source transistor, forming a floating current source structure. At this point, the current provided by the supply capacitors flows through the current source and input transistors. The input remains connected to the input signal, while the output remains connected to the output bias voltage. During this time, the source-drain voltage differential of the floating transconductance amplifier's input transistor gradually builds, and the current source transistor limits the output voltage, resulting in a stable current and input transistor gain. When the output bias voltage is low, the source voltage of the NMOS transistor in the input transistor can drop below ground, providing a high source-drain voltage differential for the NMOS transistor, keeping it in deep saturation and providing a high output impedance.

[0091] 3) Integral phase

[0092] In this phase, in addition to establishing phase connections, the output of the floating transconductance amplifier is connected to the subsequent low-voltage current-controlled ring oscillator integrator. The voltage difference in the input section is converted into a differential-mode output current of the floating transconductance amplifier, which then flows into the subsequent integrator. Furthermore, since the supply capacitors are completely isolated from the analog power supply and ground, no current loop is formed. Due to current continuity constraints, no common-mode output current is generated, which in turn does not affect the bias point and gain of the subsequent integrator. This phase, where the floating transconductance amplifier actually operates and provides gain, occupies the majority of the fine quantization cycle.

[0093] The present invention provides a continuous time increment tracking zoom sensor readout front-end circuit and its implementation method, improving the continuous time increment tracking zoom sensor readout circuit. The circuit comprises: a fine quantization dynamic range fast tracking logic circuit based on fine quantizer output detection; and a floating transconductance amplifier. The fine quantization dynamic range tracking method designed in the present invention does not introduce additional analog circuit units, fully utilizing the low quantization noise characteristics of the multi-bit fine quantizer, and directly using the fine quantizer output codeword to estimate the input signal. This avoids the high power consumption and slow tracking response problems associated with additional analog detection circuits or post-sampling tracking prediction circuits that compensate for high input slopes in traditional tracking technologies. Furthermore, the floating transconductance amplifier proposed in the present invention features high noise efficiency, simple biasing, no need for common-mode feedback, and is unaffected by the common-mode voltage at the output point. It can effectively operate in conjunction with low-voltage current-controlled ring oscillators, further improving the energy efficiency of the overall circuit. Compared with existing sensor readout front-end circuits, the present invention achieves high energy efficiency, low noise, and high dynamic range, and has broad application prospects in emerging edge applications such as the Internet of Things, medical devices, and wearable devices.

[0094] It should be noted that the purpose of disclosing the embodiments is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a floating transconductance amplifier, characterized in that: Includes: A complementary MOS transistor with its drain connected is used as the amplifier input tube. A floating current source consisting of a current source tube and a current source bias capacitor is added on the power supply side of the input tube to stabilize the operating current and transconductance gain of the amplifier. Adding a power supply capacitor connected to both ends of the input tube and the floating current source in the working state allows the amplifier to operate in the floating voltage domain; Add a charging current mirror to charge the current source bias capacitor in the charging state; A control switch composed of a MOS transistor is added to switch the charging and working states of the power supply capacitor and the current source bias capacitor. At the same time, the output of the amplifier is periodically turned off by charging the power supply capacitor, providing an amplifier dead zone that can be used to eliminate chopping artifacts. The prepared floating transconductance amplifier includes an input tube, a floating current source, a charging current mirror, a virtual transistor, a power supply capacitor and a control switch; The input tube and the floating current source of the floating transconductance amplifier are powered by a power supply capacitor and are completely disconnected from the power supply and the ground; The current flowing out of the power supply capacitor is the same as the current flowing into the power supply capacitor. The input tube does not generate common-mode current flowing to the output and does not change the common-mode bias voltage of the output point. Through the change of the voltage of the power supply capacitor to the ground, the floating voltage domain provided by the power supply capacitor is moved to both ends of the original common-mode voltage of the output point. The current source tube in the floating current source provides a stable gate-source voltage difference through the current source bias capacitor connected between the source and gate terminals, and is always biased in the saturation region to provide output impedance.

2. The method for preparing a floating transconductance amplifier according to claim 1, wherein: The input transistor includes an NMOS transistor and a PMOS transistor. The gates of the two transistors are connected together to form the input of the floating transconductance amplifier. The drains of the two transistors are connected together to form the output of the floating transconductance amplifier. Current multiplexing is achieved by connecting two sets of transistors with transconductance gain in series in the current path of the amplifier. The input transistor uses a thick-gate transistor to reduce gate leakage, so that the gate establishes a bias voltage through a pseudo-resistance bias circuit composed of transistors in the cut-off region. The floating current source includes a current source tube and a current source bias capacitor; The current source tube is a PMOS transistor; the current source bias capacitor is connected between the gate and source of the current source tube to provide a constant gate-source bias voltage for the current source tube; the floating current source is connected in series with the source terminal of the PMOS transistor in the input tube. In the working state, the current limiting effect of the current source tube keeps the current flowing through the input tube constant, thereby stabilizing the power consumption and transconductance gain of the floating transconductance amplifier; The charging current mirror uses a PMOS current mirror, and the current source bias capacitor is charged through the charging current mirror in the charging state; The source and drain of the dummy transistor are short-circuited, consuming no power. By cross-connecting the gate and drain of the input transistor with polarity opposite to that of the input transistor, the differential-mode kickback noise generated when the input transistor is working is converted into common-mode kickback noise, eliminating the impact of the kickback noise on the operation of the transconductance amplifier. The power supply capacitor is connected to the floating current source and the input tube in the working state to provide power; The control switch connects or disconnects the power supply capacitor, the current source bias capacitor, the input tube and the current source tube through the NMOS transistor and the PMOS transistor working in the linear region and the cut-off region, thereby realizing the switching between different working phases of the floating transconductance amplifier.

3. A method for implementing a continuous time increment tracking zoom sensor readout front-end circuit, characterized in that: A floating transconductance amplifier is prepared to achieve current multiplexing and low output point voltage simultaneously through floating power supply; the tracking circuit in the tracking and zoom sensor readout front end is simplified by directly detecting the output of the fine quantizer without introducing an additional input detection circuit; and the dynamic range tracking of rapidly changing signals is achieved by adjusting the digital code of the coarse quantizer using the output of the fine quantizer. The method includes the following steps: 1) Preparing a floating transconductance amplifier, comprising: A complementary MOS transistor with its drain connected is used as the amplifier input tube. A floating current source consisting of a current source tube and a current source bias capacitor is added on the power supply side of the input tube to stabilize the operating current and transconductance gain of the amplifier. Adding a power supply capacitor connected to both ends of the input tube and the floating current source in the working state allows the amplifier to operate in the floating voltage domain; Add a charging current mirror to charge the current source bias capacitor in the charging state; A control switch composed of a MOS transistor is added to switch the charging and working states of the power supply capacitor and the current source bias capacitor. At the same time, the output of the amplifier is periodically turned off by charging the power supply capacitor, providing an amplifier dead zone that can be used to eliminate chopping artifacts. The prepared floating transconductance amplifier includes an input tube, a floating current source, a charging current mirror, a virtual transistor, a power supply capacitor and a control switch; The input transistor and floating current source of the floating transconductance amplifier are powered by a power supply capacitor and are completely disconnected from the power supply and ground. The current flowing out of the power supply capacitor is equal to the current flowing into the power supply capacitor, and the input transistor does not generate a common-mode current flowing to the output, and the common-mode bias voltage at the output point is not changed. The floating voltage domain provided by the power supply capacitor is moved to both ends of the original common-mode voltage at the output point by changing the voltage of the power supply capacitor relative to the ground. The current source transistor in the floating current source provides a stable gate-source voltage difference through the current source bias capacitor connected between the source terminal and the gate terminal, and is always biased in the saturation region to provide output impedance. Then, a fine-grained dynamic range fast tracking is performed, including the execution process of step 2) and the control process of step 3); 2) preparing a multi-bit SAR sensor readout front-end circuit comprising a coarse quantization DAC, a comparator, and coarse quantization digital logic; the output digital code of the coarse quantization digital logic is connected to the digital input of the coarse quantization DAC, the top plate of the coarse quantization DAC is connected to the input of the comparator, and the comparator output is connected to the input of the coarse quantization digital logic; wherein the coarse quantization digital logic comprises asynchronous SAR logic and asynchronous counter logic sharing a data register, and is used to perform fast tracking of the fine quantization dynamic range; 3) preparing a multi-bit incremental ΔΣ sensor readout front-end circuit, comprising a fine quantization DAC, a floating transconductance amplifier, an integrator, a quantizer, and fine quantization digital logic; the fine quantization digital logic outputs a digital code connected to the fine quantization DAC input, the top plate of the fine quantization DAC is connected to the transconductance amplifier input, the transconductance amplifier input is connected to the integrator input, the integrator input is connected to the quantizer input, and the quantizer output result is connected to the fine quantization digital logic; the fine quantization digital logic comprises a fine quantization output detection logic circuit and a tracking control logic circuit, and generates a tracking control signal according to the fine quantization output digital code for controlling the fine quantization dynamic range and fast tracking; 4) connecting the charge-sharing DAC top board of the multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit to form a shared DAC component; wherein the DAC in the multi-bit SAR sensor readout front-end circuit is a coarse quantization DAC, and the DAC in the multi-bit incremental ΔΣ sensor readout front-end circuit is a fine quantization DAC; 5) A multi-bit SAR sensor readout front-end circuit is used as the first stage, and a multi-bit incremental ΔΣ sensor readout front-end circuit is used as the second stage. The two stages of the sensor readout front-end circuit are connected via a shared DAC component top plate. The tracking control logic of the fine quantization digital logic in the second stage is connected to the tracking execution logic of the coarse quantization digital logic in the first stage. A chopping switch is then added to obtain a continuous-time incremental tracking and scaling sensor readout front-end circuit.

4. The method for implementing a continuous time incremental tracking and scaling sensor readout front-end circuit according to claim 3, wherein: In step 1), in the floating transconductance amplifier prepared: The input transistor includes an NMOS transistor and a PMOS transistor. The gates of the two transistors are connected together to form the input of the floating transconductance amplifier. The drains of the two transistors are connected together to form the output of the floating transconductance amplifier. Current multiplexing is achieved by connecting two sets of transistors with transconductance gain in series in the current path of the amplifier. The input transistor uses a thick-gate transistor to reduce gate leakage, so that the gate establishes a bias voltage through a pseudo-resistance bias circuit composed of transistors in the cut-off region. The floating current source includes a current source tube and a current source bias capacitor; The current source tube is a PMOS transistor; the current source bias capacitor is connected between the gate and source of the current source tube to provide a constant gate-source bias voltage for the current source tube; the floating current source is connected in series with the source terminal of the PMOS transistor in the input tube. In the working state, the current limiting effect of the current source tube keeps the current flowing through the input tube constant, thereby stabilizing the power consumption and transconductance gain of the floating transconductance amplifier; The charging current mirror uses a PMOS current mirror, and the current source bias capacitor is charged through the charging current mirror in the charging state; The source and drain of the dummy transistor are short-circuited, consuming no power. By cross-connecting the gate and drain of the input transistor with polarity opposite to that of the input transistor, the differential-mode kickback noise generated when the input transistor is working is converted into common-mode kickback noise, eliminating the impact of the kickback noise on the operation of the transconductance amplifier. The power supply capacitor is connected to the floating current source and the input tube in the working state to provide power; The control switch connects or disconnects the power supply capacitor, the current source bias capacitor, the input tube and the current source tube through the NMOS transistor and the PMOS transistor working in the linear region and the cut-off region, thereby realizing the switching between different working phases of the floating transconductance amplifier.

5. The method for implementing a continuous time incremental tracking and scaling sensor readout front-end circuit according to claim 3, wherein: Performing fast tracking of the fine quantization dynamic range, wherein the control process is specifically implemented in the fine quantization digital logic part in step 3), and the execution process is specifically implemented in the coarse quantization digital logic in step 2); In the coarse quantization digital logic, by integrating asynchronous SAR logic and asynchronous bidirectional counter, SAR conversion and coarse quantization digital code increase and decrease can be controlled, so that the coarse quantization digital code tracks the input signal; in the fine quantization digital logic, the fine quantization output detection and judgment circuit is used to provide the control signal required for the coarse quantization level to track the input signal.

6. The method for implementing a continuous time incremental tracking and scaling sensor readout front-end circuit according to claim 3, wherein: Design a fine quantization dynamic range fast tracking logic circuit based on fine quantizer output detection to implement step 2) and step 3) to perform fine quantization dynamic range fast tracking; The fine quantization dynamic range fast tracking logic circuit based on fine quantizer output detection includes: fine quantization output detection logic, tracking control logic and tracking execution logic.

7. The method for implementing a continuous time incremental tracking and scaling sensor readout front-end circuit according to claim 3, wherein: In step 3), the integrator uses a low-pressure flow-controlled ring oscillator as a time-domain integrator.

8. The method for implementing a continuous time incremental tracking and scaling sensor readout front-end circuit according to claim 3, wherein: In step 4), the shared DAC component is composed of two parts, a multi-bit SAR sensor readout front-end circuit and a multi-bit incremental ΔΣ sensor readout front-end circuit, which are connected to each other with capacitor array top plates of different sizes.

9. The method for implementing a continuous time incremental tracking and scaling sensor readout front-end circuit according to claim 3, wherein: In step 5), chopping switches are specifically added before the input, before the input of the shared DAC component, after the output of the floating transconductance amplifier, and after the output of the comparator.

Images