Ultralow offset voltage trimming operational amplifier based on automatic trimming and trimming method

Abstract

The invention discloses an ultralow offset voltage trimming operational amplifier based on automatic trimming and a trimming method. The amplifier comprises a voltage reference source, a first two-way selection switch, a second two-way selection switch, a third two-way selection switch, a core operational amplifier, a low-pass filter, a comparator, an SAR logic module, a trimming network, a first resistor and a second resistor. The method comprises the following steps: judging an input offset voltage and a common-mode voltage, and outputting a judgment result; adjusting the control word according to a judgment result, carrying out successive approximation, and outputting an initial control word signal; and trimming the input offset voltage of the core operational amplifier according to the initial control word signal, and outputting the trimmed input offset voltage. According to the embodiment of the invention, the input offset voltage of the operational amplifier can be reduced to a microvolt level, and the voltage trimming precision of the operational amplifier is improved. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to an ultra-low offset voltage trimming operational amplifier and a trimming method based on automatic trimming. Background Art

[0002] Related methods for reducing the input offset voltage include trimming technology, chopping technology, auto-zero technology, etc. However, in applications such as medical instruments with a narrow temperature range and high source impedance, trimming technology is more attractive than the other two technologies. For wafer-level trimming, any physical stress during the process of cutting the wafer into individual die and complete packaging will cause an offset voltage shift. Package-level trimming is performed after the die is completed and packaged, which can avoid errors caused by various physical stresses and has higher trimming accuracy. However, package-level trimming is a one-time operation. Once the trimming is completed, the trimming circuit will be permanently turned off. Even if the offset voltage is reduced to the microvolt level after package-level trimming, the residual offset voltage will still change with time and temperature.

[0003] In summary, the technical problems existing in the related art need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose an ultra-low offset voltage trimming operational amplifier and a trimming method based on automatic trimming, which can reduce the input offset voltage of the operational amplifier to the microvolt level and improve the voltage trimming accuracy of the operational amplifier.

[0005] To achieve the above object, one aspect of the embodiments of the present application provides an ultra-low offset voltage trimming operational amplifier based on automatic trimming. The amplifier includes a voltage reference source, a first two-way selector switch, a second two-way selector switch, a third two-way selector switch, a core operational amplifier, a low-pass filter, a comparator, a SAR logic module, a trimming network, a first resistor, and a second resistor. The output terminal of the voltage reference source is connected to the input terminal of the first two-way selector switch. The output terminal of the first two-way selector switch is connected to the non-inverting input terminal of the core operational amplifier. The second terminal of the first resistor is respectively connected to the input terminal of the second two-way selector switch and the first terminal of the second resistor. The output terminal of the second two-way selector switch is connected to the inverting input terminal of the core operational amplifier. The output terminal of the core operational amplifier is connected to the input terminal of the third two-way selector switch. The second terminal of the second resistor and the output terminal of the third two-way selector switch are connected to the input terminal of the low-pass filter. The output terminal of the low-pass filter is connected to the positive input terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the SAR logic module. The output terminal of the SAR logic module is connected to the input terminal of the trimming network. The output terminal of the trimming network is connected to the control input terminal of the core operational amplifier, where:

[0006] The voltage reference source is used to generate a common-mode voltage;

[0007] The first two-way selector switch, the second two-way selector switch, and the third two-way selector switch are used to obtain a trimming enable signal and a trimming end signal, and configure the core operational amplifier into a trimming mode according to the trimming enable signal, and configure the core operational amplifier into a working mode according to the trimming end signal;

[0008] The core operational amplifier has an input offset voltage;

[0009] The first resistor and the second resistor are used to amplify the input offset voltage and output the amplified input offset voltage;

[0010] The low-pass filter is used to perform noise filtering on the amplified input offset voltage to obtain a filtered input offset voltage;

[0011] The comparator is used to judge the filtered input offset voltage and the common-mode voltage and output a judgment result;

[0012] The SAR logic module is used to adjust the control word according to the judgment result and perform successive approximation, and output a starting control word signal;

[0013] The trimming network is used to trim the input offset voltage of the core operational amplifier according to the starting control word signal, and output the trimmed input offset voltage.

[0014] In some embodiments, the voltage reference source includes a voltage dividing network and a voltage buffer. The voltage dividing network includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor. The first end of the first resistor and the second end of the tenth resistor are connected to the core operational amplifier. The second end of the first resistor is connected to the first end of the second resistor. The second end of the second resistor is connected to the first end of the third resistor. The second end of the third resistor is connected to the first end of the fourth resistor. The second end of the fourth resistor is connected to the first end of the fifth resistor. The second end of the fifth resistor, the first end of the sixth resistor, and the positive input terminal of the voltage buffer are connected. The negative input terminal of the voltage buffer is connected to the output terminal of the voltage buffer. The second end of the sixth resistor is connected to the first end of the seventh resistor. The second end of the seventh resistor is connected to the first end of the eighth resistor. The second end of the eighth resistor is connected to the first end of the ninth resistor. The second end of the ninth resistor is connected to the first end of the tenth resistor, where:

[0015] The voltage dividing network is used to generate a reference voltage;

[0016] The voltage buffer is used to buffer the reference voltage and output the common-mode voltage.

[0017] In some embodiments, the expression of the common-mode voltage is specifically as follows:

[0018] V CM ≈V ref =(VDD + VSS) / 2

[0019] In the above formula, V CM represents the common-mode voltage, V ref represents the reference voltage, VDD represents the high-level signal, and VSS represents the low-level signal.

[0020] In some embodiments, the first two-way selection switch, the second two-way selection switch, and the third two-way selection switch have the same two-way selection switch structure. The two-way selection switch structure includes a first CMOS switch transistor and a second CMOS switch transistor. The first CMOS switch transistor includes a first PMOS transistor and a first NMOS transistor. The second CMOS switch transistor includes a second PMOS transistor and a second NMOS transistor. Among them, the source of the second PMOS transistor is connected to the drain of the second NMOS transistor. The drain of the second PMOS transistor, the source of the second NMOS transistor, the drain of the first PMOS transistor, and the source of the first NMOS transistor are connected. The source of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor and the gate of the second PMOS transistor are both connected to a high-level signal. The gate of the first PMOS transistor and the gate of the second NMOS transistor are both connected to a low-level signal.

[0021] In some embodiments, the core operational amplifier includes a PMOS input cascode transistor, a PMOS active current mirror, an NMOS current source, and a tail current source. The PMOS input cascode transistor includes a third PMOS transistor and a fourth PMOS transistor. The PMOS active current mirror includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The NMOS current source includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. Wherein, the input end of the tail current source, the source electrodes of the fifth PMOS transistor and the sixth PMOS transistor are connected; the output end of the tail current source, the source electrodes of the third PMOS transistor and the fourth PMOS transistor are connected; the drain electrode of the third PMOS transistor, the drain electrode of the fourth NMOS transistor, and the source electrode of the sixth NMOS transistor are connected; the drain electrode of the fourth PMOS transistor, the source electrode of the fifth NMOS transistor, and the drain electrode of the third NMOS transistor are connected; the gate electrodes of the third NMOS transistor and the fourth NMOS transistor are connected; the source electrodes of the third NMOS transistor and the fourth NMOS transistor are connected; the gate electrodes of the fifth NMOS transistor and the sixth NMOS transistor are connected; the drain electrode of the fifth NMOS transistor, the drain electrode of the seventh PMOS transistor, the gate electrode of the fifth PMOS transistor, and the gate electrode of the sixth PMOS transistor are connected; the drain electrode of the sixth NMOS transistor and the drain electrode of the eighth PMOS transistor are connected; the drain electrode of the sixth PMOS transistor and the source electrode of the eighth PMOS transistor are connected; the drain electrode of the fifth PMOS transistor and the source electrode of the seventh PMOS transistor are connected.

[0022] In some embodiments, the trimming network includes a current source, an NMOS current mirror network, and a trimming polarity selection differential pair. The trimming polarity selection differential pair includes a first trimming polarity selection differential pair, a second trimming polarity selection differential pair, a third trimming polarity selection differential pair, a fourth trimming polarity selection differential pair, a fifth trimming polarity selection differential pair, a sixth trimming polarity selection differential pair, and a seventh trimming polarity selection differential pair. Wherein, the input end of the current source is connected to the input end of the tail current source of the core operational amplifier; the output end of the current source, the source terminals of the first trimming polarity selection differential pair, the source terminals of the second trimming polarity selection differential pair, the source terminals of the third trimming polarity selection differential pair, the source terminals of the fourth trimming polarity selection differential pair, the source terminals of the fifth trimming polarity selection differential pair, the source terminals of the sixth trimming polarity selection differential pair, and the source terminals of the seventh trimming polarity selection differential pair are all connected to the drain terminal of the NMOS current mirror network.

[0023] In some embodiments, the trimming polarity selection differential pair is used to control the trimming polarity of the trimming network and to control the trimming currents with different weights output by the NMOS current mirror network, and the trimming polarity is used to control the trimming direction of the input offset voltage of the core operational amplifier.

[0024] In some embodiments, the NMOS current mirror network includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. The first trimming polarity selection differential pair includes a fifteenth NMOS transistor and a sixteenth NMOS transistor. The second trimming polarity selection differential pair includes a seventeenth NMOS transistor and an eighteenth NMOS transistor. The third trimming polarity selection differential pair includes a nineteenth NMOS transistor and a twentieth NMOS transistor. The fourth trimming polarity selection differential pair includes a twenty-first NMOS transistor and a twenty-second NMOS transistor. The fifth trimming polarity selection differential pair includes a twenty-third NMOS transistor and a twenty-fourth NMOS transistor. The sixth trimming polarity selection differential pair includes a twenty-fifth NMOS transistor and a twenty-sixth NMOS transistor. The seventh trimming polarity selection differential pair includes a twenty-seventh NMOS transistor and a twenty-eighth NMOS transistor. Wherein, the source of the fifteenth NMOS transistor, the source of the sixteenth NMOS transistor are connected to the drain of the eighth NMOS transistor. The source of the seventeenth NMOS transistor, the source of the eighteenth NMOS transistor are connected to the drain of the ninth NMOS transistor. The source of the nineteenth NMOS transistor, the source of the twentieth NMOS transistor are connected to the drain of the tenth NMOS transistor. The source of the twenty-first NMOS transistor, the source of the twenty-second NMOS transistor are connected to the drain of the eleventh NMOS transistor. The source of the twenty-third NMOS transistor, the source of the twenty-fourth NMOS transistor are connected to the drain of the twelfth NMOS transistor. The source of the twenty-fifth NMOS transistor, the source of the twenty-sixth NMOS transistor are connected to the drain of the thirteenth NMOS transistor. The source of the twenty-seventh NMOS transistor, the source of the twenty-eighth NMOS transistor are connected to the drain of the fourteenth NMOS transistor. The source of the seventh NMOS transistor, the source of the eighth NMOS transistor, the source of the ninth NMOS transistor, the source of the tenth NMOS transistor, the source of the eleventh NMOS transistor, the source of the twelfth NMOS transistor, the source of the thirteenth NMOS transistor and the source of the fourteenth NMOS transistor are connected.The output terminal of the current source, the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, the gate of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor and the gate of the fourteenth NMOS transistor are connected.

[0025] To achieve the above object, on the other hand, an embodiment of the present application proposes a trimming method for an ultra-low offset voltage trimming operational amplifier based on automatic trimming. The method includes the following steps:

[0026] Obtain a common-mode voltage, a trimming enable signal and a trimming end signal, and configure the core operational amplifier into a trimming mode according to the trimming enable signal;

[0027] Amplify the input offset voltage of the core operational amplifier and output the amplified input offset voltage;

[0028] Perform noise filtering processing on the amplified input offset voltage to obtain a filtered input offset voltage;

[0029] Judge the filtered input offset voltage and the common-mode voltage, and output a judgment result;

[0030] Adjust the control word according to the judgment result and perform successive approximation, and output a starting control word signal;

[0031] Perform trimming processing on the input offset voltage of the core operational amplifier according to the starting control word signal, and output a trimmed input offset voltage;

[0032] Configure the core operational amplifier into a working mode according to the trimming end signal to achieve trimming of the core operational amplifier.

[0033] In some embodiments, it further includes:

[0034] If the filtered input offset voltage is greater than the common-mode voltage, the output of the comparator is a high-level signal, the input of the SAR logic module is a high-level signal, and the trimming polarity of the trimming network is positive. At this time, the input offset voltage of the core operational amplifier is increased;

[0035] If the filtered input offset voltage is less than the common-mode voltage, the output of the comparator is a low-level signal, the input of the SAR logic module is a low-level signal, and the trimming polarity of the trimming network is negative. At this time, the input offset voltage of the core operational amplifier is decreased.

[0036] The embodiments of the present application at least include the following beneficial effects: The present application provides an ultra-low offset voltage trimming operational amplifier and a trimming method based on automatic trimming. This solution uses on-chip automatic trimming technology to perform trimming automatically once after the operational amplifier is powered on each time. The input offset voltage of the operational amplifier is reduced to the microvolt level through the SAR logic module, and errors introduced by additional factors such as physical stress and board-level mismatch are avoided. Finally, an ultra-low input offset voltage is achieved, and the voltage trimming accuracy of the operational amplifier is improved. Brief Description of the Drawings

[0037] Figure 1 is a schematic structural diagram of an ultra-low offset voltage trimming operational amplifier based on automatic trimming provided by an embodiment of the present application;

[0038] Figure 2 is a schematic flowchart of the steps of a trimming method for an ultra-low offset voltage trimming operational amplifier based on automatic trimming provided by an embodiment of the present application;

[0039] Figure 3 is a schematic circuit diagram of a voltage reference source, a first two-way selection switch, and a core operational amplifier in the trimming mode provided by an embodiment of the present application;

[0040] Figure 4 is a schematic circuit diagram of the operational amplifier in the working mode provided by an embodiment of the present application;

[0041] Figure 5 is a schematic circuit diagram of the operational amplifier in the trimming mode provided by an embodiment of the present application;

[0042] Figure 6 is a schematic circuit structure diagram of a trimming network provided by an embodiment of the present application;

[0043] Figure 7 is a schematic flowchart of the SAR logic control process of the upper three bits of the trimming control word sel<6:0> provided by an embodiment of the present application;

[0044] Figure 8 is a schematic diagram of the simulation result of the input offset voltage without an automatic trimming circuit provided by an embodiment of the present application;

[0045] Figure 9 is a schematic diagram of the simulation result of the input offset voltage with an automatic trimming circuit provided by an embodiment of the present application.

[0046] Reference numerals: 110, voltage reference source; 121, first two-way selector switch; 122, second two-way selector switch; 123, third two-way selector switch; 130, core operational amplifier; 140, low-pass filter; 150, comparator; 160, SAR logic module; 170, trimming network; 510, non-inverting input terminal of the core operational amplifier; 520, inverting input terminal of the core operational amplifier. Detailed implementation manners

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0048] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0049] The terms "at least one", "a plurality of", "each", "any one", etc. used in the present application, at least one includes one, two or more than two, a plurality of includes two or more than two, each refers to each of the corresponding plurality, and any one refers to any one of the plurality.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0051] First of all, it should be noted that the operational amplifier (abbreviated as op-amp), as the core component of analog integrated circuits, plays an extremely important role in the electronic field. It not only promotes the progress of analog circuit technology but also continues to play a bridging role in the digital age and is an important cornerstone for the innovation and application expansion of electronic design. Among the many parameter indicators of the op-amp, the input offset voltage is particularly important, which limits the application scenarios of the op-amp and determines the accuracy and performance of the op-amp. With the continuous advancement of the feature size of transistors and the development of mixed-signal circuits, the CMOS (Complementary Metal-Oxide-Semiconductor) process has gradually replaced the BJT (Bipolar Junction Transistor) process. The input offset voltage of a typical CMOS op-amp is in the millivolt level and is not suitable for microvolt-level application scenarios. Therefore, various methods for reducing the input offset voltage have been proposed.

[0052] In the related art, there are some deficiencies. For example, package-level trimming is a one-time operation. Once the trimming is completed, the trimming circuit will be permanently turned off. Even if the offset voltage is reduced to the microvolt level after package-level trimming, the residual offset voltage will still change with time and temperature.

[0053] In view of this, in the embodiments of the present application, a trimming operational amplifier with ultra-low offset voltage based on automatic trimming is provided. By adopting on-chip automatic trimming technology, trimming is automatically performed once after the op-amp is powered on each time. Specifically, through the SAR logic network, the input offset voltage of the op-amp is reduced to the microvolt level, ensuring the accuracy of trimming and avoiding errors introduced by additional factors such as physical stress and board-level mismatch. Compared with wafer-level trimming, on-chip automatic trimming technology is performed on the chip. Since it is closer to the user side, on-chip automatic trimming can achieve higher accuracy; compared with package-level trimming, on-chip automatic trimming technology can be performed each time the op-amp is powered on, featuring repeatability and higher accuracy. In addition, on-chip automatic trimming technology has the characteristic of automatic execution and does not require additional test pins and test benches. Therefore, the operational amplifier with ultra-low offset voltage implemented based on on-chip automatic trimming technology in this embodiment has the characteristics of automatic execution of trimming, repeatable execution of trimming, and high trimming accuracy.

[0054] Refer to Figure 1 , Figure 1 is a flowchart of a trimming operational amplifier with ultra-low offset voltage based on automatic trimming provided by the embodiments of the present invention. Refer to Figure 1, the amplifier includes a voltage reference source 110, a first two-way selector switch 121, a second two-way selector switch 122, a third two-way selector switch 123, a core operational amplifier 130, a low-pass filter 140, a comparator 150, a SAR logic module 160, a trimming network 170, a first resistor and a second resistor. The output terminal of the voltage reference source is connected to the input terminal of the first two-way selector switch. The output terminal of the first two-way selector switch is connected to the non-inverting input terminal of the core operational amplifier. The second terminal of the first resistor is respectively connected to the input terminal of the second two-way selector switch and the first terminal of the second resistor. The output terminal of the second two-way selector switch is connected to the inverting input terminal of the core operational amplifier. The output terminal of the core operational amplifier is connected to the input terminal of the third two-way selector switch. The second terminal of the second resistor and the output terminal of the third two-way selector switch are connected to the input terminal of the low-pass filter. The output terminal of the low-pass filter is connected to the positive input terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the SAR logic module. The output terminal of the SAR logic module is connected to the input terminal of the trimming network. The output terminal of the trimming network is connected to the control input terminal of the core operational amplifier, where:

[0055] The voltage reference source is used to generate a common-mode voltage;

[0056] Specifically, the voltage reference source includes a voltage-dividing network and a voltage buffer U1. The voltage-dividing network includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10. The first terminal of the first resistor and the second terminal of the tenth resistor are connected to the core operational amplifier. The second terminal of the first resistor is connected to the first terminal of the second resistor. The second terminal of the second resistor is connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor and the first terminal of the sixth resistor are connected to the positive input terminal of the voltage buffer. The negative input terminal of the voltage buffer is connected to the output terminal of the voltage buffer. The second terminal of the sixth resistor is connected to the first terminal of the seventh resistor. The second terminal of the seventh resistor is connected to the first terminal of the eighth resistor. The second terminal of the eighth resistor is connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the first terminal of the tenth resistor. Among them, the voltage-dividing network is used to generate a reference voltage; the voltage buffer is used to buffer the reference voltage and output a common-mode voltage.

[0057] In this embodiment, the voltage reference source is composed of 10 series-connected resistors R1 to R10 and a voltage buffer U1; the upper end of R1 is connected to the positive power supply voltage VDD, and the lower end of R10 is connected to the negative power supply voltage VSS; the non-inverting input terminal of the voltage buffer U1 is connected to the lower end of R5 and the upper end of R6, and the output terminal and the inverting input terminal of U1 are short-circuited and configured as a voltage buffer.

[0058] The first two-way selection switch, the second two-way selection switch, and the third two-way selection switch are used to obtain the trimming enable signal and the trimming end signal, and configure the core operational amplifier into the trimming mode according to the trimming enable signal, and configure the core operational amplifier into the working mode according to the trimming end signal;

[0059] Specifically, the first two-way selection switch, the second two-way selection switch, and the third two-way selection switch have the same two-way selection switch structure. The two-way selection switch structure includes a first CMOS switch tube and a second CMOS switch tube. The first CMOS switch tube includes a first PMOS transistor MP1 and a first NMOS transistor MN1. The second CMOS switch tube includes a second PMOS transistor MP2 and a second NMOS transistor MN2. Among them, the source of the second PMOS transistor is connected to the drain of the second NMOS transistor. The drain of the second PMOS transistor, the source of the second NMOS transistor, the drain of the first PMOS transistor, and the source of the first NMOS transistor are connected. The source of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor and the gate of the second PMOS transistor are both connected to a high-level signal, and the gate of the first PMOS transistor and the gate of the second NMOS transistor are both connected to a low-level signal.

[0060] In this embodiment, the three two-way selection switches are respectively composed of two complementary metal-oxide-semiconductor field-effect transistor (CMOS) switches. Taking the first two-way selection switch as an example, MP1 and MN1 form the first CMOS switch, and MP2 and MN2 form the second CMOS switch. The source terminal of MP1 and the drain terminal of MN1 are short-connected to the first selection port. The source terminal of MP2 and the drain terminal of MN2 are short-connected to the second selection port. The drain terminal of MP1, the source terminal of MN1, the drain terminal of MP2, and the source terminal of MN2 are short-connected and then connected to the output port. The gate terminal of MN1 and the gate terminal of MP2 are connected to the control level EN, and the gate terminal of MP1 and the gate terminal of MN2 are connected to the control level ENB, where ENB is the inverse of EN.

[0061] The core operational amplifier has an input offset voltage;

[0062] Specifically, the core operational amplifier includes a PMOS input cascode transistor, a PMOS active current mirror, an NMOS current source, and a tail current source I1. The PMOS input cascode transistor includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The PMOS active current mirror includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, and an eighth PMOS transistor MP8. The NMOS current source includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. Among them, the input terminal of the tail current source, the source electrode of the fifth PMOS transistor, and the source electrode of the sixth PMOS transistor are connected. The output terminal of the tail current source, the source electrode of the third PMOS transistor, and the source electrode of the fourth PMOS transistor are connected. The drain electrode of the third PMOS transistor, the drain electrode of the fourth NMOS transistor, and the source electrode of the sixth NMOS transistor are connected. The drain electrode of the fourth PMOS transistor, the source electrode of the fifth NMOS transistor, and the drain electrode of the third NMOS transistor are connected. The gate electrode of the third NMOS transistor and the gate electrode of the fourth NMOS transistor are connected. The source electrode of the third NMOS transistor and the source electrode of the fourth NMOS transistor are connected. The gate electrode of the fifth NMOS transistor and the gate electrode of the sixth NMOS transistor are connected. The drain electrode of the fifth NMOS transistor, the drain electrode of the seventh PMOS transistor, the gate electrode of the fifth PMOS transistor, and the gate electrode of the sixth PMOS transistor are connected. The drain electrode of the sixth NMOS transistor and the drain electrode of the eighth PMOS transistor are connected. The drain electrode of the sixth PMOS transistor and the source electrode of the eighth PMOS transistor are connected. The drain electrode of the fifth PMOS transistor and the source electrode of the seventh PMOS transistor are connected.

[0063] In this embodiment, the core operational amplifier is a folded cascode amplifier, which is composed of a PMOS input cascode transistor, a PMOS active current mirror, an NMOS current source, and a tail current source I1. The PMOS input cascode transistor is composed of PMOS input common-source transistors MP3 and MP4, and common-gate transistors MN5 and MN6. The source terminals of MP3 and MP4 are short-circuited and connected to the tail current source I1. The drain terminal of MP3 is connected to the source terminal of MN6, and the gate terminal is the non-inverting input terminal. The drain terminal of MP4 is connected to the source terminal of MN5, and the gate terminal is the inverting input terminal. The gate terminals of MN5 and MN6 are short-circuited and connected to the bias voltage VB2. The PMOS active current mirror is composed of common-source transistors MP5 and MP6, and common-gate transistors MP7 and MP8. The source terminals of MP5 and MP6 are connected to VDD, and the gate terminals are connected to the drain terminal of MP7 and the drain terminal of MN5. The drain terminal of MP5 is connected to the source terminal of MP7, and the drain terminal of MP6 is connected to the source terminal of MP8. The gate terminals of MP7 and MP8 are short-circuited and connected to the bias voltage VB3. The drain terminal of MP8 is connected to the drain terminal of MN6. The NMOS current source is composed of MN3 and MN4. The source terminals of MN3 and MN4 are connected to VSS, and the gate terminals are connected to the bias voltage VB1. The drain terminal of MN3 is connected to the source terminal of MN5, and the drain terminal of MN4 is connected to the source terminal of MN6.

[0064] The first resistor R1 and the second resistor R2 are used to amplify the input offset voltage and output the amplified input offset voltage.

[0065] In this embodiment, the resistors R1 and R2 are used as the peripheral circuit of the core operational amplifier and are configured as a closed loop during the automatic trimming process, which determines the magnitude of the closed-loop gain.

[0066] The low-pass filter is used to filter the noise of the amplified input offset voltage to obtain the filtered input offset voltage.

[0067] Specifically, the low-pass filter filters the amplified input offset voltage to reduce noise and improve the signal-to-noise ratio. The filtered signal is sent to the non-inverting input terminal of the comparator and then compared by the comparator.

[0068] The comparator is used to judge the filtered input offset voltage and the common-mode voltage and output the judgment result.

[0069] Specifically, the non-inverting input terminal of the comparator is connected to the output of the low-pass filter, the inverting input terminal is connected to the output VCM of the voltage reference source, and the output terminal is connected to the SAR logic.

[0070] The SAR logic module is used to adjust the control word according to the judgment result and perform successive approximation, and output the initial control word signal.

[0071] Specifically, the SAR logic (Successive Approximation Register) is a successive approximation algorithm that can convert an analog signal into a digital signal. The input of the SAR logic is the output of a comparator, and its output is two 7-bit binary control words sel<6:0> and selb<6:0> that are inverted bit by bit. After the successive approximation is completed, sel<6:0> and selb<6:0> are sent to the trimming network.

[0072] The trimming network is used to trim the input offset voltage of the core operational amplifier according to the starting control word signal and output the trimmed input offset voltage.

[0073] Specifically, the trimming network includes a current source, an NMOS current mirror network, and a trimming polarity selection differential pair. The trimming polarity selection differential pair includes a first trimming polarity selection differential pair, a second trimming polarity selection differential pair, a third trimming polarity selection differential pair, a fourth trimming polarity selection differential pair, a fifth trimming polarity selection differential pair, a sixth trimming polarity selection differential pair, and a seventh trimming polarity selection differential pair. Among them, the input end of the current source is connected to the input end of the tail current source of the core operational amplifier, and the output end of the current source, the source ends of the first trimming polarity selection differential pair, the second trimming polarity selection differential pair, the third trimming polarity selection differential pair, the fourth trimming polarity selection differential pair, the fifth trimming polarity selection differential pair, the sixth trimming polarity selection differential pair, and the seventh trimming polarity selection differential pair are all connected to the drain ends of the NMOS current mirror network.

[0074] Among them, the trimming polarity selection differential pair is used to control the trimming polarity of the trimming network and control the NMOS current mirror network to output trimming currents with different weights. The trimming polarity is used to control the trimming direction of the input offset voltage of the core operational amplifier.

[0075] More specifically, the NMOS current mirror network includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14. The first trimming polarity selection differential pair includes a fifteenth NMOS transistor MN15 and a sixteenth NMOS transistor MN16. The second trimming polarity selection differential pair includes a seventeenth NMOS transistor MN17 and an eighteenth NMOS transistor MN18. The third trimming polarity selection differential pair includes a nineteenth NMOS transistor MN19 and a twentieth NMOS transistor MN20. The fourth trimming polarity selection differential pair includes a twenty-first NMOS transistor MN21 and a twenty-second NMOS transistor MN22. The fifth trimming polarity selection differential pair includes a twenty-third NMOS transistor MN23 and a twenty-fourth NMOS transistor MN24. The sixth trimming polarity selection differential pair includes a twenty-fifth NMOS transistor MN25 and a twenty-sixth NMOS transistor MN26. The seventh trimming polarity selection differential pair includes a twenty-seventh NMOS transistor MN27 and a twenty-eighth NMOS transistor MN28. Among them, the source of the fifteenth NMOS transistor, the source of the sixteenth NMOS transistor are connected to the drain of the eighth NMOS transistor. The source of the seventeenth NMOS transistor, the source of the eighteenth NMOS transistor are connected to the drain of the ninth NMOS transistor. The source of the nineteenth NMOS transistor, the source of the twentieth NMOS transistor are connected to the drain of the tenth NMOS transistor. The source of the twenty-first NMOS transistor, the source of the twenty-second NMOS transistor are connected to the drain of the eleventh NMOS transistor. The source of the twenty-third NMOS transistor, the source of the twenty-fourth NMOS transistor are connected to the drain of the twelfth NMOS transistor. The source of the twenty-fifth NMOS transistor, the source of the twenty-sixth NMOS transistor are connected to the drain of the thirteenth NMOS transistor. The source of the twenty-seventh NMOS transistor, the source of the twenty-eighth NMOS transistor are connected to the drain of the fourteenth NMOS transistor. The sources of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor and the fourteenth NMOS transistor are connected. The output terminal of the current source, the drain of the seventh NMOS transistor, the gates of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor and the fourteenth NMOS transistor are connected.

[0076] In this embodiment, the trimming network is composed of a current source I2, an NMOS current mirror network MN7 to MN14, and a trimming polarity selection differential pair MN15 to MN28; the trimming network receives two 7-bit control words sel<6:0> and selb<6:0> from the SAR logic, and then adjusts the input offset voltage of the core operational amplifier to achieve the trimming function; the current source I2 provides a bias current for the trimming network; the current mirror network generates seven trimming currents Itrim<6:0> with different weights; the trimming polarity selection differential pair determines the trimming direction of the input offset voltage; the sources of MN7 to MN14 are connected to VSS, and the gates are connected to the drain of MN7 and connected to the current source I2; the trimming polarity selection differential pair is composed of NMOS_L on the left and NMOS_R on the right. The sources of the two NMOSs are shorted and connected to the drain of the NMOS corresponding to their weights; the drain of NMOS_L is connected to the folding point N1, and the drain of NMOS_R is connected to the folding point N2; the gate of NMOS_L is connected to selb <n>, the gate terminal of NMOS_R is connected to sel <n>, where selb <n>It is sel <n>The non, N ranges from 6 to 0, representing the number of bits of the control word input to the trimming network.

[0077] In summary, the amplifier constructed in the embodiment of the present invention includes a voltage reference source, three two-way selection switches, a core operational amplifier, a low-pass filter, a comparator, a SAR logic, a trimming network, and a first resistor R1 and a second resistor R2; the voltage reference source generates the input common-mode voltage VCM of the operational amplifier, providing a suitable bias voltage for the automatic trimming process; the three two-way selection switches are composed of the first, second, and third two-way selection switches, where the first two-way selection switch controls the non-inverting input terminal of the core operational amplifier, the second two-way selection switch controls its inverting input terminal, and the third two-way selection switch controls its output terminal; the core operational amplifier determines the performance of the overall operational amplifier; the low-pass filter filters out noise; the comparator judges the polarity of the input offset voltage of the core operational amplifier; the SAR logic adjusts the control word according to the result of the comparator and performs successive approximation, ultimately achieving an ultra-low input offset voltage; the trimming network adjusts the input offset voltage of the core operational amplifier according to the control word; the resistors R1 and R2 amplify the input offset voltage of the core operational amplifier.

[0078] Please refer to Figure 2 , the embodiment of the present application also provides a trimming method for an ultra-low offset voltage trimming operational amplifier based on automatic trimming, which can implement the above-mentioned ultra-low offset voltage trimming operational amplifier based on automatic trimming. The method includes the following steps:

[0079] S100. Obtain the common-mode voltage, trimming enable signal, and trimming end signal, and configure the core operational amplifier as the trimming mode according to the trimming enable signal;

[0080] Specifically, the voltage reference source is composed of ten resistors R1 to R10 with a resistance value of R and a voltage buffer U1; the resistors R1 to R10 form a simple voltage division network to generate a reference voltage V ref ; the voltage buffer U1 realizes a buffering function to generate the input common-mode voltage V CM , to drive the subsequent circuit; from the above analysis, it can be calculated that in the trimming mode, the value of the input common-mode voltage V CM is:

[0081] V CM ≈V ref =(VDD + VSS) / 2

[0082] In the above formula, V CM represents the common-mode voltage, V ref represents the reference voltage, VDD represents the high-level signal, and VSS represents the low-level signal.

[0083] The first two-way selection switch consists of two CMOS switches: The CMOS switch composed of MP1 and MN1 is used to connect the input common-mode voltage VCM generated by the voltage reference source, corresponding to the trimming mode; at this time, the control signal EN = VDD and ENB = VSS. The CMOS switch composed of MP2 and MN2 is used to connect the external input port Vin+, corresponding to the working mode; at this time, the control signal EN = VSS and ENB = VDD. The control timings of the other two two-way selection switches are also the same. When EN = VDD, the second two-way selection switch is connected to the right end of the resistor R1, and the third two-way selection switch is connected to the input of the low-pass filter, corresponding to the trimming mode at this time. When EN = VSS, the second two-way selection switch is connected to the external input port Vin-, and the third two-way selection switch is connected to the external output port Vout, corresponding to the working mode at this time.

[0084] Therefore, the three two-way selection switches determine the connection method of the core operational amplifier, and thus determine the two different modes of the entire operational amplifier. The first mode is as Figure 4 shown. The three two-way selection switches respectively select two input terminals and one output terminal of the entire operational amplifier, corresponding to the working mode after trimming. After trimming, the entire operational amplifier has a total of five ports, namely the non-inverting input terminal Vin+, the inverting input terminal Vin-, the output terminal Vout, the positive power supply voltage input terminal VDD, and the negative power supply voltage input terminal VSS. The second mode is as Figure 5 shown. The three two-way selection switches are respectively connected to the voltage reference source, the resistor R1, and the low-pass filter, corresponding to the trimming mode. In the trimming mode, the non-inverting input terminal 510 of the core operational amplifier has nothing to do with the inverting input terminal 520 of the core operational amplifier and the inputs (Vin+, Vin-) of the entire operational amplifier.

[0085] S200: Amplify the input offset voltage of the core operational amplifier and output the amplified input offset voltage;

[0086] S300: Perform noise filtering on the amplified input offset voltage to obtain the filtered input offset voltage;

[0087] S400: Judge the filtered input offset voltage and the common-mode voltage and output the judgment result;

[0088] S500: Adjust the control word according to the judgment result and perform successive approximation, and output the starting control word signal;

[0089] S600: Trim the input offset voltage of the core operational amplifier according to the starting control word signal and output the trimmed input offset voltage;

[0090] Specifically, the trimming network consists of a current source I2, an NMOS current mirror network MN7 to MN14, and seven trimming polarity selection differential pairs MN15 to MN28;

[0091] The current source I2 provides a bias current for the trimming network, with a magnitude of Itrim_ref, which flows into the NMOS current mirror network.

[0092] The NMOS current mirror network generates seven trimming currents with different weights, consisting of MN7 to MN14; according to the weight magnitudes of the trimming currents, the multipliers of the eight NMOSs are set to 64, 64, 32, 16, 8, 4, 2, and 1 from left to right. Therefore, Itrim<6> = Itrim_ref, Itrim<5> = Itrim_ref / 2, Itrim<4> = Itrim_ref / 4, Itrim<3> = Itrim_ref / 8, Itrim<2> = Itrim_ref / 16, Itrim<1> = Itrim_ref / 32, and Itrim<0> = Itrim_ref / 64.

[0093] Therefore, the magnitude of the smallest trimming current unit △I is Itrim_ref / 64, which also determines that the magnitude of the smallest trimming voltage unit △V is approximately Itrim_ref / (64*gm), where gm is the transconductance of the PMOS differential input pair MP3 and MP4. The smallest trimming voltage unit △V determines the final trimming accuracy.

[0094] The trimming polarity selection differential pairs determine the trimming polarity. MN15 to MN28 form seven trimming polarity selection differential pairs, which respectively control the seven trimming currents Itrim<6:0>; when sel <n>When it is VDD, the trimming current Itrim <n>Mounted at the folding point N2, the current flowing through MP4 increases by Itrim <n>, the voltage vn is reduced by Itrim <n> / gm, at this time the input offset voltage Vos = vp - vn increases by Itrim <n> / gm; thus, sel <n>= An increase in the input offset voltage Vos corresponding to VDD, with a positive polarity. When sel <n>When it is VSS, the trimming current Itrim <n>Mounted at the folding point N1, the current flowing through the MP3 increases by Itrim <n>, the voltage vp is reduced by Itrim <n> / gm, at this time the input offset voltage Vos is reduced by Itrim <n> / gm; thus, sel <n>= VSS corresponds to a reduced input offset voltage Vos with a negative polarity.

[0095] To achieve an ultra-low input offset voltage, the present invention uses SAR logic to generate a trimming control word sel<6:0>, and then controls the trimming network to trim the input offset voltage of the core operational amplifier. The trimming control word sel<6:0> has seven bits, respectively controlling seven trimming polarity selection differential pairs. To briefly illustrate the working principle and process of SAR logic, Figure 7 Taking the three high-order bits of the trimming control word as an example, a schematic diagram of the SAR logic control process is shown.

[0096] As Figure 5 shown, sel<6:0> is first set to 7’b100_0000 and input to the trimming network; at this time, the trimming current Itrim_MP4 flowing through MP4 is Itrim<6> = Itrim_ref, and the trimming current Itrim_MP3 flowing through MP3 is (Itrim<5> + Itrim<4> + Itrim<3> + Itrim<2> + Itrim<1> + Itrim<0>) = 63*Itrim_ref / 64 ≈ Itrim_ref; therefore, the trimming currents flowing through MP4 and MP3 are basically the same, and the input offset voltage Vos at this time is approximately Vos_intrinsic, where Vos_intrinsic is the intrinsic input offset voltage of the core operational amplifier after removing the influence of the trimming network. The input offset voltage Vos is amplified by the external circuit composed of resistors R1 and R2 by (-R2 / R1) times, filtered by a low-pass filter, and then sent to the non-inverting input terminal of the inverter, denoted as Vin; finally, the SAR logic judges the result of the comparator.

[0097] If Vin > VCM, the output of the comparator is VDD, and the input of the SAR logic is at a high level. At this time, there is Vin ≈ VCM + Vos_intrinsic*(-R2 / R1)*K_LPF > VCM, where K_LPF is the DC gain of the low-pass filter. Simplifying the above formula gives: Vos_intrinsic < 0, indicating that the intrinsic input offset voltage is negative. To trim it to 0V, the trimming polarity of the trimming network should be positive, so sel<5> is set to VDD, that is, sel<6:0> is 7’b110_0000, and enter the next comparison.

[0098] If Vin < VCM, the output of the comparator is VSS and the input of the SAR logic is at a low level. Similar to the above analysis, it can be obtained that Vos_intrinsic > 0, indicating that the intrinsic input offset voltage is positive. To trim it to 0V, the trimming polarity of the trimming network should be negative. Therefore, sel<6> is set to VSS and sel<5> is set to VDD, that is, sel<6:0> is 7’b010_0000 (532), and the next comparison is entered.

[0099] S700. Configure the core operational amplifier into the working mode according to the trimming end signal to achieve trimming of the core operational amplifier.

[0100] Finally, in order to verify the function and accuracy of the on-chip automatic trimming technology proposed in the embodiments of the present invention, the input offset voltage of the operational amplifier is then subjected to Monte Carlo simulation on the cadence platform. As Figure 8 shown, without the automatic trimming circuit, the standard deviation of the input offset voltage of the operational amplifier is 241.6 uV. While with the automatic trimming circuit, the standard deviation of the input offset voltage of the operational amplifier is reduced to 11.97 uV, as Figure 9 shown. Therefore, the on-chip automatic trimming technology proposed in the embodiments of the present invention can significantly reduce the input offset voltage of the operational amplifier and is a technical means applicable to high-precision and low-offset operational amplifiers.

[0101] In summary, in combination with the operational amplifier of the present invention, the trimming method is described. Three two-way selection switches receive the trimming enable signal and configure the entire operational amplifier into the trimming mode. The first two-way selection switch is connected to the output of the voltage reference source, the second two-way selection switch is connected to the right end of the resistor R1, and the third two-way selection switch is connected to the input of the low-pass filter; after initialization, the SAR logic uses the Nbit starting control word sel <n-1:0>Input to the trimming network; the trimming network adjusts the input offset voltage of the core operational amplifier according to the control word; resistors R1 and R2 amplify the input offset voltage of the core operational amplifier, and after filtering by a low-pass filter, it is sent to the non-inverting input terminal of the comparator; the SAR logic adjusts the control word sel according to the output result of the comparator <n-1:0>The magnitude. If the SAR logic has traversed each control word, proceed to the next step; otherwise, return to the step of adjusting the input offset voltage of the core operational amplifier by the trimming network according to the control word; the three two-way selection switches receive the trimming end signal and configure the entire operational amplifier into the working mode. The first two-way selection switch is connected to the external input port Vin+, the second two-way selection switch is connected to the external input port Vin-, and the third two-way selection switch is connected to the external output port Vout.

[0102] Therefore, the on-chip automatic trimming technology of the embodiments of the present invention can automatically perform a trimming operation every time the operational amplifier is powered on. Through the SAR logic network, the input offset voltage of the operational amplifier can be reduced to the microvolt level, and errors introduced by additional factors such as physical stress and board-level mismatch are avoided. Compared with wafer-level trimming, the on-chip automatic trimming technology is performed on the chip. Since it is closer to the user end, the on-chip automatic trimming can achieve higher precision; compared with package-level trimming, the on-chip automatic trimming technology can be performed every time the operational amplifier is powered on, featuring repeatability and higher precision. In addition, the on-chip automatic trimming technology has the characteristic of automatic execution and does not require additional test pins and test benches.

[0103] It can be understood that the content in the above method embodiments is applicable to the system embodiments of the present invention. The functions specifically implemented by the system embodiments of the present invention are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0104] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of rights of the embodiments of the present application. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An ultra-low offset voltage trimming operational amplifier based on automatic trimming, characterized in that, The amplifier includes a voltage reference source, a first two-way selector switch, a second two-way selector switch, a third two-way selector switch, a core operational amplifier, a low-pass filter, a comparator, a SAR logic module, a trimming network, a first resistor, and a second resistor. The output terminal of the voltage reference source is connected to the input terminal of the first two-way selector switch. The output terminal of the first two-way selector switch is connected to the non-inverting input terminal of the core operational amplifier. The second terminal of the first resistor is respectively connected to the input terminal of the second two-way selector switch and the first terminal of the second resistor. The output terminal of the second two-way selector switch is connected to the inverting input terminal of the core operational amplifier. The output terminal of the core operational amplifier is connected to the input terminal of the third two-way selector switch. The second terminal of the second resistor and the output terminal of the third two-way selector switch are connected to the input terminal of the low-pass filter. The output terminal of the low-pass filter is connected to the positive input terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the SAR logic module. The output terminal of the SAR logic module is connected to the input terminal of the trimming network. The output terminal of the trimming network is connected to the control input terminal of the core operational amplifier, where: The voltage reference source is used to generate a common-mode voltage; The first two-way selector switch, the second two-way selector switch, and the third two-way selector switch are used to obtain a trimming enable signal and a trimming end signal, and configure the core operational amplifier into a trimming mode according to the trimming enable signal, and configure the core operational amplifier into a working mode according to the trimming end signal; The core operational amplifier has an input offset voltage; The first resistor and the second resistor are used to amplify the input offset voltage and output the amplified input offset voltage; The low-pass filter is used to perform noise filtering on the amplified input offset voltage to obtain a filtered input offset voltage; The comparator is used to judge the filtered input offset voltage and the common-mode voltage and output a judgment result; The SAR logic module is used to adjust the control word according to the judgment result and perform successive approximation, and output a starting control word signal; The trimming network is used to trim the input offset voltage of the core operational amplifier according to the starting control word signal and output a trimmed input offset voltage.

2. The amplifier according to claim 1, characterized in that, The voltage reference source includes a voltage dividing network and a voltage buffer. The voltage dividing network includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor. The first end of the first resistor and the second end of the tenth resistor are connected to the core operational amplifier. The second end of the first resistor is connected to the first end of the second resistor. The second end of the second resistor is connected to the first end of the third resistor. The second end of the third resistor is connected to the first end of the fourth resistor. The second end of the fourth resistor is connected to the first end of the fifth resistor. The second end of the fifth resistor, the first end of the sixth resistor, and the non-inverting input terminal of the voltage buffer are connected. The inverting input terminal of the voltage buffer is connected to the output terminal of the voltage buffer. The second end of the sixth resistor is connected to the first end of the seventh resistor. The second end of the seventh resistor is connected to the first end of the eighth resistor. The second end of the eighth resistor is connected to the first end of the ninth resistor. The second end of the ninth resistor is connected to the first end of the tenth resistor, where: The voltage dividing network is used to generate a reference voltage; The voltage buffer is used to buffer the reference voltage and output the common-mode voltage.

3. The amplifier according to claim 1, characterized in that, The expression of the common-mode voltage is specifically as follows: V CM ≈V ref =(VDD + VSS) / 2 In the above formula, V CM represents the common-mode voltage, V ref represents the reference voltage, VDD represents the high-level signal, and VSS represents the low-level signal.

4. The amplifier according to claim 1, wherein The first two-way selection switch, the second two-way selection switch, and the third two-way selection switch have the same two-way selection switch structure. The two-way selection switch structure includes a first CMOS switch tube and a second CMOS switch tube. The first CMOS switch tube includes a first PMOS transistor and a first NMOS transistor. The second CMOS switch tube includes a second PMOS transistor and a second NMOS transistor. Among them, the source electrode of the second PMOS transistor is connected to the drain electrode of the second NMOS transistor. The drain electrode of the second PMOS transistor, the source electrode of the second NMOS transistor, the drain electrode of the first PMOS transistor, and the source electrode of the first NMOS transistor are connected. The source electrode of the first PMOS transistor is connected to the drain electrode of the first NMOS transistor. The gate electrode of the first NMOS transistor and the gate electrode of the second PMOS transistor are both connected to a high-level signal. The gate electrode of the first PMOS transistor and the gate electrode of the second NMOS transistor are both connected to a low-level signal.

5. The amplifier according to claim 1, characterized in that, The core operational amplifier includes a PMOS input cascode transistor, a PMOS active current mirror, an NMOS current source, and a tail current source. The PMOS input cascode transistor includes a third PMOS transistor and a fourth PMOS transistor. The PMOS active current mirror includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The NMOS current source includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. Among them, the input terminal of the tail current source, the source electrode of the fifth PMOS transistor, and the source electrode of the sixth PMOS transistor are connected; the output terminal of the tail current source, the source electrode of the third PMOS transistor, and the source electrode of the fourth PMOS transistor are connected; the drain electrode of the third PMOS transistor, the drain electrode of the fourth NMOS transistor, and the source electrode of the sixth NMOS transistor are connected; the drain electrode of the fourth PMOS transistor, the source electrode of the fifth NMOS transistor, and the drain electrode of the third NMOS transistor are connected; the gate electrode of the third NMOS transistor and the gate electrode of the fourth NMOS transistor are connected; the source electrode of the third NMOS transistor and the source electrode of the fourth NMOS transistor are connected; the gate electrode of the fifth NMOS transistor and the gate electrode of the sixth NMOS transistor are connected; the drain electrode of the fifth NMOS transistor, the drain electrode of the seventh PMOS transistor, the gate electrode of the fifth PMOS transistor, and the gate electrode of the sixth PMOS transistor are connected; the drain electrode of the sixth NMOS transistor and the drain electrode of the eighth PMOS transistor are connected; the drain electrode of the sixth PMOS transistor and the source electrode of the eighth PMOS transistor are connected; the drain electrode of the fifth PMOS transistor and the source electrode of the seventh PMOS transistor are connected.

6. The amplifier according to claim 1, characterized in that The trimming network includes a current source, an NMOS current mirror network, and a trimming polarity selection differential pair. The trimming polarity selection differential pair includes a first trimming polarity selection differential pair, a second trimming polarity selection differential pair, a third trimming polarity selection differential pair, a fourth trimming polarity selection differential pair, a fifth trimming polarity selection differential pair, a sixth trimming polarity selection differential pair, and a seventh trimming polarity selection differential pair. Among them, the input terminal of the current source is connected to the input terminal of the tail current source of the core operational amplifier; the output terminal of the current source, the source terminal of the first trimming polarity selection differential pair, the source terminal of the second trimming polarity selection differential pair, the source terminal of the third trimming polarity selection differential pair, the source terminal of the fourth trimming polarity selection differential pair, the source terminal of the fifth trimming polarity selection differential pair, the source terminal of the sixth trimming polarity selection differential pair, and the source terminal of the seventh trimming polarity selection differential pair are all connected to the drain terminal of the NMOS current mirror network.

7. The amplifier according to claim 6, characterized in that, The trimming polarity selection differential pair is used to control the trimming polarity of the trimming network and control the trimming currents with different weights output by the NMOS current mirror network, and the trimming polarity is used to control the trimming direction of the input offset voltage of the core operational amplifier.

8. The amplifier according to claim 6, characterized in that, The NMOS current mirror network includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. The first trimming polarity selection differential pair includes a fifteenth NMOS transistor and a sixteenth NMOS transistor. The second trimming polarity selection differential pair includes a seventeenth NMOS transistor and an eighteenth NMOS transistor. The third trimming polarity selection differential pair includes a nineteenth NMOS transistor and a twentieth NMOS transistor. The fourth trimming polarity selection differential pair includes a twenty-first NMOS transistor and a twenty-second NMOS transistor. The fifth trimming polarity selection differential pair includes a twenty-third NMOS transistor and a twenty-fourth NMOS transistor. The sixth trimming polarity selection differential pair includes a twenty-fifth NMOS transistor and a twenty-sixth NMOS transistor. The seventh trimming polarity selection differential pair includes a twenty-seventh NMOS transistor and a twenty-eighth NMOS transistor. Among them, the source of the fifteenth NMOS transistor, the source of the sixteenth NMOS transistor are connected to the drain of the eighth NMOS transistor. The source of the seventeenth NMOS transistor, the source of the eighteenth NMOS transistor are connected to the drain of the ninth NMOS transistor. The source of the nineteenth NMOS transistor, the source of the twentieth NMOS transistor are connected to the drain of the tenth NMOS transistor. The source of the twenty-first NMOS transistor, the source of the twenty-second NMOS transistor are connected to the drain of the eleventh NMOS transistor. The source of the twenty-third NMOS transistor, the source of the twenty-fourth NMOS transistor are connected to the drain of the twelfth NMOS transistor. The source of the twenty-fifth NMOS transistor, the source of the twenty-sixth NMOS transistor are connected to the drain of the thirteenth NMOS transistor. The source of the twenty-seventh NMOS transistor, the source of the twenty-eighth NMOS transistor are connected to the drain of the fourteenth NMOS transistor. The sources of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, and the fourteenth NMOS transistor are connected. The output terminal of the current source, the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, the gate of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor are connected.

9. A trimming method for an operational amplifier with ultra-low offset voltage trimming based on automatic trimming, characterized in that, The method includes the following steps: Obtain a common-mode voltage, a trimming enable signal, and a trimming end signal, and configure the core operational amplifier into a trimming mode according to the trimming enable signal; Amplify the input offset voltage of the core operational amplifier and output the amplified input offset voltage; Perform noise filtering processing on the amplified input offset voltage to obtain a filtered input offset voltage; Judge the filtered input offset voltage and the common-mode voltage and output a judgment result; Adjust the control word according to the judgment result and perform successive approximation to output a starting control word signal; Perform trimming processing on the input offset voltage of the core operational amplifier according to the starting control word signal and output a trimmed input offset voltage; Configure the core operational amplifier into an operating mode according to the trimming end signal to achieve trimming of the core operational amplifier.

10. The method according to claim 9, characterized in that It further includes: If the filtered input offset voltage is greater than the common-mode voltage, the output of the comparator is a high-level signal, the input of the SAR logic module is a high-level signal, the trimming polarity of the trimming network is positive, and at this time, the input offset voltage of the core operational amplifier is increased; If the filtered input offset voltage is less than the common-mode voltage, the output of the comparator is a low-level signal, the input of the SAR logic module is a low-level signal, the trimming polarity of the trimming network is negative, and at this time, the input offset voltage of the core operational amplifier is decreased.

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