Error amplifier, voltage regulator, chip, device, error amplification method and medium

Abstract

The invention relates to an error amplifier, a voltage stabilizer, a chip, equipment, an error amplification method and a medium, the error amplifier comprises an operational amplifier module and a common-source amplifier module, the input end of the common-source amplifier is connected with the output end of the operational amplifier, and the operational amplifier module is used for receiving a feedback voltage signal and a reference voltage signal; the common source amplifier is used for receiving the feedback voltage signal and the reference voltage signal, carrying out differential amplification processing on the feedback voltage signal and the reference voltage signal and generating and outputting a first-stage differential amplification signal, and the common source amplifier is used for receiving the first-stage differential amplification signal, carrying out further amplification processing on the first-stage differential amplification signal and generating and outputting a second-stage differential amplification signal. Therefore, according to the error amplifier provided by the embodiment of the invention, the differential signal between the feedback voltage signal and the reference voltage signal is amplified stage by stage through the cooperation of the two stages of cascade amplification modules, so that the overall gain of the error amplifier is improved, the adjustment of the output voltage is more accurate, and the stability of a power supply is effectively improved.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to an error amplifier, a voltage regulator, a chip, a device, an error amplification method, and a medium. Background Art

[0002] The error amplifier is an indispensable key component in an electronic system, and plays a crucial role particularly in a voltage regulator such as a low dropout regulator (LDO). The main function of the error amplifier is to regulate the output voltage and ensure its stability. However, with the continuous improvement of the demand for power supply stability in modern electronic systems, the related technologies of the error amplifier urgently need to be improved to cope with new challenges. Summary of the Invention

[0003] This application provides an error amplifier, a voltage regulator, a chip, a device, an error amplification method, and a medium. The technical solution of this application is as follows:

[0004] An embodiment of the first aspect of this application provides an error amplifier, including:

[0005] An operational amplification module, configured to receive a feedback voltage signal and a reference voltage signal, and perform differential amplification processing on the feedback voltage signal and the reference voltage signal to generate and output a first-stage differential amplification signal;

[0006] A common-source amplification module, the input end of the common-source amplifier is connected to the output end of the operational amplifier, and the common-source amplifier is configured to receive the first-stage differential amplification signal and perform further amplification processing on the first-stage differential amplification signal to generate and output a second-stage differential amplification signal.

[0007] An embodiment of the second aspect of this application provides a voltage regulator, including: the error amplifier as described above.

[0008] An embodiment of the third aspect of this application provides a chip, including: the voltage regulator as described above.

[0009] An embodiment of the fourth aspect of this application provides an electronic device, including: the chip as described above.

[0010] An embodiment of the fifth aspect of this application provides an error amplification method, including:

[0011] Receiving a feedback voltage signal and a reference voltage signal, and performing differential amplification processing on the feedback voltage signal and the reference voltage signal to generate and output a first-stage differential amplification signal;

[0012] Receiving the first-stage differential amplification signal, and performing further amplification processing on the first-stage differential amplification signal to generate and output a second-stage differential amplification signal.

[0013] The sixth aspect embodiment of the present application provides a non - transitory computer - readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above - mentioned error amplification method is implemented.

[0014] The technical solutions provided by the embodiments of the present application at least bring the following beneficial effects:

[0015] The error amplifier of the embodiment of the present application includes an operational amplifier module and a common - source amplifier module. The input end of the common - source amplifier is connected to the output end of the operational amplifier. The operational amplifier module is used to receive a feedback voltage signal and a reference voltage signal, perform differential amplification processing on the feedback voltage signal and the reference voltage signal, generate and output a first - stage differential amplification signal. The common - source amplifier is used to receive the first - stage differential amplification signal and perform further amplification processing on the first - stage differential amplification signal, generate and output a second - stage differential amplification signal. Thus, through the coordinated cooperation of two - stage cascaded amplification modules, the error amplifier of the embodiment of the present application gradually amplifies the differential signal between the feedback voltage signal and the reference voltage signal, thereby improving the overall gain of the error amplifier, making the regulation of the output voltage more accurate, and effectively improving the power supply stability.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application, and do not constitute an improper limitation to the present application.

[0018] Figure 1 is a block diagram of an error amplifier according to an embodiment of the present application;

[0019] Figure 2 is a block diagram of an error amplifier according to another embodiment of the present application;

[0020] Figure 3 is a circuit diagram of an error amplifier according to an embodiment of the present application;

[0021] Figure 4 is a circuit diagram of a voltage regulator according to an embodiment of the present application;

[0022] Figure 5 is a flowchart of an error amplification method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To enable those of ordinary skill in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0024] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are only examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0025] The error amplifier, voltage regulator, chip, device, error amplification method, and medium of the embodiments of this application will be described below with reference to the accompanying drawings.

[0026] Figure 1 is a schematic diagram of an error amplifier according to an embodiment of this application.

[0027] As Figure 1 shown, the error amplifier 100 of the embodiment of this application includes: an operational amplifier module 110 and a common-source amplifier module 120.

[0028] Among them, the operational amplifier module 110 is used to receive a feedback voltage signal Vfb and a reference voltage signal Vref, and perform differential amplification processing on the feedback voltage signal Vfb and the reference voltage signal Vref to generate and output a first-stage differential amplification signal. For example, when the operational amplifier module 110 is a symmetric transconductance operational amplifier, the first-stage differential amplification signal output by the operational amplifier module 110 is a current signal proportional to the differential signal (the differential signal is a signal obtained by subtracting the feedback voltage signal Vfb from the reference voltage signal Vref), and this current signal is used as a driving signal and output to the subsequent common-source amplifier module 120 for further amplification processing.

[0029] The input end of the common-source amplifier module 120 is connected to the output end of the operational amplifier module 110, and is used to receive the first-stage differential amplification signal and perform further amplification processing on the first-stage differential amplification signal to generate and output a second-stage differential amplification signal Verr. The common-source amplifier module 120 significantly improves the overall performance of the error amplifier 100 by enhancing the gain, ensuring that the output signal has sufficient amplitude to meet the requirements of the subsequent circuit.

[0030] Thus, the error amplifier 100 according to the embodiments of the present application realizes the step-by-step amplification of the differential signal between the feedback voltage signal and the reference voltage signal through the collaborative cooperation of two-stage cascaded amplification modules (operational amplification module 110 and common-source amplification module 120), thereby improving the overall gain of the error amplifier 100, making the regulation of the output voltage more accurate, and effectively enhancing the power supply stability.

[0031] In order to buffer the second-stage differential amplification signal Verr output by the common-source amplification module 120, a source follower module 130 is connected to the subsequent stage of the common-source amplification module 120 in the present application. The following are the specific functions and working principles of the source follower module 130:

[0032] As Figure 2 shown, the input end of the source follower module 130 is connected to the output end of the common-source amplification module 120, and is used to receive the second-stage differential amplification signal Verr and buffer the second-stage differential amplification signal Verr to generate and output the buffered second-stage differential amplification signal Verr'.

[0033] By buffering the second-stage differential amplification signal Verr, the source follower module 130 effectively reduces the output impedance and improves the driving ability, so that the buffered second-stage differential amplification signal Verr' can be more stable and better adapt to the requirements of the subsequent stage circuit.

[0034] The buffered second-stage differential amplification signal Verr' output by the source follower module 130 can be directly used to drive the control end (i.e., the gate) of the subsequent-stage MOS transistor. Due to the buffering effect of the source follower module 130, the buffered second-stage differential amplification signal Verr has a lower output impedance and higher stability, thus ensuring that the subsequent-stage MOS transistor can work normally under high-load conditions.

[0035] To enable those skilled in the art to more clearly understand the error amplifier 100 according to the embodiments of the present application, the error amplifier 100 according to the embodiments of the present application will be introduced below in conjunction with Figure 3 For the error amplifier 100 according to the embodiments of the present application.

[0036] It should be noted that the operational amplification module 110 according to the embodiments of the present application can be a symmetric transconductance operational amplifier 110, Figure 3 and the operational amplification module 110 in

[0037] As Figure 3As shown, the symmetric transconductance operational amplifier 110 includes: a first transistor Mp1, a second transistor Mp2, a third transistor Mp3, a fourth transistor Mp4, a fifth transistor Mp5, a sixth transistor Mn1, a seventh transistor Mn2, an eighth transistor Mn3, and a ninth transistor Mn4. Among them, the first transistor Mp1, the second transistor Mp2, the third transistor Mp3, the fourth transistor Mp4, and the fifth transistor Mp5 can be one of P-type MOS transistors or N-type MOS transistors, and the sixth transistor Mn1, the seventh transistor Mn2, the eighth transistor Mn3, and the ninth transistor Mn4 are the other of P-type MOS transistors or N-type MOS transistors.

[0038] For ease of explanation, Figure 3 Taking the first transistor Mp1, the second transistor Mp2, the third transistor Mp3, the fourth transistor Mp4, and the fifth transistor Mp5 all being P-type MOS transistors, and the sixth transistor Mn1, the seventh transistor Mn2, the eighth transistor Mn3, and the ninth transistor Mn4 all being N-type MOS transistors as an example for illustration.

[0039] Among them, the control terminal of the first transistor Mp1 serves as the first input terminal of the symmetric transconductance operational amplifier 110 and is used to receive the feedback voltage signal Vfb;

[0040] The control terminal of the second transistor Mp2 serves as the second input terminal of the symmetric transconductance operational amplifier 110 and is used to receive the reference voltage signal Vref;

[0041] The first ends of the third transistor Mp3, the fourth transistor Mp4, and the fifth transistor Mp5 are all connected to the positive power supply VDD;

[0042] The first ends of the sixth transistor Mn1, the seventh transistor Mn2, the eighth transistor Mn3, and the ninth transistor Mn4 are all connected to the negative power supply VSS or the ground terminal;

[0043] The second end of the fifth transistor Mp5, the first end of the first transistor Mp1, and the first end of the second transistor Mp2 are connected;

[0044] The second end of the third transistor Mp3, the control terminal of the third transistor Mp3, the control terminal of the fourth transistor Mp4, and the second end of the eighth transistor Mn3 are connected;

[0045] The control terminal of the sixth transistor Mn1, the second end of the sixth transistor Mn1, the control terminal of the eighth transistor Mn3, and the second end of the first transistor Mp1 are connected;

[0046] The control terminal of the seventh transistor Mn2, the second end of the seventh transistor Mn2, the control terminal of the ninth transistor Mn4, and the second end of the second transistor Mp2 are connected;

[0047] The first node J1 formed after connecting the second ends of the fourth transistor Mp4 and the ninth transistor Mn4 serves as the output end of the symmetric transconductance operational amplifier 110 and is used to output the first-stage differential amplification signal.

[0048] As Figure 3 shown, the common-source amplification module 120 of the embodiment of the present application includes: a tenth transistor Mn5 and an eleventh transistor Mp6. Among them, the tenth transistor Mn5 can be one of a P-type MOS transistor or an N-type MOS transistor, and the eleventh transistor Mp6 is the other of a P-type MOS transistor or an N-type MOS transistor.

[0049] For ease of description, Figure 3 taking the tenth transistor Mn5 as an N-type MOS transistor and the eleventh transistor Mp6 as a P-type MOS transistor as an example for illustration.

[0050] Among them, the control end of the tenth transistor Mn5 serves as the input end of the common-source amplification module 120 and is used to receive the first-stage differential amplification signal;

[0051] The first end of the tenth transistor Mn5 is connected to the negative power supply VSS or the ground terminal, and the first end of the eleventh transistor Mp6 is connected to the positive power supply VDD;

[0052] The second node J2 formed after connecting the second ends of the tenth transistor Mn5 and the eleventh transistor Mp6 serves as the output end of the common-source amplification module 120 and is used to output the second-stage differential amplification signal Verr.

[0053] As Figure 3 shown, the source follower module 130 of the embodiment of the present application includes: a twelfth transistor Mp7 and a thirteenth transistor Mp8. Among them, the twelfth transistor Mp7 and the thirteenth transistor Mp8 can be one of a P-type MOS transistor or an N-type MOS transistor.

[0054] For ease of description, Figure 3 taking the twelfth transistor Mp7 and the thirteenth transistor Mp8 as P-type MOS transistors as an example for illustration.

[0055] Among them, the control end of the thirteenth transistor Mp8 serves as the input end of the source follower module 130 and is used to receive the second-stage differential amplification signal Verr;

[0056] The first end of the twelfth transistor Mp7 is connected to the positive power supply VDD;

[0057] The third node J3 formed after connecting the second terminal of the twelfth transistor Mp7 to the first terminal of the thirteenth transistor Mp8 serves as the output terminal of the source follower module 130 and is used to output the buffered second-stage differential amplified signal Verr'.

[0058] The second terminal of the thirteenth transistor Mp8 is connected to the negative power supply VSS or the ground terminal.

[0059] As Figure 3 shown, the first terminals of the first transistor Mp1, the second transistor Mp2, the third transistor Mp3, the fourth transistor Mp4, the fifth transistor Mp5, the sixth transistor Mn1, the seventh transistor Mn2, the eighth transistor Mn3, the ninth transistor Mn4, the tenth transistor Mn5, the eleventh transistor Mp6, the twelfth transistor Mp7, and the thirteenth transistor Mp8 are source electrodes;

[0060] The second terminals of the first transistor Mp1, the second transistor Mp2, the third transistor Mp3, the fourth transistor Mp4, the fifth transistor Mp5, the sixth transistor Mn1, the seventh transistor Mn2, the eighth transistor Mn3, the ninth transistor Mn4, the tenth transistor Mn5, the eleventh transistor Mp6, the twelfth transistor Mp7, and the thirteenth transistor Mp8 are drain electrodes;

[0061] The control terminals of the first transistor Mp1, the second transistor Mp2, the third transistor Mp3, the fourth transistor Mp4, the fifth transistor Mp5, the sixth transistor Mn1, the seventh transistor Mn2, the eighth transistor Mn3, the ninth transistor Mn4, the tenth transistor Mn5, the eleventh transistor Mp6, the twelfth transistor Mp7, and the thirteenth transistor Mp8 are gate electrodes.

[0062] The error amplifier 100 according to the embodiment of the present application can improve the overall gain of the error amplifier 100 by adding a common-source amplification module 120 composed of a tenth transistor Mn5 and an eleventh transistor Mp6, making the regulation of the output voltage more accurate. In this way, when the error amplifier 100 according to the embodiment of the present application is applied to a voltage regulator, if the voltage regulator outputs a large current, the gate voltages of the adjustment element (such as a PMOS transistor) and the thirteenth transistor Mp8 in the voltage regulator will both become low. In this case, even if the tenth transistor Mn5 enters the linear region, the gate voltage of the tenth transistor Mn5 (i.e., the drain voltage of the ninth transistor Mn4) will not decrease, thereby ensuring that the state of the operational amplification module 110 will not be affected. This can ensure that the error amplifier 100 will not have large changes in gain, bandwidth, etc. due to the increase in the output current of the adjustment element, thereby ensuring the stability of the output voltage of the entire voltage regulator.

[0063] In summary, the error amplifier according to the embodiment of the present application includes an operational amplification module and a common-source amplification module. The input end of the common-source amplifier is connected to the output end of the operational amplifier. The operational amplification module is used to receive a feedback voltage signal and a reference voltage signal, perform differential amplification processing on the feedback voltage signal and the reference voltage signal, generate and output a first-stage differential amplification signal. The common-source amplifier is used to receive the first-stage differential amplification signal and perform further amplification processing on the first-stage differential amplification signal, generate and output a second-stage differential amplification signal. Thus, the error amplifier according to the embodiment of the present application cooperatively matches through two cascaded amplification modules, gradually amplifies the differential signal between the feedback voltage signal and the reference voltage signal, thereby improving the overall gain of the error amplifier, making the regulation of the output voltage more accurate, and effectively improving the power supply stability.

[0064] To implement the above embodiment, the embodiment of the present application also proposes a voltage regulator.

[0065] It should be noted that the voltage regulator according to the embodiment of the present application can be a low-dropout linear regulator LDO.

[0066] As Figure 3 shown, the voltage regulator 1000 according to the embodiment of the present application includes: an error amplifier 100.

[0067] It should be noted that the voltage regulator 1000 according to the embodiment of the present application can be a low-dropout linear regulator.

[0068] As Figure 3 shown, the voltage regulator 1000 further includes: an adjustment element Mpass ( Figure 3 in which the adjustment element Mpass takes a PMOS transistor as an example) and a feedback network 200.

[0069] Among them, the control end of the adjustment element Mpass is connected to the output end of the source follower module 130 in the error amplifier 100;

[0070] The first end of the adjustment element Mpass is connected to the positive power supply VDD;

[0071] The fourth node J4 formed after the second end of the adjustment element Mpass is connected to the first end of the feedback network 200 serves as the voltage output end Vout of the voltage regulator 1000;

[0072] The second end of the feedback network 200 is connected to the first input end of the operational amplifier module 110 in the error amplifier 100;

[0073] The third end of the feedback network 200 is connected to the negative power supply VSS or the ground terminal.

[0074] In this embodiment, the error amplifier 100 is used to detect the deviation between the feedback voltage signal Vfb and the reference voltage signal Vref, generate and output a buffered second-stage differential amplification signal Verr'. The adjustment element Mpass adjusts its on-off state according to the output buffered second-stage differential amplification signal Verr', thereby controlling the magnitude of the output voltage Vout. The feedback network 200 divides a part of the output voltage Vout of the voltage regulator 1000 and sends it back to the error amplifier 100 to form a closed-loop control system.

[0075] As Figure 3 shown, the voltage regulator 1000 further includes: a capacitor C.

[0076] Among them, the first end of the capacitor C is connected to the fourth node J4, and the second end of the capacitor C is connected to the second end of the second transistor Mp2 in the operational amplifier module 110 of the error amplifier 100. This capacitor C is used to stabilize the output voltage Vout and improve the transient response performance.

[0077] As Figure 3 shown, the feedback network 200 includes: a first resistor R1 and a second resistor R2.

[0078] Among them, the first end of the first resistor R1 serves as the first end of the feedback network 200;

[0079] The fifth node J5 formed after the second end of the first resistor R1 is connected to the first end of the second resistor R2 serves as the second end of the feedback network 200 for outputting the feedback voltage signal Vfb;

[0080] The second end of the second resistor R2 serves as the third end of the feedback network 200.

[0081] Generally, in a voltage regulator system, the ability to adjust the gate voltage of the adjustment element Mpass (such as a PMOS transistor) directly affects the output current. To achieve a high output current, the gate voltage of the adjustment element Mpass needs to be set low enough. In this application, by optimizing the design of the error amplifier 100, it is possible to ensure that the swing of the difference signal between the feedback voltage signal and the reference voltage signal is large enough, so as to effectively drive the gate of the adjustment element Mpass and make it operate in a suitable conduction state.

[0082] The voltage regulator 1000 according to the embodiment of this application can be applied to application scenarios with high output current. In addition, even when the load current increases significantly, the error amplifier 100 can still provide a stable error signal to ensure that the output voltage of the voltage regulator system remains stable.

[0083] In summary, for the voltage regulator according to the embodiment of this application, by using the above error amplifier, since the error amplifier amplifies the differential signal between the feedback voltage signal and the reference voltage signal step by step through the coordinated cooperation of two cascaded amplification modules, the overall gain of the error amplifier is improved, so that the voltage regulation output by the voltage regulator is more accurate, effectively improving the stability of the output voltage of the voltage regulator.

[0084] Based on the above embodiment, this application also proposes a chip, which includes the above voltage regulator.

[0085] In the embodiment of this application, the chip can be a dedicated power management chip.

[0086] Based on the above embodiment, this application also proposes an electronic device, which includes the above chip.

[0087] In the embodiment of this application, the electronic device can be a vehicle, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0088] Figure 5 It is a flowchart of an error amplification method according to an embodiment of this application.

[0089] As Figure 5 shown, the error amplification method according to the embodiment of this application includes:

[0090] S1, receiving a feedback voltage signal and a reference voltage signal, and performing differential amplification processing on the feedback voltage signal and the reference voltage signal to generate and output a first-stage differential amplification signal.

[0091] S2, receiving the first-stage differential amplification signal, and performing further amplification processing on the first-stage differential amplification signal to generate and output a second-stage differential amplification signal.

[0092] In one embodiment of the present application, the above method further includes:

[0093] Receiving a second-stage differential amplification signal, buffering the second-stage differential amplification signal, and generating and outputting the buffered second-stage differential amplification signal.

[0094] It should be noted that for the details not disclosed in the error amplification method of the embodiments of the present application, please refer to the details disclosed in the error amplifier of the embodiments of the present application, which will not be elaborated here specifically.

[0095] According to the error amplification method of the embodiments of the present application, after receiving the feedback voltage signal and the reference voltage signal, the feedback voltage signal and the reference voltage signal are subjected to differential amplification processing to generate and output a first-stage differential amplification signal, and after receiving the first-stage differential amplification signal, the first-stage differential amplification signal is further amplified to generate and output a second-stage differential amplification signal. Thus, the present application gradually amplifies the differential signal between the feedback voltage signal and the reference voltage signal, which can improve the overall gain of the error amplifier, make the adjustment of the output voltage more accurate, and effectively improve the power supply stability.

[0096] To implement the above embodiments, the present application also proposes a non-transitory computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above error amplification method is implemented.

[0097] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0098] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0099] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process. The scope of the preferred embodiments of the present application includes additional implementations, where functions may be executed in a manner that is not shown or discussed, including in a substantially simultaneous manner according to the involved functions or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0100] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with such instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (Random Access Memory, abbreviated as RAM), a read-only memory (Read-Only Memory, abbreviated as ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (Compact Disc Read-Only Memory, abbreviated as CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then storing it in a computer memory.

[0101] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), and the like.

[0102] Those of ordinary skill in the art can understand that all or part of the steps carried by the method of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0103] In addition, in each embodiment of the present application, each functional unit can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0104] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

[0105] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only to be regarded as exemplary, and the true scope and spirit of the present application are pointed out by the appended claims.

[0106] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An error amplifier, characterized in that, Comprising: An operational amplifier module, configured to receive a feedback voltage signal and a reference voltage signal, and perform differential amplification processing on the feedback voltage signal and the reference voltage signal to generate and output a first-stage differential amplification signal; A common-source amplifier module, wherein an input end of the common-source amplifier is connected to an output end of the operational amplifier, and the common-source amplifier is configured to receive the first-stage differential amplification signal and perform further amplification processing on the first-stage differential amplification signal to generate and output a second-stage differential amplification signal.

2. The error amplifier according to claim 1, wherein The error amplifier further comprises: A source follower module, wherein an input end of the source follower module is connected to an output end of the common-source amplifier module, and the source follower module is configured to receive the second-stage differential amplification signal and perform buffering processing on the second-stage differential amplification signal to generate and output a buffered second-stage differential amplification signal.

3. The error amplifier according to claim 1, wherein In response to the operational amplifier module being a symmetric transconductance operational amplifier, the first-stage differential amplification signal is a current signal proportional to a difference between the feedback voltage signal and the reference voltage signal; The symmetric transconductance operational amplifier comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; wherein, A control end of the first transistor serves as a first input end of the symmetric transconductance operational amplifier and is configured to receive the feedback voltage signal; A control end of the second transistor serves as a second input end of the symmetric transconductance operational amplifier and is configured to receive the reference voltage signal; A first end of the third transistor, a first end of the fourth transistor, and a first end of the fifth transistor are all connected to a positive power supply terminal; A first end of the sixth transistor, a first end of the seventh transistor, a first end of the eighth transistor, and a first end of the ninth transistor are all connected to a negative power supply terminal or a ground terminal; A first end of the first transistor, a first end of the second transistor, and a second end of the fifth transistor are connected; A second end of the third transistor, a control end of the third transistor, a control end of the fourth transistor, and a second end of the eighth transistor are connected; A control end of the sixth transistor, a second end of the sixth transistor, a control end of the eighth transistor, and a second end of the first transistor are connected; A control end of the seventh transistor, a second end of the seventh transistor, a control end of the ninth transistor, and a second end of the second transistor are connected; A first node formed after a second end of the fourth transistor and a second end of the ninth transistor are connected serves as an output end of the symmetric transconductance operational amplifier and is configured to output the first-stage differential amplification signal.

4. The error amplifier according to claim 1, wherein The common-source amplifier module comprises: a tenth transistor and an eleventh transistor; wherein, A control end of the tenth transistor serves as an input end of the common-source amplifier module and is configured to receive the first-stage differential amplification signal; A first end of the tenth transistor is connected to a negative power supply terminal or a ground terminal, and a first end of the eleventh transistor is connected to a positive power supply terminal; The second terminal of the eleventh transistor is connected to the second terminal of the tenth transistor to form a second node, which serves as the output terminal of the common-source amplification module for outputting the second-stage differential amplification signal.

5. The error amplifier according to claim 2, characterized in that, The source follower module includes: a twelfth transistor and a thirteenth transistor; wherein, The control terminal of the thirteenth transistor serves as the input terminal of the source follower module for receiving the second-stage differential amplification signal; The first terminal of the twelfth transistor is connected to the positive power supply; The second terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor to form a third node, which serves as the output terminal of the source follower module for outputting the buffered second-stage differential amplification signal; The second terminal of the thirteenth transistor is connected to the negative power supply or the ground terminal.

6. The error amplifier according to any one of claims 3-5, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor are one of P-type MOS transistors or N-type MOS transistors, and the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are the other of P-type MOS transistors or N-type MOS transistors.

7. A voltage regulator, characterized in that, It includes the error amplifier according to any one of claims 1-6.

8. The voltage regulator according to claim 7, characterized in that, The voltage regulator further includes: an adjustment element and a feedback network; wherein, The control terminal of the adjustment element is connected to the output terminal of the source follower module in the error amplifier; The first terminal of the adjustment element is connected to the positive power supply; The fourth node formed by connecting the second terminal of the adjustment element and the first terminal of the feedback network serves as the voltage output terminal of the voltage regulator for outputting a DC voltage to the load; The second terminal of the feedback network is connected to the first input terminal of the operational amplification module in the error amplifier; The third terminal of the feedback network is connected to the negative power supply or the ground terminal.

9. The voltage regulator according to claim 8, wherein, The voltage regulator further includes: A capacitor, the first terminal of the capacitor is connected to the fourth node, and the second terminal of the capacitor is connected to the second terminal of the second transistor in the operational amplification module of the error amplifier.

10. The voltage regulator according to claim 8 or 9, characterized in that, The feedback network includes: a first resistor and a second resistor; wherein, The first terminal of the first resistor serves as the first terminal of the feedback network; The fifth node formed by connecting the second terminal of the first resistor and the first terminal of the second resistor serves as the second terminal of the feedback network for outputting a feedback voltage signal; The second terminal of the second resistor serves as the third terminal of the feedback network.

11. A chip, characterized in that, It includes: The voltage regulator according to any one of claims 7-10.

12. An electronic device, characterized in that, It includes: The chip according to claim 11.

13. An error amplification method, characterized in that, It includes: Receiving a feedback voltage signal and a reference voltage signal, performing differential amplification processing on the feedback voltage signal and the reference voltage signal, and generating and outputting a first-stage differential amplification signal; Receiving the first-stage differential amplification signal, performing further amplification processing on the first-stage differential amplification signal, and generating and outputting a second-stage differential amplification signal.

14. The method according to claim 13, wherein The method further includes: Receiving the second-stage differential amplification signal, performing buffer processing on the second-stage differential amplification signal, and generating and outputting the buffered second-stage differential amplification signal.

15. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by a processor, they implement the error amplification method according to claim 13 or 14.

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