Four-phase ring voltage-controlled oscillator circuit and calibration method thereof

Abstract

The invention discloses a four-phase ring voltage-controlled oscillator circuit and a calibration method thereof. The circuit comprises a voltage-current conversion module, a current mirror module, an automatic frequency control module and a secondary ring oscillator module. The method comprises the following steps: acquiring an output frequency of a secondary ring oscillator module, and comparing the output frequency with a preset reference frequency to obtain a frequency comparison result; acquiring a numerical control signal generated by an automatic frequency control module based on a preset reference frequency; according to a frequency comparison result, performing logic control on the numerical control signal to generate a control tail current source signal; and the output frequency of the secondary ring oscillator module is calibrated according to the control tail current source signal, and a four-phase differential clock oscillation signal is output. According to the embodiment of the invention, the anti-noise performance and the output precision of the whole phase-locked loop can be improved, the power consumption and the area of circuit design are reduced, and the tolerance of process deviation in different PVT scenes is improved. The circuit can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a four-phase ring voltage-controlled oscillator circuit and its calibration method. Background Art

[0002] For realizing high-bandwidth and low-latency data transmission, the locking time of a phase-locked loop (PLL) determines whether the signal can be quickly synchronized, and it also faces challenges in process variation adaptability and jitter performance. The PLL can complete signal modulation and demodulation, clock recovery, and generate a local oscillator signal for carrier recovery of mixers and wireless receivers. The oscillator structure is an indispensable module for the PLL to generate clock signals. A ring oscillator is an oscillating circuit based on a loop structure, which is mainly formed by connecting several inverters (or other delay units) end to end to form a loop. Due to its simplicity and effectiveness, this structure is widely used in integrated circuits, especially suitable for the voltage-controlled oscillator (VCO) in the PLL. In a high-speed serial interface circuit, for the clock generation circuit, it is particularly important to be able to directly generate stable and high-performance four-phase clocks. Therefore, more stringent requirements are also put forward for the performance of the PLL such as noise, power consumption, and jitter.

[0003] For a phase-locked loop (PLL) adopting an LC_VCO architecture, it can provide an extremely high output frequency. However, in the practical application of CMOS technology, the implementation of the LC_VCO faces problems of high cost and insufficient energy efficiency. The oscillation frequency and power consumption performance of a CMOS ring oscillator (RO) have been significantly improved, but the RO also faces problems such as high jitter, weak anti-interference ability, and sensitivity to process variations.

[0004] In summary, the technical problems existing in the related art need to be improved. Summary of the Invention

[0005] The main purpose of the embodiments of this application is to propose a four-phase ring voltage-controlled oscillator circuit and its calibration method, which can improve the anti-noise performance and output accuracy of the overall phase-locked loop, reduce the power consumption and area of the circuit design, and improve the tolerance of process deviations in different PVT scenarios.

[0006] To achieve the above object, on the one hand, an embodiment of this application proposes a four-phase ring voltage-controlled oscillator circuit, which includes a voltage-current conversion module, a current mirror module, an automatic frequency control module, and a secondary ring oscillator module. The output end of the voltage-current conversion module is connected to the first input end of the current mirror module, the output end of the automatic frequency control module is connected to the second input end of the current mirror module, and the output end of the current mirror module is connected to the input end of the secondary ring oscillator module, where:

[0007] The voltage-current conversion module is used to generate a bias current;

[0008] The current mirror module is used to amplify the bias current to obtain an amplified bias current;

[0009] The automatic frequency control module is used to generate a numerically controlled signal and control the switch of the current mirror module;

[0010] The second-order ring oscillator module is used to perform frequency control according to the amplified bias current and output a four-phase differential clock oscillation signal.

[0011] In some embodiments, the voltage-current conversion module includes a first rail-to-rail operational amplifier, a first PMOS transistor, a first NMOS transistor, and a seventh NMOS transistor. Among them, the negative input terminal of the first rail-to-rail operational amplifier is connected to a control voltage input signal, the drain of the first PMOS transistor is connected to a high level, the positive input terminal of the first rail-to-rail operational amplifier, the source of the first PMOS transistor, the drain of the first NMOS transistor, and the gate of the seventh NMOS transistor are connected, the output terminal of the first rail-to-rail operational amplifier is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor is connected to the current mirror module, the source of the first NMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is connected to the current mirror module.

[0012] In some embodiments, the current mirror module includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. Among them, the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor. The drains of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected and output the amplified bias current. The gates of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are respectively connected to the automatic frequency control module. The gates of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are all connected to the gate of the seventh NMOS transistor. The sources of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are connected and grounded. The source of the second NMOS transistor is connected to the drain of the eighth NMOS transistor. The source of the third NMOS transistor is connected to the drain of the ninth NMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the tenth NMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the eleventh NMOS transistor. The source of the sixth NMOS transistor is connected to the drain of the twelfth NMOS transistor.

[0013] In some embodiments, the digital control signals generated by the automatic frequency control module include a first digital control signal, a second digital control signal, a third digital control signal, and a fourth digital control signal. The first digital control signal is connected to the gate of the third NMOS transistor. The second digital control signal is connected to the gate of the fourth NMOS transistor. The third digital control signal is connected to the gate of the fifth NMOS transistor. The fourth digital control signal is connected to the gate of the sixth NMOS transistor.

[0014] In some embodiments, the second-order ring oscillator module includes a first delay unit and a second delay unit. The negative input terminal of the first delay unit is connected to the negative output terminal of the second delay unit. The positive input terminal of the first delay unit is connected to the positive output terminal of the second delay unit. The negative output terminal of the first delay unit is connected to the positive input terminal of the second delay unit. The positive output terminal of the first delay unit is connected to the negative input terminal of the second delay unit. The ground terminals of the first delay unit and the second delay unit are both connected to the amplified bias current.

[0015] In some embodiments, the second delay unit includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The input terminal of the first inverter serves as the positive input terminal of the second delay unit, and the input terminal of the second inverter serves as the negative input terminal of the second delay unit. The output terminal of the first inverter, the output terminal of the third inverter, and the input terminal of the fourth inverter are connected and serve as the negative output terminal of the second delay unit. The output terminal of the second inverter, the input terminal of the third inverter, and the output terminal of the fourth inverter are connected and serve as the positive output terminal of the second delay unit.

[0016] In some embodiments, the first inverter and the second inverter form the oscillation circuit of the second-order ring oscillator module, and the third inverter and the fourth inverter serve as the phase compensation circuit of the second-order ring oscillator module.

[0017] In some embodiments, the fourth inverter includes a second PMOS transistor, a third PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. Among them, the gates of the second PMOS transistor, the third PMOS transistor, the thirteenth NMOS transistor, and the fourteenth NMOS transistor are connected and serve as the input terminal of the fourth inverter. The drain of the second PMOS transistor is connected to a high level. The source of the second PMOS transistor is connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the drain of the thirteenth NMOS transistor and serves as the output terminal of the fourth inverter. The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is grounded.

[0018] To achieve the above object, on the other hand, an embodiment of the present application proposes a calibration method for a four-phase ring voltage-controlled oscillator circuit. The method includes the following steps:

[0019] Obtain the output frequency of the second-order ring oscillator module, and compare it with a preset reference frequency to obtain a frequency comparison result;

[0020] Based on the preset reference frequency, obtain the digital control signal generated by the automatic frequency control module;

[0021] According to the frequency comparison result, perform logic control on the digital control signal to generate a control tail current source signal;

[0022] Calibrate the output frequency of the second-order ring oscillator module according to the control tail current source signal, and output a four-phase differential clock oscillation signal.

[0023] In some embodiments, the expression of the control tail current source signal is specifically as follows:

[0024]

[0025] In the above formula, I vco represents the control tail current source signal, I ctrl represents the control current input signal, i represents the branch number, SW represents a numerical control signal, and m represents the amplification factor.

[0026] The embodiments of the present application at least include the following beneficial effects: The present application provides a four-phase ring voltage-controlled oscillator circuit and its calibration method. This solution uses a current mirror as the current control stage of the oscillator to monitor the output current of the oscillator. Further, by obtaining the output frequency of the secondary ring oscillator module, comparing it with a preset reference frequency, and obtaining the numerical control signal generated by the automatic frequency control module, it accurately selects the corresponding frequency band line according to the current input-output clock difference, effectively suppressing the error caused by process temperature. After the automatic frequency control module controls different current mirror switches, the output frequency band width is broadened, which can cope with the process deviation in different PVT scenarios. According to the frequency comparison result, logical control is performed on the numerical control signal to generate a control tail current source signal to calibrate the output frequency of the secondary ring oscillator module. The generated four-phase clock can be directly used as the high-speed serial interface clock for effective data transmission and reception, improving the overall circuit efficiency. The current from the ring oscillator circuit to the ground is monitored and controlled by the current mirror, and the frequency of the secondary ring oscillator is modulated by the current. The output four-phase high-frequency differential signal eliminates the power consumption and area of the additional clock generation circuit design of the high-speed serial interface. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of a four-phase ring voltage-controlled oscillator circuit provided by an embodiment of the present application;

[0028] Figure 2 is a schematic step flow diagram of a calibration method for a four-phase ring voltage-controlled oscillator circuit provided by an embodiment of the present application;

[0029] Figure 3 is a schematic principle diagram of a four-phase ring voltage-controlled oscillator circuit provided by an embodiment of the present application;

[0030] Figure 4 is a schematic principle diagram of a secondary ring oscillator module provided by an embodiment of the present application;

[0031] Figure 5 is a schematic diagram of the simulation output frequency band of a four-phase ring voltage-controlled oscillator circuit provided by an embodiment of the present application;

[0032] Figure 6 is a schematic calibration flow diagram of an automatic frequency control module provided by an embodiment of the present application. Detailed Embodiments

[0033] In order to make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description involves the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0034] It can be understood that the terms "first", "second", etc. used in the present application can be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the words "if", "when" as used herein can be interpreted as "when...", "while...", or "in response to determining".

[0035] The terms "at least one", "multiple", "each", "any one", etc. used in the present application, at least one includes one, two, or more than two, multiple includes two or more than two, each refers to each one of the corresponding multiple, and any one refers to any one of the multiple.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0037] Refer to Figure 1 and Figure 3 , Figure 1 is a schematic structural diagram of a four-phase ring voltage-controlled oscillator circuit provided by an embodiment of the present invention. Refer to Figure 1 , the circuit includes a voltage-current conversion module, a current mirror module, an automatic frequency control module, and a second-level ring oscillator module. The output end of the voltage-current conversion module is connected to the first input end of the current mirror module, the output end of the automatic frequency control module is connected to the second input end of the current mirror module, and the output end of the current mirror module is connected to the input end of the second-level ring oscillator module.

[0038] In this embodiment, a four-phase ring voltage-controlled oscillator circuit provided by an embodiment of the present invention is used to provide a controllable oscillation clock in a phase-locked loop circuit. Different control words are output through an AFC circuit to adjust the magnitude of the current flowing through the oscillator, thereby affecting the delay time to control the frequency change of the output clock. The control word is set according to the required frequency band and calibrated through a clock calibration circuit.

[0039] Furthermore, it should be noted that the voltage-current conversion module is used to generate a constant bias current and output it to the current mirror module; the current mirror module is used to receive the bias current and amplify the bias current for current output; the AFC module is used to output a control word to control the current mirror switch; the oscillator module generates an oscillation signal and generates a four-phase differential clock signal.

[0040] The rail-to-rail operational amplifier circuit in the voltage-current conversion module provides a high-linear current source; a current mirror is used as the current control stage of the oscillator to monitor the output current of the oscillator; an AFC is used to generate a numerically controlled signal to accurately select the corresponding frequency band line according to the current input-output clock phase difference, effectively suppressing the errors caused by process temperature; the current flowing from the secondary ring oscillator circuit to the ground is monitored and controlled by the current mirror, and the frequency of the secondary ring oscillator is modulated by the current, and the output four-phase high-frequency differential signal eliminates the power consumption and area of the additional clock generation circuit design of the high-speed serial interface.

[0041] Among them:

[0042] The voltage-current conversion module is used to generate a bias current;

[0043] In this embodiment, the voltage-current conversion circuit adopts a rail-to-rail operational amplifier to maximize the expansion of the range of the input control voltage V ctrl and convert it into a controllable current signal I ctrl , providing a high-linear reference current for the subsequent current mirror circuit.

[0044] Specifically, the voltage-current conversion module includes a first rail-to-rail operational amplifier, a first PMOS transistor, a first NMOS transistor, and a seventh NMOS transistor. Among them, the negative input terminal of the first rail-to-rail operational amplifier is connected to the control voltage input signal, the drain of the first PMOS transistor is connected to the high level, the positive input terminal of the first rail-to-rail operational amplifier, the source of the first PMOS transistor, the drain of the first NMOS transistor, and the gate of the seventh NMOS transistor are connected, the output terminal of the first rail-to-rail operational amplifier is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor is connected to the current mirror module, the source of the first NMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is connected to the current mirror module.

[0045] More specifically, the voltage-current conversion module includes a first rail-to-rail operational amplifier OP, a first PMOS transistor MP1, a first NMOS transistor MN1, and a seventh NMOS transistor MN7; the drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor MN1 and is connected to the positive input terminal of the first rail-to-rail operational amplifier OP1, the source of the first NMOS transistor MN1 is connected to the drain of the seventh NMOS transistor MN7 and is grounded through the source of MN7, and the negative input terminal of OP1 serves as an input node to receive the input V ctrl signal, and its output terminal is connected to the gate of the first PMOS transistor PM1.

[0046] The current mirror module is used to amplify the bias current to obtain an amplified bias current;

[0047] In this embodiment, the programmable current mirror is one of the core parts of the designed oscillator. By increasing the number of current mirror branches, sub-bands with different frequency bands can be provided. The key to being able to control the frequency of the loop through digital codes lies in passing through SW <x>The high and low levels of the control word control the conduction and cut-off of the NMOS switches in each branch, thereby controlling the magnitude of the I voc current and changing the delay time of the oscillator delay unit, thereby changing the frequency of the output square wave.

[0048] Specifically, the current mirror module includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. Among them, the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the drains of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected and output an amplified bias current. The gates of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are respectively connected to the automatic frequency control module. The gates of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are all connected to the gate of the seventh NMOS transistor. The sources of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are connected and grounded. The source of the second NMOS transistor is connected to the drain of the eighth NMOS transistor. The source of the third NMOS transistor is connected to the drain of the ninth NMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the tenth NMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the eleventh NMOS transistor. The source of the sixth NMOS transistor is connected to the drain of the twelfth NMOS transistor.

[0049] More specifically, the current mirror module includes a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor NM4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor NM10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12. The gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1. The gates of the third NMOS transistor MN3, the fourth NMOS transistor NM4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are respectively controlled by the control word SW<0:3> output by the AFC module. The gates of the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor NM10, and the eleventh NMOS transistor MN11 are all connected to the gate of the seventh NMOS transistor MN7 and connected to the positive input terminal of OP1, forming a numerically controlled current mirror. The drain of the second NMOS transistor NM2 serves as the output node A to output the control tail current source I of the VCO voc .

[0050] The automatic frequency control module is used to generate a numerically controlled signal and control the switches of the current mirror module;

[0051] In this embodiment, the AFC control circuit is also an important part of the designed oscillator. The AFC circuit determines whether the deviation between the output clock signal and the input clock signal is within the required frequency band range, and outputs different control words to switch the corresponding frequency band according to the error magnitude.

[0052] Specifically, the numerically controlled signal generated by the automatic frequency control module includes a first digital control signal, a second digital control signal, a third digital control signal, and a fourth digital control signal. The first digital control signal is connected to the gate of the third NMOS transistor, the second digital control signal is connected to the gate of the fourth NMOS transistor, the third digital control signal is connected to the gate of the fifth NMOS transistor, and the fourth digital control signal is connected to the gate of the sixth NMOS transistor.

[0053] The second-order ring oscillator module is used to perform frequency control according to the amplified bias current and output a four-phase differential clock oscillation signal.

[0054] In this embodiment, the second-order ring oscillator adopts a second-order oscillator topology unit, and I voc controls its oscillation frequency magnitude, which includes an oscillation delay element and a phase compensator, and realizes the output of a four-phase differential oscillation signal with the minimum area.

[0055] Specifically, the second-order ring oscillator module includes a first delay unit and a second delay unit. The negative input terminal of the first delay unit is connected to the negative output terminal of the second delay unit, the positive input terminal of the first delay unit is connected to the positive output terminal of the second delay unit, the negative output terminal of the first delay unit is connected to the positive input terminal of the second delay unit, the positive output terminal of the first delay unit is connected to the negative input terminal of the second delay unit, and the ground terminals of the first delay unit and the second delay unit are both connected to the amplified bias current.

[0056] More specifically, the oscillator module includes two delay units, a first delay unit delay1 and a second delay unit delay2; the negative input terminal of the first delay circuit delay1 is connected to the negative output terminal of the second delay circuit delay2, the positive input terminal of the first delay circuit delay1 is connected to the positive output terminal of the second delay circuit delay2, the positive output terminal of the first delay circuit delay1 is connected to the negative input terminal of the second delay circuit delay2, the negative output terminal of the first delay circuit delay1 is connected to the positive input terminal of the second delay circuit delay2, the ground terminals of the first delay circuit delay1 and the second delay circuit delay2 are connected to the output node A of the current mirror, and the power supply terminals of the first delay circuit delay1 and the second delay circuit delay2 are connected to the power supply voltage.

[0057] Among them, the second delay unit includes a first inverter, a second inverter, a third inverter and a fourth inverter. The input terminal of the first inverter serves as the positive input terminal of the second delay unit, and the input terminal of the second inverter serves as the negative input terminal of the second delay unit. The output terminal of the first inverter, the output terminal of the third inverter and the input terminal of the fourth inverter are connected and serve as the negative output terminal of the second delay unit. The output terminal of the second inverter, the input terminal of the third inverter and the output terminal of the fourth inverter are connected and serve as the positive output terminal of the second delay unit.

[0058] Specifically, the delay unit of the second-stage ring oscillator circuit oscillation circuit includes a first inverter inv1, a second inverter inv2, a third inverter inv3, and a fourth inverter inv4. The first inverter inv1 and the second inverter inv2 form an oscillation circuit. The input terminal X of the first inverter inv1 serves as the positive input terminal of the first and second delay circuits of the second-stage ring oscillator circuit oscillation circuit. The output terminal Y of the first inverter inv1 is connected to the Y terminal of the third inverter inv3, the X terminal of the fourth inverter inv4, and serves as the negative output terminal of the first and second delay circuits of the second-stage ring oscillator circuit oscillation circuit. The input terminal X of the second inverter inv2 serves as the negative input terminal of the first and second delay circuits of the second-stage ring oscillator circuit oscillation circuit. The output terminal Y of the second inverter inv2, the X terminal of the third inverter inv3, and the Y terminal of the fourth inverter inv4 serve as the positive output terminal of the first and second delay circuits of the second-stage ring oscillator circuit oscillation circuit. The second inverter inv2 and the third inverter inv3 form an oscillator phase compensation loop.

[0059] The first inverter and the second inverter form the oscillation circuit of the second-stage ring oscillator module, and the third inverter and the fourth inverter serve as the phase compensation circuit of the second-stage ring oscillator module.

[0060] The fourth inverter includes a second PMOS transistor, a third PMOS transistor, a thirteenth NMOS transistor and a fourteenth NMOS transistor. Among them, the gates of the second PMOS transistor, the third PMOS transistor, the thirteenth NMOS transistor and the fourteenth NMOS transistor are connected and serve as the input terminal of the fourth inverter. The drain of the second PMOS transistor is connected to a high level. The source of the second PMOS transistor is connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the drain of the thirteenth NMOS transistor and serves as the output terminal of the fourth inverter. The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is grounded.

[0061] Please refer to Figure 2 , the embodiment of the present application also provides a calibration method for a four-phase ring voltage-controlled oscillator circuit, which can implement the above-mentioned four-phase ring voltage-controlled oscillator circuit. The method includes the following steps:

[0062] S100, obtaining the output frequency of the secondary ring oscillator module, and comparing it with a preset reference frequency to obtain a frequency comparison result;

[0063] S200, acquiring a numerical control signal generated by an automatic frequency control module based on a preset reference frequency;

[0064] S300, performing logic control on the digital control signal according to the frequency comparison result to generate a control tail current source signal;

[0065] S400, calibrating the output frequency of the secondary ring oscillator module according to the control tail current source signal, and outputting a four-phase differential clock oscillation signal;

[0066] In some specific embodiments, the current mirror module branch is controlled by the AFC output control word, MN3-MN6 constitutes a current mirror switch, the gate is controlled by the control word (0 / 1), and different branch combinations correspond to different frequency band lines. The programmable current mirror is one of the core parts of the designed oscillator. In order to achieve higher calibration accuracy, the digitally controlled oscillator circuit designed in this article has a total of 4-bit control words and a total of 5 current mirror branches. One of the current mirrors is kept normally open to ensure that there is still control current when SW outputs 0000 (that is, when all digitally controlled current mirror branches are turned off). MN9-MN12 replicates the current branch, and the branch current size is controlled according to the aspect ratio, which is used for the bias current I ctrl Proportional amplification output I vco ; The formula is as follows, I ctrl By V ctrl The control reference current generated, i represents the branch number, SW <0> -SW <3> Takes "1" or "0".

[0067]

[0068] The AFC control circuit widens the output bandwidth after controlling different current mirror switches, which can cope with process deviations in different PVT scenarios. Since the circuit is used in different environments each time, the control word SW<0:3> corresponding to the target clock frequency is different according to different field environments, and the initial value is set to 1000; after each power-on, the AFC module will calibrate the clock according to the current output clock signal; the AFC calibration process is as follows Figure 6 As shown. At the beginning of calibration, the current control word is calibrated first, and the input clock is synchronized in the reference clock domain (CLK_AFC and CLK_REF1) to obtain a rising edge pulse. The clock signal CLK_REF2 is a delay of 1 second from CLK_REF1 (τ1<1 / 2T CLK_REF1 ) obtained, f CLF_REF1 =f CLK_REF2 ,p*f CLK_REF1 = f CLK_AFC .

[0069] After receiving the rising edge pulse signal, Counter 1 and Counter 2 start counting N simultaneously Count and N Count1 . Whenever Counter 2 increments, that is, when a rising edge pulse is received, it indicates that another input clock has passed. At this time, N Count and N Count1 are judged for their quantitative relationship. If the ideal quantitative relationship between the reference clock and the target output clock is satisfied, that is, N Count1 * p = N Count , it indicates that the current counted time is sufficient to identify the frequency difference between the input clock and the reference clock, and the current control word is output; if N Count1 * p < N Count , it means the output is too fast, and the control word is decremented by one; if N Count1 * p > N Count , it means the output is too slow, and the control word is incremented by one; when the control word is incremented or decremented, the reference clock signal used for counting will be switched. After the CLK_REF1 operation ends, the CLK_REF2 signal will be switched to continue counting; in this way, by switching back and forth directly between the two reference clocks, since the delay between these two signals does not exceed half a cycle, the waiting time until the next rising edge of CLK_REF (CLK_REF1 / CLK_REF2) can be shortened, making the waiting idle time less than 1 / 2T CLK_REF ; continue counting until the quantitative relationship is judged to be satisfied, and output the current control word. After testing, as Figure 5 shown, under different combinations of control words SW<0:3>, the frequency band coverage can reach 1.5G - 8GHz, and K VCO can cover the process deviation in the range of 50M - 350M;

[0070] The secondary ring oscillator module generates a flow control oscillation signal to generate a four-phase differential clock; its output tail current source is controlled by the current mirror from the node current I to the ground, as VCO shown in Figure 4 . Inv1 and inv2 are used as the oscillation circuits, and inv3 and in4 provide phase compensation. Through the phase compensation of the two inverters, oscillation can be achieved through the delay unit with only two stages. After calibration, the oscillator will switch to the appropriate frequency band line. For different process deviations and temperatures, the corresponding frequency band lines are different, realizing dynamic frequency adjustment and high anti-interference ability.

[0071] The present invention provides a good anti-interference ability for the PLL during process variations by introducing a high-precision AFC control circuit, ensuring the stable operation of the circuit. The proposed AFC control word algorithm shortens the calibration time of the traditional AFC and optimizes the fast locking time of the overall phase-locked loop. At the same time, the secondary ring oscillator performs well in terms of layout area and circuit performance, and simplifies the clock generation circuit to a certain extent.

[0072] In summary, an embodiment of the present invention includes a voltage-controlled oscillator circuit, which includes a voltage-current conversion module, a current mirror module, a secondary ring oscillator module, and an AFC (Automatic Frequency Control) module that are electrically connected in sequence. The VCO circuit adopted generates a bias current I that follows the input control voltage (generated by the charge pump of the VCO front-end circuit). ctrl The bias current I is linearly controlled from rail to rail through the feedback loop of the operational amplifier, maximizing the dynamic range of the current change and suppressing the input noise; the adopted AFC module outputs a 4-bit binary control word by logically processing the reference clock and the output clock; the adopted current mirror module is used to receive the bias current I. ctrl and the total output current I (flowing into the secondary ring oscillator) is controlled by the control word output by the AFC, linearly controlling the output frequency of the oscillator and expanding its frequency oscillation range; the adopted secondary ring oscillator generates a four-phase differential clock signal controlled by I. The embodiment of the present invention realizes high-precision linearized control of the frequency output through each module, and at the same time, the generated four-phase clock can be directly used as the clock of the high-speed serial interface for effective data transmission and reception, improving the overall circuit efficiency. ctrl vco (flowing into the secondary ring oscillator), linearly controlling the output frequency of the oscillator and expanding its frequency oscillation range; the adopted secondary ring oscillator generates a four-phase differential clock signal controlled by I. The embodiment of the present invention realizes high-precision linearized control of the frequency output through each module, and at the same time, the generated four-phase clock can be directly used as the clock of the high-speed serial interface for effective data transmission and reception, improving the overall circuit efficiency. vco

[0073] In summary, the embodiment of the present invention can solve the frequency band deviation caused by the traditional process variability; the rail-to-rail operational amplifier is used as the input stage of the current source, and the large input resistance of the amplifier effectively suppresses the noise of the VCO front-end control voltage and improves the output range and linearity of the current I. ctrl improving the anti-noise performance and output accuracy of the overall phase-locked loop; the secondary ring oscillator structure provides the smallest area occupation ratio, and the generation of the four-phase clock saves the power consumption of the clock generation module in the high-speed serial interface, further improving the overall circuit efficiency.

[0074] It can be understood that the content in the above method embodiments is applicable to the system embodiments of the present invention. The functions specifically implemented by the system embodiments of the present invention are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0075] ​​The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.< / x>

Claims

1. A four-phase ring voltage-controlled oscillator circuit, characterized in that, The circuit includes a voltage-current conversion module, a current mirror module, an automatic frequency control module, and a second-order ring oscillator module. The output terminal of the voltage-current conversion module is connected to the first input terminal of the current mirror module. The output terminal of the automatic frequency control module is connected to the second input terminal of the current mirror module. The output terminal of the current mirror module is connected to the input terminal of the second-order ring oscillator module, where: The voltage-current conversion module is used to generate a bias current; The current mirror module is used to amplify the bias current to obtain an amplified bias current; The automatic frequency control module is used to generate a numerically controlled signal and control the switch of the current mirror module; The second-order ring oscillator module is used to perform frequency control according to the amplified bias current and output a four-phase differential clock oscillation signal.

2. The circuit according to claim 1, characterized in that, The voltage-current conversion module includes a first rail-to-rail operational amplifier, a first PMOS transistor, a first NMOS transistor, and a seventh NMOS transistor. Among them, the negative input terminal of the first rail-to-rail operational amplifier is connected to a control voltage input signal. The drain of the first PMOS transistor is connected to a high level. The positive input terminal of the first rail-to-rail operational amplifier, the source of the first PMOS transistor, the drain of the first NMOS transistor, and the gate of the seventh NMOS transistor are connected. The output terminal of the first rail-to-rail operational amplifier is connected to the gate of the first PMOS transistor. The gate of the first NMOS transistor is connected to the current mirror module. The source of the first NMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is grounded. The gate of the seventh NMOS transistor is connected to the current mirror module.

3. The circuit according to claim 2, wherein The current mirror module includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. Among them, the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor. The drains of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected and output the amplified bias current. The gates of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are respectively connected to the automatic frequency control module. The gates of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are all connected to the gate of the seventh NMOS transistor. The sources of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are connected and grounded. The source of the second NMOS transistor is connected to the drain of the eighth NMOS transistor. The source of the third NMOS transistor is connected to the drain of the ninth NMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the tenth NMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the eleventh NMOS transistor. The source of the sixth NMOS transistor is connected to the drain of the twelfth NMOS transistor.

4. The circuit according to claim 3, wherein The digital control signals generated by the automatic frequency control module include a first digital control signal, a second digital control signal, a third digital control signal, and a fourth digital control signal. The first digital control signal is connected to the gate of the third NMOS transistor. The second digital control signal is connected to the gate of the fourth NMOS transistor. The third digital control signal is connected to the gate of the fifth NMOS transistor. The fourth digital control signal is connected to the gate of the sixth NMOS transistor.

5. The circuit according to claim 1, characterized in that, The second-level ring oscillator module includes a first delay unit and a second delay unit. The negative input terminal of the first delay unit is connected to the negative output terminal of the second delay unit. The positive input terminal of the first delay unit is connected to the positive output terminal of the second delay unit. The negative output terminal of the first delay unit is connected to the positive input terminal of the second delay unit. The positive output terminal of the first delay unit is connected to the negative input terminal of the second delay unit. The ground terminals of the first delay unit and the second delay unit are both connected to the amplified bias current.

6. The circuit according to claim 5, characterized in that, The second delay unit includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The input terminal of the first inverter serves as the positive input terminal of the second delay unit, and the input terminal of the second inverter serves as the negative input terminal of the second delay unit. The output terminal of the first inverter, the output terminal of the third inverter, and the input terminal of the fourth inverter are connected and serve as the negative output terminal of the second delay unit. The output terminal of the second inverter, the input terminal of the third inverter, and the output terminal of the fourth inverter are connected and serve as the positive output terminal of the second delay unit.

7. The circuit according to claim 6, wherein The first inverter and the second inverter constitute the oscillation circuit of the second-order ring oscillator module, and the third inverter and the fourth inverter serve as the phase compensation circuit of the second-order ring oscillator module.

8. The circuit according to claim 6, wherein The fourth inverter includes a second PMOS transistor, a third PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. Among them, the gates of the second PMOS transistor, the third PMOS transistor, the thirteenth NMOS transistor, and the fourteenth NMOS transistor are connected and serve as the input terminal of the fourth inverter. The drain of the second PMOS transistor is connected to a high level. The source of the second PMOS transistor is connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the drain of the thirteenth NMOS transistor and serves as the output terminal of the fourth inverter. The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is grounded.

9. A calibration method for a four-phase ring voltage-controlled oscillator circuit, characterized in that, The method includes the following steps: Obtain the output frequency of the second-order ring oscillator module, compare it with a preset reference frequency, and obtain a frequency comparison result; Based on the preset reference frequency, obtain the digital control signal generated by the automatic frequency control module; According to the frequency comparison result, perform logical control on the digital control signal to generate a control tail current source signal; Calibrate the output frequency of the second-order ring oscillator module according to the control tail current source signal, and output a four-phase differential clock oscillation signal.

10. The method according to claim 9, wherein The expression of the control tail current source signal is specifically as follows: In the above formula, I vco represents the control tail current source signal, I ctrl represents the control current input signal, i represents the branch number, and SW represents the digital control signal, and m represents the amplification factor.

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