High-voltage pulse source generator with controllable amplitude and frequency and large-depth ground penetrating radar device

Abstract

The invention provides a high-voltage pulse source generator with controllable amplitude and frequency and a large-depth ground penetrating radar device, and relates to the technical field of electronic circuits, and the high-voltage pulse source generator comprises an edge trigger signal circuit, a pulse generation adjusting circuit, a comparison adjusting circuit, an MCU control circuit, a high-voltage generation adjusting circuit, a high-voltage MOS drive circuit, an MOS tube high-side power supply circuit and a wireless communication circuit. Wherein the edge trigger signal circuit is connected with the pulse generation adjusting circuit; the pulse generation adjusting circuit is connected with the comparison adjusting circuit and the MCU control circuit. The comparison adjusting circuit is connected with the MCU control circuit and the high-voltage MOS drive circuit. The MCU control circuit is connected with the high voltage generation adjusting circuit and the wireless communication circuit. The high-voltage MOS driving circuit is connected with the high-voltage generation adjusting circuit and the MOS tube high-side power supply circuit. The high-voltage MOS tube driving circuit is used for adjusting the positive pulse signal and the negative pulse signal. According to the invention, the control precision of the high-voltage pulse source generator can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a high-voltage pulse source generator with controllable amplitude and frequency and a large-depth ground-penetrating radar device. Background Art

[0002] A high-voltage pulse power supply is a power supply device that stores energy at a low speed and releases it at a high speed. By turning on and off various forms of switches, it outputs high-voltage pulses with a certain width, amplitude, and frequency. Currently, high-voltage pulse power supplies are mainly applied in basic research fields such as gas discharge, dielectric insulation aging, and pulse jet mechanism, as well as industrial application fields such as material surface modification, wastewater / gas treatment, and sterilization and disinfection. In experimental research, it is necessary to change parameters such as the pulse width, frequency, and amplitude of the pulse to analyze the influence of changes in each power supply parameter on different discharge forms. In industrial applications, it is necessary to change parameters such as the pulse width, frequency, and amplitude to deal with different treatment objects.

[0003] Chinese Patent with Publication No. CN114400989A discloses a pulse generation circuit, a pulse generation device, and its control method, including a high-voltage DC power supply, at least one magnetic drive circuit, and a Marx main circuit connected in parallel with the high-voltage DC power supply. The output end of the half-bridge control circuit in the magnetic drive circuit and at least one gate drive circuit group transmit control signals through high-voltage wires using the law of electromagnetic induction. The gate drive circuit group is provided with a first output end and a second output end. The first output end is connected to the main switch in the Marx main circuit, and the second output end is connected to the tail cut switch in the Marx main circuit. However, the above scheme relies on the magnetic induction method to transmit control signals through high-voltage wires, which is easily affected by electromagnetic interference, signal attenuation, and delay. Moreover, although the positive and negative pulses have the same pulse width, there are limitations in precise synchronization and amplitude consistency, resulting in a decrease in control accuracy. Therefore, providing a high-voltage pulse source generator with controllable amplitude and frequency and a large-depth ground-penetrating radar device helps to improve the control accuracy of the high-voltage pulse source generator and is very necessary. Summary of the Invention

[0004] In view of this, the present invention proposes a high-voltage pulse source generator with controllable amplitude and frequency and a large-depth ground-penetrating radar device. By comparing and adjusting the relative delay of positive and negative pulse signals according to a reference voltage in the comparison and adjustment circuit, accurate relative delay between the positive and negative pulse signals is ensured. At the same time, the MOS drive circuit adjusts the positive and negative pulse signals, thereby improving the control accuracy of the high-voltage pulse source generator.

[0005] The present invention provides a high-voltage pulse source generator with controllable amplitude and frequency, including an edge-triggered signal circuit, a pulse generation and adjustment circuit, a comparison and adjustment circuit, an MCU control circuit, a high-voltage generation and adjustment circuit, a high-voltage MOS drive circuit, a MOS tube high-side power supply circuit, and a wireless communication circuit, wherein,

[0006] The edge trigger signal circuit is connected to the pulse generation and regulation circuit;

[0007] The pulse generation and regulation circuit is respectively connected to the comparison and regulation circuit and the MCU control circuit. The pulse generation and regulation circuit is used to receive the external synchronous trigger edge signal sent by the edge trigger signal circuit and generate positive and negative pulse signals with electrically adjustable pulse widths;

[0008] The comparison and regulation circuit is respectively connected to the MCU control circuit and the high-voltage MOS drive circuit. The comparison and regulation circuit is used to perform relative delay adjustment on the positive and negative pulse signals output by the pulse generation and regulation circuit according to the positive and negative pulse signals generated by the pulse generation and regulation circuit and the reference voltage, so as to obtain positive and negative pulse signals with relative delays;

[0009] The MCU control circuit is respectively connected to the high-voltage generation and regulation circuit and the wireless communication circuit. The high-voltage generation and regulation circuit responds to the instruction of the MCU control circuit, outputs a DC voltage with adjustable amplitude, and provides a DC bias for the high-voltage MOS transistor drive circuit;

[0010] The high-voltage MOS drive circuit is respectively connected to the high-voltage generation and regulation circuit and the MOS transistor high-side power supply circuit. The high-voltage MOS drive circuit is used to regulate the positive and negative pulse signals to generate two high-voltage pulse signals with the same pulse width, amplitude and opposite polarities.

[0011] On the basis of the above technical solutions, preferably, the edge trigger signal circuit includes a fiber optic receiver U3, a capacitor C16, a capacitor C20, a capacitor C23, a comparator U52, a resistor R4, a resistor R8 and a resistor R23. The first end of the fiber optic receiver U3 is connected to one end of the capacitor C23. The other end of the capacitor C23 and the inverting input terminal of the comparator U52 are both connected to one end of the resistor R23. The second end of the fiber optic receiver U3 is grounded. The third end of the fiber optic receiver U3 is externally connected to a voltage input terminal. The fourth end of the fiber optic receiver U3 is connected to the capacitor C16. The other end of the capacitor C16 and the non-inverting input terminal of the comparator U52 are both connected to one end of the resistor R4. The other end of the resistor R4 is respectively connected to the output terminal of the comparator U52 and one end of the resistor R8. The common end of the resistor R8 and the resistor R23 is respectively connected to one end of the capacitor C20 and the pulse generation and regulation circuit. The other end of the capacitor C20 is grounded.

[0012] Based on the above technical solutions, preferably, the pulse generation and regulation circuit includes a multivibrator U60, a digital potentiometer U61, an oscillation resistor R130, an oscillation capacitor C132, and a resistor R131. The first pin of the multivibrator U60 is grounded. The external synchronous trigger edge signal is input through the second pin of the multivibrator U60. The third pin of the multivibrator U60 is connected to one end of the resistor R131. The fourth pin of the multivibrator U60 and the other end of the resistor R131 are commonly grounded. The fifth pin of the multivibrator U60 is externally connected to a voltage input terminal. The sixth pin of the multivibrator U60 is connected to the common terminal of the oscillation resistor R130 and the oscillation capacitor C132. The seventh pin of the multivibrator U60 is connected to the other end of the oscillation capacitor C132. The other end of the oscillation resistor R130 is connected to the digital potentiometer U61.

[0013] More preferably, the comparison and regulation circuit includes a DAC output chip U59, a comparator U51, and a comparator U55. The first pin of the DAC output chip U59 is externally connected to a voltage input terminal. The second pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U51. The third pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U55. The non-inverting input terminals of both the comparator U51 and the comparator U55 are connected to the pulse generation and regulation circuit. The output terminals of both the comparator U51 and the comparator U55 are connected to the high-voltage MOS transistor drive circuit.

[0014] More preferably, the high-voltage generation and regulation circuit includes resistors R74, R75, R78, R80, R83, R85, R86, R127, R128, R129, capacitors C97, C101, C104, C106, C130, a PWM controller U32, an NMOS transistor U56, a filter inductor L10, a rectifier diode D19, a diode D22, and a high-frequency transformer T5, where

[0015] One end of the resistor R80 is grounded through the resistor R85. One end of the resistor R80 is connected to the MCU control circuit through the resistor R86. One end of the resistor R80 is also connected to the common terminal of the resistor R83, the capacitor C106, and the PWM controller U32. The other common terminal of the resistor R83 and the capacitor C106 is connected to the first pin of the PWM controller U32. The third pin of the PWM controller U32 is connected to the common terminal of the resistor R83 and the capacitor C101. The fourth pin of the PWM controller U32 is connected to the common terminal of the resistor R75 and the capacitor C104. The common terminal of the capacitor C104 and the resistor R74 is grounded. The common terminal of the resistor R75 and the resistor R74 is connected to the source electrode of the NMOS transistor U56. The other end of the capacitor C104 is grounded through the resistor R78. The other end of the resistor R75 and the fifth pin of the PWM controller U32 are commonly connected to an external voltage input terminal. The common terminal of the sixth pin of the PWM controller U32 and the filter inductor L10 is connected to an external voltage input terminal. The seventh pin of the PWM controller U32 is connected to the gate electrode of the NMOS transistor U56. The eighth pin of the PWM controller U32 is grounded. The drain electrode of the NMOS transistor U56 is respectively connected to the positive electrode of the diode D22 and the second terminal of the high-frequency transformer T5. The negative electrode of the diode D22 is connected to the first common terminal of the resistor R127 and the capacitor C130. The second common terminal of the resistor R127 and the capacitor C130 is respectively connected to the other end of the filter inductor L10 and the first terminal of the high-frequency transformer T5. The third terminal of the high-frequency transformer T5 is connected to the positive electrode of the rectifier diode D19. The negative electrode of the rectifier diode D19, one end of the capacitor C97, and the resistor R128 are connected to the other end of the resistor R80. The capacitor C97 and the fourth terminal of the high-frequency transformer T5 are commonly grounded. The common terminal of the resistor R128 and the resistor R129 is connected to the MCU control circuit. The other end of the resistor R129 is grounded.

[0016] More preferably, the high-voltage MOS transistor driving circuit includes a first driving sub-circuit and a second driving sub-circuit. Both the first driving sub-circuit and the second driving sub-circuit are connected to the comparison and regulation circuit, the high-voltage generation and regulation circuit, and the MOS transistor high-side power supply circuit.

[0017] More preferably, the first driving sub-circuit includes a multi-channel inverter U8, a transformer T4, a gate driver U5, a gate driver U11, a resistor R7, a resistor R12, a resistor R21, a resistor R35, a resistor R110, a resistor R111, a power resistor R25, a capacitor C22, a capacitor C25, a capacitor C28, an NMOS transistor Q3, an NMOS transistor Q5, a zener diode D6, a zener diode D7, and a zener diode D46. The first pin of the multi-channel inverter U8 is respectively connected to the comparison and regulation circuit and one end of the capacitor C25. The second pin of the multi-channel inverter U8 is connected to the first end of the transformer T4 through the capacitor C28. The second end of the transformer T4 is grounded. The third end of the transformer T4 is connected to the third pin of the gate driver U5. The fourth end of the transformer T4 is connected to the common end of the resistor R7 and the resistor R12. The first pin of the gate driver U5 is connected to the MOS transistor high-side power supply circuit. The second pin of the gate driver U5, the other end of the resistor R12, the source of the NMOS transistor Q3, the positive electrode of the zener diode D46, one end of the power resistor R25, and the common end of the capacitor C22 and the resistor R110 are all connected to the MOS transistor high-side power supply circuit. The fourth pin of the gate driver U5 is connected to the gate of the NMOS transistor Q3. The fifth pin of the gate driver U5 is connected to the other end of the resistor R7. The drain of the NMOS transistor Q3 is respectively connected to the negative electrode of the zener diode D46 and the high-voltage generation and regulation circuit. The third pin of the multi-channel inverter U8 is connected to the common end of the capacitor C25 and the resistor R21. The other end of the resistor R21 is grounded. The fourth pin of the multi-channel inverter U8 is connected to the sixth pin of the multi-channel inverter U8. The fifth pin of the multi-channel inverter U8 is externally connected to the power input terminal. The seventh pin of the multi-channel inverter U8 is respectively connected to the first pin of the gate driver U11 and one end of the resistor R35 through the zener diode D6. The other end of the resistor R35 is connected to the third pin of the gate driver U11. The second pin of the gate driver U11 is connected to the gate of the NMOS transistor Q5. The drain of the NMOS transistor Q5 and the negative electrode of the zener diode D7 are both connected to the other end of the power resistor R2. The source of the NMOS transistor Q5 and the positive electrode of the zener diode D7 are commonly grounded. The common end of the resistor R110 and the resistor R111 is grounded. The common end of the capacitor C22 and the resistor R111 is used as the output feed point of the positive pulse signal.

[0018] More preferably, the second drive sub-circuit includes a multi-channel inverter U52, a transformer T6, a gate driver U54, a gate driver U53, a resistor R120, a resistor R121, a resistor R124, a resistor R125, a resistor R126, a power resistor R22, a capacitor C127, a capacitor C128, a capacitor C129, an NMOS transistor Q28, an NMOS transistor Q29, a zener diode D44, a zener diode D8, and a resistor R123. The first pin of the multi-channel inverter U52 is respectively connected to the comparison and regulation circuit and one end of the capacitor C128. The second pin of the multi-channel inverter U52 is connected to the first end of the transformer T6 through the capacitor C127. The second end of the transformer T6 is grounded. The third end of the transformer T6 is connected to the third pin of the gate driver U54. The fourth end of the transformer T6 is connected to the common end of the resistor R126 and the resistor R125. The first pin of the gate driver U54 is connected to the MOS transistor high-side power supply circuit. The second pin of the gate driver U54, the other end of the resistor R125, the source of the NMOS transistor Q29, one end of the power resistor R22, and the common end of the capacitor C129 and the resistor R123 are all connected to the MOS transistor high-side power supply circuit. The fourth pin of the gate driver U54 is connected to the gate of the NMOS transistor Q29. The fifth pin of the gate driver U54 is connected to the other end of the resistor R126. The drain of the NMOS transistor Q29 is respectively connected to the other end of the resistor R123 and the high-voltage generation and regulation circuit. The third pin of the multi-channel inverter U52 is connected to the common end of the capacitor C128 and the resistor R120. The other end of the resistor R120 is grounded. The fourth pin of the multi-channel inverter U52 is connected to the sixth pin of the multi-channel inverter U52. The fifth pin of the multi-channel inverter U52 is externally connected to the power supply input terminal. The seventh pin of the multi-channel inverter U52 is respectively connected to the first pin of the gate driver U53 and one end of the resistor R121 through the zener diode D44. The other end of the resistor R121 is connected to the third pin of the gate driver U53. The second pin of the gate driver U53 is connected to the gate of the NMOS transistor Q28. The drain of the NMOS transistor Q28 and the negative electrode of the zener diode D8 are both connected to the other end of the power resistor R22. The source of the NMOS transistor Q28 and the positive electrode of the zener diode D8 are commonly grounded. One end of the resistor R124 is grounded. The common end of the capacitor C129 and the resistor R124 is used as the output feed point of the negative pulse signal.

[0019] In the second aspect of the present application, a large-depth ground penetrating radar device is provided, which includes a main body housing, multi-component segmented antenna rods arranged on opposite sides of the main body housing, and a high-voltage pulse source generator with controllable amplitude and frequency arranged inside the main body housing.

[0020] More preferably, the segmented antenna rod includes a plurality of hollow cylindrical antennas with a diameter of 5-20 mm. Any two adjacent hollow cylindrical antennas are threadedly connected. A strip-shaped PCB is arranged inside the hollow cylindrical antenna, and a patch diode, a resistor, and a capacitor are placed on the strip-shaped PCB. The diode is used to select the center frequency of the antenna.

[0021] The high-voltage pulse source generator with controllable amplitude and frequency and the large-depth ground penetrating radar device provided by the present invention have the following beneficial effects compared with the prior art:

[0022] (1) Through the edge trigger signal circuit and the pulse generation and regulation circuit, the capture of the external synchronous trigger signal and the generation of positive and negative pulse signals with electrically adjustable pulse widths are realized, so that the pulse signals can be accurately controlled in terms of timing and width. In the comparison and regulation circuit, the relative delay of the positive and negative pulse signals is adjusted according to the reference voltage to ensure an accurate relative delay between the positive and negative pulse signals, thereby improving the overall accuracy and consistency of the pulse signals. The high-voltage generation and regulation circuit can output a DC high voltage with adjustable amplitude to provide flexible voltage regulation ability for the generation of high-voltage pulses, enabling the high-voltage pulse source generator to adapt to different detection depths and target characteristics, enhancing the applicability and detection accuracy of the high-voltage pulse source generator. At the same time, the MOS drive circuit adjusts the positive and negative pulse signals to generate two high-voltage pulse signals with the same pulse width, amplitude, and opposite polarities, ensuring the symmetry and consistency of the signals, thereby improving the control accuracy of the high-voltage pulse source generator.

[0023] (2) By using the cooperation of multiple inverters and a dedicated gate driver, the precise driving of the NMOS transistor is realized, thereby ensuring a steep edge of the high-voltage pulse and stable pulse width and amplitude, improving the overall pulse output accuracy. Through the reasonable configuration of components such as transformers, capacitors, and resistors, effective isolation between the signal and the power supply is achieved, reducing the influence of external interference on the drive circuit, and at the same time ensuring the matching of the parameters of each part of the circuit and enhancing the drive performance. The series and parallel design of the devices at all levels in the circuit makes the delay and response of the drive signal consistent, thereby realizing the stable feeding of the positive pulse output signal and meeting the requirements of high-speed switching and bilateral drive. With the help of components such as the MOS transistor high-side power supply circuit and the zener diode, the circuit provides a stable bias and DC voltage, which not only ensures the consistency of the output pulses but also enhances the anti-interference ability of the circuit to power supply fluctuations and electromagnetic interference. Description of the Drawings

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0025] Figure 1 Schematic framework diagram of a high-voltage pulse source generator with controllable amplitude and frequency provided by the present invention;

[0026] Figure 2 Circuit diagram of the edge-triggered signal circuit provided by the present invention;

[0027] Figure 3 Circuit diagram of the pulse generation and regulation circuit provided by the present invention;

[0028] Figure 4 Circuit diagram of the comparison and regulation circuit provided by the present invention;

[0029] Figure 5 Circuit diagram of the high-voltage generation and regulation circuit provided by the present invention;

[0030] Figure 6 Circuit diagram of the high-voltage MOS transistor drive circuit provided by the present invention;

[0031] Figure 7 Circuit diagram of the MOS transistor high-side power supply circuit provided by the present invention;

[0032] Figure 8 Schematic diagram of the principle of antenna radiation pulse provided by the present invention;

[0033] Figure 9 Schematic structural diagram of a large-depth ground penetrating radar device provided by the present invention;

[0034] Figure 10 Schematic structural diagram of a hollow cylindrical antenna provided by the present invention;

[0035] Figure 11 Schematic structural diagram of the mainframe base provided by the present invention;

[0036] Figure 12 Explosion diagram of the armrest bracket provided by the present invention.

[0037] Description of the reference numerals: 1. Edge trigger signal circuit; 2. Pulse generation and adjustment circuit; 3. Comparison and adjustment circuit; 4. MCU control circuit; 5. High-voltage generation and adjustment circuit; 6. High-voltage MOS drive circuit; 7. MOS transistor high-side power supply circuit; 8. Wireless communication circuit; 9. Main body housing; 10. Segmented antenna rod; 101. External-threaded copper part; 102. Male plugging part; 103. Nut; 104. FPC flexible board; 105. Female plugging part; 106. Internal-threaded copper part; 107. Protective antenna housing; 11. Main body base; 111. Antenna connection part; 112. Nut; 113. Main body bottom cover board; 114. Rubber pad; 115. Bull's-eye ball; 116. Main body base housing; 117. Contact copper part; 12. Fixed block; 13. Armrest bracket; 131. Handheld rod; 131a. Locking connection male head; 132. Ring screw; 133. Upright rod; 133a. Locking connection female head; 134. Cam screw; 135. Stabilizing block; 136. Screw; 137. Plug pin. Detailed implementation manners

[0038] Next, in combination with the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention belongs. The "first", "second" and similar terms used in the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "one" or "a" do not denote a quantity limitation, but mean that there is at least one. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship also changes accordingly.

[0040] Refer to Figure 1 , the present invention provides a high-voltage pulse source generator with controllable amplitude and frequency, including an edge trigger signal circuit 1, a pulse generation and adjustment circuit 2, a comparison and adjustment circuit 3, an MCU control circuit 4, a high-voltage generation and adjustment circuit 5, a high-voltage MOS drive circuit 6, a MOS transistor high-side power supply circuit 7 and a wireless communication circuit 8, wherein,

[0041] The edge-triggered signal circuit 1 is connected to the pulse generation and regulation circuit 2, as Figure 2 shown. The edge-triggered signal circuit 1 includes an optical fiber receiver U3, a capacitor C16, a capacitor C20, a capacitor C23, a comparator U52, a resistor R4, a resistor R8, and a resistor R23. The first terminal of the optical fiber receiver U3 is connected to one end of the capacitor C23. The other end of the capacitor C23 and the inverting input terminal of the comparator U52 are both connected to one end of the resistor R23. The second terminal of the optical fiber receiver U3 is grounded. The third terminal of the optical fiber receiver U3 is externally connected to a voltage input terminal. The fourth terminal of the optical fiber receiver U3 is connected to the capacitor C16. The other end of the capacitor C16 and the non-inverting input terminal of the comparator U52 are both connected to one end of the resistor R4. The other end of the resistor R4 is respectively connected to the output terminal of the comparator U52 and one end of the resistor R8. The common terminal of the resistor R8 and the resistor R23 is respectively connected to one end of the capacitor C20 and the pulse generation and regulation circuit 2. The other end of the capacitor C20 is grounded.

[0042] Furthermore, the edge-triggered signal circuit 1 includes an optical fiber receiver and a high-speed comparator. Using a high-speed optical fiber receiver can cooperate with a 650nm plastic optical fiber to achieve a high-performance optical fiber communication link, which is used to receive the synchronous trigger signal sent by the host computer. The receiver has a built-in pulse width calibration circuit, which can ensure that the pulse width distortion is within 4ns. At the same time, the high-speed comparator U52 is designed as a hysteresis comparison circuit, which has strong anti-interference ability. After the output signal of the optical fiber receiver is processed by this comparison circuit, a stable and reliable synchronous trigger signal is obtained.

[0043] The pulse generation and regulation circuit 2 is respectively connected to the comparison and regulation circuit 3 and the MCU control circuit 4. The pulse generation and regulation circuit 2 is used to receive the external synchronous trigger edge signal sent by the edge-triggered signal circuit 1 and generate positive and negative pulse signals with electrically adjustable pulse widths.

[0044] Furthermore, the pulse generation and regulation circuit 2 includes a multivibrator U60, a digital potentiometer U61, an oscillating resistor R130, an oscillating capacitor C132, and a resistor R131. The first pin of the multivibrator U60 is grounded. The external synchronous trigger edge signal is input from the second pin of the multivibrator U60. The third pin of the multivibrator U60 is connected to one end of the resistor R131. The fourth pin of the multivibrator U60 and the other end of the resistor R131 are commonly grounded. The fifth pin of the multivibrator U60 is externally connected to a voltage input terminal. The sixth pin of the multivibrator U60 is connected to the common terminal of the oscillating resistor R130 and the oscillating capacitor C132. The seventh pin of the multivibrator U60 is connected to the other end of the oscillating capacitor C132. The other end of the oscillating resistor R130 is connected to the digital potentiometer U61.

[0045] In this embodiment, the multivibrator U60 receives a synchronous trigger signal and outputs a pulse signal with a controllable pulse width and period. The pulse width Tw = 1 * (R130 + Rw) * C132, where Rw is the resistance from the center tap of the digital potentiometer U61 to the B terminal. The MCU controller drives the digital potentiometer U61 through the SPI interface to adjust the resistance Rw, thereby realizing the adjustment of the output pulse width. The minimum pulse width is Tw = R130 * C132, and its adjustment accuracy depends on the minimum resolution of the digital potentiometer.

[0046] As Figure 3 shown, the pulse generation and regulation circuit 2 includes a multivibrator U60, a digital potentiometer U61, an oscillation resistor R130, and an oscillation capacitor C132. The processed external synchronous trigger edge signal is directly connected to the input of channel B of the second pin of the multivibrator U60. The first pin of the multivibrator U60, channel A, is directly grounded. One end of the oscillation resistor R130 is connected to the center tap of the sixth pin of the digital potentiometer U61, and the other end is connected in series with the oscillation capacitor C132 and then connected to the fifteenth pin of U60. The other end of the capacitor C132 is connected to the fourteenth pin of U60. The seventh pin B tap of the digital potentiometer U61 is connected to VCC_5V, and the thirteenth pin Q of U60 is the adjusted pulse output pin. The pulse width range of the external synchronous trigger edge signal is 100 ns to 4 μs, and the amplitude range is 2.5 V to 5.5 V. The resistance value range of the oscillation resistor R130 is 500 Ω to 2 kΩ, the capacitance value range of the oscillation capacitor C132 is 500 pF to 2000 pF, the resistance value range of the digital potentiometer U61 is 1 kΩ to 10 kΩ, its resolution range is 256 steps (8 bits) to 1024 steps (10 bits), and the pulse width range of the output of the thirteenth pin of the multivibrator U60 is 100 ns to 20 μs, with an amplitude of 5 V.

[0047] The comparison and regulation circuit 3 is respectively connected to the MCU control circuit 4 and the high-voltage MOS drive circuit 6. The comparison and regulation circuit 3 is used to relatively delay-adjust the positive and negative pulse signals output by the pulse generation and regulation circuit 2 according to the positive and negative pulse signals and the reference voltage generated by the pulse generation and regulation circuit 2, so as to obtain positive and negative pulse signals with relative delay.

[0048] Further, the comparison and regulation circuit 3 includes a DAC output chip U59, a comparator U51, and a comparator U55. The first pin of the DAC output chip U59 is externally connected to the voltage input terminal. The second pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U51. The third pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U55. The non-inverting input terminals of the comparator U51 and the comparator U55 are both connected to the pulse generation and regulation circuit 2. The output terminals of the comparator U51 and the comparator U55 are both connected to the high-voltage MOS transistor drive circuit.

[0049] AsFigure 4 As shown in Figure 4 , the comparison and regulation circuit 3 includes a multi-channel DAC output chip U59, a comparator U51, and a comparator U55. Among them, the output B channel of the 7th pin of the multi-channel DAC output chip U59 is connected to the inverting input terminal of the 2nd pin of the comparator U51, and the output A channel of the 6th pin of the multi-channel DAC output chip U59 is connected to the inverting input terminals of the 2nd pins of the comparator U51 and the comparator U55. The non-inverting input terminals of the 3rd pins of the comparators U51 and U55 are connected to the pulse signals generated by the pulse generation and regulation circuit 2, and the 1st pin is the output. The models of the comparators U51 and U55 are exactly the same, or they are the two outputs of the same comparator. The output edges of the comparators U51 and U55 have a relative delay, and the delay range is 0 to 100 ns. Their pulse amplitudes and pulse widths are the same. The multi-channel DAC output chip U59 has a resolution of not less than 4096 (12 bits). The DAC output chip U59 is a four-channel DAC chip. The four-channel DAC chip is driven by an I2C interface and is connected to the I2C interface of the single-chip microcomputer. The pulse signals are respectively connected to the non-inverting input terminals of U51 and U55. The A channel and B channel of the four-channel DAC output are respectively connected to the inverting input terminals of U51 and U55 as reference terminals. The single-chip microcomputer can control the relative delay of the pulses output by U51 and U55 by adjusting the voltage difference between the A and B channels output by the DAC.

[0050] The MCU control circuit 4 is respectively connected to the high-voltage generation and regulation circuit 5 and the wireless communication circuit 8. The high-voltage generation and regulation circuit 5 responds to the instructions of the MCU control circuit 4, outputs a DC voltage with adjustable amplitude, and provides a DC bias for the high-voltage MOS tube drive circuit.

[0051] In this embodiment, the MCU uses the Huada HC32L36 series of low-power single-chip microcomputers, but it is not limited thereto. The MCU needs to satisfy at least one UART interface for external wireless communication; at least one I2C interface to realize battery power monitoring, temperature monitoring, and DAC chip driving; at least one SPI interface to realize digital potentiometer chip driving; at least one ADC interface to realize high-voltage source output voltage monitoring; at least ten IOs are available for the electrical control enabling drive of each module. Other models of MCU main controls that meet the above requirements can also implement the high-voltage pulse source generator in this solution.

[0052] Further, the high-voltage generation and regulation circuit 5 includes resistors R74, R75, R78, R80, R83, R85, R86, R127, R128, R129, capacitors C97, C101, C104, C106, C130, a PWM controller U32, an NMOS tube U56, a filter inductor L10, a rectifier diode D19, a diode D22, and a high-frequency transformer T5, where

[0053] One end of resistor R80 is grounded through resistor R85. One end of resistor R80 is connected to MCU control circuit 4 through resistor R86. One end of resistor R80 is also connected to the common terminal of resistor R83, capacitor C106, and PWM controller U32. The other common terminal of resistor R83 and capacitor C106 is connected to the first pin of PWM controller U32. The third pin of PWM controller U32 is connected to the common terminal of resistor R83 and capacitor C101. The fourth pin of PWM controller U32 is connected to the common terminal of resistor R75 and capacitor C104. The common terminal of capacitor C104 and resistor R74 is grounded. The common terminal of resistor R75 and resistor R74 is connected to the source electrode of NMOS transistor U56. The other end of capacitor C104 is grounded through resistor R78. The other end of resistor R75 and the fifth pin of PWM controller U32 are commonly connected to an external voltage input terminal. The common terminal of the sixth pin of PWM controller U32 and filter inductor L10 is connected to an external voltage input terminal. The seventh pin of PWM controller U32 is connected to the gate electrode of NMOS transistor U56. The eighth pin of PWM controller U32 is grounded. The drain electrode of NMOS transistor U56 is respectively connected to the positive electrode of diode D22 and the second terminal of high-frequency transformer T5. The negative electrode of diode D22 is connected to the first common terminal of resistor R127 and capacitor C130. The second common terminal of resistor R127 and capacitor C130 is respectively connected to the other end of filter inductor L10 and the first terminal of high-frequency transformer T5. The third terminal of high-frequency transformer T5 is connected to the positive electrode of rectifier diode D19. The negative electrode of rectifier diode D19, one end of capacitor C97, and resistor R128 are connected to the other end of resistor R80. Capacitor C97 and the fourth terminal of high-frequency transformer T5 are commonly grounded. The common terminal of resistor R128 and resistor R129 is connected to MCU control circuit 4. The other end of resistor R129 is grounded.

[0054] As Figure 5 shown, the high-voltage generation and regulation circuit 5 includes a PWM control circuit, a transformer rectification circuit, an RCD spike absorption circuit, a current feedback circuit, and a voltage feedback circuit. Among them,

[0055] The PWM control circuit includes a PWM controller U32, a resistor R75, a capacitor C104, a resistor R78, and an N-channel MOS transistor U56. One side of the resistor R75 is connected to the reference voltage output from the 8th pin of the PWM controller U32, and the other side is connected in series with one side of the capacitor C104 and then connected to the 4th pin of the PWM controller U32. The other side of the capacitor C104 is connected in series with the resistor R78 and then connected to the ground. The 6th pin of the PWM controller U32 is the pwm output pin and is connected to the gate of the MOS transistor U56. The resistance value of the resistor R75 ranges from 1 kΩ to 10 kΩ, and the capacitance value of the capacitor C104 ranges from 500 pF to 2000 pF. The resistor R75 and the capacitor C104 are connected in series and then connected to the 4th pin of the PWM controller U32 to form an RC oscillation circuit. The 6th pin of the PWM controller U32 outputs a pwm signal with an amplitude of 12V, which is connected to the gate of the N-channel MOS transistor U56. The pwm output frequency fo = 1.72 / (R75 * C104).

[0056] The transformer rectifier circuit includes a high-frequency transformer T5, a filter inductor L10, a rectifier diode D19, and a filter capacitor C97. The same-name terminal of the primary side of the transformer T5 is connected to DC12V through the filter inductor L10. The non-same-name terminal of T5 is connected to the drain of the MOS transistor U56. The non-same-name terminal of the secondary side of the transformer T5 is connected to the anode of the rectifier diode D19. The cathode of the rectifier diode D19 is connected to one side of the filter capacitor C97 as the high-voltage output point. The other side of the filter capacitor C97 and the same-name terminal of the secondary side of T5 are connected together to the ground electrode. The operating frequency range of the high-frequency transformer T5 is 20 kHz to 300 kHz, and the primary / secondary turn ratio range is 1:20 to 1:50. The high-frequency transformer T5 uses the sandwich winding method.

[0057] The RCD spike absorption circuit includes a diode D22, a capacitor C130, and a resistor R127. The anode of the diode D22 is connected to the non-same-name terminal of the primary side of the transformer T5. The capacitor C130 and the resistor R127 are connected in parallel, and one end is connected to the same-name terminal of the primary side of the transformer T5, and the other end is connected to the cathode of the diode D22. The RC value depends on the switching frequency of the mos transistor. Since all the energy of spike absorption is dissipated in the form of heat on the R127, factors such as heat dissipation and power need to be considered when selecting the package of R127.

[0058] The current feedback circuit includes a sampling resistor R74, a filter capacitor C101, and a filter resistor R83. One side of the sampling resistor is connected to the source of the MOS transistor U56, and the sampled voltage signal is filtered by the low-pass filter composed of R83 and C101 and then connected to the 3rd pin (current sampling pin) of the PWM controller U32.

[0059] The voltage feedback circuit includes resistor R80, resistor R85, resistor R86, resistor R83, and capacitor C106. One side of resistor R80 is connected to the high-voltage output VCC_HV after the transformer rectification circuit, and the other side is connected to resistor R85 and resistor R86 and then connected to the voltage feedback pin of the second foot of PWM controller U32. The other side of resistor R85 is connected to the ground, and the other side of resistor R86 is connected to the regulated voltage signal generated by the MCU control circuit 4. The feedback network composed of resistor R80, resistor R85, and resistor R86 and PWM controller U32 has its values satisfying the relationship formula (Vhv - 2.5V) / R80 + (Vadj - 2.5V) / R86 = 2.5V / R85, where Vhv is the amplitude voltage of the high-voltage output VCC_HV, with a range of (0 to 5000V), and Vadj is the voltage regulation signal HV_ADJUST, with an amplitude range of (0 to 5V). Resistor R83 and capacitor C106 are connected in parallel and then connected to the first foot and the second foot of PWM controller U32 respectively, serving as the feedback channel of the internal error amplifier of PWM controller U32.

[0060] The voltage output from the transformer rectification is divided by R80 and R85 and then sent to the second foot of the feedback pin of PWM controller U32. The voltage output by the single-chip microcomputer DAC is also connected to this feedback point through resistor R86. By adjusting the voltage output by the DAC, the single-chip microcomputer can adjust the PWM duty cycle output by PWM controller U32, thereby realizing the electronic control adjustment of the output voltage VCC_HV. The adjustment range of VCC_HV is (0V - 5000V). Among them, the feedback network composed of R80, R85, and R86 satisfies Kirchhoff's KCL law; R83 is the feedback resistor of the internal error amplifier of U32, which determines the internal feedback coefficient of PWM controller U32 and ultimately affects the high-voltage output accuracy.

[0061] The high-voltage MOS drive circuit 6 is respectively connected to the high-voltage generation and regulation circuit 5 and the MOS high-side power supply circuit 7. The high-voltage MOS drive circuit is used to adjust the positive pulse signal and the negative pulse signal to generate two high-voltage pulse signals with the same pulse width and opposite polarities.

[0062] In this embodiment, the high-voltage MOS drive circuit includes a first drive sub-circuit and a second drive sub-circuit. Both the first drive sub-circuit and the second drive sub-circuit are connected to the comparison and regulation circuit 3, the high-voltage generation and regulation circuit 5, and the MOS high-side power supply circuit 7.

[0063] The first driving sub - circuit includes a multiplexer inverter U8, a transformer T4, a gate driver U5, a gate driver U11, a resistor R7, a resistor R12, a resistor R21, a resistor R35, a resistor R110, a resistor R111, a power resistor R25, a capacitor C22, a capacitor C25, a capacitor C28, an NMOS transistor Q3, an NMOS transistor Q5, a zener diode D6, a zener diode D7, and a zener diode D46. The first pin of the multiplexer inverter U8 is respectively connected to the comparison and regulation circuit 3 and one end of the capacitor C25. The second pin of the multiplexer inverter U8 is connected to the first end of the transformer T4 through the capacitor C28. The second end of the transformer T4 is grounded. The third end of the transformer T4 is connected to the third pin of the gate driver U5. The fourth end of the transformer T4 is connected to the common end of the resistor R7 and the resistor R12. The first pin of the gate driver U5 is connected to the MOS - tube high - side power supply circuit 7. The second pin of the gate driver U5, the other end of the resistor R12, the source of the NMOS transistor Q3, the positive electrode of the zener diode D46, one end of the power resistor R25, and the common end of the capacitor C22 and the resistor R110 are all connected to the MOS - tube high - side power supply circuit 7. The fourth pin of the gate driver U5 is connected to the gate of the NMOS transistor Q3. The fifth pin of the gate driver U5 is connected to the other end of the resistor R7. The drain of the NMOS transistor Q3 is respectively connected to the negative electrode of the zener diode D46 and the high - voltage generation and regulation circuit 5. The third pin of the multiplexer inverter U8 is connected to the common end of the capacitor C25 and the resistor R21. The other end of the resistor R21 is grounded. The fourth pin of the multiplexer inverter U8 is connected to the sixth pin of the multiplexer inverter U8. The fifth pin of the multiplexer inverter U8 is externally connected to the power input terminal. The seventh pin of the multiplexer inverter U8 is respectively connected to the first pin of the gate driver U11 and one end of the resistor R35 through the zener diode D6. The other end of the resistor R35 is connected to the third pin of the gate driver U11. The second pin of the gate driver U11 is connected to the gate of the NMOS transistor Q5. The drain of the NMOS transistor Q5 and the negative electrode of the zener diode D7 are both connected to the other end of the power resistor R2. The source of the NMOS transistor Q5 and the positive electrode of the zener diode D7 are commonly grounded. The common end of the resistor R110 and the resistor R111 is grounded. The common end of the capacitor C22 and the resistor R111 is used as the output feed point of the positive pulse signal.

[0064] The second driving sub-circuit includes a multi-channel inverter U52, a transformer T6, a gate driver U54, a gate driver U53, a resistor R120, a resistor R121, a resistor R124, a resistor R125, a resistor R126, a power resistor R22, a capacitor C127, a capacitor C128, a capacitor C129, an NMOS transistor Q28, an NMOS transistor Q29, a zener diode D44, a zener diode D8, and a resistor R123. The first pin of the multi-channel inverter U52 is respectively connected to the comparison and regulation circuit 3 and one end of the capacitor C128. The second pin of the multi-channel inverter U52 is connected to the first end of the transformer T6 through the capacitor C127. The second end of the transformer T6 is grounded. The third end of the transformer T6 is connected to the third pin of the gate driver U54. The fourth end of the transformer T6 is connected to the common end of the resistor R126 and the resistor R125. The first pin of the gate driver U54 is connected to the MOS high-side power supply circuit 7. The second pin of the gate driver U54, the other end of the resistor R125, the source of the NMOS transistor Q29, one end of the power resistor R22, and the common end of the capacitor C129 and the resistor R123 are all connected to the MOS high-side power supply circuit 7. The fourth pin of the gate driver U54 is connected to the gate of the NMOS transistor Q29. The fifth pin of the gate driver U54 is connected to the other end of the resistor R126. The drain of the NMOS transistor Q29 is respectively connected to the other end of the resistor R123 and the high-voltage generation and regulation circuit 5. The third pin of the multi-channel inverter U52 is connected to the common end of the capacitor C128 and the resistor R120. The other end of the resistor R120 is grounded. The fourth pin of the multi-channel inverter U52 is connected to the sixth pin of the multi-channel inverter U52. The fifth pin of the multi-channel inverter U52 is externally connected to the power input terminal. The seventh pin of the multi-channel inverter U52 is respectively connected to the first pin of the gate driver U53 and one end of the resistor R121 through the zener diode D44. The other end of the resistor R121 is connected to the third pin of the gate driver U53. The second pin of the gate driver U53 is connected to the gate of the NMOS transistor Q28. The drain of the NMOS transistor Q28 and the negative pole of the zener diode D8 are both connected to the other end of the power resistor R22. The source of the NMOS transistor Q28 and the positive pole of the zener diode D8 are commonly grounded. One end of the resistor R124 is grounded. The common end of the capacitor C129 and the resistor R124 is used as the output feed point of the negative pulse signal.

[0065] Please refer to Figure 6 , taking the first driving circuit as an example, the first driving circuit includes a pulse signal inversion processing circuit, a high-side MOS transistor driving circuit, a low-side MOS transistor driving circuit, and an output coupling circuit. Among them,

[0066] The pulse signal inverting processing circuit includes a multiplex inverter U8, a resistor R21, and a capacitor C25. The first-channel input terminal of the first pin of the multiplex inverter U8 is connected to the first pulse input signal generated by the comparison and adjustment circuit 3. The second pin of the multiplex inverter U8 is connected to the high-side drive signal coupling capacitor C28. One side of the capacitor C25 is connected to the first pin of the multiplex inverter U8, and the other side is connected in series with the resistor R21 and then connected to the fifth pin of the multiplex inverter U8. The other side of the resistor R21 is grounded. The other channels of U8 are connected in a cascaded manner, that is, the sixth pin is connected to the thirteenth pin, the twelfth pin is connected to the eleventh pin, the tenth pin is connected to the ninth pin, and the eighth pin is the output after four cascades. The values of the capacitor C25 and the resistor R21 satisfy that the time constant 100ns < (τ = C25 * R21) < 3us. The capacitor C25 and C128 have the same parameter model, the resistor R21 and R120 have the same parameter model, and the multiplex inverter U8 and U52 have the same model parameters.

[0067] The high-side MOS transistor drive circuit includes a coupling capacitor C28, an isolation transformer T4, a gate driver U5, a resistor R7, a resistor R12, and an N-channel high-voltage MOS transistor Q3. One side of the coupling capacitor C28 is connected to the first-channel output of the second pin of the multiplex inverter U8, and the other side is connected to the non-homonymous end of the primary side of the isolation transformer T4. The homonymous end of the primary side of the isolation transformer T4 is connected to the ground, and the homonymous end of the secondary side is connected to the input of the third pin of the gate driver U5. The output reference of the fifth pin of the gate driver U5 is connected to the non-homonymous end of the secondary side of the isolation transformer T4 after being divided by the series connection of the resistors R7 and R12. The output of the fourth pin of the gate driver U5 is connected to the gate of Q3. The positive power supply terminal of the first pin and the ground power supply terminal of the second pin of the gate driver U5 are connected to the isolated output power supply generated by the MOS transistor high-side power supply circuit 7. The drain of Q3 is connected to the output voltage VCC_HV of the high-voltage generation and adjustment circuit 5, and the source is connected to the ground terminal P1_H_GATE_VCOM of the isolated output power supply generated by the MOS transistor high-side power supply circuit 7. The operating frequency range of the isolation transformer T4 is 0 to 500 kHz, the primary / secondary turn ratio is 1:6, the inductance value range of the primary side is 5uH - 30uH, the capacitance value of the coupling capacitor C28 is 1nF to 100nF, the values of the resistors R7 and R12 are the same, the isolation transformers T4 and T5 have the same model parameters, and the resistors R7, R12, R126, and R125 have the same model parameters.

[0068] The low-side MOS transistor driving circuit includes a voltage stabilizing diode D6, a gate driver U11, a bias resistor R35, an N-channel MOS transistor Q5, and a power resistor R25. The anode of the voltage stabilizing diode D6 is connected to the 8th pin of the multi-channel inverter U8, and the cathode is connected to the input of the 3rd pin of the gate driver U11. The reference output of the 5th pin of the gate driver U11 is connected to one side of R35, and the other side of R35 is connected to the anode of D6. The 1st and 2nd pins of the gate driver U11 are respectively connected to a 22V DC voltage and the ground electrode. The output of the 4th pin of the gate driver U11 is connected to the gate of Q5. The drain of Q5 is connected in series with the power resistor R25 and then connected to the source of Q3. The source of Q5 is grounded. The power resistors R25 and R22 have the same model parameters, and the resistance value ranges from 500Ω to 1500Ω. The voltage stabilizing diodes D6 and D44 have the same model parameters, and the voltage stabilizing range is from 1.6V to 6V. The MOS transistors Q3, Q5, Q29, and Q28 have exactly the same model parameters. The gate drivers U5, U11, U54, and U53 have exactly the same model parameters;

[0069] The positive pulse output coupling circuit of the output coupling circuit includes a capacitor C22, a resistor R110, and a resistor R111. The left side of the coupling capacitor C22 is respectively connected to one side of the resistor R110 and the source of Q3. The right side of C22 is connected to one side of the resistor R111 as the pulse output feed point. The other sides of R110 and R111 are directly grounded. The negative pulse output coupling circuit includes C129, R123, and R124. One side of the coupling capacitor C129 is connected to the source of Q29 and one side of R123. The other side of R123 is connected to the high-voltage bias voltage VCC_HV. The other side of the coupling capacitor C129 is connected to the resistor R124 as the negative pulse output feed point. The other side of R124 is grounded. The value ranges of the coupling capacitors C22 and C129 are from 100nF to 1000nF, and the resistors R110, R111, R123, and R124 have the same value.

[0070] Taking the first driving circuit as an example, in this driving circuit, due to the use of a totem-pole topology, the high-side and low-side MOS transistors need to be alternately turned on and off. Its control pulse signal is the single-ended pulse signal generated by the comparison and regulation circuit 3 in the above text 5. Therefore, a multi-channel inverter is used here. After the single-ended pulse signal is processed by the inverter, two pulse driving signals are obtained to respectively control the on and off of the high-side and low-side MOS transistors. Due to the existence of the Miller effect of the MOS transistor, there must be a certain dead time between the two pulse driving signals, and this dead time is determined by the time constant of R21 and C25. The function of the zener diode D6 is that the amplitude of the inverter output signal is 5V, while the minimum driving voltage of the gate driver is 6V. Here, the zener diode is used to provide a DC voltage bias through the resistor R35, so that the inverter output signal can directly drive the gate driver, and this method can improve the driving speed. The zener diode D6 is selected as (1.6V - 6V). Similarly, after R7 and R12 are voltage-divided, they are connected to the isolation transformer T4 to provide a basic DC voltage bias for the output terminal of the gate driver U5. The power resistor R25 exists on the one hand to limit the current, and on the other hand to quickly release the energy stored in the MOS transistor junction capacitance during the high-speed on and off process, reducing the trailing edge of the output pulse.

[0071] For the second driving circuit, its main implementation method is to utilize the fact that the voltage across the C129 capacitor cannot change suddenly. Under normal conditions, the left side of C129 is pulled up to the high-voltage bias voltage VCC_HV by the R123 resistor, and the right side is pulled down to the ground electrode by the R125. When the lower transistor Q28 is turned on instantaneously, the left side of C129 is pulled down to the ground, and at this time, the output on the right side of C129 is -VCC_HV.

[0072] As Figure 7 As shown, the high-side power supply circuit 7 for the MOS transistor includes an oscillation circuit, a power amplifier circuit, and a transformer isolation voltage doubling circuit. The oscillation circuit includes a high-speed operational amplifier U2 and an external resistor to form a feedback and frequency selection circuit, and the circuit outputs an oscillation frequency f = 1 / (2*pi*R103*C54). The power amplifier circuit includes a dual-channel integrated power amplifier U34. R97 and R6 form the first feedback circuit, and R98 and R50 form the second feedback circuit. C111 and C112 are the operational amplifier output coupling capacitors. The transformer isolation voltage doubling circuit includes the first transformer T1 and the second transformer T2. The dual-channel power amplifier outputs are respectively connected to the primary sides of the transformers T1 and T2 at the same-name terminals through the coupling capacitors C119 and C114. The diodes D1, D35, and the capacitor C121 form the first voltage doubling circuit and are connected to the secondary side of the transformer T1 at the same-name terminal through the coupling capacitor C120. Similarly, the diodes D8, D38, and the capacitor C123 form the second voltage doubling rectification circuit and are connected to the secondary side of the transformer T2 at the same-name terminal through the coupling capacitor C115. Finally, the oscillating signal after power amplification is isolated by the transformer and then voltage-doubled and rectified to obtain a DC voltage output with a doubled amplitude for the high-side drive power supply of the MOS transistor.

[0073] In this embodiment, the wireless communication circuit 8 is a WIFI module, which is connected to the MCU through a serial port to achieve wireless-to-serial communication. However, it is not limited thereto, and the wireless communication circuit 8 can also be Bluetooth or other wireless implementation forms.

[0074] In one example, the high-voltage pulse source generator includes a wireless communication circuit 8 for implementing a communication interface with the host computer; an MCU control circuit 4 for modulating the parameters of the high-voltage pulse source generator, cooperating with the wireless communication circuit 8 to communicate with the host computer, and realizing function interactions such as parameter setting and status monitoring; an edge trigger signal circuit 1 for receiving the trigger signal from the host computer side and synchronizing the working states of the transmitter and receiver; a pulse generation circuit for receiving the edge trigger signal and generating two trigger signals with adjustable pulse widths; a comparison and adjustment circuit 3 for adjusting the relative delay of the positive and negative pulse trigger signals; a high-voltage generation and adjustment circuit 5 for the MCU to adjust and generate a high-voltage source output with adjustable amplitude; a MOS high-side power supply for isolating the power input of the high-side gate driver to ensure reliable driving of the high-side MOS transistor; a MOS driving circuit for driving the adjusted pulse signal to generate positive and negative high-voltage pulse output signals.

[0075] In this embodiment, the working process of the high-voltage pulse source generator is as follows:

[0076] Step 1: The edge signal trigger circuit receives and processes the synchronous trigger signal sent by the host computer in the optical fiber link to obtain a stable and reliable trigger signal;

[0077] Step 2: The pulse generation and adjustment circuit 2 generates a pulse signal with controllable pulse width according to the trigger signal;

[0078] Step 3: The comparison and adjustment circuit 3 generates two pulse signals with relative delay according to the pulse signal in Step 2. As shown in the appendix, the delay time is T2 - T1, and their amplitudes and pulse widths are exactly the same; Figure 8 As shown, the delay time is T2 - T1, and their amplitudes and pulse widths are exactly the same;

[0079] Step 4: The high-voltage generation and adjustment circuit 5 generates a high-voltage output with controllable amplitude (output range 0V - 5000V), and the MOS high-side power supply circuit 7 generates an isolated DC voltage output (output range 22V - 28V)

[0080] Step 5: The two pulse signals generated in Step 3 are respectively used as the input pulse drive signals for the positive and negative pulse drive circuits;

[0081] Step 6: The positive and negative pulse drive circuits, according to the input pulse drive signals, obtain high and low side alternating control gate control signals after being processed by an inverter. The high side gate control signal is input to the gate driver through an isolation transformer to drive the high side MOS transistor to turn on and off, and the low side gate control signal is directly output to the low side gate driver to control the low side MOS transistor to turn on and off;

[0082] Step 7: The MOS transistor drives the output signal, which is output after being coupled by a coupling capacitor. Using the fact that the voltages across the coupling capacitor cannot change suddenly, positive and negative pulse signals with relative delays are respectively generated, and the delay time is T2 - T1;

[0083] Step 8: The positive and negative pulses generated in Step 7 can obtain a pulse output with adjustable pulse width and amplitude after being coupled by the antenna, as Figure 8 shown.

[0084] The high-voltage pulse source generator mainly uses a high-voltage MOS transistor as the core driving unit, adopts a totem-pole topology to achieve high-speed switching driving, and the DC high-voltage source of the pulse output uses a flyback circuit topology. The output voltage is adjusted by electronically controlling the feedback loop voltage. At the same time, the characteristics that the voltages across the capacitors cannot change suddenly are used to generate positive and negative high-voltage pulse outputs. The overall implementation method is to electronically control and adjust the high-voltage output and the pulse signal width through the MCU control circuit 4, so as to generate a high-voltage pulse signal with controllable amplitude and pulse width.

[0085] Through the edge trigger signal circuit 1 and the pulse generation and regulation circuit 2, the capture of the external synchronous trigger signal and the generation of positive and negative pulse signals with electronically adjustable pulse widths are realized, so that the pulse signals can be accurately controlled in terms of timing and width. In the comparison and regulation circuit 3, the relative delay of the positive and negative pulse signals is adjusted according to the reference voltage to ensure an accurate relative delay between the positive and negative pulse signals, thereby improving the overall accuracy and consistency of the pulse signals. The high-voltage generation and regulation circuit 5 can output a DC high voltage with adjustable amplitude, providing a flexible voltage regulation ability for the generation of high-voltage pulses, enabling the high-voltage pulse source generator to adapt to different detection depths and target characteristics, improving the applicability and detection accuracy of the high-voltage pulse source generator. At the same time, the MOS drive circuit adjusts the positive and negative pulse signals to generate two high-voltage pulse signals with the same pulse width, amplitude and opposite polarities, ensuring the symmetry and consistency of the signals, thereby improving the control accuracy of the high-voltage pulse source generator.

[0086] As Figure 9 shown, based on the above high-voltage pulse source generator with controllable amplitude and frequency, an embodiment of the present application discloses a large-depth ground penetrating radar device, including a main body housing 9, multi-component segmented antenna rods 10 arranged on opposite sides of the main body housing 9, and a high-voltage pulse source generator with controllable amplitude and frequency as described in any one of claims 1 to 8 arranged in the main body housing 9. The segmented antenna rod 10 includes a plurality of hollow cylindrical antennas with a diameter of 5 - 20 mm. Any two adjacent hollow cylindrical antennas are threadedly connected. A strip-shaped PCB is arranged inside the hollow cylindrical antenna, and a patch diode, a resistor and a capacitor are placed on the strip-shaped PCB. The diode is used to select the center frequency of the antenna.

[0087] In one example, the large-depth ground penetrating radar device includes a mainframe housing 9, a segmented antenna rod 10, a mainframe base 11, a fixing block 12, and an armrest bracket 13. Antenna connectors 111 are fixedly installed on both sides of the mainframe base 11. There are 8 connection positions for a total of 8 segmented antenna rods 10 symmetrically designed on both sides of the mainframe base 11, with a longitudinal spacing of 70 mm between the first and the second antenna, a longitudinal spacing of 250 mm between the first and the third antenna, and a longitudinal spacing of 320 mm between the first and the fourth antenna.

[0088] A contact copper piece 117 is fixedly installed on the upper side of the mainframe base 11. As Figure 10 shown, a protective antenna housing 107 is provided outside the segmented antenna rod 10. A male head plug 102 is fixed on one side of the segmented antenna rod 10. The male head plug 102 is inserted into an externally threaded copper piece 101, and a nut 112 is fixedly installed on the externally threaded copper piece 101. A female head plug 105 is fixed on one side of the segmented antenna rod 10. The female head plug 105 is inserted into an internally threaded copper piece 106, and a nut 112 is fixedly installed on the internally threaded copper piece 106. The externally threaded copper piece 101 and the internally threaded copper piece 106 are connected and fixed using an FPC flexible board 104. The segmented antenna rod 10 includes an externally threaded copper piece 101, a male head plug 102, an internally threaded copper piece 106, and a female head plug 105. The segmented antenna rod 10 extends into the interior of the mainframe base 11, and the internally threaded copper piece 106 is threadedly connected inside the antenna connector 111. The segmented antenna rod 10 is connected to the segmented antenna rod 10a. A threaded hole is provided inside the externally threaded copper piece 101 of the male head plug of the segmented antenna rod 10, which is threadedly docked with the internally threaded copper piece 106 of the female head plug to form an antenna assembly.

[0089] As Figure 11 shown, the components of the mainframe base 11 are an antenna connector 111, a nut 112, a mainframe bottom cover plate 113, a rubber pad 114, a bull's-eye ball 115, the housing of the mainframe base 11, and a contact copper piece 117. The housing of the mainframe base 11 provides a basic connection structure for the entire mainframe base 11. There are 8 pairs of connectors composed of antenna connectors 111 and nuts 112 on the left and right sides, in a symmetrical manner, for connecting and fixing the antenna rod structure below; the mainframe bottom cover plate 113 and the rubber pad 114 are used for crimping and supporting with the mainframe housing 9; the contact copper piece 117 is used for reliable connection of the feed point between the output pulse signal of the high-voltage pulse source circuit board and the antenna structure.

[0090] As Figure 12As shown, the upper part of the armrest bracket 13 is a hand-held rod 131. At both ends of the hand-held rod 131, locking connection male heads 131a are fixedly installed. The lower part of the armrest bracket 13 is a vertical rod 133. At the upper end of the vertical rod 133, a locking connection female head 133a is fixedly installed. The locking connection male head 131a is connected using an annular screw 136 through a circular hole groove. At the lower end of the vertical rod 133, a stabilizing block 135 is fixedly connected. At the lower end of the stabilizing block 135, a circular hole groove is opened for fixedly connecting a pin 137. The stabilizing block 135 is fixedly installed with a cam screw 134. The bottom end of the vertical rod 133 includes the stabilizing block 135. Four through holes are opened on the side of the stabilizing block 135 for inserting the segmented antenna rod 10, and it is locked and fixed by pressing down with the cam screw 134. The armrest bracket 13 includes the locking connection male head 131a. The locking connection male head 131a is inserted into the locking connection female head 133a for fixation, and the annular screw 136 is threadedly connected for locking. The lower end circular tube of the vertical rod 133 is inserted into the upper end opening of the stabilizing block 135, and is locked and fixed on the side using the pin 137.

[0091] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A high-voltage pulse source generator with controllable amplitude and frequency, characterized in that It includes an edge-triggered signal circuit (1), a pulse generation and regulation circuit (2), a comparison and regulation circuit (3), an MCU control circuit (4), a high-voltage generation and regulation circuit (5), a high-voltage MOS drive circuit (6), a MOS high-side power supply circuit (7), and a wireless communication circuit (8). Among them, the edge-triggered signal circuit (1) is connected to the pulse generation and regulation circuit (2); the pulse generation and regulation circuit (2) is respectively connected to the comparison and regulation circuit (3) and the MCU control circuit (4). The pulse generation and regulation circuit (2) is used to receive the external synchronous trigger edge signal sent by the edge-triggered signal circuit (1) and generate positive and negative pulse signals with electrically adjustable pulse widths; the comparison and regulation circuit (3) is respectively connected to the MCU control circuit (4) and the high-voltage MOS drive circuit (6). The comparison and regulation circuit (3) is used to perform relative delay adjustment on the positive and negative pulse signals output by the pulse generation and regulation circuit (2) according to the positive and negative pulse signals generated by the pulse generation and regulation circuit (2) and the reference voltage, so as to obtain positive and negative pulse signals with relative delays; the MCU control circuit (4) is respectively connected to the high-voltage generation and regulation circuit (5) and the wireless communication circuit (8). The high-voltage generation and regulation circuit (5) responds to the instruction of the MCU control circuit (4), outputs a DC voltage with adjustable amplitude, and provides a DC bias for the high-voltage MOS drive circuit; the high-voltage MOS drive circuit (6) is respectively connected to the high-voltage generation and regulation circuit (5) and the MOS high-side power supply circuit (7). The high-voltage MOS drive circuit is used to regulate the positive and negative pulse signals to generate two high-voltage pulse signals with the same pulse width, amplitude, and opposite polarities.

2. A high-voltage pulse source generator with controllable amplitude and frequency as claimed in claim 1, characterized in that, The edge-triggered signal circuit (1) includes an optical fiber receiver U3, a capacitor C16, a capacitor C20, a capacitor C23, a comparator U52, a resistor R4, a resistor R8, and a resistor R23. The first end of the optical fiber receiver U3 is connected to one end of the capacitor C23. The other end of the capacitor C23 and the inverting input terminal of the comparator U52 are both connected to one end of the resistor R23. The second end of the optical fiber receiver U3 is grounded. The third end of the optical fiber receiver U3 is externally connected to a voltage input terminal. The fourth end of the optical fiber receiver U3 is connected to the capacitor C16. The other end of the capacitor C16 and the non-inverting input terminal of the comparator U52 are both connected to one end of the resistor R4. The other end of the resistor R4 is respectively connected to the output terminal of the comparator U52 and one end of the resistor R8. The common terminal of the resistor R8 and the resistor R23 is respectively connected to one end of the capacitor C20 and the pulse generation and regulation circuit (2). The other end of the capacitor C20 is grounded.

3. The high-voltage pulse source generator with controllable amplitude and frequency as described in claim 1, characterized in that, The pulse generation and regulation circuit (2) includes a multivibrator U60, a digital potentiometer U61, an oscillation resistor R130, an oscillation capacitor C132, and a resistor R131. The first pin of the multivibrator U60 is grounded. The external synchronous trigger edge signal is input through the second pin of the multivibrator U60. The third pin of the multivibrator U60 is connected to one end of the resistor R131. The fourth pin of the multivibrator U60 and the other end of the resistor R131 are commonly grounded. The fifth pin of the multivibrator U60 is externally connected to a voltage input terminal. The sixth pin of the multivibrator U60 is connected to the common terminal of the oscillation resistor R130 and the oscillation capacitor C132. The seventh pin of the multivibrator U60 is connected to the other end of the oscillation capacitor C132. The other end of the oscillation resistor R130 is connected to the digital potentiometer U61.

4. A high-voltage pulse source generator with controllable amplitude and frequency as claimed in claim 1, characterized in that, The comparison and regulation circuit (3) includes a DAC output chip U59, a comparator U51, and a comparator U55. The first pin of the DAC output chip U59 is externally connected to a voltage input terminal. The second pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U51. The third pin of the DAC output chip U59 is connected to the inverting input terminal of the comparator U55. The non-inverting input terminals of both the comparator U51 and the comparator U55 are connected to the pulse generation and regulation circuit (2). The output terminals of both the comparator U51 and the comparator U55 are connected to the high-voltage MOS transistor drive circuit.

5. A high-voltage pulse source generator with controllable amplitude and frequency as claimed in claim 1, characterized in that, The high-voltage generation and regulation circuit (5) includes resistors R74, R75, R78, R80, R83, R85, R86, R127, R128, R129, capacitors C97, C101, C104, C106, C130, a PWM controller U32, an NMOS transistor U56, a filter inductor L10, a rectifier diode D19, a diode D22, and a high-frequency transformer T5, where One end of the resistor R80 is grounded through the resistor R85. One end of the resistor R80 is connected to the MCU control circuit (4) through the resistor R86. One end of the resistor R80 is also connected to the common terminal of the resistor R83, the capacitor C106, and the PWM controller U32. The other common terminal of the resistor R83 and the capacitor C106 is connected to the first pin of the PWM controller U32. The third pin of the PWM controller U32 is connected to the common terminal of the resistor R83 and the capacitor C101. The fourth pin of the PWM controller U32 is connected to the common terminal of the resistor R75 and the capacitor C104. The common terminal of the capacitor C104 and the resistor R74 is grounded. The common terminal of the resistor R75 and the resistor R74 is connected to the source electrode of the NMOS transistor U56. The other end of the capacitor C104 is grounded through the resistor R78. The other end of the resistor R75 and the fifth pin of the PWM controller U32 are commonly connected to an external voltage input terminal. The common terminal of the sixth pin of the PWM controller U32 and the filter inductor L10 is connected to an external voltage input terminal. The seventh pin of the PWM controller U32 is connected to the gate electrode of the NMOS transistor U56. The eighth pin of the PWM controller U32 is grounded. The drain electrode of the NMOS transistor U56 is respectively connected to the positive electrode of the diode D22 and the second terminal of the high-frequency transformer T5. The negative electrode of the diode D22 is connected to the first common terminal of the resistor R127 and the capacitor C130. The second common terminal of the resistor R127 and the capacitor C130 is respectively connected to the other end of the filter inductor L10 and the first terminal of the high-frequency transformer T5. The third terminal of the high-frequency transformer T5 is connected to the positive electrode of the rectifier diode D19. The negative electrode of the rectifier diode D19, one end of the capacitor C97, and the resistor R128 are connected to the other end of the resistor R80. The capacitor C97 and the fourth terminal of the high-frequency transformer T5 are commonly grounded. The common terminal of the resistor R128 and the resistor R129 is connected to the MCU control circuit (4). The other end of the resistor R129 is grounded.

6. The high-voltage pulse source generator with controllable amplitude and frequency as claimed in claim 1, wherein The high-voltage MOS transistor drive circuit includes a first drive sub-circuit and a second drive sub-circuit. Both the first drive sub-circuit and the second drive sub-circuit are connected to the comparison and regulation circuit (3), the high-voltage generation and regulation circuit (5), and the MOS transistor high-side power supply circuit (7).

7. The high-voltage pulse source generator with controllable amplitude and frequency as described in claim 6, characterized in that, The first driving sub-circuit includes a multi-channel inverter U8, a transformer T4, a gate driver U5, a gate driver U11, a resistor R7, a resistor R12, a resistor R21, a resistor R35, a resistor R110, a resistor R111, a power resistor R25, a capacitor C22, a capacitor C25, a capacitor C28, an NMOS transistor Q3, an NMOS transistor Q5, a zener diode D6, a zener diode D7, and a zener diode D46. The first pin of the multi-channel inverter U8 is respectively connected to the comparison and regulation circuit (3) and one end of the capacitor C25. The second pin of the multi-channel inverter U8 is connected to the first end of the transformer T4 through the capacitor C28. The second end of the transformer T4 is grounded. The third end of the transformer T4 is connected to the third pin of the gate driver U5. The fourth end of the transformer T4 is connected to the common end of the resistor R7 and the resistor R12. The first pin of the gate driver U5 is connected to the MOS transistor high-side power supply circuit (7). The second pin of the gate driver U5, the other end of the resistor R12, the source of the NMOS transistor Q3, the positive electrode of the zener diode D46, one end of the power resistor R25, and the common end of the capacitor C22 and the resistor R110 are all connected to the MOS transistor high-side power supply circuit (7). The fourth pin of the gate driver U5 is connected to the gate of the NMOS transistor Q3. The fifth pin of the gate driver U5 is connected to the other end of the resistor R7. The drain of the NMOS transistor Q3 is respectively connected to the negative electrode of the zener diode D46 and the high-voltage generation and regulation circuit (5). The third pin of the multi-channel inverter U8 is connected to the common end of the capacitor C25 and the resistor R21. The other end of the resistor R21 is grounded. The fourth pin of the multi-channel inverter U8 is connected to the sixth pin of the multi-channel inverter U8. The fifth pin of the multi-channel inverter U8 is externally connected to the power supply input terminal. The seventh pin of the multi-channel inverter U8 is respectively connected to the first pin of the gate driver U11 and one end of the resistor R35 through the zener diode D6. The other end of the resistor R35 is connected to the third pin of the gate driver U11. The second pin of the gate driver U11 is connected to the gate of the NMOS transistor Q5. The drain of the NMOS transistor Q5 and the negative electrode of the zener diode D7 are both connected to the other end of the power resistor R2. The source of the NMOS transistor Q5 and the positive electrode of the zener diode D7 are grounded together. The common end of the resistor R110 and the resistor R111 is grounded. The common end of the capacitor C22 and the resistor R111 is used as the output feed point of the positive pulse signal.

8. The high-voltage pulse source generator with controllable amplitude and frequency as claimed in claim 6, wherein The second driving sub-circuit includes a multi-channel inverter U52, a transformer T6, a gate driver U54, a gate driver U53, a resistor R120, a resistor R121, a resistor R124, a resistor R125, a resistor R126, a power resistor R22, a capacitor C127, a capacitor C128, a capacitor C129, an NMOS transistor Q28, an NMOS transistor Q29, a zener diode D44, a zener diode D8, and a resistor R123. The first pin of the multi-channel inverter U52 is respectively connected to the comparison and regulation circuit (3) and one end of the capacitor C128. The second pin of the multi-channel inverter U52 is connected to the first end of the transformer T6 through the capacitor C127. The second end of the transformer T6 is grounded. The third end of the transformer T6 is connected to the third pin of the gate driver U54. The fourth end of the transformer T6 is connected to the common end of the resistor R126 and the resistor R125. The first pin of the gate driver U54 is connected to the MOS transistor high-side power supply circuit (7). The second pin of the gate driver U54, the other end of the resistor R125, the source of the NMOS transistor Q29, one end of the power resistor R22, and the common end of the capacitor C129 and the resistor R123 are all connected to the MOS transistor high-side power supply circuit (7). The fourth pin of the gate driver U54 is connected to the gate of the NMOS transistor Q29. The fifth pin of the gate driver U54 is connected to the other end of the resistor R126. The drain of the NMOS transistor Q29 is respectively connected to the other end of the resistor R123 and the high-voltage generation and regulation circuit (5). The third pin of the multi-channel inverter U52 is connected to the common end of the capacitor C128 and the resistor R120. The other end of the resistor R120 is grounded. The fourth pin of the multi-channel inverter U52 is connected to the sixth pin of the multi-channel inverter U52. The fifth pin of the multi-channel inverter U52 is externally connected to the power supply input terminal. The seventh pin of the multi-channel inverter U52 is respectively connected to the first pin of the gate driver U53 and one end of the resistor R121 through the zener diode D44. The other end of the resistor R121 is connected to the third pin of the gate driver U53. The second pin of the gate driver U53 is connected to the gate of the NMOS transistor Q28. The drain of the NMOS transistor Q28 and the negative pole of the zener diode D8 are both connected to the other end of the power resistor R22. The source of the NMOS transistor Q28 and the positive pole of the zener diode D8 are commonly grounded. One end of the resistor R124 is grounded. The common end of the capacitor C129 and the resistor R124 is used as the output feed point of the negative pulse signal.

9. A large-depth ground penetrating radar device, characterized in that, It includes a host housing (9), multi-component segmented antenna rods (10) arranged on opposite sides of the host housing (9), and a high-voltage pulse source generator with controllable amplitude and frequency as described in any one of claims 1 to 8 arranged inside the host housing (9).

10. A large-depth ground penetrating radar device according to claim 9, characterized in that, The segmented antenna rod (10) includes multiple hollow cylindrical antennas with a diameter of 5 to 20 mm. Any two adjacent hollow cylindrical antennas are connected by threads. A strip-shaped PCB is disposed inside the hollow cylindrical antenna. A patch diode, a resistor, and a capacitor are placed on the strip-shaped PCB. The diode is used to select the center frequency of the antenna.

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